L6229

Datasheet

DMOS driver for 3-phase brushless DC motor

Features
• Operating supply voltage from 8 to 52 V
• 2.8 A output peak current (1.4 A DC)
• RDS(ON) 0.73 Ω typ. value at Tj = 25 °C
• Operating frequency up to 100 kHz
• Non-dissipative overcurrent detection and protection
Power S036 • Diagnostic output
• Constant tOFF PWM current controller
• Slow decay synchronous rectification
• 60° and 120° Hall effect decoding logic
• Brake function
• Tachometer output for speed loop
• Cross conduction protection
• Thermal shutdown
• Undervoltage lockout
SO24 • Integrated fast free wheeling diodes
(20 + 2 + 2)

Application
• Factory automation end-points
• Home appliances
Product status link • Small pumps
L6229
• ATMs

Product summary
Description
Order code Package Packing
The L6229 is a DMOS fully integrated 3-phase motor driver with overcurrent
L6229D SO-24 Tube protection.

L6229DTR SO-24
Tape and Realized in BCD technology, the device combines isolated DMOS power transistors
reel with CMOS and bipolar circuits on the same chip.
L6229PD PowerSO36 Tube The device includes all the circuitry needed to drive a 3-phase BLDC motor including:
Tape and a 3-phase DMOS bridge, a constant off time PWM current controller and the
L6229PDTR PowerSO36 decoding logic for single ended Hall sensors that generates the required sequence
reel
for the power stage.
Product label Available in Power SO36 and SO24 (20 + 2 + 2) packages, the L6229 features a
non-dissipative overcurrent protection on the high-side power MOSFET and thermal
shutdown.

DS3275 - Rev 7 - April 2022 www.st.com

For further information contact your local STMicroelectronics sales office.
 L6229
Block diagram

1 Block diagram

Figure 1. Block diagram

VBOOT VS A
VBOOT VBOOT
CHARGE THERMAL
VCP
PUMP PROTECTION

OCD1
OUT 1
DIAG OCD1 10 V
OCD OCD2
OCD3
OCD
EN VBOOT
BRAKE
FWD/REV
OCD2
OUT 2
H3 GATE 10 V
LOGIC
HALL EFFECT
H2 SENSORS
DECODING
LOGIC SENSE A

H1 VBOOT VS B

TACHO
RCPULSE OCD3
MONOSTABLE OUT 3
10 V
TACHO
10 V 5V
SENSE B
PWM
VOLTAGE
ONE SHOT MASKING +
REGULATOR
MONOSTABLE TIME SENSE - VREF
COMPARATOR

RCOFF

DS3275 - Rev 7 page 2/34

 L6229
Absolute maximum ratings

2 Absolute maximum ratings

Table 1. Absolute maximum ratings

Symbol Parameter Test conditions Value Unit

VS Supply voltage VSA = VSB = VS 60 V

Differential voltage between: VSA = VSB = VS = 60 V;

VOD 60 V
VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB VSENSEA = VSENSEB = GND

VBOOT Bootstrap peak voltage VSA = VSB = VS VS + 10 V

VIN, VEN Logic inputs voltage range - -0.3 to 7 V

VREF Voltage range at pin VREF - -0.3 to 7 V

VRCOFF Voltage range at pin RCOFF - -0.3 to 7 V

VRCPULSE Voltage range at pin RCPULSE - -0.3 to 7 V

VSENSE Voltage range at pins SENSEA and SENSEB - -1 to 4 V

IS(peak) Pulsed supply current (for each VSA and VSB pin) VSA = VSB = VS; tPULSE < 1 ms 3.55 A

IS DC supply current (for each VSA and VSB pin) VSA = VSB = VS 1.4 A

Tstg, TOP Storage and operating temperature range - -40 to 150 °C

DS3275 - Rev 7 page 3/34

 L6229
Recommended operating condition

3 Recommended operating condition

Table 2. Recommended operating condition

Symbol Parameter Test conditions Min. Max. Unit

VS Supply voltage VSA = VSB = VS 8 52 V

Differential voltage between: VSA = VSB = VS;

VOD - 52 V
VSA, OUT1, OUT2, SENSEA and VSB, OUT3, SENSEB VSENSEA = VSENSEB

VREF Voltage range at pin VREF - -0.1 5 V

(pulsed tW < trr) -6 6

VSENSE Voltage range at pins SENSEA and SENSEB V
(DC) -1 1

IOUT DC output current VSA = VSB = VS - 1.4 A

fSW Switching frequency - - 100 kHz

DS3275 - Rev 7 page 4/34

 L6229
Thermal data

4 Thermal data

Table 3. Thermal data

Symbol Description SO24 PowerSO36 Unit

Rth(j-pins) Maximum thermal resistance junction pins 15 - °C/W

Rth(j-case) Maximum thermalresistance junction case - 2 °C/W

Rth(j-amb)1 Maximum thermal resistance junction ambient (1) 55 - °C/W

Rth(j-amb)1 Maximum thermal resistance junction ambient (2) - 36 °C/W

Rth(j-amb)1 Maximum thermal resistance junction ambient (3) - 16 °C/W

Rth(j-amb)2 Maximum thermal resistance junction ambient (4) 78 63 °C/W

1. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 μm).
2. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm).
3. Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm), 16
via holes and a ground layer.
4. Mounted on a multilayer FR4 PCB without any heat-sinking surface on the board.

DS3275 - Rev 7 page 5/34

 L6229
Pin connections

5 Pin connections

Figure 2. Pin connections (top view)

GND 1 36 GND
N.C. 2 35 N.C.
H1 1 24 H3 N.C. 3 34 N.C.
DIAG 2 23 H2 VS A 4 33 VS B

S ENS E A 3 22 VCP OUT2 5 32 OUT3

N.C. 6 31 N.C.
RCOFF 4 21 OUT2
VCP 7 30 VBOOT
OUT1 5 20 VS A
H2 8 29 BRAKE
GND 6 19 GND H3 9 28 VREF
GND 7 18 GND H1 10 27 EN
TACHO 8 17 VS B DIAG 11 26 FWD/REV
RCP ULS E 9 16 OUT3 SENSE A 12 25 SENSE B

S ENS E B 10 15 VBOOT RCOFF 13 24 RCPULSE

N.C. 14 23 N.C.
FWD/REV 11 14 BRAKE
OUT1 15 22 TACHO
EN 12 13 VREF
N.C. 16 21 N.C.
N.C. 17 20 N.C.
GND 18 19 GND

SO24 PowerSO36 (1)

1. The slug is internally connected to pins 1, 18, 19 and 36 (GND pins).

Table 4. Pin functions

Package

SO24 PowerSO36 Pin name Type Function

Pin no. Pin no.

1 10 H1 Sensor input Single ended Hall effect sensor input 1.

Overcurrent detection and thermal protection pin. An internal open

Open drain
2 11 DIAG drain transistor pulls to GND when an overcurrent on one of the high-
output
side MOSFET is detected or during thermal protection.
Half-bridge 1 and half-bridge 2 source pin. This pin must be connected
3 12 SENSEA Power supply together with pin SENSEB to power ground through a sensing power
resistor.
RC network pin. A parallel RC network connected between this pin and
4 13 RCOFF RC pin
ground sets the current controller OFF-time.

5 15 OUT1 Power output Output 1

Ground terminals. On SO24 package, these pins are also used for
6, 7, 18,
1, 18, 19, 36 GND GND heat dissipation toward the PCB. On PowerSO36 package the slug is
19
connected on these pins.

Open drain Frequency-to-voltage open drain output. Every pulse from pin H1 is
8 22 TACHO
output shaped as a fixed and adjustable length pulse.
RC network pin. A parallel RC network connected between this pin
9 24 RCPULSE RC pin and ground sets the duration of the monostable pulse used for the
frequency-to-voltage converter.
Half-bridge 3 source pin. This pin must be connected together with pin
10 25 SENSEB Power supply SENSEA to power ground through a sensing power resistor. At this pin
also the inverting input of the sense comparator is connected.
Selects the direction of the rotation. HIGH logic level sets forward
11 26 FWD/REV Logic input operation, whereas LOW logic level sets reverse operation. If not used,
it has to be connected to GND or +5 V.

DS3275 - Rev 7 page 6/34

 L6229
Pin connections

Package

SO24 PowerSO36 Pin name Type Function

Pin no. Pin no.

Chip enable. LOW logic level switches OFF all power MOSFET. If not
12 27 EN Logic input
used, it has to be connected to +5 V.
Current controller reference voltage. Do not leave this pin open or
13 28 VREF Logic input
connect to GND.
Brake input pin. LOW logic level switches ON all high- side power
14 29 BRAKE Logic input MOSFET, implementing the brake function. If not used, it has to be
connected to +5 V.
Supply
15 30 VBOOT Bootstrap voltage needed for driving the upper power MOSFETs.
voltage

16 32 OUT3 Power output Output 3.

Half-bridge 3 power supply voltage. It must be connected to the supply

17 33 VSB Power supply
voltage together with pin VSA.

Half-bridge 1 and half-bridge 2 power supply voltage. It must be

20 4 VSA Power supply
connected to the supply voltage together with pin VSB.

21 5 OUT2 Power output Output 2.

22 7 VCP Output Charge pump oscillator output.

23 8 H2 Sensor input Single ended Hall effect sensor input 2.

24 9 H3 Sensor input Single ended Hall effect sensor input 3.

DS3275 - Rev 7 page 7/34

 L6229
Electrical characteristics

6 Electrical characteristics

Table 5. Electrical characteristics

Test conditions: VS = 48 V, Tamb = 25 °C , unless otherwise specified)
Symbol Parameter Test conditions Min. Typ. Max. Unit

VSth(ON) Turn ON threshold - 5.8 6.3 6.8 V

VSth(OFF) Turn OFF threshold - 5 5.5 6 V

All bridges OFF;

IS Quiescent supply current - 5 10 mA
TJ = -25 to 125 °C (1)

TJ(OFF) Thermal shutdown temperature - - 165 - °C

Output DMOS transistors

TJ = 25 °C - 1.47 1.69 Ω
RDS(ON) High-side + low-side switch ON resistance
TJ = 125 °C(2) - 2.35 2.70 Ω

EN = low; OUT = VCC - - 2 mA

IDSS Leakage current
EN = low; OUT = GND -0.3 - - mA
Source drain diodes
VSD Forward ON voltage ISD = 1.4 A, EN = low - 1.15 1.3 V

trr Reverse recovery time If = 1.4 A - 300 - ns

tfr Forward recovery time - - 200 - ns

Logic input (H1, H2, H3, EN, FWD/REV, BRAKE)

VIL Low level logic input voltage - -0.3 - 0.8 V

VIH High level logic input voltage - 2 - 7 V

IIL Low level logic input current GND logic input voltage -10 - - μA

IIH High level logic input current 7V logic input voltage - - 10 μA

Vth(ON) Turn-ON input threshold - - 1.8 2.0 V

Vth(OFF) Turn-OFF input threshold - 0.8 1.3 - V

VthHYS Input thresholds hysteresis - 0.25 0.5 - V

Switching characteristics
tD(on)EN Enable to out turn-ON delay time(2) ILOAD = 1.4 A, resistive load 500 650 800 ns

tD(off)EN Enable to out turn-OFF delay time(2) ILOAD = 1.4 A, resistive load 500 - 1000 ns

tD(on)IN Other logic inputs to output turn-ON delay time ILOAD = 1.4 A, resistive load - 1.6 - µs

tD(off)IN Other logic inputs to out turn-OFF delay time ILOAD = 1.4 A, resistive load - 800 - ns

tRISE Outputrise time (2) ILOAD = 1.4 A, resistive load 40 - 250 ns

tFALL Outputfall time (2) ILOAD = 1.4 A, resistive load 40 - 250 ns

tDT Deadtime - 0.5 1 - µs

fCP Charge pump frequency TJ = -25 to 125 °C(1) - 0.6 1 MHz

PWM comparator and monostable

IRCOFF Source current at pin RCOFF VRCOFF = 2.5 V 3.5 5.5 - mA

VOFFSET Offset voltage on sense comparator Vref = 0.5 V - ±5 - mV

DS3275 - Rev 7 page 8/34

 L6229
Electrical characteristics

Symbol Parameter Test conditions Min. Typ. Max. Unit

tprop Turn OFF propagation delay(3) Vref = 0.5 V - 500 - ns

tblank Internal blanking time on sense comparator - - 1 - µs

tON(min) Minimum on time - - 2.5 3 µs

ROFF = 20 kΩ; COFF = 1 nF - 13 - μs

tOFF PWM recirculation time
ROFF = 100 kΩ; COFF = 1 nF - 61 - μs

IBIAS Input bias current at pin VREF - - - 10 µA

TACHO monostable
IRCPULSE Source current at pin RCPULSE VRCPULSE = 2.5 V 3.5 5.5 - mA

RPUL = 20 kΩ; CPUL = 1 nF - 12 - ms

tPULSE Monostable of time
RPUL = 100 kΩ; CPUL = 1 nF - 60 - ms

RTACHO Open drain ON resistance - - 40 60 Ω

Overcurrent detection and protection

ISOVER Supply overcurrent protection threshold TJ = -25 to 125 °C(1) 2 2.8 3.55 A

ROPDR Open drain ON resistance IDIAG = 4 mA - 40 60 Ω

IOH OCD high level leakage current VDIAG = 5 V - 1 - µA

tOCD(ON) OCD turn-ON delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 200 - ns

tOCD(OFF) OCD turn-OFF delay time(4) IDIAG = 4mA; CDIAG < 100 pF - 100 - ns

1. Tested at 25 °C in a restricted range and guaranteed by characterization.

2. See Figure 3: Switching characteristic definition.
3. Measured applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF.
4. See Figure 4: Overcurrent detection timing definition.

Figure 3. Switching characteristic definition

EN

Vth(ON)

Vth(OFF)

t
IOUT

90%

10%
t
tFALL tRIS E
tD(OFF)EN tD(ON)EN

DS3275 - Rev 7 page 9/34

 L6229
Electrical characteristics

Figure 4. Overcurrent detection timing definition

IOUT

IS OVER

ON
BRIDGE
OFF

VDIAG

90%

10%

tOCD(ON) tOCD(OFF)

DS3275 - Rev 7 page 10/34

 L6229
Circuit description

7 Circuit description

7.1 Power stages and charge pump

The L6229 device integrates a 3-phase bridge, which consists of 6 power MOSFETs connected as shown in Block
diagram . Each power MOS has an RDS(ON) = 0.73 Ω (typical value at 25 °C) with intrinsic fast free-wheeling
diode. Switching patterns are generated by the PWM current controller and the Hall effect sensor decoding
logic (see Section 8 PWM current control and Section 10 Decoding logic). Cross conduction protection is
implemented by using a deadtime (tDT = 1 μs typical value) set by internal timing circuit between the turn off and
turn on of two power MOSFETs in one leg of a bridge.
Pins VSA and VSB must be connected together to the supply voltage (VS).
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive voltage above the power
supply voltage.
The bootstrapped supply (VBOOT) is obtained through an internal oscillator and few external components to
realize a charge pump circuit as shown in Figure 5. The oscillator output (pin VCP) is a square wave at 600
kHz (typically) with 10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown in
Table 6.

Table 6. Charge pump external component values

Component Value

CBOOT 220 nF

CP 10 nF

RP 100 Ω

D1 1N4148

D2 1N4148

Figure 5. Charge pump circuit

VS

D1 C BOOT
D2

RP

CP

VCP VBOOT VS A VS B

DS3275 - Rev 7 page 11/34

 L6229
Logic inputs

7.2 Logic inputs

Pins FWD/REV, BRAKE, EN, H1, H2 and H3 are TTL/CMOS compatible logic inputs. The internal structure is
shown in Figure 6. Typical value for turn-ON and turn-OFF thresholds are respectively Vth(ON) = 1.8 V and
Vth(OFF) = 1.3 V.
Pin EN (enable) may be used to implement overcurrent and thermal protection by connecting it to the open
collector DIAG output. If the protection and an external disable function are both desired, the appropriate
connection must be implemented. When the external signal is from an open collector output, the circuit in Figure 7
can be used.
For external circuits that are push-pull outputs the circuit in Figure 8 could be used. The resistor REN should be
chosen in the range from 2.2 kΩ to 180 kΩ.
Recommended values for REN and CEN are respectively 100 kΩ and 5.6 nF. More information for selecting the
values can be found Section 12 Non-dissipative overcurrent detection and protection.

Figure 6. Logic input internal structure

5V

ESD
PROTECTION

Figure 7. Pin EN open collector driving

DIAG
5V
5V
R EN

OPEN
COLLECTOR
OUTPUT EN
C EN
ESD
PROTECTION

Figure 8. Pin EN push-pull driving

DIAG

5V

R EN
PUSH-PULL
OUTPUT EN
C EN ESD
PROTECTION

DS3275 - Rev 7 page 12/34

 L6229
PWM current control

8 PWM current control

The L6229 device includes a constant off time PWM current controller. The current control circuit senses the
bridge current by sensing the voltage drop across an external sense resistor connected between the source of
the three lower power MOS transistors and ground, as shown in Figure 9. As the current in the motor increases
the voltage across the sense resistor increases proportionally. When the voltage drop across the sense resistor
becomes greater than the voltage at the reference input pin VREF the sense comparator triggers the monostable
switching the bridge off. The power MOS remains off for the time set by the monostable and the motor current
recirculates around the upper half of the bridge in slow decay mode as described in Section 9 Slow decay
mode. When the monostable times out, the bridge will again turn on. Since the internal deadtime, used to prevent
cross conduction in the bridge, delays the turn on of the power MOS, the effective off time tOFF is the sum of the
monostable time plus the deadtime.
Figure 10 shows the typical operating waveforms of the output current, the voltage drop across the sensing
resistor, the pin RC voltage and the status of the bridge. More details regarding the synchronous rectification and
the output stage configuration are included in Section 9 Slow decay mode.
Immediately after the power MOS turns on, a high peak current flows through the sense resistor due to the
reverse recovery of the freewheeling diodes. The L6229 device provides a 1 μs blanking time tBLANK that inhibits
the comparator output so that the current spike cannot prematurely retrigger the monostable.

Figure 9. PWM current controller simplified schematic

VS
VS B VS A

BLANKING TIME
TO GATE MONOSTABLE
LOGIC
FROM THE
LOW-SIDE
GATE DRIVERS

5 mA MONOSTABLE
SET
S BLANKER
OUT 2
Q
(0) (1) OUT 3
R
OUT 1
DRIVERS DRIVERS
+ +
- DEADTIME DEADTIME DRIVERS
5V + +
2.5 V DEADTIME

+
SENSE -
COMPARATOR

RCOFF VREF SENSE B SENSE A

C OFF
R OFF R SENSE

DS3275 - Rev 7 page 13/34

 L6229
PWM current control

Figure 10. Output current regulation waveforms

IOUT
VREF
R SENSE

tOFF tON tOFF

VSENSE

VREF

Slow decay Slow decay

0

VRC tRCRISE tRCRISE

5V

2.5 V
tRCFALL tRCFALL

ON

SYNCHRONOUS RECTIFICATION
OFF
B C D A B C D

Figure 11 shows the magnitude of the off time tOFF versus COFF and ROFF values. It can be approximately
calculated from the equations:

tRCFALL = 0.6 ⋅ ROFF ⋅ COFF (1)

tOFF = tRCFALL + tDT = 0.6 ⋅ ROFF ⋅ COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated deadtime with:

20kΩ ≤ ROFF ≤ 100 kΩ (2)

0.47 nF ≤ COFF ≤ 100 nF
tDT = 1μs tipical value

Therefore:
tOFF MIN = 6.6 μs (3)
tOFF MAX = 6 ms

These values allow a sufficient range of tOFF to implement the drive circuit for most motors.
The capacitor value chosen for COFF also affects the rise time tRCRISE of the voltage at the pin RCOFF. The rise
time tRCRISE will only be an issue if the capacitor is not completely charged before the next time the monostable
is triggered. Therefore, the on time tON, which depends by motors and supply parameters, has to be bigger than
tRCRISE for allowing a good current regulation by the PWM stage. Furthermore, the on time tON cannot be smaller
than the minimum on time tON(MIN).

tON > tON MIN = 2.5μs typ.value

(4)
tON > tRCRISE − tDT
tRCRISE = 600 ⋅ COFF

DS3275 - Rev 7 page 14/34

 L6229
PWM current control

Figure 12 shows the lower limit for the on time tON for having a good PWM current regulation capacity. It has to be
said that tON is always bigger than tON(MIN) because the device imposes this condition, but it can be smaller than
tRCRISE - tDT. In this last case the device continues to work but the off time tOFF is not more constant.
So, small COFF value gives more flexibility for the applications (allows smaller on time and, therefore, higher
switching frequency), but, the smaller is the value for COFF, the more influential will be the noises on the circuit
performance.

Figure 11. tOFF versus COFF and ROFF

4
1 .10

R OFF = 10

3
1 .10
R OFF = 47

R OFF = 20 k

10 0

10

1
0.1 1 10 10 0
C OFF [nF]

Figure 12. Area where tON can vary maintaining the PWM regulation

100

10

1.5

1
0. 1 1 10 10 0
C OFF [nF]

DS3275 - Rev 7 page 15/34

 L6229
Slow decay mode

9 Slow decay mode

Figure 13 shows the operation of the bridge in the slow decay mode during the off time. At any time only two legs
of the 3-phase bridge are active, therefore only the two active legs of the bridge are shown in Figure 13 and the
third leg will be off.
At the start of the off time, the lower power MOS is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After the deadtime the
upper power MOS is operated in the synchronous rectification mode reducing the impedance of the freewheeling
diode and the related conducting losses. When the monostable times out, upper MOS that was operating the
synchronous mode turns off and the lower power MOS is turned on again after some delay set by the deadtime to
prevent cross conduction.

Figure 13. Slow decay mode output stage configurations

A) ON TIME C) SYNCHRONOUS
RECTIFICATION

DS3275 - Rev 7 page 16/34

 L6229
Decoding logic

10 Decoding logic

The decoding logic section is a combinatory logic that provides the appropriate driving of the 3-phase bridge
outputs according to the signals coming from the three Hall effetct sensors that detect rotor position in a 3-phase
BLDC motor.
This novel combinatory logic discriminates between the actual sensors position for sensors spaced at 60, 120,
240 and 300 electrical degrees. This decoding method allows the implementation of a universal IC without
dedicating pins to select the sensor configuration.
There are eight possible input combinations for three sensor inputs. Six combinations are valid for rotor positions
with 120 electrical degrees sensor phasing (see Figure 14, positions 1, 2, 3a, 4, 5 and 6a) and six combinations
are valid for rotor positions with 60 electrical degrees phasing (see Figure 15, positions 1, 2, 3b, 4, 5 and 6b).
Four of them are in common (1, 2, 4 and 5) whereas there are two combinations used only in 120 electrical
degrees sensor phasing (3a and 6a) and two combinations used only in 60 electrical degrees sensor phasing (3b
and 6b).
The decoder can drive motors with different sensor configuration simply by following Table 7. For any input
configuration (H1, H2 and H3) there is one output configuration (OUT1, OUT2 and OUT3). The output configuration
3a is the same as 3b and analogously output configuration 6a is the same as 6b.
The sequence of the Hall codes for 300 electrical degrees phasing is the reverse of 60 and the sequence of the
Hall codes for 240 phasing is the reverse of 120. So, by decoding the 60 and the 120 codes it is possible to drive
the motor with all the four conventions by changing the direction set.

Table 7. 60 and 120 electrical degree decoding logic in forward direction

Hall 120° 1 2 3a - 4 5 6a -

Hall 60° 1 2 - 3b 4 5 - 6b

H1 H H L H L L H L

H2 L H H H H L L L

H3 L L L H H H H L

OUT1 Vs High Z GND GND GND High Z Vs Vs

OUT2 High Z Vs Vs Vs High Z GND GND GND

OUT3 GND GND High Z High Z Vs Vs High Z High Z

Phasing 1⇒3 2⇒3 2⇒1 2⇒1 3⇒1 3⇒2 1⇒2 1⇒2

DS3275 - Rev 7 page 17/34

 L6229
Decoding logic

Figure 14. 120° Hall sensor sequence

H1 H1 H1 H1 H1 H1

H3 H2 H3 H2 H3 H2 H3 H2 H3 H2 H3 H2

1 2 3a 4 5 6a
=H =L

Figure 15. 60° Hall sensor sequence

H1 H1 H1 H1 H1 H1

H2 H2 H2 H2 H2 H2
H3 H3 H3 H3 H3 H3

1 2 3b 4 5 6b
=H =L

DS3275 - Rev 7 page 18/34

 L6229
Tachometer

11 Tachometer

A tachometer function consists of a monostable, with constant off time (tPULSE), whose input is one Hall effect
signal (H1). It allows developing an easy speed control loop by using an external op amp, as shown in Figure 16.
For component values refer to Section 13 Application information.
The monostable output drives an open drain output pin (TACHO). At each rising edge of the Hall effect sensors
H1, the monostable is triggered and the MOSFET connected to pin TACHO is turned off for a constant time tPULSE
(see Figure 17). The off time tPULSE can be set using the external RC network (RPUL, CPUL) connected to the pin
RCPULSE.
Figure 18 gives the relation between tPULSE and CPUL, RPUL. We have approximately:

tPULSE = 0.6 ⋅ RPUL ⋅ CPUL (5)

where CPUL should be chosen in the range from 1 nF to 100 nF and RPUL in the range from 20 kΩ to 100 kΩ.
By connecting the tachometer pin to an external pull-up resistor, the output signal average value VM is
proportional to the frequency of the Hall effect signal and, therefore, to the motor speed. This realizes a simple
frequency-to-voltage converter. An op amp, configured as an integrator, filters the signal and compares it with a
reference voltage VREF, which sets the speed of the motor.

t
VM = PULSE ⋅ VDD (6)
T

Figure 16. TACHO operation waveforms

H1

H2

H3

VTACHO
VDD
VM
t PULSE

DS3275 - Rev 7 page 19/34

 L6229
Tachometer

Figure 17. Tachometer speed control loop

H1

RCP ULSE
TACHO
MONOST ABLE

VDD
R PU L C PU L

R DD
R3 TACHO

C1

R4
R1 VREF
VRE F

C RE F2 R2 C RE F1

Figure 18. tPULSE versus CPUL and RPUL

4
1 .10

R PU L = 10

R PU L = 47
3
1 .10

R PU L = 20
tPULSE

10 0

10
1 1 0 1 00
C PUL [nF]

DS3275 - Rev 7 page 20/34

 L6229
Non-dissipative overcurrent detection and protection

12 Non-dissipative overcurrent detection and protection

The L6229 device integrates an “Overcurrent Detection” circuit (OCD) for full protection.
This circuit provides output to output and output to ground short-circuit protection as well.
With this internal overcurrent detection, the external current sense resistor normally used and its associated
power dissipation are eliminated. Figure 19 shows a simplified schematic for the overcurrent detection circuit.
To implement the overcurrent detection, a sensing element that delivers a small but precise fraction of the output
current is implemented with each high-side power MOS. Since this current is a small fraction of the output current
there is very little additional power dissipation. This current is compared with an internal reference current IREF.
When the output current reaches the detection threshold (typically ISOVER = 2.8 A) the OCD comparator signals a
fault condition. When a fault condition is detected, an internal open drain MOS with a pull down capability of 4 mA
connected to pin DIAG is turned on.
The pin DIAG can be used to signal the fault condition to a microcontroller or to shut down the 3-phase bridge
simply by connecting it to pin EN and adding an external R-C (see REN, CEN).

Figure 19. Overcurrent protection simplified schematic

OUT 1 VS A OUT 2 OUT 3 VS B

HIGH-SIDE DMOS HIGH-SIDE DMOS HIGH-SIDE DMOS

I1 I2 I3

POWER SENSE POWER SENSE POWER SENSE

1 cell POWER DMOS POWER DMOS 1 cell POWER DMOS 1 cell
TO GATE n cells n cells n cells
LOGIC +
VDD
I1 / n I2 / n
OCD
R EN EN COMPARATOR
I1 +I2 / n
C EN
INTERNAL IREF
DIAG OPEN DRAIN

OVERTEMPERATURE

I3 / n
IREF

Figure 20 shows the overcurrent detection operation. The disable time tDISABLE before recovering normal
operation can be easily programmed by means of the accurate thresholds of the logic inputs. It is affected
whether by CEN and REN values and its magnitude is reported in Figure 21. The delay time tDELAY before turning
off the bridge when an overcurrent has been detected depends only by CEN value. Its magnitude is reported in
Figure 22.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore the value of CEN should
be chosen as big as possible according to the maximum tolerable delay time and the REN value should be chosen
according to the desired disable time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN
are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs disable time.

DS3275 - Rev 7 page 21/34

 L6229
Non-dissipative overcurrent detection and protection

Figure 20. Overcurrent protection waveforms

IOUT

IS OVER

ON
BRIDGE
OFF

VDIAG

90%

10%

tOCD(ON) tOCD(OFF)

Figure 21. tDISABLE versus CEN and REN

R E N = 2 2 0 kkΩ R EN = 100 k
3
1 .1 0 R E N = 4 7 kΩ
k
R EN = 33 k

R EN = 10 k

1 00
t DISABLE

10

1
1 1 0 1 00

C E N [n F ]

DS3275 - Rev 7 page 22/34

 L6229
Non-dissipative overcurrent detection and protection

Figure 22. tDELAY versus CEN

10

1
tDELAY

0.1
00

C EN [nF]

DS3275 - Rev 7 page 23/34

 L6229
Application information

13 Application information

A typical application using the L6229 device is shown in Figure 23. Typical component values for the application
are shown in Table 8. A high quality ceramic capacitor (C2) in the range of 100 nF to 200 nF should be
placed between the power pins VSA and VSB and ground near the L6229 device to improve the high frequency
filtering on the power supply and reduce high frequency transients generated by the switching. The capacitor
(CEN) connected from the EN input to ground sets the shutdown time when an overcurrent is detected (see
Section 12 Non-dissipative overcurrent detection and protection). The two current sensing inputs (SENSEA and
SENSEB) should be connected to the sensing resistor RSENSE with a trace length as short as possible in the
layout. The sense resistor should be non-inductive resistor to minimize the di/dt transients across the resistor. To
increase noise immunity, unused logic pins are best connected to 5 V (high logic level) or GND (low logic level)
see Table 4. It is recommended to keep power ground and signal ground separated on PCB.

Table 8. Component values for typical application

Component Value

C1 100 µF

C2 100 nF

C3 220 nF

CBOOT 220 nF

COFF 1 nF

CPUL 10 nF

CREF1 33 nF

CREF2 100 nF

CEN 5.6 nF

CP 10 nF

D1 1N4148

D2 1N4148

R1 5.6 kΩ

R2 1.8 kΩ

R3 4.7 kΩ

R4 1 MΩ

RDD 1 kΩ

REN 100 kΩ

RP 100 Ω

RSENSE 0.6 Ω

ROFF 33 kΩ

RPUL 47 kΩ

RH1, RH2, RH3 10 Ω

DS3275 - Rev 7 page 24/34

 L6229
Output current capability and IC power dissipation

Figure 23. Typical application

VS A VREF R1 + VREF
+ 20 13
VS - C REF2
C1 C2 VS B C REF1 R2
8 - 52 V DC 17 C3
POWER D1 CP
GROUND RP VCP
- 22
DIAG
D2 2 R4
C BOOT
VBOOT EN R EN
SIGNAL 15 12 ENABLE
GROUND R SENSE C EN
SENSE A R3
3
SENSE B 11 FWD/REV
3-PHASE MOTOR 10 FWD/REV
OUT 1 14 BRAKE
5 BRAKE
HALL OUT 2
M 21
SENSOR OUT 3 8
+5 V 16 TACHO
C OFF R DD
R H1 H1
1
R H2 H2 5V
23 4 RCOFF R OFF
R H3 H3
24 C PUL
18
19 RCPULSE
6 9
7 R PUL
GND

13.1 Output current capability and IC power dissipation

In Figure 24 is shown the approximate relation between the output current and the IC power dissipation using
PWM current control.
For a given output current the power dissipated by the IC can be easily evaluated, in order to establish which
package should be used and how large must be the on-board copper dissipating area to guarantee a safe
operating junction temperature (125 °C maximum).

Figure 24. IC power dissipation versus output power

I1
10 IOUT

8 I2 IOUT
P D [W]
6
I3 IOUT
4

2
Tes t c on dition s:
S upp ly voltage = 24 V
0
0 0.25 0.5 0.75 1 1.25 1.5
No P WM
IOUT [A] fS W = 30 kHz (s low de cay)

DS3275 - Rev 7 page 25/34

 L6229
Thermal management

13.2 Thermal management

In most applications the power dissipation in the IC is the main factor that sets the maximum current that can
be delivered by the device in a safe operating condition. Selecting the appropriate package and heatsinking
configuration for the application is required to maintain the IC within the allowed operating temperature range for
the application.
Figure 25 and Figure 26 show the junction to ambient thermal resistance values for the PowerSO36 and SO24
packages.
For instance, using a PowerSO package with a copper slug soldered on a 1.5 mm copper thickness FR4 board
with a 6 cm2 dissipating footprint (copper thickness of 35 μm), the Rth(j-amb) is about 35 °C/W. Figure 26 shows
mounting methods for this package. Using a multilayer board with vias to a ground plane, thermal impedance can
be reduced down to 15 °C/W.

Figure 25. PowerSO36 junction ambient thermal resistance versus on-board copper area

º C/ W
43

38

33
Without ground layer

28 With ground layer

With ground layer

23 + 16 via holes

On-board copper area

18

13
1 2 3 4 5 6 7 8 9 10 11 12 13
s q . cm

Figure 26. SO24 junction ambient thermal resistance versus on-board copper area

º C/ W
68 On-board copper area
66

64

62

60 Copper area is
on top side
58

56

54

52

50

48
1 2 3 4 5 6 7 8 9 10 11 12

s q . cm

Figure 27. Mounting the PowerSO package

Slug soldered Slug soldered Slug soldered to PCB with

to PCB with to PCB with dissipating area plus ground layer
dissipating area dissipating area contacted through via holes
plus ground layer

DS3275 - Rev 7 page 26/34

 L6229
Package information

14 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,
depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product
status are available at: www.st.com. ECOPACK is an ST trademark.

14.1 PowerSO36 package information

Figure 28. PowerSO36 package outline

N N

a2 A
c

A e a1
DETAIL B
DETAIL A E
e3

H DETAIL A
lead

a3 slug

36 19 BOTTOM VIEW

E3
B

E1
E2
D1
DETAIL B

0.35
Gage Plane
1 1 8 -C -

S SEATING PLANE
L
G C
h x 45 û b ⊕ 0.12 M AB
(COPLANARITY)

DS3275 - Rev 7 page 27/34

 L6229
PowerSO36 package information

Table 9. PowerSO36 package mechanical data

Dimensions

Symbol mm inch

Min. Typ. Max. Min. Typ. Max.

A - - 3.60 - - 0.141
a1 0.10 - 0.30 0.004 - 0.012
a2 - - 3.30 - 0.130
a3 0 - 0.10 0 - 0.004
b 0.22 - 0.38 0.008 - 0.015
c 0.23 - 0.32 0.009 - 0.012

D (1) 15.80 - 16.00 0.622 - 0.630

D1 9.40 - 9.80 0.370 - 0.385

E 13.90 - 14.50 0.547 - 0.570
e - 0.65 - - 0.0256 -
e3 - 11.05 - - 0.435 -

E1 (1) 10.90 - 11.10 0.429 - 0.437

E2 - - 2.90 - 0.114
E3 5.80 - 6.20 0.228 - 0.244
E4 2.90 - 3.20 0.114 - 0.126
G 0 - 0.10 0 - 0.004
H 15.50 - 15.90 0.610 - 0.626
h - - 1.10 - 0.043
L 0.80 - 1.10 0.031 - 0.043
N 10° (max.)
S 8° (max.)

1. “D” and “E1” do not include mold flash or protrusions.

• - Mold flash or protrusions shall not exceed 0.15 mm (0.006 inch)
• - Critical dimensions are “a3”, “E” and “G”.

DS3275 - Rev 7 page 28/34

 L6229
SO24 package information

14.2 SO24 package information

Figure 29. SO24 package outline

Table 10. SO24 package mechanical data

Dimensions (mm) Dimensions (inch)

Symbol
Min. Typ. Max. Min. Typ. Max.

A 2.35 - 2.65 0.093 - 0.104

A1 0.10 - 0.30 0.004 - 0.012
B 0.33 - 0.51 0.013 - 0.020
C 0.23 - 0.32 0.009 - 0.013

D (1) 15.20 - 15.60 0.598 - 0.614

E 7.40 - 7.60 0.291 - 0.299

e - 1.27 - - 0.050 -
H 10.0 - 10.65 0.394 - 0.419
h 0.25 - 0.75 0.010 - 0.030
L 0.40 - 1.27 0.016 - 0.050
k 0°(min.), 8° (max.)
ddd - - 0.10 - - 0.004

1. “D” dimension does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15 mm per side.

DS3275 - Rev 7 page 29/34

 L6229

Revision hystory

Date Revision Changes

1-Sep-2003 1 First issue

1-Jan-2004 2 Migration from ST-Press dms to EDOCS
1-Oct-2004 3 Updated the style graphic form
Updated Section :Features on page 1 (removed section number from: Features, minor modifications).
Updated Section : Description on page 1 (removed section number from:Description, removed
“MultiPower-” from “MultiPower-BCD technology”). Added Contents on page 2.
Updated Section 1: Blockdiagramonpage 3(added section title, renumbered
Figure1:Block diagram ).
Added title to Section 2:Maximum ratingson page 4.
Added title to Section 3: Pin connections on page 6, renumbered Figure 2: Pin connections (top
view), renumbered note 1below Figure 2.
Added title to Section 4:Electricalcharacteristics onpage 8, renumbered notes 1
to4below Table 6, renumbered Figure 3and Figure 4.
Renumbered Section 5:Circuitdescription onpage 11, Section 5.1 and
Section5.2. Removed “and mC” fromfirst sentence in Section 5.2. Added header to
Table7.Renumbered Figure 5 to Figure 8.
Renumbered Section6:PWMcurrentcontrolonpage 13. Renumbered Figure9to
6-Mar-2014 4 Figure12. Numbered Equation 1 to Equation 4.
Renumbered Section 7:Slowdecaymode on page 17and Figure 13. Renumbered Section 8:Decoding
logicon page 18, Figure14and Figure 15. Renumbered and renamed Section 9: Tachometer on page
20, renumbered
Figure16to Figure 18. Numbered Equation 5 and Equation 6.
Renumbered Section 10:Non-dissipativeovercurrent detectionand protection on page 22, Figure 19to
Figure22.
Renumbered Section 11:Applicationinformation on page 25,Section 11.1 and Section 11.2. Added
header to Table 9. Renumbered Figure 23 to Figure 28. Updated Section 12: Package information on
page 29 (added main title and
ECOPACK text. Added titles from Table 10: PowerSO36 package mechanical data
toTable 12: SO24 package mechanical data and from Figure 29: PowerSO36 package outline to
Figure 31: SO24 package outline, reversed order of named tables and figures. Removed 3D figures
of packages. Replaced 0.200 by0.020 inch of max. B value in Table 12).
Added cross-references throughout document.
Added section number and title to Section13:Revisionhistory. Minor modifications throughout
document
Removed PowerDIP24 package from the whole document. Removed “Tj“ from Table 3
4-Oct-2018 5
Minor modifications throughout document
Added Application section in cover page.
4-Nov-2021 6 Updated order codes, see Product status link / summary in cover page
Updated VS Min. value in Table 2

1-Apr-2022 7 Updated Cover image

DS3275 - Rev 7 page 30/34

 L6229
Contents

Contents
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3 Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
4 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
5 Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
6 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
7.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
7.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

8 PWM current control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13

9 Slow decay mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
10 Decoding logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
11 Tachometer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
12 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
13 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
13.1 Output current capability and IC power dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.2 Thermal management. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

14 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

14.1 PowerSO36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
14.2 SO24 package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
List of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
List of figures. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33

DS3275 - Rev 7 page 31/34

 L6229
List of tables

List of tables
Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Table 2. Recommended operating condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Charge pump external component values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 7. 60 and 120 electrical degree decoding logic in forward direction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 8. Component values for typical application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. PowerSO36 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 10. SO24 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

DS3275 - Rev 7 page 32/34

 L6229
List of figures

List of figures
Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. Pin connections (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Switching characteristic definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 4. Overcurrent detection timing definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 5. Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure 6. Logic input internal structure. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7. Pin EN open collector driving . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 8. Pin EN push-pull driving. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 9. PWM current controller simplified schematic. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 10. Output current regulation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 11. tOFF versus COFF and ROFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 12. Area where tON can vary maintaining the PWM regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 13. Slow decay mode output stage configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 14. 120° Hall sensor sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. 60° Hall sensor sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. TACHO operation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 17. Tachometer speed control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18. tPULSE versus CPUL and RPUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 19. Overcurrent protection simplified schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Overcurrent protection waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21. tDISABLE versus CEN and REN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22. tDELAY versus CEN. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23. Typical application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 24. IC power dissipation versus output power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 25. PowerSO36 junction ambient thermal resistance versus on-board copper area . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 26. SO24 junction ambient thermal resistance versus on-board copper area . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 27. Mounting the PowerSO package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 28. PowerSO36 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 29. SO24 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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 L6229

IMPORTANT NOTICE – READ CAREFULLY

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