CO Previous Year O.U
CO Previous Year O.U
CO Previous Year O.U
15083/AICTE
FACULTY OF ENGINEERING
B.E. IV Semester (AICTE) (Main & Backlog) Examination, October 2021
Subject: Computer Organization
Max. Marks: 75
Time: 2 hours
Note: Missing data, if any, may be suitably assumed.
PART-A
(5x3 = 15 Marks)
Answer any five questions.
tf)4_RT-B
Answer any four questions. \ , ~ (4x15 = 60 Marks)
11 (a) what do you unders6~~Je term" Addressing Modes"? Explain any six
addressing mod~wt,~ amples.
~b) Write an Assembfy1~guage program to evaluate (w+x+y)-(u/v) using
three,two,one,and zero address instructions.
,l•
12(a) Explain~ block diagram how CPU and IOP communicate with each other.
/ (b) Ex_pla~ 9 "ree different modes of data transfer.
15 Explain Data transfer and Arithmetic instructions of 8086 in detail with examples.
/16(a) Explain Asynchronous data transfer with neat block and timing diagrams.
·(b) Explain types of interrupts in detail. Draw interrupts cycle.
FACULTY OF ENGINEERING
B.E. IV-Semester (CBCS) (CSE) (Suppl.) Examination, Dec. 2018/ January 2019
Subject: Computer Organization
Note: Answer all questions from Part-A and Any five questions from Part-B.
9 What is CAM? 2
10 Differentiate between RISC and CISC. 2
15 a) Explain how the communication takes place between CPU and IOP. 6
b) Draw the block diagram of RAM chip and explain with the help of function table. 4
17 Explain in detail different kinds of asynchronous data transfer methods with the
help of block and timing diagrams. 10
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Code No. 11459 /
CBCS
FACULTY OF ENGINEERING
B.E. (CSE) IV – Semester (CBCS)(Main & Backlog) Examination, May / June 2019
T1: BB̄
T2: AA+B
6 What is meant by Pipelining? 2
7 Define virtual memory. 2
8 What is meant by basic computer instruction format? 2
14 a) Discuss in detail about Read and write operation with timing diagram. 5
b) Explain the concept of Array Processor. 5
16 a) What is cache memory, explain a mechanism of data transfer between cache and
main memory. 6