VN5050AJ-E

Single channel high side driver with analog

current sense for automotive applications

Features
Max supply voltage VCC 41 V
Operating voltage range VCC 4.5 to 36V PowerSSO-12
Max On-State resistance RON 50 mΩ
– Reverse battery protection ( see
Current limitation (typ) ILIMH 16.5 A Application schematic )
Off state supply current IS 2 µA – Electrostatic discharge protection

■ General features Application

– Inrush current active management by
power limitation ■ All types of resistive, inductive and capacitive
loads
– Very low stand-by current
– 3.0V CMOS compatible input ■ Suitable as LED driver
– Optimized electromagnetic emission
Description
– Very low electromagnetic susceptibility
– In compliance with the 2002/95/EC The VN5050AJ-E is a monolithic device made
European directive using STMicroelectronics VIPower technology. It
is intended for driving resistive or inductive loads
■ Diagnostic functions
with one side connected to ground. Active VCC
– Proportional load current sense
pin voltage clamp protects the device against low
– High current sense precision for wide range energy spikes (see ISO7637 transient
currents compatibility table).
– Current sense disable This device integrates an analog current sense
– Thermal shutdown indication which delivers a current proportional to the load
– Very low current sense leakage current (according to a known ratio) when
CS_DIS is driven low or left open.
■ Protection
When CS_DIS is driven high, the CURRENT
– Undervoltage shut-down SENSE pin is in a high impedance condition.
– Overvoltage clamp Output current limitation protects the device in
– Load current limitation overload condition. In case of long overload
– Self limiting of fast thermal transients duration, the device limits the dissipated power to
safe level up to thermal shut-down intervention.
– Protection against loss of ground and loss
Thermal shut-down with automatic restart allows
of VCC
the device to recover normal operation as soon as
– Thermal shut down
fault condition disappears.

Table 1. Device summary

Order codes
Package
Tube Tape and Reel
PowerSSO-12 VN5050AJ-E VN5050AJTR-E

September 2013 Rev 7 1/31

www.st.com 31

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 Contents VN5050AJ-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 21
3.1.1 Solution 1: resistor in the ground line (RGND only) . . . . . . . . . . . . . . . . 21
3.1.2 Solution 2: diode (DGND) in the ground line . . . . . . . . . . . . . . . . . . . . . . 22
3.2 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 23

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

4.1 PowerSSO-12™ thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.1 ECOPACK® packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.2 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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 VN5050AJ-E List of tables

List of tables

Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Table 2. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 3. Suggested connections for unused and N.C. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 5. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Switching (VCC=13V, Tj=25°C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 8. Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 9. Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 10. Current sense (8V<VCC<16V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. Electrical transient requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 13. Thermal parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Table 14. PowerSSO-12™ mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 15. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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 List of figures VN5050AJ-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 5. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Delay response time between rising edge of ouput current and rising edge of current sense
(CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8. IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 20. Turn-On voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 21. ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 22. Turn-Off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 27. Maximum turn Off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 28. PowerSSO-12™ PC Board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 24
Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . 25
Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ . . . . . . . . . . . . . . . . . 25
Figure 32. PowerSSO-12™ package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 33. PowerSSO-12™ tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

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 VN5050AJ-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram

VCC

VCC
CLAMP UNDERVOLTAGE

PwCLAMP
DRIVER
OUTPUT
GND ILIM

LOGIC VDSLIM
PwrLIM
INPUT
OVERTEMP.
IOUT
K CURRENT
SENSE
CS_DIS

Table 2. Pin function

Name Function

VCC Battery connection.

OUTPUT Power output.

Ground connection. Must be reverse battery protected by an external

GND
diode/resistor network.
Voltage controlled input pin with hysteresis, CMOS compatible. Controls output
INPUT
switch state.

CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current.

CS_DIS Active high CMOS compatible pin, to disable the current sense pin.

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 Block diagram and pin description VN5050AJ-E

Figure 2. Configuration diagram (top view)

TAB = Vcc

N.C. 12 N.C.
1
GND 2 11 OUTPUT
INPUT 3 10 OUTPUT
CURRENT SENSE 4 9 OUTPUT
CS_DIS 5 8 OUTPUT
N.C. 6 7
N.C.

Note: The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The
new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are
connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,
these pins should be left unconnected.

Table 3. Suggested connections for unused and N.C. pins

Connection / Pin Current Sense N.C. Output Input CS_DIS

Floating N.R. X X X X
Through 10kΩ Through
To ground Through 1kΩ resistor X N.R.(1)
resistor 10kΩ resistor
1. Not recommended.

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 VN5050AJ-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions

IS
VCC
VF

ICSD IOUT
CS_DIS OUTPUT
VCC
IIN
INPUT ISENSE
VOUT
VCSD CURRENT SENSE
VIN GND VSENSE

IGND

Note: VF = VOUT - VCC during reverse battery condition.

2.1 Absolute maximum ratings

Stressing the device above the rating listed in the “Absolute maximum ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to the conditions in table below for extended
periods may affect device reliability. Refer also to the STMicroelectronics SURE Program
and other relevant quality document.

Table 4. Absolute maximum ratings

Symbol Parameter Value Unit
VCC DC supply voltage 41 V
-VCC Reverse DC supply voltage 0.3 V
- IGND DC reverse ground pin current 200 mA
Internally
IOUT DC output current A
limited
- IOUT Reverse DC output current 30 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
-ICSENSE DC reverse CS pin current 200 mA
VCC-41 V
VCSENSE Current sense maximum voltage
+VCC V
Maximum switching energy (single pulse)
EMAX 104 mJ
(L= 3mH; RL=0Ω; Vbat=13.5V; Tjstart=150ºC; IOUT = IlimL(Typ.) )

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 Electrical specifications VN5050AJ-E

Table 4. Absolute maximum ratings (continued)

Symbol Parameter Value Unit
Electrostatic discharge (Human Body Model: R=1.5kΩ; C=100pF)
- INPUT 4000 V
- CURRENT SENSE 2000 V
VESD
- CS_DIS 4000 V
- OUTPUT 5000 V
- VCC 5000 V
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C

2.2 Thermal data

Table 5. Thermal data
Symbol Parameter Max value Unit

Rthj-case Thermal resistance junction-case (MAX) 2.7 °C/W

Rthj-amb Thermal resistance junction-ambient (MAX) See Figure 29. °C/W

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 VN5050AJ-E Electrical specifications

2.3 Electrical characteristics

Values specified in this section are for 8V < VCC < 36V; -40°C < Tj < 150°C, unless
otherwise specified.

Table 6. Power section

Symbol Parameter Test conditions Min. Typ. Max. Unit

Operating supply
VCC 4.5 13 36 V
voltage
Undervoltage
VUSD 3.5 4.5 V
shutdown
Undervoltage
VUSDhyst 0.5 V
shutdown hysteresis
IOUT= 2A; Tj=25°C 50 mΩ
RON On state resistance IOUT= 2A; Tj=150°C 100 mΩ
IOUT= 2A; VCC=5V; Tj=25°C 65 mΩ
Vclamp Clamp voltage IS= 20mA 41 46 52 V

Off State; VCC=13V; Tj=25°C;

IS Supply current VIN=VOUT=VSENSE=VCSD=0V 2(1) 5(1) µA
On State; VCC=13V; VIN=5V; IOUT=0A 1.5 3 mA
VIN=VOUT=0V; VCC=13V; Tj=25°C 0 0.01 3
IL(off) Off state output current µA
VIN=VOUT=0V; VCC=13V; Tj=125°C 0 5
Output - VCC diode
VF -IOUT= 2A; Tj= 150°C 0.7 V
voltage
1. PowerMOS leakage included.

Table 7. Switching (VCC=13V, Tj=25°C)

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL= 6.5Ω (see Figure 7.) 20 µs

td(off) Turn-off delay time RL= 6.5Ω (see Figure 7.) 40 µs
See
(dVOUT/dt)on Turn-on voltage slope RL= 6.5Ω V/µs
Figure 20
See
(dVOUT/dt)off Turn-off voltage slope RL= 6.5Ω V/µs
Figure 22
Switching energy losses
WON RL= 6.5Ω (see Figure 7.) 0.20 mJ
during twon
Switching energy losses
WOFF RL= 6.5Ω (see Figure 7.) 0.3 mJ
during twoff

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 Electrical specifications VN5050AJ-E

Table 8. Logic input

Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Input low level voltage 0.9 V

IIL Low level input current VIN= 0.9V 1 µA
VIH Input high level voltage 2.1 V
IIH High level input current VIN= 2.1V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
IIN= 1mA 5.5 7 V
VICL Input clamp voltage
IIN= -1mA -0.7 V
VCSDL CS_DIS low level voltage 0.9 V
ICSDL Low level CS_DIS current VCSD= 0.9V 1 µA
VCSDH CS_DIS high level voltage 2.1 V
ICSDH High level CS_DIS current VCSD= 2.1V 10 µA
VCSD(hyst) CS_DIS hysteresis voltage 0.25 V
ICSD= 1mA 5.5 7 V
VCSCL CS_DIS clamp voltage
ICSD= -1mA -0.7 V

Table 9. Protection and diagnostics(1)

Symbol Parameter Test conditions Min. Typ. Max. Unit

DC Short circuit VCC = 13V 12 16.5 23 A

IlimH
current 5V<VCC<36V 23 A
Short circuit current
IlimL VCC=13V TR<Tj<TTSD 7 A
during thermal cycling
Shutdown
TTSD 150 175 200 °C
temperature
TR Reset temperature TRS + 1 TRS + 5 °C
Thermal reset of
TRS 135 °C
STATUS
Thermal hysteresis
THYST 7 °C
(TTSD-TR)
Turn-off output voltage
VDEMAG IOUT= 2A; VIN= 0; L= 6mH VCC-41 VCC-46 VCC-52 V
clamp
IOUT= 0.1A;
Output voltage drop
VON Tj= -40°C...+150°C 25 mV
limitation
(see Figure 5.)
1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device operates under
abnormal conditions this software must limit the duration and number of activation cycles.

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Table 10. Current sense (8V<VCC<16V)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT= 0.05A; VSENSE=0.5V; VCSD=0V;

K0 IOUT/ISENSE 1100 2440 3480
Tj= -40°C...150°C
IOUT=1A; VSENSE=0.5V; VCSD=0V;
1600 2030 2580
Tj= -40°C...150°C
K1 IOUT/ISENSE
IOUT= 1A; VSENSE= 0.5V; VCSD= 0V;
1630 2030 2430
Tj= 25°C...150°C
IOUT=1A; VSENSE= 0.5V;
(1) Current sense ratio
dK1/K1 VCSD=0V; -10 +10 %
drift
TJ=-40 °C to 150 °C
IOUT= 2A; VSENSE= 4V; VCSD= 0V;
1770 2000 2310
Tj= -40°C...150°C
K2 IOUT/ISENSE
IOUT= 2A; VSENSE= 4V; VCSD= 0V;
1800 2000 2200
Tj= 25°C...150°C
IOUT= 2 A; VSENSE= 4 V;
Current sense ratio
dK2/K2(1) VCSD= 0V; -6 +6 %
drift
TJ= -40 °C to 150 °C
IOUT= 4A; VSENSE= 4V; VCSD= 0V;
1860 1970 2140
Tj= -40°C...150°C
K3 IOUT/ISENSE
IOUT= 4A; VSENSE= 4V; VCSD= 0V;
1870 1970 2120
Tj= 25°C...150°C
IOUT= 4 A; VSENSE= 4 V;
Current sense ratio
dK3/K3(1) VCSD=0V; -3 +3 %
drift
TJ=-40 °C to 150 °C
IOUT= 0A; VSENSE=0V;
VCSD= 5V; VIN=0V; Tj= -40°C...150°C 0 1 µA
Analog sense VCSD= 0V; VIN=5V; Tj= -40°C...150°C 0 2 µA
ISENSE0
leakage current
IOUT= 2A; VSENSE= 0V;
VCSD= 5V; VIN=5V; Tj= -40°C...150°C 0 1 µA
Openload ON state
IOL current detection VIN = 5V, ISENSE= 5 µA 4 20 mA
threshold
Max analog sense
VSENSE IOUT=2A; VCSD=0V 5 V
output voltage
Analog sense
output voltage in
VSENSEH VCC=13V; RSENSE=10KΩ 9 V
overtemperature
condition
Analog sense
output current in
ISENSEH VCC=13V, VSENSE=5V 8 mA
overtemperature
condition

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Table 10. Current sense (8V<VCC<16V) (continued)

Symbol Parameter Test conditions Min. Typ. Max. Unit

Delay response VSENSE<4V, 0.5A<Iout<4A

tDSENSE1H time from falling ISENSE=90% of ISENSEmax 50 100 µs
edge of CS_DIS pin (see Figure 4.)

Delay response VSENSE<4V, 0.5A<Iout<4A

tDSENSE1L time from rising ISENSE=10% of ISENSEmax 5 20 µs
edge of CS_DIS pin (see Figure 4.)

Delay response VSENSE<4V, 0.5A<Iout<4A

tDSENSE2H time from rising ISENSE=90% of ISENSE max 80 250 µs
edge of INPUT pin (see Figure 4.)
Delay response
time between rising VSENSE < 4V,
edge of output ISENSE = 90% of ISENSEMAX, µ
ΔtDSENSE2H 65
current and rising IOUT = 90% of IOUTMAX s
edge of current IOUTMAX=2A (see Figure 6)
sense
Delay response VSENSE<4V, 0.5A<Iout<4A
tDSENSE2L time from falling ISENSE=10% of ISENSE max 100 250 µs
edge of INPUT pin (see Figure 4.)
1. Parameter guaranteed by design; it is not tested.

Figure 4. Current sense delay characteristics

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L

Figure 5. Output voltage drop limitation

Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

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Figure 6. Delay response time between rising edge of ouput current and rising
edge of current sense (CS enabled)

VIN

ΔtDSENSE2H

IOUT
IOUTMAX

90% IOUTMAX

ISENSE ISENSEMAX

90% ISENSEMAX

Figure 7. Switching characteristics

VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf
t

INPUT
td(on) td(off)

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Figure 8. IOUT/ISENSE Vs. IOUT (see Table 10. for details)

Iout / Isense
2800

2600
max Tj = -40 °C to 150 °C

2400

2200
max Tj = 25 °C to 150 °C

2000
typical value

min Tj = 25 °C to 150 °C
1800

1600 min Tj = -40 °C to 150 °C

1400

1200
1 1,5 2 2,5 3 3,5 4 4,5 5

IOUT (A)

Figure 9. Maximum current sense ratio drift vs load current

dk/k(%)

15

10

-5

-10

-15
1 2 3 4
IOUT (A)

Note: Parameter guaranteed by design; it is not tested.

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Table 11. Truth table

Conditions Input Output Sense (VCSD=0V)(1)

L L 0
Normal operation
H H Nominal
L L 0
Overtemperature
H L VSENSEH
L L 0
Undervoltage
H L 0
L L 0
Short circuit to GND
H L 0 if Tj < TTSD
(Rsc ≤ 10 mΩ)
H L VSENSEH if Tj > TTSD
L H 0
Short circuit to VCC
H H < Nominal
Negative output voltage
L L 0
clamp
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.

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 Electrical specifications VN5050AJ-E

Table 12. Electrical transient requirements

ISO 7637-2: Test levels Number of
2004(E) Burst cycle/pulse Delays and
pulses or
repetition time Impedance
Test pulse III IV test times

1 -75V -100V 5000 pulses 0.5 s 5s 2 ms, 10 Ω

2a +37V +50V 5000 pulses 0.2 s 5s 50 μs, 2 Ω

3a -100V -150V 1h 90 ms 100 ms 0.1 μs, 50 Ω

3b +75V +100V 1h 90 ms 100 ms 0.1 μs, 50 Ω

100 ms, 0.01

4 -6V -7V 1 pulse
Ω

5b(2) +65V +87V 1 pulse 400 ms, 2 Ω

ISO 7637-2: Test level results(1)

2004(E)
Test pulse III IV

1 C C

2a C C

3a C C

3b C C

4 C C

5b(2) C C
1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b.
2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Class Contents

C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
E
disturbance and cannot be returned to proper operation without replacing the device.

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Figure 10. Waveforms

NORMAL OPERATION

INPUT
CS_DIS

LOAD CURRENT

SENSE CURRENT

UNDERVOLTAGE

VUSDhyst
VCC
VUSD
INPUT
CS_DIS
LOAD CURRENT

SENSE CURRENT

SHORT TO VCC

INPUT
CS_DIS
LOAD VOLTAGE
LOAD CURRENT
SENSE CURRENT
<Nominal <Nominal

OVERLOAD OPERATION

TR TTSD
Tj
TRS

INPUT
CS_DIS
ILIMH
ILIML
LOAD CURRENT
VSENSEH
SENSE CURRENT

current power thermal cycling

limitation limitation
SHORTED LOAD NORMAL LOAD

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 Electrical specifications VN5050AJ-E

2.4 Electrical characteristics curves

Figure 11. Off state output current Figure 12. High level input current

TBD

Figure 13. Input clamp voltage Figure 14. Input low level

Figure 15. Input high level Figure 16. Input hysteresis voltage

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Figure 17. On state resistance vs. Tcase Figure 18. On state resistance vs. VCC

Figure 19. Undervoltage shutdown Figure 20. Turn-On voltage slope

Figure 21. ILIMH Vs. Tcase Figure 22. Turn-Off voltage slope

TBD

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 Electrical specifications VN5050AJ-E

Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage

Figure 25. CS_DIS low level voltage

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 VN5050AJ-E Application information

3 Application information

Figure 26. Application schematic

+5V

VCC

Rprot CS_DIS

Dld

μC Rprot INPUT
OUTPUT
Rprot
CURRENT SENSE
GND

RSENSE
RGND
VGND DGND
Cext

3.1 GND protection network against reverse battery

This section provides two solutions for implementing a ground protection network against
reverse battery.

3.1.1 Solution 1: resistor in the ground line (RGND only)

This can be used with any type of load.
The following show how to dimension the RGND resistor:
1. RGND ≤ 600mV / (IS(on)max)
2. RGND ≥ (−VCC) / (-IGND)
where -IGND is the DC reverse ground pin current and can be found in the absolute
maximum rating section of the device datasheet.
Power dissipation in RGND (when VCC<0 during reverse battery situations) is:
PD= (-VCC)2/ RGND
This resistor can be shared amongst several different HSDs. Please note that the value of
this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the
maximum on-state currents of the different devices.
Please note that, if the microprocessor ground is not shared by the device ground, then the
RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output
values. This shift will vary depending on how many devices are ON in the case of several
high side drivers sharing the same RGND.

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 Application information VN5050AJ-E

If the calculated power dissipation requires the use of a large resistor, or several devices
have to share the same resistor, then ST suggests using solution 2 below.

3.1.2 Solution 2: diode (DGND) in the ground line

Note that a resistor (RGND=1kΩ) should be inserted in parallel to DGND if the device drives
an inductive load.
This small signal diode can be safely shared amongst several different HSDs. Also in this
case, the presence of the ground network will produce a shift (j600mV) in the input
threshold and in the status output values if the microprocessor ground is not common to the
device ground. This shift will not vary if more than one HSD shares the same diode/resistor
network.

3.2 Load dump protection

Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCC maximum DC rating. The same applies if the device is subject to transients on the VCC
line that are greater than those shown in the ISO T/R 7637/1 table.

3.3 MCU I/O protection

If a ground protection network is used and negative transients are present on the VCC line,
the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to
prevent the µC I/O pins from latching up.
The value of these resistors is a compromise between the leakage current of µC and the
current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of µC
I/Os:
-VCCpeak/Ilatchup ≤ Rprot ≤ (VOHμC-VIH-VGND) / IIHmax

Equation 1:
For the following conditions:
VCCpeak= - 100V
Ilatchup ≥ 20mA
VOHμC ≥ 4.5V
5kΩ ≤ Rprot ≤ 180kΩ.
Recommended values are:
Rprot =10kΩ, CEXT=10nF

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3.4 Maximum demagnetization energy (VCC = 13.5V)

Figure 27. Maximum turn Off current versus inductance

100

A
A
B
C B
C
10
I (A)

1
0,1 1 L (mH) 10 100

A: Tjstart = 150°C single pulse

B: Tjstart = 100°C repetitive pulse
C: Tjstart = 125°C repetitive pulse

VIN, IL

Demagnetization Demagnetization Demagnetization

Note: Values are generated with RL =0 Ω.In case of repetitive pulses, Tjstart (at beginning of each
demagnetization) of every pulse must not exceed the temperature specified above for
curves A and B.

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 Package and PCB thermal data VN5050AJ-E

4 Package and PCB thermal data

4.1 PowerSSO-12™ thermal data

Figure 28. PowerSSO-12™ PC Board

Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4
area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 µm (front and back side),
Copper areas: from minimum pad lay-out to 8cm2).

Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition

RTHj_amb( °C/ W)
65

60

55

50

45

40

35
0 2 4 6 8 10
PCB Cu heatsink area (cm^ 2)

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 VN5050AJ-E Package and PCB thermal data

Figure 30. PowerSSO-12™ thermal impedance junction ambient single pulse

ZTH ( °C/ W)
100 Footprint

2 cm2

8 cm2

10

0,1
0,001 0,01 0,1 1 10 100 1000
Time ( s)

Equation 2: pulse calculation formula

Z = R ⋅δ+Z (1 – δ)
THδ TH THtp
where δ = tP/T

Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12™ (a)

a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

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Table 13. Thermal parameter

Area/island (cm2) Footprint 2 8

R1 (°C/W) 0.7

R2 (°C/W) 2.8

R3 (°C/W) 3

R4 (°C/W) 8 8 7

R5 (°C/W) 22 15 10

R6 (°C/W) 26 20 15

C1 (W.s/°C) 0.001

C2 (W.s/°C) 0.0025

C3 (W.s/°C) 0.0166

C4 (W.s/°C) 0.2 0.1 0.1

C5 (W.s/°C) 0.27 0.8 1

C6 (W.s/°C) 3 6 9

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5 Package information

5.1 ECOPACK® packages

In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second-level interconnect. The category of
Second-Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97.
The maximum ratings related to soldering conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.

5.2 Package mechanical data

Figure 32. PowerSSO-12™ package dimensions

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Table 14. PowerSSO-12™ mechanical data

Millimeters
Symbol
Min. Typ. Max.

A 1.250 1.620

A1 0.000 0.100

A2 1.100 1.650

B 0.230 0.410

C 0.190 0.250

D 4.800 5.000

E 3.800 4.000

e 0.800

H 5.800 6.200

h 0.250 0.500

L 0.400 1.270

k 0° 8°

X 2.200 2.800

Y 2.900 3.500

ddd 0.100

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5.3 Packing information

Figure 33. PowerSSO-12™ tube shipment (no suffix)

B
Base Q.ty 100
C
Bulk Q.ty 2000
Tube length (± 0.5) 532
A 1.85
A
B 6.75
C (± 0.1) 0.6

All dimensions are in mm.

Figure 34. PowerSSO-12™ tape and reel shipment (suffix “TR”)

REEL DIMENSIONS
Base Q.ty 2500
Bulk Q.ty 2500
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 12.4
N (min) 60
T (max) 18.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb. 1986
Tape width W 12
Tape Hole Spacing P0 (± 0.1) 4
Component Spacing P 8
Hole Diameter D (± 0.05) 1.5
Hole Diameter D1 (min) 1.5
Hole Position F (± 0.1) 5.5
Compartment Depth K (max) 4.5
Hole Spacing P1 (± 0.1) 2

All dimensions are in mm.

End

Start

Top No components Components No components

cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

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 Revision history VN5050AJ-E

6 Revision history

Table 15. Document revision history

Date Revision Changes

24-Jan-2006 1 Initial release.

Jul-2006 2 Minor updates.
Document reformatted.
Table 14: PowerSSO-12™ mechanical data, X and Y values (slug
dimensions) updated.
06-Feb-2007 3
Table 10: Current sense (8V<VCC<16V) tDSENSE2H entry updated.
Figure 27: Maximum turn Off current versus inductance and
Table 13: Thermal parameter updated.
Document reformatted and restructured.
Contents and lists of tables and figures added.
Figure 2: Configuration diagram (top view) updated: pins 1-6-7-12
left unconnected (N.C).
Table 4: Absolute maximum ratings: updated EMAX entries.
Table 10 : added dk1/k1, dk2/k2, dk3/k3, ΔtDSENSE2H.
13-Sep-2007 4 Added Figure 6: Delay response time between rising edge of ouput
current and rising edge of current sense (CS enabled).
Updated Figure 8: IOUT/ISENSE Vs. IOUT (see Table 10. for details).
Added Figure 9: Maximum current sense ratio drift vs load current.
Table 12: Electrical transient requirements : updated test level values
III and IV for test pulse 5b and notes.
Corrected Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse.
Figure 2: Configuration diagram (top view): added note.
Updated Table 10: Current sense (8V<VCC<16V) :
– changed tDSENSE2H max value from 300 µs to 250µs.
– added IOL parameter.
Updated Section 4.1: PowerSSO-12™ thermal data:
– changed Figure 29: Rthj-amb Vs. PCB copper area in open box
free air condition.
7-Dec-2007 5
– changed Figure 30: PowerSSO-12™ thermal impedance junction
ambient single pulse.
– updated Table 13: Thermal parameter:
R1 value changed from 0.6 to 0.7 °C/W.
R3 value changed from 6.5 to 3 °C/W
R4 values changed from 10 /10 /9 to 8 /8 /7 °C/W.
C3 value changed from 0.022 to 0.0166 W.s/°C
Corrected typing error in Table 10: Current sense (8V<VCC<16V) :
12-Feb-2008 6
changed IOL test condition from VIN = 0V to VIN = 5V.
23-Sep-2013 7 Updated Disclaimer.

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 VN5050AJ-E

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