1.

GATE CSE 2002

A computer system uses 32-bit virtual address, and 32-bit physical address. The physical
memory is byte addressable, and the page size is 4 kbytes. It is decided to use two level page
tables to translate from virtual address to physical address. Equal number of bits should be
used for indexing first level and second level page table, and the size of each page table entry
is 4 bytes.

(a) Give a diagram showing how a virtual address would be translated to a physical address.

(b) What is the number of page table entries that can be contained in each page?

(c) How many bits are available for storing protection and other information in each page table
entry?

Answer
(b) No of entries in each page =210
(c) 12 bits.

2>GATE CSE 1999

A certain computer system has the segmented paging architecture for virtual memory. The
memory is byte addressable. Both virtual and physical address spaces contain 216 bytes each.
The virtual address space is divided into 8 non-overlapping equal size segments. The memory
management unit (MMU) has a hardware segment table, each entry of which contains the
physical address of the page table for the segment. Page table are stored in the main memory
and consists of 2 byte page table entries.

(a) What is the minimum page size in bytes so that the page table for a segment requires at
most one page to store it? Assume that the page size can only be a power of 2.

(b) Now suppose that the pages size is 512 bytes. It is proposed to provide a TLB (Translation
look-aside buffer) for speeding up address translation. The proposed TLB will be capable of
storing page table entries for 16 recently referenced virtual pages, in a fast cache that will use
the direct mapping scheme. What is the number of tag bits that will need to be associated with
each cache entry

(c) Assume that each page table entry contains (besides other information) 1 valid bit, 3 bits
for page protection and 1 dirty bit. How many bits are available in page table entry for storing
the aging information for the page? Assume that the page size is 512 bytes.

Answer
(a) Page size =128 Bytes
(b) Tag Bits =3
(c) 7 bits
3>GATE CSE 1998
In a computer system where the ‘best-fit’ algorithm is used for allocating ‘jobs’ to ‘memory
partitions’, the following situation was encountered:

When will the 20 K job complete?

Answer
After 19 unit time 20K job will be completed

4>GATE CSE 1996

A demand paged virtual memory system uses 16 bit virtual address, page size of 256 bytes,
and has 1 Kbyte of main memory. LRU page replacement is implemented using a list, whose
current status (page numbers in decimal ) is

↑LRU Page
For each hexa decimal address in the address sequence given below,
00FF, 010D, 10FF, 11B0
Indicate,
i) The new status of the list
ii) Page faults, if any, and
iii) Page replacements, if any

Answer
(ii) Page fault =3
(iii) Page replacement

5>GATE CSE 1995

A computer installation has 1000K of main memory. The jobs arrive and finish in the following
sequence.
Job 1 requiring 200k arrives
Job 2 requiring 350k arrives
Job 3 requiring 300k arrives
Job 1 finishes
Job 4 requiring 120k arrives
Job 5 requiring 150k arrives
Job 6 requiring 80k arrives
(a) Draw the memory allocation table using Best Fit and First fit algorithm.
(b) Which algorithm performs better for this sequence?

Answer
Solve it.

6>GATE CSE 1993

The following page addresses, in the given sequence, were generated by a program:
12341352154323

This program is run on a demand paged virtual memory system, with main memory size equal
to 4 pages. Indicate the page references for which page faults occurs for the following page
replacement algorithms.
(a) LRU
(b) FIFO

Assume that the main memory is empty initially.

Answer
(a) 9 page fault
(b) 7 page fault.

7>GATE CSE 1992

Let the page reference and the working set window be c c d b c e c e a d and 4, respectively. The
initial working set at time t=0 contains the pages {a, d, e}, where a was referenced at
time t=0,d was referenced at time t=−1, and e was referenced at time t=−2. Determine the total
number of page faults and the average number of page frames used by computing the working set
at each reference.

Answer
No of page fault =4
Average page frames used =4

8>GATE CSE 2020

Consider a paging system that uses a 1-level page table residing in main memory and a TLB
for address translation. Each main memory access takes 100 ns and TLB lookup takes 20 ns.
Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page
fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written
back to disk before the required page is read in from disk. TLB update time is negligible. The
average memory access time in ns (round off to 1 decimal places) is ______.

Answer
Correct Answer is 154.5
9>GATE CSE 2019
Assume that in a certain computer, the virtual addresses are 64 bits long and the physical addresses are
48 bits long. The memory is word addressable. The page size is 8 kB and the word size is 4 bytes. The
Translation Look-aside Buffer (TLB) in the address translation path has 128 valid entries. At most how
many distinct virtual addresses can be translated without any TLB miss?
16 × 210

8 × 220
4 × 220

256 × 210(Right)

10>GATE CSE 2018

Consider a process executing on an operating system that uses demand paging. The average
time for a memory access in the system is M units if the corresponding memory page is
available in memory, and D units if the memory access causes a page fault. It has been
experimentally measured that the average time taken for a memory access in the process
is X units.

Which one of the following is the correct expression for the page fault rate experienced by the
process?

Ans:-(X-M)/(D-M)
11>GATE CSE 2016 Set 1
Consider a computer system with 40-bit virtual addressing and page size of sixteen kilobytes.
If the computer system has a one-level page table per process and each page table entry
requires 48 bits, then the size of the per-process page table ____________ is megabytes.

Answer
Correct Answer is 384
12>GATE CSE 2015 Set 2
Consider six memory partitions of
sizes 200 KB, 400 KB, 600 KB, 500 KB, 300 KB and 250 KB, where KB refers to kilobyte. These
partitions need to be allotted to four processes of sizes 357 KB, 210 KB, 468 KB and 491 KB in
that order. If the best fit algorithm is used, which partitions are NOT allotted to any process?

Ans: 200KB and 300KB

13> GATE CSE 2015 Set 2

A computer system implements 8 kilobyte pages and a 32-bit physical address space. Each
page table entry contains a valid bit, a dirty bit, three permission bits, and the translation. If the
maximum size of the page table of a process is 24 megabytes, the length of the virtual
address supported by the system is _______________ bits.

Answer
Correct Answer is 36
14> GATE CSE 2014 Set 1
Assume that there are 3 page frames which are initially empty. If the page reference string
is 1,2,3,4,2,1,5,3,2,4,6, the number of page faults using the optimal replacement policy
is______________.

Answer
Correct Answer is 7
15> GATE CSE 2014 Set 3
Consider a paging hardware with a TLB. Assume that the entire page table and all the pages are in the

physical memory. It takes 10 milliseconds to search the TLB and 80 milliseconds to access the

physical memory. If the TLB hit ratio is 0.6, the effective memory access time (in milliseconds)

is______________.

Answer
Correct Answer is 122

15>GATE CSE 2012

MCQ (Single Correct Answer)

Consider the virtual page reference string1,2,3,2,4,1,3,2,4,1

On a demand paged virtual memory system running on a computer system that has main memory size of 3 page

frames which are initially empty. Let LRU, FIFO and OPTIMAL denote the number of page faults under the

corresponding page replacement policy. Then

Ans:-OPTIMAL<FIFO<LRU

16> GATE CSE 2008

A processor uses 36 bit physical addresses and 32 bit virtual addresses, with a page frame size of 4 Kbytes. Each

page table entry is of size 4 bytes. A three level page table is used for virtual to physical address translation,

where the virtual address is used as follows:

∗ Bits 30-31 are used to index into the first level page table

∗ Bits 21-29 are used to index into the second level page table

∗ Bits 12-20 are used to index into the third level page table, and

∗ Bits 0-11 are used as offset within the page

The number of bits required for addressing the next level page table (or page frame) in the page table
entry of the first, second and third level page tables are respectively
a)20, 20 and 20

b)24, 24 and 24(ans)

c)24, 24, and 20

d)25, 25 and 24
17> GATE CSE 2007
A process has been allocated 3 page frames. Assume that none of the pages of the process
are available in the memory initially. The process makes the following sequence of page
references (reference string):1,2,1,3,7,4,5,6,3,1

Least Recently Used (LRU) page replacement policy is a practical approximation to optimal
page replacement. For the above reference string, how many more page faults occur with LRU
than with the optimal page replacement policy?
Ans:- 2

18> GATE CSE 2007

A process has been allocated 3 page frames. Assume that none of the pages of the process are

available in the memory initially. The process makes the following sequence of page references

(reference string):1,2,1,3,7,4,5,6,3,1

If optimal page replacement policy is used, how many page faults occur for the above
reference string?
Ans:-7
19> GATE CSE 2004
Consider a System with a two-level paging scheme in which a regular memory access takes 150 nanoseconds,

and servicing a page fault takes 8 milliseconds. An average instruction takes 100 nanoseconds of CPU time, and

two memory accesses. The TLB hit ratio is 90% and the page fault rate is one in every 10,000 instructions. What

is the effective average instruction execution time?

Ans:-645 nanoseconds
20> (GATE 2013)
A laptop uses 46–bit virtual address, 32–bit physical address, and a three–level paged page table organization.
The page table base register stores the base address of the first–level table (T1), that occupies specifically one
page. every entry of T1 stores the base address of a page of the second–level table (T2). every entry of T2
stores the base address of a page of the third–level table (T3). every entry of T3 stores a page table entry (PTE).
The PTE is thirty two bits in size. The processor employed in the pc encompasses a one MB sixteen way set
associativevirtually indexed physically labeled cache. The cache block size is sixty four bytes. What is the size of
a page in KB during this computer?

A.2
B.4
C.8
D.16
21>(GATE 2013)
A system uses first in first out policy for page replacement. it’s four page frames with no pages
loaded to start with. The system initial accesses a hundred distinct pages in some
order so accesses hundred distinct pages in some order and then wants to access 100 pages
in reverse order. what number page faults can occur?
A.196
B.192
C.197
D.195

22> In a demand paging memory system, page table is held in registers. The time taken
to service a page fault is 8 m.sec. if an empty frame is available or if the replaced page is
not modified, and it takes 20 m.secs., if the replaced page is modified. What is the
average access time to service a page fault assuming that the page to be replaced is
modified 70% of the time ?
ans: 16.4 m.sec.
June 2014

Q23. In a paged memory management algorithm, the hit ratio is 70%. If it takes 30
nanoseconds to search Translation Look-aside Buffer (TLB) and 100 nanoseconds (ns) to
access memory, the effective memory access time is
ans:- 160 ns
24>>A processor user 2-level page tables for virtual to physical address translation. Page tables for both levels
are stored in the main memory. Virtual and physical adresses are both 32 bits wide. The memory is byte
addressable. For virtual to physical address translation, the 10 most significant bits of the virtual address are
used as index into the first level page table while the next 10 bits are used as index into the second level page
table. The 12 least significant bits of the virtual address are used as offset within the page. Assume that the
page table entries in both levels of page tables are 4 bytes wide. Further, the processor has a translation look-
aside buffer (TLB), with a hit rate of 96% . The TLB caches recently used virtual page numbers and the
corresponding physical page numbers. The processor also has a physically addressed cache with a hit ratio of
90 %. Main memory access time is 10 ns, cache access time is 1 ns. and TLB access time is also 1 ns.

Suppose a process has only the following pages in its virtual address space: two contiguous code pages
starting at virtual address 0 x 00000000, two contiuous data page starting at virtual address 0 x FFFFF000.
The amount of memory required for storing the page tables of this process is--
Solution

The correct option is C 16KB

Logical address = 32 bits
P 1 P2 P3
10 bits 10 bits 12 bits

P1= 1st level page table.

P2= 2nd level page table.
d = Page offset

First virtual address given

Address will be found in first level page table first block.

Second virtual address given

Address will be found in first level page table second

block.

Third virtual address given

Address will be found in first level page table last

block.
 To execute the process we need to bring all the above 4
page tables in main memory.
4×210×4 B=16 KB