SUMO UM82450 / UM825 0

-============
fl~ Asynchronous Communication
Element (ACE)

Feature

• Adds or deletes standard asynchronous communication • Fully programmable serial-interface characteristics

bits (Start, Stop, and Parity) to or from serial data 5-,6-,7-, or 8-Bit characters
stream - Even, Odd, or No-Parity bit generation and detection
• Full double buffering eliminates need for precise ...;.. 1-,1 %-, or 2-Stop bit generation
synchronization - Baud rate generation (DC to 56K baud)
• Independently controlled transmit, receive, line status, • False start bit detection
and data set interrupts ( • Complete status reporting capabilities
• Programmable baud rate generator allows division of • Easily interfaces to most popular microprocessors
any input clock by 1 to (2 16 - 1) and generates the • Line break generation and detection
internal 16x clock • Internal diagnostic capabilities
• I ndependent receiver clock input - Loopback controls for communications link fault
• Modem control functions (CTS, RTS, DSR, DTR, RI, isolation
and carrier detect) - Break, parity, overrun, framing error simulation
• Single +5 volt power supply • Full prioritized interrupt system controls

General Description
UM82450 and UM8250 are programmable Asynchronous status of the ACE at any time during the functional
Communication Element (ACE) chips fabricated with operation. They also includes a programmable baud rate
Si -Gate NMOS process. The UM82450 is an improved generator that is capable of dividing the timing reference
specification version of the UM8250. These two products
perform serial-to-parallel conversion on data characters clock input by divisors of 1 to (2 16 - 1), and producing
received from the CPU. The CPU can read the complete a 16x clock for driving the internal transmitter logic.

Pin Configuration

DO VCC
01 AT
02 RLSO
03 OSR
04 CTS
05 MR
06 OUT1
07 OTR
RCLK RTS
SIN OUT2
SOUT INTRPT
CSO NC
CS1 AO
CS2 A1
BAUOOUT A2
XTAL1 ADS
XTAL2 CSOUT
OOSTR OOIS
DOSTR DISTR
VSS OISTR

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 UM82450/ UM8250

Block Diagram

INTERNAL
DATA BUS RECEIVER
DATA RECEIVER

~
A
D7.DO BUS BUFFER V SHIFT I'---SI N
,--- REGISTER
BUFFER ~ REGISTER
~

~ECEIVER
~ LINE
CONTROL TIMING I---R CLK
rV REGISTER
t--- -
&
CONTROL

AO
-- DIVISOR
A1
A2
- ~
r-V
LATCH (LS)

DIVISOR
LATCH (MS)
BAUD
GENERATOR - BAUDOUT

CSO) -
CS1 _
CS2_
AD
-
S- SELECT TRANSMITTER
MR &
DIST R _ CONTROL
DIST R _ LOGIC
=; LINE
STATUS
REGISTER
TIMING
&
CONTROL

DOST R _
DOSTR -
DDI S -
TRANSMITTER
CSOU T - ~ TRANSMITTER
XTAL1 - -v'
HOL DING
REGISTER
...J\"
~
/
SHIFT
REGISTER
r---- SOUT
XTAL 2 -

r----
=>
MODEM ..,J\ RTS
CONTROL ) I - - - CTS
REGISTER v
r---- DIR
MODEM I - - DSR
CONTROL
MODEM LOGIC I - - RLSD

~
A
STATUS J4-- AT
REGISTER " I---- OUT1
I---- OUT2

~ INTERRUPT
ENABLE ~ INTERRUPT
INTRPT
IV' REGISTER ~ CONTROL
LOGIC

'-----
INTERRUPT
ID
A
JJ
REGISTER
'"

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