SN54/74LS160A

SN54/74LS161A
BCD DECADE COUNTERS/ SN54/74LS162A
4-BIT BINARY COUNTERS SN54/74LS163A
The LS160A / 161A / 162A / 163A are high-speed 4-bit synchronous count-
ers. They are edge-triggered, synchronously presettable, and cascadable
MSI building blocks for counting, memory addressing, frequency division and
other applications. The LS160A and LS162A count modulo 10 (BCD). The BCD DECADE COUNTERS /
LS161A and LS163A count modulo 16 (binary.) 4-BIT BINARY COUNTERS
The LS160A and LS161A have an asynchronous Master Reset (Clear)
input that overrides, and is independent of, the clock and all other control LOW POWER SCHOTTKY
inputs. The LS162A and LS163A have a Synchronous Reset (Clear) input that
overrides all other control inputs, but is active only during the rising clock
edge.
BCD (Modulo 10) Binary (Modulo 16)
Asynchronous Reset LS160A LS161A J SUFFIX
CERAMIC
Synchronous Reset LS162A LS163A
CASE 620-09
16
• Synchronous Counting and Loading 1

• Two Count Enable Inputs for High Speed Synchronous Expansion

• Terminal Count Fully Decoded
• Edge-Triggered Operation
N SUFFIX
• Typical Count Rate of 35 MHz PLASTIC
• ESD > 3500 Volts CASE 648-08
16
1
CONNECTION DIAGRAM DIP (TOP VIEW)

VCC TC Q0 Q1 Q2 Q3 CET PE
16 15 14 13 12 11 10 9 D SUFFIX
NOTE: SOIC
16
The Flatpak version
1 CASE 751B-03
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
ORDERING INFORMATION
*MR for LS160A and LS161A
*SR for LS162A and LS163A SN54LSXXXJ Ceramic
1 2 3 4 5 6 7 8 SN74LSXXXN Plastic
*R CP P0 P1 P2 P3 CEP GND SN74LSXXXD SOIC

PIN NAMES LOADING (Note a) LOGIC SYMBOL

HIGH LOW 9 3 4 5 6
PE Parallel Enable (Active LOW) Input 1.0 U.L. 0.5 U.L.
P0 – P3 Parallel Inputs 0.5 U.L. 0.25 U.L.
CEP Count Enable Parallel Input 0.5 U.L. 0.25 U.L. PE P0 P1 P2 P3
7 CEP
CET Count Enable Trickle Input 1.0 U.L. 0.5 U.L.
CP Clock (Active HIGH Going Edge) Input 0.5 U.L. 0.25 U.L. 10 CET TC 15
MR Master Reset (Active LOW) Input 0.5 U.L. 0.25 U.L. 2 CP
SR Synchronous Reset (Active LOW) Input 1.0 U.L. 0.5 U.L. *R Q0 Q1 Q2 Q3
Q0 – Q3 Parallel Outputs (Note b) 10 U.L. 5 (2.5) U.L.
TC Terminal Count Output (Note b) 10 U.L. 5 (2.5) U.L.
NOTES: 1 14 13 12 11
a) 1 TTL Unit Load (U.L.) = 40 µA HIGH/1.6 mA LOW. VCC = PIN 16
b) The Output LOW drive factor is 2.5 U.L. for Military (54) and 5 U.L. for Commercial (74) GND = PIN 8
Temperature Ranges.
*MR for LS160A and LS161A
*SR for LS162A and LS163A

FAST AND LS TTL DATA

5-1
 SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A

STATE DIAGRAM
LS160A • LS162A LS161A • LS163A
LOGIC EQUATIONS
0 1 2 3 4 0 1 2 3 4
Count Enable = CEP • CET • PE
TC for LS160A & LS162A = CET • Q0 • Q1 • Q2 • Q3
TC for LS161A & LS163A = CET • Q0 • Q1 • Q2 • Q3
15 5 15 5 Preset = PE • CP + (rising clock edge)
Reset = MR (LS160A & LS161A)
Reset = SR • CP + (rising clock edge)
14 6 14 6 Reset = (LS162A & LS163A)

13 7 13 7 NOTE:
The LS160A and LS162A can be preset to any state,
but will not count beyond 9. If preset to state 10, 11,
12 11 10 9 8 12 11 10 9 8 12, 13, 14, or 15, it will return to its normal sequence
within two clock pulses.

FUNCTIONAL DESCRIPTION
The LS160A / 161A / 162A / 163A are 4-bit synchronous the Binary counters). Note that TC is fully decoded and will,
counters with a synchronous Parallel Enable (Load) feature. therefore, be HIGH only for one count state.
The counters consist of four edge-triggered D flip-flops with The LS160A and LS162A count modulo 10 following a
the appropriate data routing networks feeding the D inputs. All binary coded decimal (BCD) sequence. They generate a TC
changes of the Q outputs (except due to the asynchronous output when the CET input is HIGH while the counter is in state
Master Reset in the LS160A and LS161A) occur as a result of, 9 (HLLH). From this state they increment to state 0 (LLLL). If
and synchronous with, the LOW to HIGH transition of the loaded with a code in excess of 9 they return to their legitimate
Clock input (CP). As long as the set-up time requirements are sequence within two counts, as explained in the state
met, there are no special timing or activity constraints on any diagram. States 10 through 15 do not generate a TC output.
of the mode control or data inputs. The LS161A and LS163A count modulo 16 following a
Three control inputs — Parallel Enable (PE), Count Enable binary sequence. They generate a TC when the CET input is
Parallel (CEP) and Count Enable Trickle (CET) — select the HIGH while the counter is in state 15 (HHHH). From this state
mode of operation as shown in the tables below. The Count they increment to state 0 (LLLL).
Mode is enabled when the CEP, CET, and PE inputs are HIGH. The Master Reset (MR) of the LS160A and LS161A is
When the PE is LOW, the counters will synchronously load the asynchronous. When the MR is LOW, it overrides all other
data from the parallel inputs into the flip-flops on the LOW to input conditions and sets the outputs LOW. The MR pin should
HIGH transition of the clock. Either the CEP or CET can be never be left open. If not used, the MR pin should be tied
used to inhibit the count sequence. With the PE held HIGH, a through a resistor to VCC, or to a gate output which is
LOW on either the CEP or CET inputs at least one set-up time permanently set to a HIGH logic level.
prior to the LOW to HIGH clock transition will cause the The active LOW Synchronous Reset (SR) input of the
existing output states to be retained. The AND feature of the LS162A and LS163A acts as an edge-triggered control input,
two Count Enable inputs (CET • CEP) allows synchronous overriding CET, CEP and PE, and resetting the four counter
cascading without external gating and without delay accu- flip-flops on the LOW to HIGH transition of the clock. This
mulation over any practical number of bits or digits. simplifies the design from race-free logic controlled reset
The Terminal Count (TC) output is HIGH when the Count circuits, e.g., to reset the counter synchronously after
Enable Trickle (CET) input is HIGH while the counter is in its reaching a predetermined value.
maximum count state (HLLH for the BCD counters, HHHH for

MODE SELECT TABLE

*SR PE CET CEP Action on the Rising Clock Edge ( )
L X X X RESET (Clear) *For the LS162A and
H L X X LOAD (Pn → Qn) *LS163A only.
H H H H COUNT (Increment) H = HIGH Voltage Level
H H L X NO CHANGE (Hold) L = LOW Voltage Level
H H X L NO CHANGE (Hold) X = Don’t Care

FAST AND LS TTL DATA

5-2
 SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A

GUARANTEED OPERATING RANGES

Symbol Parameter Min Typ Max Unit
VCC Supply Voltage 54 4.5 5.0 5.5 V
74 4.75 5.0 5.25
TA Operating Ambient Temperature Range 54 – 55 25 125 °C
74 0 25 70
IOH Output Current — High 54, 74 – 0.4 mA
IOL Output Current — Low 54 4.0 mA
74 8.0

LS160A and LS161A

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

Input HIGH Current

MR, Data, CEP, Clock 20 µA VCC = MAX, VIN = 2.7 V
IIH PE, CET 40
MR, Data, CEP, Clock 0.1 mA VCC = MAX, VIN = 7.0 V
PE, CET 0.2
Input LOW Current
IIL MR, Data, CEP, Clock – 0.4 mA VCC = MAX, VIN = 0.4 V
PE, CET – 0.8
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
Power Supply Current
ICC Total, Output HIGH 31 mA VCC = MAX
Total, Output LOW 32
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

FAST AND LS TTL DATA

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 SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A

LS162A and LS163A

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
Guaranteed Input HIGH Voltage for
VIH Input HIGH Voltage 2.0 V
All Inputs
54 0.7 Guaranteed Input
p LOW Voltage
g for
VIL Input LOW Voltage V
74 0.8 All Inputs

VIK Input Clamp Diode Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA
54 2.5 3.5 V VCC = MIN,, IOH = MAX,, VIN = VIH
VOH Output HIGH Voltage
74 2.7 3.5 V or VIL per Truth Table

54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN,

VOL Output LOW Voltage VIN = VIL or VIH
74 0.35 0.5 V IOL = 8.0 mA per Truth Table

Input HIGH Current

Data, CEP, Clock 20 µA VCC = MAX, VIN = 2.7 V
IIH PE, CET, SR 40
Data, CEP, Clock 0.1 mA VCC = MAX, VIN = 7.0 V
PE, CET, SR 0.2
Input LOW Current
IIL Data, CEP, Clock, PE, SR – 0.4 mA VCC = MAX, VIN = 0.4 V
CET – 0.8
IOS Short Circuit Current (Note 1) – 20 – 100 mA VCC = MAX
Power Supply Current
ICC Total, Output HIGH 31 mA VCC = MAX
Total, Output LOW 32
Note 1: Not more than one output should be shorted at a time, nor for more than 1 second.

AC CHARACTERISTICS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
fMAX Maximum Clock Frequency 25 32 MHz
tPLH Propagation Delay 20 35
ns
tPHL Clock to TC 18 35
tPLH Propagation Delay 13 24 VCC = 5.0
50V
ns
tPHL Clock to Q 18 27 CL = 15 pF
tPLH Propagation Delay 9.0 14
ns
tPHL CET to TC 9.0 14
tPHL MR or SR to Q 20 28 ns

FAST AND LS TTL DATA

5-4
 SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A

AC SETUP REQUIREMENTS (TA = 25°C)

Limits
S b l
Symbol P
Parameter Min Typ Max U i
Unit T
Test C
Conditions
di i
tWCP Clock Pulse Width Low 25 ns
tW MR or SR Pulse Width 20 ns
ts Setup Time, other* 20 ns
ts Setup Time PE or SR 25 ns VCC = 5.0
50V
th Hold Time, data 3 ns
th Hold Time, other 0 ns
trec Recovery Time MR to CP 15 ns
*CEP, CET or DATA

DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time required nition. A negative HOLD TIME indicates that the correct logic
for the correct logic level to be present at the logic input prior to level may be released prior to the clock transition from LOW to
the clock transition from LOW to HIGH in order to be recog- HIGH and still be recognized.
nized and transferred to the outputs.
RECOVERY TIME (trec) — is defined as the minimum time re-
HOLD TIME (th) — is defined as the minimum time following quired between the end of the reset pulse and the clock transi-
the clock transition from LOW to HIGH that the logic level must tion from LOW to HIGH in order to recognize and transfer
be maintained at the input in order to ensure continued recog- HIGH Data to the Q outputs.

AC WAVEFORMS

tW
tW(H) tW(L) MR 1.3 V
1.3 V OTHER CONDITIONS: trec OTHER CONDITIONS:
CP 1.3 V
PE = MR (SR) = H PE = L
1.3 V
tPHL tPLH CEP = CET = H CP P0 = P1 = P2 = P3 = H
tPHL
Q 1.3 V 1.3 V
Q0 ⋅ Q1 ⋅ Q2 ⋅ Q3 1.3 V

Figure 1. Clock to Output Delays, Count Figure 2. Master Reset to Output Delay, Master Reset
Frequency, and Clock Pulse Width Pulse Width, and Master Reset Recovery Time

FAST AND LS TTL DATA

5-5
 SN54/74LS160A • SN54/74LS161A
SN54/74LS162A • SN54/74LS163A

AC WAVEFORMS (continued)

COUNT ENABLE TRICKLE INPUT

TO TERMINAL COUNT OUTPUT DELAYS 1.3 V 1.3 V
CET
The positive TC pulse occurs when the outputs are in the tPLH tPHL
(Q0 • Q1 • Q2 • Q3) state for the LS160 and LS162 and the
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163. TC 1.3 V 1.3 V

Figure 3 OTHER CONDITIONS: CP = PE = CEP = MR = H

CLOCK TO TERMINAL COUNT DELAYS

CP 1.3 V 1.3 V 1.3 V

The positive TC pulse is coincident with the output state tPLH tPHL
(Q0 • Q1 • Q2 • Q3) state for the LS161 and LS163 and
(Q0 • Q1 • Q2 • Q3) for the LS161 and LS163. TC 1.3 V 1.3 V

Figure 4 OTHER CONDITIONS: PE = CEP = CET = MR = H

CP 1.3 V 1.3 V

SETUP TIME (ts) AND HOLD TIME (th) ts(H) ts(L)

FOR PARALLEL DATA INPUTS th(H) = 0 th(L) = 0

The shaded areas indicate when the input is permitted to P0 • P1 • P2 • P3 1.3 V 1.3 V 1.3 V
change for predictable output performance.

Q0 • Q1 • Q2 • Q3

Figure 5 OTHER CONDITIONS: PE = L, MR = H

SETUP TIME (ts) AND HOLD TIME (th) FOR

COUNT ENABLE (CEP) AND (CET) AND
PARALLEL ENABLE (PE) INPUTS
The shaded areas indicate when the input is permitted to
change for predictable output performance.

CP 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V

CP
ts(L) ts(H) ts(H) ts(L)
th (L) = 0 th(H) = 0 th(H) = 0 th(L) = 0
SR or PE 1.3 V 1.3 V CEP 1.3 V 1.3 V
PARALLEL LOAD COUNT MODE ts(L)
(See Fig. 5) (See Fig. 7) ts(H)
th(H) = 0 th(L) = 0
Q RESPONSE TO PE 1.3 V 1.3 V
CET 1.3 V 1.3 V

RESET COUNT OR LOAD COUNT HOLD HOLD

Q RESPONSE TO SR Q

OTHER CONDITIONS: PE = H, MR = H

Figure 6 Figure 7

FAST AND LS TTL DATA

5-6