DLD Lab Report 07

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Lab report # 07
Design and Implementation of 𝒏 – 𝒃𝒊𝒕 Adder/Subtractor on FPGA
1.1: Objectives
1.1.1: Part 1:
This experiment is to design gate-level hierarchal description of a 4 − 𝑏𝑖𝑡 binary Adder /
Subtractor in HDL and implement it on FPGA and using ICs.
1.1.2: Part 2:
Introduce the different Verilog keyword (parameter) and use it to make the module
parameterized in Verilog. Parameterized method will allow us to make 𝑛 − 𝑏𝑖𝑡 binary Adder
/ Subtractor in Verilog.
1.1.3: Pre-Lab:
1.1.4: Background theory:
Binary Adder is digital circuit that produces the arithmetic sum of two binary numbers. It can
be constructed with full adders connected in cascade, with the output carry from each full
adder connected to the input carry of the next full adder in the chain. The process of addition
proceeds on a bit-by-bit basis, right to left, beginning with the least significant bit. After the
least significant bit, addition at each position adds not only the respective bits of the words,
but also consider a possible carry bit from addition at the previous position. Addition of 𝑛 −
𝑏𝑖𝑡 binary numbers requires the use of a 𝑛 full adder, or a chain of one-half adder and 𝑛 − 1
full adders. The four-bit adder is an example of a standard component. It can be used in many
applications involving arithmetic operations.
Binary Adder/Subtractor can be combined into one circuit with one common binary adder by
including an exclusive-OR gate with each full adder. A four-bit adder/subtractor circuit of
two binary numbers 𝐴(𝐴3𝐴2𝐴1𝐴0) and 𝐵(𝐵3𝐵2𝐵1𝐵0) is shown in Figure 7.1. The mode
input 𝑀 controls the operation. When 𝑀 = 0, the circuit is an adder. As 𝐵 ⊕ 0 = 𝐵,
𝐶0 = 0 , full adders receive the value of 𝐵, and the circuit performs 𝐴 + 𝐵. when 𝑀 = 1,
the circuit becomes a subtractor. Now we have 𝐵 ⊕ 1 = 𝐵
̅ and 𝐶0 = 1. The 𝐵 input is
complemented and a 1 is added through the input carry (𝐶0). The circuit performs the
operation 𝐴 plus the 2’s complement of 𝐵 i.e., 𝐴 − 𝐵. The exclusive-OR with output 𝑉 is for
detecting an overflow and 𝐶 is carry out.
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2.1: Pre-Lab Task:

Using Gate-level model, write a Verilog description of a Half-Adder.
Figure:2.1.1: gate level code in Xilinx
2.2: Test bench code:
Figure:2.2.1: test bench for figure 2.1.1

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2.3: Test bench:
Figure:2.3.1: output of figure 2.1.1

2.4: IN LAB TASKS:
2.4.1: Part 1(a): Implementing of a 4-bit binary adder / Subtractor
with overflow using ICs.
Procedure:
1) Implement a 4-bit adder/subtractor with overflow ICs circuitry.
2) Use 4-bit full adder IC (7483) and XOR gate.
3) Connect all the input M, A and B (4-bit for each binary number) on slide
4) switches, and output are observed on the LEDs.
5) Observe the behaviour of adder/subtractor by using different values
Figure:2.4.2: Results
2.4.2: Part 1(b): Implementing hierarchal description of a 4-bit binary adder /

Subtractor4-bit binary adder / Subtractor is implemented by using the
following method.
Procedure:
1) Write the HDL Verilog code for 4-bit binary adder in Xilinx software
2) Create HDL project
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3) Set the project settings:

4) Family to Spartan3E
5) Device to XC3S500E
6) Package to FG320
7) Speed to -4.
8) Add the design files ‘my_4bit_ adder’ with two inputs A, B and outputs S, C, V.
9) then define submodules ‘Full Adder’ having three inputs and two outputs.
10) Interconnect these ‘Full Adder’ modules as shown in figure 7.2.
11) Simulate your design using XST simulator.
12) Define 8 inputs for A and B (4 bits for each binary number) on data slide
13) switches on FPGA. then 6 outputs are observed on LEDs.
14) Burn the .bit file on FPGA and test the behaviour of Adder /Subtractor by
15) choosing the two different binary numbers.
16) Fill the table with addition of any two binary numbers and their result observed on
FPGA.
Figure:2.4.3: results
Figure:2.4.4: code in Xilinx

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Figure:2.4.5: selecting button on FPGA
Parameter Example: n-bit comparator:

Comparator is a circuit that computes two inputs (a and b). If a is greater then
Greater Than flag will be high, if a is lesser than b, then Lesser Than flag will be high, and if a
is equal to b, then Equal flag will be high. a and b have any number of
bits. The example of n-bit comparator is given below.
Figure: 2.4.6: behavourial modeling code for n-bit parameter

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To instantiate parameterized module for different values of n:
Figure:2.4.7: comparator
3.1: POST LAB TASKS:

1) Using Behavioural model, write a Verilog description of n-bit Adder/Subtractor.
2) Make one stimulus for two different parameters values and show the
3) wave forms result.
4) Analyse the circuit implementation of Gate-Level 4-bit Adder/Subtractor, in
5) term of resource utilization and critical path delay.
3.1.1: TASK:
Question # 01:
Part 1:
Module:
On next page:
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3.1.3: Test bench:

Figure of testbench on next page
Figure:3.1.4: test bench

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Simulation:
Figure:3.1.5: output
3.2: Question # 02:

Module:

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Test bench:
Figure:3.2.2: test bench
Simulation:
Figure:3.2.3: output
Question # 02:
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Analyze the circuits implementation of the structural-level 4-bit Adder/Subtractor and

behavioral-level 4-bit Adder/Subtractor, in term of source utilization and critical part delay.
Answer:
Gate level Modelling is used and implemented in part 1, By using of the resource
utilization, the implementation can be analysis in a best way. Functions can be implemented on
FGFA by using Behavioural modelling in part 2. To analyse the behavioural modelling, the
Critical Path Delay is an appropriate method because the processing time by the critical path
delay can be minimized effectively. This is because it uses many Registers and their Addresses
etc
Discussion and conclusion:

Discussion:
In this lab we discuss how to code In Xilinx for implementing the program on FPGA and also we
prove that adder-subtracter which we make in theory
In next part, we implement the above function on hardware, using ics and 4 bit full adder ics
Proof of the above work is given in figure
Conclusion:
In this lab we have analysed that by a computer the addition of any two numbers is very basic
task to be implemented and processed on Xilinx and FPGA. The same circuit implementation
can also be used for subtraction. In this lab I have learnt how to design a 4-bit binary and
subtractor and implemented on FPGA. In Verilog.we have used Parameter and always
command, and we have analysed the result of it. These results were for 4- bit and 8-bit binary
numbers which are shown above in simulation graphs.
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Page 1 of 11

2.1: Pre-Lab Task:

Figure:2.1.1: gate level code in Xilinx

2.2: Test bench code:

Figure:2.2.1: test bench for figure 2.1.1

2.3: Test bench:

Figure:2.3.1: output of figure 2.1.1

2.4.2: Part 1(b): Implementing hierarchal description of a 4-bit binary adder /

3) Set the project settings:

Figure:2.4.4: code in Xilinx

Figure:2.4.5: selecting button on FPGA

Parameter Example: n-bit comparator:

Figure: 2.4.6: behavourial modeling code for n-bit parameter

To instantiate parameterized module for different values of n:

3.1: POST LAB TASKS:

Figure:3.1.2: code in Xilinx

3.1.3: Test bench:

Figure:3.1.4: test bench

3.2: Question # 02:

Figure:3.2.1: code in Xilinx

Figure:3.2.2: test bench

Analyze the circuits implementation of the structural-level 4-bit Adder/Subtractor and

Discussion and conclusion:

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