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    PDF Lab 2 DLD

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    Sana Khitran

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    © All Rights Reserved
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    PDF Lab 2 DLD

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    Sana Khitran
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    PDF Lab 2 DLD

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    Sana Khitran

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    © All Rights Reserved
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    of 13

    Department of Electrical Engineering

    Dated: 13/02/24
    Faculty Member: Mughees Ahmed

    Semester: 2nd Section: BSDS-1A


    Group No: 9

    EE-221: Digital Logic Design

    Lab 2: Introduction to Verilog

    PLO4/CLO4 PLO4/CLO4 PLO5/CLO5 PLO8/CLO6 PLO9/CLO7

    Name Reg. No Viva / Lab Analysis Modern Ethics and Individual Total
    Performance of data in Tool Usage Safety and Team marks
    Lab Report Work Obtained

    5 Marks 5 Marks 5 Marks 5 Marks 5 Marks 25 Marks


    Sana Khan Khitran 464597

    Rimsha Mahmood 455080

    Amna Akhtar Nawabi 462939

    Aimen Ahsan 467032

    EE-221: Digital Logic Design Page 1


    Lab2: Introduction to Verilog, Gate-level/Behavioral Modeling and Hardware
    Implementation of Basic Logic Circuit

    This Lab has been divided into two parts.

    In first part you will be introduced to Verilog and Gate-Level Modeling.


    The next part is the hardware implementation of a Boolean function given to you.

    Objectives:

     Understand HDL and compare it with normal programming languages.


     Simulate Basic Gates using Verilog with ModelSim
     Write stimulus using Verilog
     Derive algebraic expression for a Boolean function from the given schematics.
     Hardware Implementation of Logic Circuit

    Lab Instructions

     This lab activity comprises three parts, namely Pre-lab, Lab tasks, and Post-Lab Viva session.
     The lab report will be uploaded on LMS three days before scheduled lab date. The students will
    get hard copy of lab report, complete the Pre-lab task before coming to the lab and deposit it with
    teacher/lab engineer for necessary evaluation. Alternately each group to upload completed lab
    report on LMS for grading.
     The students failing to submit Pre-Lab will not be allowed to perform Lab work.
     The students will start lab task and demonstrate design steps separately for step-wise evaluation
    (course instructor/lab engineer will sign each step after ascertaining functional verification)
     Remember that a neat logic diagram with pins numbered coupled with nicely patched circuit will
    simplify trouble-shooting process.
     After the lab, students are expected to unwire the circuit and deposit back components before
    leaving.
     The students will complete lab task and submit complete report to Lab Engineer before leaving
    lab. Verilog tutorial part is non-printable and for reference only.
     There are related questions at the end of this activity. Give complete answers.

    EE-221: Digital Logic Design Page 2


    Pre-Lab Task: (To be done before coming to the lab) (2 marks)
    1. Read the manual Getting Started with Verilog and answer the following questions.

    a) HDL stands for:

    Hardware Description Language

    b) Two standard versions of HDL are:

    1. VHDL
    2. Verilog HDL

    c) Give the different levels of abstraction in Verilog HDL

    1. Behavioral Level: Focuses on what the design should do rather than how it should be
    implemented.

    2. Register Transfer Level: Describes the design in terms of registers, data paths, and control
    signals.

    3. Gate Level: Specifies the logical connections between gates and the timing behavior of the
    design.

    4. Switch Level: This level of abstraction models the behavior of individual transistors and
    switches.

    EE-221: Digital Logic Design Page 3


    Lab Tasks: (8 marks)
    Lab Task 1: (2 marks)
    Model and simulate the basic gates i.e. NOT, AND & OR in Verilog (Gate level) using Modelsim. Compare
    the simulation waveform results with truth table in the space given below.

    1. NOT GATE
    Code:

    Waveform:

    EE-221: Digital Logic Design Page 4


    Truth Table:

    Input Output
    1 0
    0 1

    The results of stimulation and truth table are same.

    2. AND GATE:
    Code:

    Waveform:

    EE-221: Digital Logic Design Page 5


    Truth Table:

    IN 1 IN 2 OUT
    1 1 1
    1 0 0
    0 1 0
    0 0 0

    The results of stimulation and truth table are same.

    3. OR GATE: Code:

    EE-221: Digital Logic Design Page 6


    Waveform:

    Truth Table:

    IN 1 IN 2 OUT
    1 1 1
    1 0 1
    0 1 1
    0 0 0

    The results of stimulation and truth table are same.

    Lab Task 2: (2 marks)

    Write the Verilog Code using Gate Level modeling for the following circuit. List the code for design as well as
    stimulus below:

    EE-221: Digital Logic Design Page 7


    CODE:

    Simulate below circuit on Proteus and perform it on hardware.

    EE-221: Digital Logic Design Page 8


    Proteus:

    1. x = y = sum = carry = 0

    2. x = 0, y = 1, sum = 1, carry = 0

    EE-221: Digital Logic Design Page 9


    3. x = 1, y = 0, sum = 1, carry = 0

    4. x = 1, y = 1, sum = 0, carry = 1

    EE-221: Digital Logic Design Page 10


    Lab Task 3: (2 marks)
    Label each gate output in the above circuit and derive algebraic expressions for SUM and Carry Out. Fill in
    the following truth table and determine the function performed by the circuit.

    Truth Table
    x y Sum Carry Out

    0 0 0 0
    0 1 1 0
    1 0 1 0
    1 1 0 1

    Expressions:

    𝑠𝑢𝑚=𝐴′𝐵+𝐴𝐵′

    𝑐𝑎𝑟𝑟𝑦=𝐴𝐵

    Lab Task 4: (2 marks)

    After determining the function performed by the circuit given in Lab Task 2, write the Verilog description of
    the circuit in dataflow. Comment on the two different modeling levels you used to model the same circuit.
    (Paste snapshots of the codes and stimuluses below)

    EE-221: Digital Logic Design Page 11


    Code:

    Waveform:

    Observations/Comments:

    During the laboratory session, we were introduced to Verilog and became acquainted with its
    functionalities and utilization within the ModelSim software environment. Our instruction encompassed a
    comprehensive understanding of ModelSim operations, including the generation of output formats
    convertible into truth tables. Through practical exercises, we simulated diverse logic gate operations using
    both ModelSim and Proteus software platforms, complementing our learning by executing corresponding
    tasks on hardware interfaces.

    EE-221: Digital Logic Design Page 12


    EE-221: Digital Logic Design Page 13

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