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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

A 1.8-nW, −73.5-dB PSRR, 0.2-ms Startup

Time, CMOS Voltage Reference With Self-
Biased Feedback and Capacitively
Coupled Schemes
Cheng-Ze Shao , Student Member, IEEE, Shih-Che Kuo, Graduate Student Member, IEEE,
and Yu-Te Liao , Member, IEEE

Abstract— This article presents a nanowatt CMOS voltage (sub-BGRs) usually have larger power consumption (>μW)
reference using self-biased and capacitively coupled schemes for and chip areas, although they may have better temperature
improving the power supply rejection ratio (PSRR) and settling coefficients (TCs) when compared to the CMOS counter-
time without power-intensive auxiliary amplifiers and bias
circuits. The chip was fabricated in a 0.18-μm CMOS process. parts [5]–[7]. Switched bipolar junction transistor (BJT) [8]
With the proposed schemes, the design can achieve a 1% sub-bandgap references [15], [16] can reduce the static power
settling time of 0.2 ms and a −73.5-dB PSRR at 100 Hz while consumption to tens of nanowatts. Meanwhile, the compli-
only consuming 1.8 nW. The average temperature coefficient cated control circuits and capacitance for noise suppression
of 15 chips is 62 ppm/◦ C in a temperature range from −40 ◦ C significantly increase the chip area. Recently, leakage-based
to 130 ◦ C. The average voltage at 20 ◦ C is 0.26 V, while the
standard deviation is 1.1 mV and 3 σ accuracy is 0.43%. hybrid VRs combining the characteristic of CMOS and BJT
have achieved low power consumption and good TCs simulta-
Index Terms— CMOS voltage reference (VR), low power, neously. However, the parasitic diode leakage current leads
power supply rejection ratio (PSRR), startup time.
to a temperature range problem [9]. Lee and Blaauw [10]
I. I NTRODUCTION can achieve a temperature range from 0 ◦ C to 170 ◦ C
because the proposed approach weakens the impact of the

V OLTAGE references (VRs) are widely used to generate

a stable voltage that is independent of process, supply
voltage, and temperature (PVT) variations for electronic sys-
leakage current without a need of perfectly matched Vds
of the proportional-to-absolute-temperature (PTAT) generation
transistors. Moreover, the native MOSFET is used to create a
tems. For advanced applications, such as battery-free sensory
large impedance from the power supply to the core circuit
systems [1], [2], the ambient energy supplying these devices
for improving the line sensitivity (LS). Alternatively, two-
usually fluctuates over time. The startup time becomes critical
NMOS-based [11], NMOS-stacked [12], and stacked diode-
for intermittent operations since the system needs a stable bias
connected MOS transistors (SDMTs) [7], [17], [18] generate
voltage before regular operations. During the long startup time,
a PVT-immunity reference voltage by the threshold voltage
the malfunctions in the circuits could make the system draw
differences between transistors. Although these designs can
extra current and even stop functions at the limited power.
achieve good LS and low power consumption, one of the
Thus, VR designs aim at low power consumption, small areas,
critical issues for practical implementation is that power reduc-
fast activation, and being trimming free. However, low-power
tion makes the suppression of interference coupling, such as a
designs imply a slow startup time and low power supply
50–60-Hz interference, a severe problem thanks to the limited
rejection (PSR) bandwidth [3].
bandwidth. The power supply rejection ratio (PSRR) of these
With the increasing demands for self-powering, integrated
designs is only about −50 dB. Another issue is that the low-
sensors, various temperature-stabilized, sub-1-V and sub-
power operation requires a large impedance from the supply
microwatt VRs, such as sub-bandgap and CMOS-only archi-
to the VR output, which deteriorates the settling speed to
tecture, have been developed [4]–[14]. The sub-bandgap VRs
longer than tens of milliseconds. Also, the PSRR and settling
Manuscript received April 20, 2020; revised July 3, 2020, August 26, 2020, time of VR significantly affect the performance of the voltage
and September 22, 2020; accepted September 23, 2020. This article was regulator that supplies a stable voltage to the whole system.
approved by Associate Editor Dennis Sylvester. This work was supported
by the Ministry of Science and Technology, Taiwan, under Grant 109- Fast transient and sufficient PSRR is vital for improving the
2636-E-009-006 (Young Scholar Fellowship Program). The chip fabrication tolerance of the continual switching activities from power sup-
was supported by the Taiwan Semiconductor Research Institute, Taiwan. ply fluctuations and interference coupling. The high-frequency
(Corresponding author: Yu-Te Liao.)
The authors are with the Department of Electrical and Computer Engi- PSRR can be improved by adding large capacitors at the output
neering, National Chiao Tung University, Hsinchu City 300, Taiwan R.O.C. with sacrifices in the silicon areas and startup speeds [3].
(e-mail: [email protected]). Kim and Cho [13] employed auxiliary amplifiers and a supply
Color versions of one or more of the figures in this article are available
online at http://ieeexplore.ieee.org. regulation loop to enhance the PSRR. As a result, the design
Digital Object Identifier 10.1109/JSSC.2020.3028506 also causes an increment in power consumption and design
0018-9200 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 1. Conceptual diagram of the SDMT VR over temperature, process, and supply variations.

complexity. Kim et al. [14] reported using a clock injection in sensitive to process variations, and the TC is not superior to
the VR circuit to reduce the startup time to sub-milliseconds. the BJT bandgap reference [15], [16]. In previous designs,
However, the design consumes more than 50 μW in the low-power, CMOS-only reference circuits needed trimming
startup phase and, thus, is not suitable for the designs powered circuits to achieve tens of ppm/◦ C [5], and the TC became
by ambient energy intermittently. Therefore, it is crucial to worse in a wide temperature range. The SDMT structure
devise the low-power VRs incorporating fast startup times has advantages in good tolerance to PVT variations, and the
and high PSRR while maintaining excellent PVT tolerance detailed analysis is discussed as follows.
for advanced, energy-autonomous sensors.
In this work, we propose a startup time enhancement
technique using self-biased and capacitively coupled schemes A. Temperature Compensation
for SDMT VR. The design achieves a 1% settling time Fig. 1 shows the conceptual diagram of the SDMT VR and
of 0.2 ms, improved by 274 times when compared with the comparisons to the diode-connected CMOS reference circuit.
design without the settling enhancement at the same power The diode-connected structure consists of an NMOS transistor
consumption of 1.8 nW. The measured PSRR is −73.5 dB at biased by a current source and operated in the saturation
100 Hz, which is sufficient to suppress the primary interference region [4]. The reference voltage is directly related to the
coupling from the power supply. This article is organized threshold voltage, which usually incurs an excessively large
as follows. Section II describes the design and analysis of temperature slope. The output reference voltage significantly
the SDMT VR structure. The design details of the proposed changes with the process variation. Another serious impact of
CMOS VR are presented in Section III. The measured results this architecture is that the resistance (R) of the current source
are shown in Section IV. Finally, Section V briefly addresses is supposed to be large enough to suppress the interference of
the conclusion. the supply voltage, limiting the startup speed and bandwidth
of PSRR. Different from the diode-connected VRs, the SDMT
structure adopts the threshold difference to eliminate the
II. SDMT A RCHITECTURE
temperature dependence. The stacked transistors, Mt and Mb ,
The MOS transistors operating in the subthreshold region operate in the subthreshold region. The drain current (ID ) of
can generate the voltage of PTAT and complementary- these transistors can be expressed as
to-absolute-temperature (CTAT) for linear temperature   2    
compensation, which can significantly reduce the power W VGS − VTH −VDS
ID = μn Cox V exp 1 − exp
consumption [6]. Without BJTs, the silicon area is quite L T mVT VT
small. However, the threshold voltage (VTH ) variation is (1)

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SHAO et al.: CMOS VR WITH SELF-BIASED FEEDBACK AND CAPACITIVELY COUPLED SCHEMES 3

where μn is the mobility of the NMOS, Cox is the gate

oxide capacitance, m is the subthreshold slope factor, VTH is
the threshold voltage, and VT is the thermal voltage. Since
the same drain current flows through Mt and Mb , the slope
factor is similar. Therefore, assuming VDS ≥ 3V T , Vref can be
approximated as
   
mt μt Coxt W t L b
Vref ≈ VTHb − VTHt + m t VT ln
mb μb Coxb W b L t
 
mt
+ 1− VGSb . (2)
mb
Observed from (2), Vref is insensitive to the bias current. Fur-
thermore, the threshold difference creates a CTAT voltage, and
the thermal voltage VT generates a PTAT voltage. Therefore, Fig. 2. Simulated process dependence of the slope factor ratio and device
ratio.
by selecting the appropriate width and length of Mt and Mb ,
the temperature dependence of Vref is eliminated to the first
order. gives a smaller deviation among process corners in the small
Previous work, employing a single, normal NMOS transistor device ratio. For the small device ratio, a large PTAT voltage
[4], generated the CTAT voltage by the threshold voltage, slope is necessary to compensate for the TC. Therefore, in this
VTH . These designs require a large PTAT temperature slope to design, we choose a Wt /Wb ratio of 0.1. Since the slope factor
cancel the CTAT temperature slope of VTH equally. The large can be controlled through proper transistor size design, the
PTAT/CTAT slopes usually cause voltage deviations at high SDMT architecture can further reduce the voltage spread to
and low temperatures, limiting the operational temperature 15 mV among all corners from the simulation. From the Monte
range of the VR. Carlo simulation at the same bias current and output voltage,
In the SDMT architecture, VTH is derived through thin- the σ /μ of the SDMT and diode-connected architectures is
oxide and thick-oxide NMOS transistors, which scale down 0.097 and 0.24, respectively.
the CTAT voltage and the slope over temperature
VTH (T ) = VTH (T0 ) − (αb − αt )(T − T0 ) (3) C. Line Sensitivity
Supply voltage variation immunity is a decisive parameter
where α is the first derivative of the threshold voltage with of performance, whereas reduced power consumption usually
respect to temperature. The VTH has a CTAT temperature results in degradation of LS. The LS of the diode structure is
slope reduced by (αb − αt ) [7]. Thus, only a small PTAT calculated as
slope is necessary for temperature compensation. In this way,
1
the temperature range of low TC can be extended at low and Vref gmd
≈ . (4)
high temperatures accordingly. VDD R + gmd
1

The small bias current makes the transistor operate in the sub-
B. Process Variations
threshold region, and the transconductance is small. The
The process variations for both within-die (WID) and die- increasing resistance of the diode-connection transistor
to-die (D2D) variations are critical. WID causes a mismatch imposes a large output resistor (R) of the current source to
between transistor parameters in the same chip and influ- maintain the proper LS. As for the SDMT structure, the output
ences the relative accuracy of the parameters. Careful layout voltage is expressed as
techniques and using large transistor sizes can reduce the
  1
variations. Unfortunately, the D2D variation influences the Vref gmb gmb
accuracy of output voltage Vref because the VTH of CMOS ≈ 1− . (5)
VDD gmt R + g1
mb
VR circuits are sensitive to process variations [6]. In the
SDMT CMOS VR, both Mb and Mt use the NMOS transistors. Ideally, while the bias current of both transistors is the same,
In this design, the transistor size of the Mb is chosen to gmt equals gmb , which nulls the supply dependence. In practice,
be larger than Mt to provide positive voltage changes from the dimensions of the stacked transistors are designed for
the slow to fast process corners. Besides, the slope factor temperature compensation, and the slope factors (m t and m b )
can vary in different process corners. Ji et al. [9] analyzed of the two transistors are slightly different so that the LS is not
the relationship between the slope factor and transistor size. zero under actual conditions. In other words, the ratio of the
The output voltage is related to the ratio of the slope factor two slope factors directly affects the sensitivity of the power
and the threshold voltage, (m t /m b )VTHb and (1 − m t /m b )VG . supply. In the standard CMOS process, the slope factor is
Fig. 2 shows the simulation results of the slope effects at around 1–1.5, and thus, the ratio of the two slope factors does
different process corners. Observed from (2) and the results, not significantly deviate. In our simulation, when m t = 0.9m b ,
the (1 − m t /m b ) × VGsb and m t /m b × VTHb − VTHt change in a the LS can improve by 20 dB more than the diode-connected
reverse direction in SS and FF corners. The sum of two results structure with the same value of R.

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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

TABLE I
D ESIGN PARAMETERS OF THE P ROPOSED A RCHITECTURE

Fig. 4. Results of the output voltage and TC over process corners.

so that it can extend the operational temperature range and

has good process tolerance. Moreover, the CTAT or PTAT
characteristics can be created by sizing the ratio of top and
bottom transistors. The thick and thin transistors are used in
the first stage for increasing the threshold voltage difference.
Compared to the architecture with thin transistor and thick
transistor combination, the stacked stage with thin transistors
only has large PTAT slope since the CTAT term from the fourth
term in (6) is mitigated. A small size ratio in the stacked stage
can be employed for compensating the temperature deviations
in the first stage. The results of the output voltage over
temperature at different process corners are presented in Fig. 4.
The simulated TCs are 7–17 ppm/◦ C from −40 ◦ C to 130 ◦ C
among all process corners.
As for improving the LS, a cascode current mirror is placed
on top of the core circuit to increase the impedance from
the VDD to the VR output. In addition, although adding more
stages of SDMT can increase the output voltage and reduce
Fig. 3. Schematic of the proposed CMOS VR. the process dependence, it also increases power consumption,
area, and minimum operating voltage simultaneously. Based
III. D ESIGN OF THE P ROPOSED CMOS VR on these reasons, a two-stage SDMT architecture in the core
circuit is adopted in this design.
A. Operating Principle
In the proposed architecture, the current path and two
Fig. 3 illustrates the schematic of the proposed CMOS core paths have similar architecture (two PMOS and two
VR with self-biased feedback and capacitively coupled NMOS transistors). A self-bias current reference, as proposed
schemes, and the design parameter is shown in Table I. in [7], [17], and [18], is derived from SDMT output voltage
The core circuit is implemented with a two-stage SDMT through a feedback path (path 1). The high-impedance ele-
architecture. The transistors operate in the subthreshold region, ments composed of Mn5,6 and Mp3,4 suppress the effect of sup-
and their bias currents (Ip1 and Ip3 ) are mirrored from the ply variation, resulting in supply-independent bias current. The
bias current source, Ip5 . Thus, the output voltage Vref can be core generation current is the drain current of Mn6 . The self-
derived as biasing architecture requires startup circuits to avoid the zero-
   
2μn1 Coxn1 W n1 L n2 m n1 current condition. However, the startup circuit may increase
Vref = m n1 VT ln + VTHn2 − VTHn1
μ C W L m the leakage current, which is detrimental to the TC and
 n2 oxn2 n2 n1   n2  power consumption of VR. Therefore, this design adopts the
μn3 Coxn3 W n3 L n4 m n3
+ m n3 VT ln + VTHn4 −VTHn3 self-biasing feedback loop (path 2). The bias voltage of Mp4
μ C W L m n4
  n4 oxn4  n4 n3  and Mp6 is generated from the source voltage of Mn6 and Mn4 ,
m n1 m n3
+ 1− VGn2 + 1 − VGn4 . (6) respectively. Since Mn4 and Mn5 have similar gate voltages,
m n2 m n4 the source voltages are, thus, similar when the current mirror
From (6), the temperature-independent Vref is obtained by replicates the bias current. At power-up, the low voltages at
selecting the size of the transistors and the difference of nodes A and B activate the PMOS transistors, providing a
the threshold voltage, and is insensitive to the bias current. current path from the supply to ground. Note that the feedback
Note that the SDMT structure has a reduced slope of TC loop directly drives the gate of transistors so that there is no

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SHAO et al.: CMOS VR WITH SELF-BIASED FEEDBACK AND CAPACITIVELY COUPLED SCHEMES 5

Fig. 5. Results of the Monte Carlo simulation with process variation and
mismatch.

loading effect that may cause extra current and voltage drops to
the original core circuit. The feedback loop also helps stabilize
the supply-caused fluctuation in the bias current and creates
a large output impedance. Instead of the auxiliary bias circuit
or amplifier, the gate bias voltages of Mp4 and Mp6 are set by
VB and VA , respectively, without the extra power consumption
and silicon area. Therefore, the circuit is made to further
reduce the process variations by using the replica-biasing
architecture that tracks the changes in process parameters.
Fig. 5 shows the results of the Monte-Carlo simulation with
process variations and mismatch. In the 1000 runs, the mean
value of the output voltage is 260 mV, while the standard
deviation is 17.5 mV. Fig. 6. Simulated results of the voltage transients at VC and VD (a) without
C1,2 and (b) with C1,2 .

B. Startup Enhancement C. PSRR Analysis

The self-biased feedback also ensures the startup of the The analysis in Section II characterizes the LS to the power
VR. When the power is switched ON, VA ,B in the low-voltage supply. In order to boost the output impedance of the current
state turns on the circuit quickly. Then, VB is decreased by source, the bias voltage of the cascode current mirror circuit is
the cross-coupled loop, thereby avoiding the zero-current generated from the core of the VR and its replica bias circuits,
condition. The embedded feedback without auxiliary elements forming feedback loops. The LS improvements using SDMT
eliminates the leakage from the startup circuits that could schemes only benefit the low-frequency PSRR. In order to
enlarge power consumption and deteriorate the TC in extend the bandwidth, a zero-transport technique is proposed
low-power VR designs. Although the self-biased structure in this design. A simplified model is shown in Fig. 8, where
guarantees the normal operation of the circuit, due to the low RS , R1 , and R2 represent the resistances of the current sources,
power consumption, the startup speed is still limited to tens and C1 and C2 are the effective capacitances seen by R1 and
of milliseconds. As for the startup time improvement, two R2 , respectively. Before adding C2 , the main path from VDD to
capacitors, C1 (45 fF) and C2 (450 fF), are added from nodes Vref is composed of R1−2 –C1 –Mn1−4 , and its transfer function
C to D and E (see Fig. 3), respectively, coupling the fast can be characterized as follows:
signal changes from the supply voltage to the core circuit. The Vref,main As+B
simulated results of the design with and without C1 and C2 are (s) ∼
=  C 
 (7)
VDD s 1
+ 1 + Rs C  + 1
C
shown in Fig. 6(a) and (b). With C1 and C2 , the settling time gm,n4 gm,n2 1
at nodes C and D decrease from 35 to 0.5 ms. Owing to the C1 C1 
C1
cross-coupled structure, a capacitor (C3 = 1.2 pF) is added to A= − + (7-a)
gm,n4 gm,n3 gm,n2
reduce the overshooting ripples at node B, thereby improving 1 1 1
the settling speed. Fig. 7(a) and (b) shows the simulation B= − +
gm,n4 R1 gm,n3 R1 gm,n2 R1
results of the startup improvement using the capacitively 1 1
coupled technique. In this work, C1,2 creates the lead and + − . (7-b)
gm,n2 R2 gm,n1 R2
lag paths from the supply to Vref , respectively, which also
helps the PSRR enhancement. The analysis is discussed in As seen in (7), by setting B to zero, the LS (at dc) is nulled;
Section III-C since the fluctuations from supply through Mn1−2 and Mn3−4

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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 9. Simulated LS versus R1 /R2 ratio of the schematic in Fig. 8 excluding

C2 .

between the LS and bandwidth set by the ratio of B/A.

Fig. 10 shows the simulated PSRR according to the ratio of
R1 and R2 . The flattened PSRR bandwidth increases, while
the ratio deviates from the optimal value (k) for LS.
In order to extend the bandwidth while maintaining a good
LS, C2 is added, and the transfer function of Vref /VDD becomes
Vref
(s)
VDD
Ds 2 + Es + F
=      
Rs C1 C2 Rs C1 C2 C  +C 
+ g1m,n2 2 + Rs C1 + C2 +1
C1
s2 gm,n1
+ gm,n4
+s gm,n4
(9)
Fig. 7. Simulated results of the voltage transients at VA and VB (a) without C1 C2 C1 C2 C1 C2
C3 and (b) with C3 .
D= + − (9-a)
gm,n1 gm,n2 gm,n2 gm,n4 gm,n1 gm,n3
C1 C1 C1 C2 C2
E= − + + − (9-b)
gm,n4 gm,n3 gm,n2 gm,n2 gm,n1
1 1 1 1 1
F= − + + − .
gm,n4 R1 gm,n3 R1 gm,n2 R1 gm,n2 R2 gm,n1 R2
(9-c)

The auxiliary path created by C2 makes the transfer func-

tion a second-order system. When the value of C2 changes,
the weights of the two paths change correspondingly, leading
to the change of zero location. By setting E = 0, a pair of pure
imaginary zeros is generated, resulting in a notch response.
Fig. 11 shows the simulated results of bandwidth at various
C2 /C1 . From the plot, the bandwidth is maximal when the ratio
equals k. Therefore, the PSRR bandwidth and LS optimization
are achieved simultaneously. Note that the optimal value is
Fig. 8. Simplified model of the proposed VR circuit. changed due to the leakage increases at high temperature,
breaking the assumption of ID3 = ID4 . From the simulation,
are opposite phases so that their contributions are canceled at in the temperature from −40 ◦ C to 100 ◦ C, the optimal value
the output, while their magnitudes are equal. The minimum increases from 1.73 to 1.84 and becomes 2.78 at 130 ◦ C.
value occurs when the ratio of R1 and R2 is derived To obtain more insight, we analyze this system from an
intuitive perspective. When the zeros move to the imaginary
  1
− g1 + g1
R1 g axis, C1 and C2 create the lead and lag paths from VDD to
= m,n4 1 m,n3 1 m,n2 = k. (8) Vref , respectively. As per the phase analysis, the phases start
R2 opt gm,n1
− gm,n2
to split at 0.1× zero frequency ( f z ), and the phase difference
The result is also verified by the simulation. Fig. 9 shows reach 180◦ at 10 × f z , thus extending the bandwidth.
the simulated results of the LS versus R1 /R2 ratio. The LS Fig. 12 shows the simulated PSRR of the proposed design
achieves its minimum at an optimal R1 /R2 ratio, which is in Fig. 3. Although the parasitics on the paths diminish the
1.78 in this design. However, there is a fundamental tradeoff notch response, the bandwidth can be extended to around

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SHAO et al.: CMOS VR WITH SELF-BIASED FEEDBACK AND CAPACITIVELY COUPLED SCHEMES 7

Fig. 10. Simulated PSRR over R1 /R2 of the schematic in Fig. 8

excluding C2 .

Fig. 11. Simulated bandwidth over the C2 /C1 ratio of the schematic in Fig. 8.

10 × f z without increasing power consumption. The bandwidth

relies on the parameters of active devices, which may cause
variations in the implementation. From the Monte Carlo
simulation, the average PSRR bandwidth is 200 Hz with
the standard deviation of 180 Hz, and 85% runs have their
bandwidth larger than 50 Hz in 100 runs. This design can
suppress the primary 50–60-Hz interference without external
large load capacitance. Fig. 12. Simulated frequency response from the supply to the output of
(a) magnitude, (b) phase, and (c) PSRR of the proposed design in Fig. 5.
IV. M EASUREMENT R ESULTS
The proposed CMOS VR is fabricated using 180-nm
technology. Fig. 13 shows the chip micrograph. The active
area is 5900 μm2 . The chip was first mounted on a PCB
for characterization. Fig. 14 plots the measured Vref over
the temperature across fifteen chips. Without trimming,
the TC ranges from 35 to 108 ppm/◦C in the temperature
range of −40 ◦ C to 130 ◦ C, and the resulting average TC is
62 ppm/◦ C. Fig. 15 shows the statistics of the output voltage
of the 15 chips in the same wafer. The average output voltage
Fig. 13. Micrograph of the proposed CMOS VR.
is 0.261 V at 20 ◦ C, the standard deviation is 1.11 mV,
and 3σ accuracy is 0.43%. The operating current at room
temperature is 2 nA under a 0.9-V supply voltage, resulting improvement of 274× when compared to the design without
in a power consumption of 1.8 nW. C1−3 , and the power consumption is only 3 nW at the startup
Fig. 16 shows the measured results of the startup time. The state. The measured settling time at 20 ◦ C and −40 ◦ C is
design with and without the capacitively coupled schemes is ∼0.2 and ∼2 ms, respectively. Fig. 17 shows the measured
fabricated in the same chip. Without the enhancement scheme, results of the LS. When the power supply changes from 0.9 to
the startup time is around 55 ms. The proposed enhancement 1.8 V, the output voltage slightly drifts 0.03 mV, and thus,
scheme improves the 1% settling time to 0.2 ms, showing an the resulting LS is 0.013%/V. The LS among five chips is

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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 14. Measured output voltage from −40 ◦ C to 130 ◦ C over 15 samples.

Fig. 15. Measured output voltage distribution over 15 samples.

from 0.013%/V to 0.033%/V. The measured PSRR is shown

in Fig. 18. The PSRR is characterized by using the vector
network analyzer. The bandwidth of the design without C1−3
is about 30 Hz. With C1−3, the PSRR is −75.3 dB at dc
and −73.5 dB at 100 Hz without any decoupling capacitor
at the output. With the proposed schemes, the bandwidth
can be extended to 100 Hz for suppressing the 50–60-Hz Fig. 16. Measured startup time (a) w/ and w/o C1−3 , (b) w/ C1−3 at 20 ◦ C,
and (c) at −40 ◦ C (five chips).
power-supply interference.
Table II provides a performance comparison of low-power
reference circuits in recent years. From the comparison table,
the temperature stability of the CMOS-only VR is usually
worse than that of the BGR type. The CMOS VRs usually
require trimming to achieve a TC of less than 100 ppm/◦ C.
However, the temperature range of the nanowatt VRs is usually
limited. This work can operate in a wide temperature range
of 170 ◦ C while keeping the TC below 100 ppm/◦ C. Similar
to [7], the SDMT architecture can reduce the process variation
in terms of the differential threshold voltage. This work, using
two-stage SDMT and slope factor sizing, can further reach a
3σ accuracy of 0.43%. The design in [18] achieves a PSRR Fig. 17. Measured LS.
of −62 dB at 100 Hz and a startup time of 3.2 ms, and the
lowest TC after trimming. Compared with [7], [8], and [15], consumes 20× more power than the proposed design because
our design has much lower power consumption, and it can it requires a voltage regulation loop and trimming elements.
significantly reduce the startup time. A startup time of less As a consequence, the proposed design adopting an SDMT
than 1 ms is achieved in [14], but the design consumes more structure can reduce the PVT dependence with accurate sizing
than 50 μW in the startup phase. As per the PSRR results, of the devices. The proposed capacitively coupled scheme can
the design improves the PSRR approximately 20–30 dB at improve the startup time and bandwidth of PSRR at a sacrifice
100 Hz. Although the design in [13] can attain a similar of the increased minimal supply voltage and overhead area
PSRR at 100 Hz, it occupies a 5.7× larger chip area and from the coupling capacitance.

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SHAO et al.: CMOS VR WITH SELF-BIASED FEEDBACK AND CAPACITIVELY COUPLED SCHEMES 9

TABLE II
P ERFORMANCE S UMMARY AND C OMPARISON W ITH O THER W ORKS

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10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

[18] Y. Wang, Q. Sun, H. Luo, X. Wang, R. Zhang, and H. Zhang, Shih-Che Kuo (Graduate Student Member, IEEE)
“A 48 pW, 0.34 V, 0.019%/V line sensitivity self-biased subthreshold received the B.S. degree from the Department
voltage reference with DIBL effect compensation,” IEEE Trans. Circuits of Electrical and Computer Engineering, National
Syst. I, Reg. Papers, vol. 67, no. 2, pp. 611–621, Feb. 2020. Chiao Tung University, Hsinchu, Taiwan, in 2019,
[19] J. M. Lee et al., “A 29nW bandgap reference circuit,” in IEEE Int. where he is currently pursuing the M.S. degree.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, San Francisco, His research interests include low-power RF cir-
CA, USA, Feb. 2015, pp. 1–3. cuit and sensor interface design.
[20] K. K. Lee, T. S. Lande, and P. D. Hafliger, “A sub-μW bandgap reference Mr. Kuo received the NOVATEK Fellowship
circuit with an inherent curvature-compensation property,” IEEE Trans. in 2020. He is a member of Phi-Tau-Phi.
Circuits Syst. I, Reg. Papers, vol. 62, no. 1, pp. 1–9, Jan. 2015.
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all-in-one bandgap voltage and current reference circuit,” in IEEE Int.
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CA, USA, Feb. 2017, pp. 100–101.
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voltage reference without requiring resistors or BJTs,” IEEE Trans. Very
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[24] C.-J. Huang et al., “A 4.2 nW and 18 ppm/◦ C temperature coeffi-
cient leakage-based square root compensation (LSRC) CMOS voltage
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[25] M. Eberlein, G. Panagopoulos, and H. Pretl, “A 40nW, sub-IV truly Yu-Te Liao (Member, IEEE) received the B.S.
‘digital’ reverse bandgap reference using bulk-diodes in 16nm FinFET,” degree in electrical engineering from National Cheng
in Proc. IEEE Asian Solid-State Circuits Conf. (A-SSCC), Nov. 2018, Kung University, Tainan, Taiwan, in 2003, the M.S.
pp. 99–102. degree in electronics engineering from National Tai-
wan University, Taipei, Taiwan, in 2005, and the
Ph.D. degree in electrical engineering from the Uni-
Cheng-Ze Shao (Student Member, IEEE) received versity of Washington, Seattle, WA, USA, in 2011.
the B.S. degree in electronic and computer engi- In August 2011, he joined the Electrical Engineer-
neering from the National Taiwan University of ing Department, National Chung Cheng University,
Science and Technology, Taipei, Taiwan, in 2018. Chiayi, Taiwan, as an Assistant Professor. He is cur-
He is currently pursuing the M.S. degree with the rently an Associate Professor with the Department
Department of Electrical and Computer Engineering, of Electrical and Computer Engineering, National Chiao Tung University,
National Chiao Tung University, Hsinchu, Taiwan. Hsinchu, Taiwan. His research interests are the design of low-power RF
His research focuses on low-power analog circuit integrated circuits, integrated sensors, and biomedical circuits and systems.
and sensor interface design. Dr. Liao was a co-recipient of the Best Paper Award of IEEE VLSI-DAT
Mr. Shao received the NOVATEK Fellowship Conference in 2019. He has been an Associate Editor of IEEE S ENSORS
in 2020. He is a member of Phi-Tau-Phi. J OURNAL since 2017.

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