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IEEE JOURNAL OF SOLID-STATE CIRCUITS 1

Fully Integrated Switched-Inductor-Capacitor

Voltage Regulator With 0.82-A/mm2 Peak Current
Density and 78% Peak Power Efficiency
Nghia Tang, Member, IEEE, Wookpyo Hong , Member, IEEE, Bai Nguyen , Member, IEEE,
Zhiyuan Zhou, Member, IEEE, Jong-Hoon Kim, and Deukhyoun Heo , Senior Member, IEEE

Abstract— Fully integrated voltage regulators (FIVRs) can

improve the performance and reduce the power consumption
of a system-on-chip (SoC) by providing point-of-load voltage
regulation with dynamic voltage scaling. The desirable attributes
of FIVRs include high power efficiency, high power density,
and fast transient response, which are difficult to achieve due
to on-chip area constraint and parasitic effects. Low-quality
and low-density on-chip inductors and capacitors are currently
the main performance-limiting factors. This article presents a Fig. 1. Basic buck converter.
switched-inductor-capacitor (SIC) voltage converter that can
operate more efficiently with compact on-chip air-cored metal-
tracked inductors than existing step-down voltage converters. The
SIC converter consists of an inductor, a flying capacitor, and three desirable attributes of FIVRs include high power efficiency,
power switches, and it can provide fine-grained voltage regulation high power density, and fast transient response. FIVRs can be
by using pulsewidth-modulation (PWM) control. The unique linear or switching. A linear regulator can have high power
SIC converter topology eases the on-chip inductor integration density and fast transient response, but its power efficiency
by positioning the inductor at the input power supply and
is inherently limited by the voltage conversion ratio (VCR),
reducing the current stress of the inductor. A proof-of-concept
fully integrated SIC voltage regulator is fabricated in a 65-nm i.e., the ratio of the output voltage to the input voltage,
CMOS process, with an area of 1.3 mm × 0.5 mm excluding VOUT /VIN [1]. Thus, linear regulators are not suitable for appli-
pads. The output voltage can be regulated from 0.6 to 0.9 V cations where the VCR is small or dynamically changes over a
given a 1.2-V input power supply. The output voltage ripple is wide range. In contrast, switching regulators can be designed
below 56 mV over the entire range of output voltages and load
with high power efficiency across a wide range of output
currents. The peak power efficiency is 78% at an output of 0.9 V
and 406 mA. The peak power density is 730 mW/mm2 , and the voltages, but they suffer from performance degradation when
peak current density is 820 mA/mm2 . being fully integrated due to the on-chip area constraint and
Index Terms— Buck converters, fully integrated voltage regu-
parasitic effects [7]. Specifically, low-quality and low-density
lators (FIVRs), on-chip inductors, switched-capacitor (SC) con- on-chip passive components, i.e., inductors and capacitors, are
verters. currently the main performance-limiting factors of switching
FIVRs.
Two commonly used switching regulators for step-down
I. I NTRODUCTION voltage conversion are switched-inductor (SI) buck converters
and switched-capacitor (SC) converters. Fig. 1 shows a basic
F ULLY integrated voltage regulators (FIVRs) can improve
the performance and reduce the power consumption of a
system-on-chip (SoC) by providing point-of-load voltage reg-
SI buck converter. A pulsewidth-modulation (PWM) signal
with a frequency f SW and a duty cycle D is used to control
ulation with dynamic voltage scaling capability [1]–[3]. The the power switches, and the resulting PWM voltage waveform
at VX is filtered by an LC low-pass filter to produce a low-
Manuscript received June 13, 2020; revised August 25, 2020 and Octo- ripple output voltage VOUT . The VCR can be changed by
ber 15, 2020; accepted October 25, 2020. This article was approved by
Associate Editor Piero Malcovati. This work was supported in part by Intel adjusting the duty cycle. Ideally, for continuous-conduction
Corporation and in part by the Korea Food Research Institute (KFRI) under mode (CCM), the VCR is equal to the duty cycle D, and
Grant E0162502. (Corresponding author: Deukhyoun Heo.) the power efficiency is 100% for the entire range of VCRs
Nghia Tang, Wookpyo Hong, Bai Nguyen, Zhiyuan Zhou, and
Deukhyoun Heo are with the Department of Electrical Engineering and from 0 to 1. In practice, the power loss of the inductor and
Computer Science, Washington State University, Pullman, WA 99164 USA the power switches limits the achievable power efficiency.
(e-mail: [email protected]; [email protected]; [email protected]; If the converter is operated in CCM with a triangular current
[email protected]; [email protected]).
Jong-Hoon Kim is with the Korea Food Research Institute, Jeollabuk 55365, waveform through the inductor, the conduction loss of the
South Korea (e-mail: [email protected]). inductor can be estimated as [1]
Color versions of one or more of the figures in this article are available
online at https://ieeexplore.ieee.org. I L2
Digital Object Identifier 10.1109/JSSC.2020.3036394 PL ,LOSS ≈ I L2 ,dc R L ,dc + R L ,ac (1)
12
0018-9200 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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2 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 2. Basic 2:1 SC converter.

Fig. 3. Basic 3-level converter.

where I L ,dc is the average inductor current, I L is the peak-

to-peak inductor current ripple, R L ,dc is the dc resistance
of the inductor, and R L ,ac is the resistance of the inductor
at the frequency of the current ripple. The average inductor
current I L ,dc is equal to the output current IOUT , where IOUT
= VOUT /RLOAD . The peak-to-peak inductor current ripple can
be estimated as
D(1 − D)VIN
I L = . (2)
f SW L
An inductor with large inductance and small resistance
is desirable for high power efficiency, but it is difficult to
integrate on chip due to area constraint and parasitic effects.
Various techniques have been used to design on-chip inductors,
such as air-cored metal-tracked inductors [1], [4], [5], [7],
[12]–[14], bond-wire inductors [15]–[17], silicon-embedded
inductors [18], magnetic-cored inductors [19], [20], and glass-
substrate-integrated inductors [21]. Air-cored metal-tracked
inductors are an economical choice because they use the back-
end-of-line (BEOL) metal layers available in a standard fab-
rication process. However, the BEOL limitations, such as no
magnetic material, low metal thickness, and planar 2-D struc- Fig. 4. SIC regulator with VCR from 1/2 to 1.
ture, hinder the performance of metal-tracked inductors. This
type of inductors typically has inductance ranging from hun-
dreds of pH to tens of nH and resistance on the order of hun- Hybrid converter topologies that combine the advantages of
dreds of m. High switching frequencies (close to 100 MHz SI converter and SC converter have captured great attention
and beyond) are often used to reduce the current ripple of such recently. For example, input-passive-stacked third-order buck
small inductors [1], [4], [5], [7], [13]–[16], [18]–[22], at the converter [29] and flying-inductor hybrid converter [30]–[32]
cost of higher switching loss. have been shown to produce a continuous range of VCR
An SC converter is conventionally designed to provide a and demonstrated unique characteristics and benefits. How-
fixed VCR. The operation is based on using flying capacitors ever, these converters have not been considered to improve
to move charge and energy from the input power supply the performance of FIVRs. Fully integrated resonant hybrid
to the load. For example, Fig. 2 shows a 2:1 SC converter converters [10], [11] have shown great efficiency, but they
that produces a VCR of 1/2 by periodically switching the use relatively large inductors, resulting in low power density.
flying capacitor CFLY between series connection and parallel Another example is the fully integrated three-level converter
connection with the output capacitor COUT . Multiple SC [1], which combines the characteristics of a 2:1 SC converter
converter topologies can be merged to form a reconfigurable and a SI buck converter, as shown in Fig. 3. The power
SC converter to produce multiple VCRs for a wide range of switches are controlled by a PWM signal with a frequency
output voltages. For example, Le et al. [23] presented an SC f SW and a duty cycle D, and the resulting PWM voltage
converter that can reconfigure to three different topologies waveform at VX is filtered to produce a low-ripple output
that have VCRs of 1/3, 1/2, and 2/3. Reconfigurable SC voltage VOUT . The VCR can be changed by adjusting the duty
converters with higher numbers of VCRs have been presented, cycle, and the average inductor current I L ,dc is equal to the
but the numbers of power switches and flying capacitors grow output current IOUT , as the basic buck converter in Fig. 1.
quickly and result in larger power loss and lower power However, the voltage VX swings between VIN and VIN /2 or
density [24]–[27]. Short-channel transistors and high-density between VIN /2 and GND at a frequency of 2 × f SW , resulting
capacitors in advanced process technologies are often used to in a lower inductor current ripple. The inductor current ripple
improve the performance of reconfigurable SC converters [28]. can be estimated as (3) for 0 < D < 0.5 and (4) for

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TANG et al.: FULLY INTEGRATED SIC VOLTAGE REGULATOR 3

0.5 < D < 1

D(1 − 2D)VIN
I L = (3)
2 f SW L
(2D − 1)(1 − D)VIN
I L = . (4)
2 f SW L
Compared with the basic SI buck converter, which will sim-
ply be called the buck converter from this point on, the three-
level converter has lower power loss due to its smaller inductor
current ripple. Alternatively, it can use a smaller inductor,
which has lower dc resistance, to have lower dc loss. However,
it should be noted that the three-level converter has twice the
number of power switches that contribute to switching loss Fig. 5. Inductor current ripple of the three converters at the same VIN and
and conduction loss. Therefore, the decrease in the inductor’s f SW .
power loss may be offset by the increase in power loss of the
power switches.
From (5)–(8), the relationship between VOUT and VIN can
In this article, we demonstrate a fully integrated switched-
be expressed as
inductor-capacitor (SIC) hybrid converter that can work more
efficiently with a compact on-chip air-cored metal-tracked VOUT 1
= . (9)
inductor than the existing step-down voltage converters. The VIN 2− D
SIC converter operates with one inductor and one flying Thus, the SIC converter can change its VCR from 1/2 to
capacitor. Using PWM control, the SIC converter can finely 1 by controlling the duty cycle D from 0 to 1 (excluding
change its VCR between 1/2 and 1, thus avoiding the use 0). Because the input power must ideally equal to the output
of many flying capacitors in contrast to a reconfigurable SC power, the average inductor current I L ,dc , which is also the
converter. Compared with the buck converter and the three- average input current, is related to the output current IOUT by
level converter, the SIC converter can use an on-chip air-cored
metal-tracked inductor more efficiently. Because the inductor VOUT IOUT
I L ,dc = . (10)
of the SIC converter is positioned at the input power supply, VIN
the average inductor current is reduced for lower conduction Practically, I L ,dc is greater than the ideal value expected
loss, and only three power switches are used to keep area in (10), due to power loss in the system. From (5) and (9),
and power overheads small. The SIC converter is described, the peak-to-peak amplitude of the inductor current ripple can
analyzed, and compared with the buck converter and the three- be estimated as
level converter in Section II. The design of a fully integrated D(1 − D)VIN
SIC voltage regulator is described in Section III. Validation of I L = . (11)
(2 − D) fSW L
the design is presented in Section IV, and Section V provides
concluding remarks.
B. Comparison With the Buck Converter and the Three-Level
II. S WITCHED -I NDUCTOR -C APACITOR C ONVERTER Converter
A. Fundamental Operating Characteristics We compare the performance metrics of the proposed SIC
Fig. 4 shows a basic topology of the SIC converter. The converter with those of the buck converter and the three-level
core devices include inductor L, flying capacitor CFLY , output converter by considering the power loss of the inductors and
capacitor COUT , and three power switches controlled in two the power switches. The inductors have conduction loss arising
phases by a PWM signal with frequency f SW and duty from the average current (I L ,dc ) and current ripple (I L ). The
cycle D. power switches have both conduction loss and switching loss.
In phase 1, switches 1HI and 1LO are turned on for To simplify the comparison, it is assumed that the three voltage
a duration of D/ f SW , and current I L through inductor L converters use identical inductors and the same type of power
increases by I L1 . In phase 2, switch 2 is turned on for a switches, i.e., NMOS transistors.
duration of (1 −D)/ f SW , and I L decreases by I L2 . By using The average inductor current I L ,dc equals the output current
the state-space averaging method [33], the following equations IOUT in the buck converter and the three-level converter.
can be written for the steady-state condition: In contrast, I L ,dc in the SIC converter is a scaled version of
IOUT by a factor equal to the VCR, according to (10). Thus,
(VIN − VOUT )D
I L1 = (5) when the VCR is smaller than 1, the inductor of the SIC
L f SW converter can have lower conduction loss than those of the
(VIN − VOUT − VFLY )(1 − D)
I L2 = (6) other two converters due to its lower average current.
L f SW Equations (2), (4), and (11) are plotted in Fig. 5 to compare
VOUT = VFLY (7) the inductor current ripples of the three voltage converters for
I L1 + I L2 = 0. (8) VCRs between 1/2 and 1, given the same supply voltage VIN

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4 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 6. Inductor current ripple when the buck converter and the SIC converter Fig. 8. Simulated average inductor current.
switch 4× and 2.74× faster than the three-level converter, respectively.

Fig. 9. Simulated power loss of the inductor.

Fig. 7. Simulated inductor current ripple peak-to-peak amplitude.

and switching frequency f SW . The three-level converter has the

lowest peak inductor current ripple, which is about 4× smaller
than that of the buck converter and 2.74× smaller than that of
the SIC converter. Therefore, it can have the lowest ac power
loss from the current ripple. However, it is possible to make
the peak inductor current ripple the same for the three voltage
converters by switching the buck converter 4× faster and the
SIC converter 2.74× faster than the three-level converter. For
example, if the three-level converter is operated at f SW , then
the buck converter can be operated at 4× f SW , and the SIC
converter can be operated at 2.74 × f SW . Fig. 6 compares Fig. 10. Simulated power loss of switch drivers.
the inductor current ripples of the three voltage converters in
such conditions. Note that the inductor current ripples of the
three voltage converters peak at different VCRs. The SIC and converter for the same conduction loss. In that case, compared
the three-level converters have similar current ripple across the to the buck converter, the three-level converter has twice the
VCR range, and therefore, they can have similar ac power loss number of power switches, each with twice the size, and thus
from the current ripple. four times larger capacitance to drive.
Although the three-level converter can switch at a lower For comparison, the three voltage converters are simulated
frequency than the other two converters, it does not necessarily with the same supply voltage of 1 V and the same load
have the lowest switching loss. In the three-level converter, any of 2.5  over a range of VCR. They all use the same
current paths include three resistive elements in series, i.e., inductor with 1-nH inductance and 400-m dc resistance.
two power switches and one inductor. In contrast, any current An electromagnetic solver is used to model the inductor’s
paths in the buck converter and the SIC converter include two high-frequency characteristic. To limit the maximum inductor
resistive elements in series, i.e., one power switch and one current ripple below 0.4 A, the theoretical frequency choices
inductor, or two power switches. Thus, the power switches in for the buck converter, the three-level converter, and the SIC
the buck converter and the SIC converter can be sized smaller converter are 657, 164, and 450 MHz, respectively. However,
than those in the three-level converter. Each power switch in in simulation, the peak current ripple of the SIC converter
the buck converter can be half the size of that in the three-level is 0.42 A, and the frequencies of the buck converter and the

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TANG et al.: FULLY INTEGRATED SIC VOLTAGE REGULATOR 5

TABLE I
PARAMETERS U SED IN S IMULATION

Fig. 11. Simulated ID∗VDS loss of switches. The simulated average inductor currents (I L ,dc ) are shown
in Fig. 8, where the SIC converter has lower I L ,dc than the
other two converters. Note that at VCR = 0.5, I L ,dc of the SIC
is slightly higher than the ideal value predicted by (10) due to
power loss in the system. The power losses of the inductors
are compared in Fig. 9, showing a considerably lower loss
for the SIC converter. At VCR = 0.5, the inductor power
loss of the SIC is 12 mW and 10 mW lower than that of
the buck and the three-level converters, respectively. For VCR
< 0.55, the buck converter has slightly higher inductor loss
than the three-level because its inductor current ripple is larger.
The simulated power losses of the switches, including driver
loss and ID∗VDS loss, are shown in Figs. 10 and 11. The
ID∗VDS loss is obtained from the drain currents and drain–
Fig. 12. Simulated power efficiency of the three converters. source voltages of all the switches. The difference in switch
driver losses of the three converters is relatively small, less
2 mW, which is expected from the frequency choice and the
number of switches of each converter. The ID∗VDS loss of the
SIC converter is relatively higher, especially at lower VCRs,
which is also expected. Because the switches of the buck
converter and the three-level converter are placed at the input,
their conduction losses are smaller, for the same reason that
the SIC converter has smaller inductor power loss. In other
words, the SIC converter places more burden on the switches;
however, since the switches can easily be made with lower
resistance than the inductor, the SIC converter has lower total
power loss than the other two converters. Fig. 12 compares the
power efficiency, which is calculated by dividing the output
power by the input power. The input power accounts for all
Fig. 13. Simulated efficiency with CFLY_BOT loss.
forms of power losses in the system. The three-level converter
has better power efficiency than the buck converter at VCR
= 1/2 because it has much smaller inductor current ripple
three-level are increased to 900 and 195 MHz, respectively, at this VCR. This observation is very similar to the result
to have peak current ripple equal to that of the SIC, as shown reported in [1] and consistent with the inductor loss result
in Fig. 7. All power switches are implemented by NMOS in Fig. 9. On the other hand, the SIC converter has better power
transistors in a 65-nm CMOS process, and the NMOS power efficiency than the other two converters at any VCR between
switches in the three-level converter have twice the width 1/2 and 1. Depending on the process technology, the flying
of those in the other two converters. The switches are sized capacitor can introduce additional power loss from its bottom
such that their switching loss and conduction loss are similar plate capacitance (CFLY_BOT ). The metal–oxide–semiconductor
over the operating range of interest. The parameters of the (MOS) capacitor of the process technology used for this work
components used in the experiment are shown in Table I. The has a 2% bottom-plate capacitance. If MOS capacitors are used
inductor’s ac resistance (ACR) at the corresponding switching for the flying capacitors in the three-level converter and the
frequency of each converter is also shown. Because the fre- SIC converter, a decrease in their power efficiency is observed
quency of the inductor current in the three-level converter is in Fig. 13. Because the bottom-plate loss of the SIC converter
twice the switching frequency, the inductor’s ACR is quoted increases with VOUT , the SIC’s power efficiency is lower than
at 390 MHz. that of the other two converters at higher VCRs. It is also worth

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6 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 14. Schematic of the fully integrated SIC voltage regulator. The arrows indicate a positive current direction through the inductor and power switches.

Fig. 16. Simulated gate drive signals of the switches at VOUT = 700 mV.

Fig. 15. Layout and extracted characteristics of the on-chip inductor.

error amplifier (Error Amp) with output capacitor Co, which
forms an integrator, a comparator (CMP), a non-overlap signal
noting that if the inductor is implemented by an advanced generator, a charge pump, a level shifter, and inverter-chain
technology that has lower resistance, the SIC converter may drivers for the power switches. The error amplifier integrates
lose its efficiency advantage because the power loss of the the difference between output voltage VOUT and reference
inductor becomes nondominant among other forms of power voltage VREF . From the integrated error signal and a 450-MHz
losses in the system. ramp signal, the comparator outputs a PWM signal to drive
the power switches such that VOUT is regulated to match VREF .
III. F ULLY I NTEGRATED SIC VOLTAGE R EGULATOR The inductor is fully integrated on chip by using the top
A fully integrated prototype is designed in a 65-nm CMOS copper layer of the process and has a planar spiral octagonal
process to prove the operation of the proposed SIC converter. structure, as shown in Fig. 15. To save area, the inductor is
Fig. 14 shows the schematic/block diagram of the fully inte- placed above the flying capacitor CFLY . A patterned ground
grated SIC voltage regulator. To provide output voltage regu- shield is inserted between the inductor and CFLY to reduce
lation, a simple integral control system is used, including an noise coupling between the two components [34]. An electro-

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TANG et al.: FULLY INTEGRATED SIC VOLTAGE REGULATOR 7

Fig. 18. Simulated voltages of the flying capacitor and output capacitor.

Fig. 17. Simulated current through the switches and inductor. The polarity
of the currents follows the flow direction in Fig. 14.

Fig. 19. Simulated efficiency of the prototype chip.

magnetic field solver is used to characterize the inductor, and
the results are presented in Fig. 15, showing an inductance
of 0.85 nH and a resistance of 340 m at 450 MHz, giving
an equivalent Q factor of 7. The flying capacitor CFLY and
the output capacitor COUT are 1.72 and 3.1 nF, respectively,
created by MOS capacitors and metal–oxide–metal (MOM)
capacitors, with a total capacitance density of 10 nF/mm2 .
The substrate-coupling capacitance of the bottom plate of
CFLY is 30 pF. The power loss from switching this parasitic
capacitance at 450 MHz was found to be 4.8, 6.6, 8.6, and Fig. 20. Chip micrograph of the fully integrated SIC voltage regulator.
11 mW at VOUT = 600, 700, 800, and 900 mV, respectively,
which contributes to less than 20% of the total power loss.
Due to conduction loss of the inductor and power switches, giving a gate–source voltage of 1.2 V to turn on the power
VOUT = 600 mV can be produced with a duty cycle of 12%. switch. Practically, the charge pump voltage is lower when
Table II summarizes the characteristics of the on-chip inductor being loaded, and thus, M1 would not have the full 1.2 V to
and capacitors. turn on. As shown in Fig. 14, the charge pump is a single-stage
Power switches M1 and M2 are implemented by NMOS design operated by counter-phase signals S1 and S2 switching
transistors. Power switch M3 is implemented by a PMOS at 450 MHz, with a 36-pF flying capacitor and a 36-pF output
transistor to simplify the driver at the cost of efficiency. capacitor. The driver of M3 is operated between VOUT and
If M3 is implemented by an NMOS, a bootstrap driver would GND because M3 can be turned off when its gate voltage is
be needed. The drivers are implemented by tapered inverter equal to VOUT . The switching loss is thus smaller than it would
chains. The charge pump generates a voltage equal to VHI = be if the gate voltage were pulled up to VIN . It is worth noting
VIN + VOUT to ensure that power switch M1 is turned on with that if VOUT is near 0 V at start-up, M3 cannot be turned on
a sufficiently high gate–source voltage. For example, when because its gate voltage can only go as low as GND. However,
VOUT is 0.9 V, the gate of M1 can be pulled up to 2.1 V, the operation of M1 and M2 allows VOUT to rise initially, and

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8 IEEE JOURNAL OF SOLID-STATE CIRCUITS

Fig. 21. Measured power efficiency of the fully integrated SIC regulator.

Fig. 22. Load response at the 700-mV output voltage.

M3 becomes active when VOUT is higher than the threshold

voltage of the PMOS transistor, which is about 0.45 V in the
process being used. Therefore, the SIC voltage regulator does Fig. 23. (a) Response to reference change between 600 and 900 mV. (b)
not need an assisting circuit to start-up. Fig. 16 shows the Zoomed-in down transition. (c) Zoomed-in up transition.
simulated gate drive voltages of the power switches for the
case of 700-mV and 200-mA output. Note that M1 gate drive
TABLE II
signal swings between 700 mV, which is VOUT , and 1.6 V,
C HARACTERISTICS OF O N -C HIP I NDUCTOR AND C APACITORS
which is the charge pump’s loaded output voltage. Meanwhile,
M3 gate drive signal swings between ground and VOUT .
Figs. 17 and 18 show the simulated waveforms of important
current and voltage signals in the SIC converter. Fig. 19 shows
the simulated power efficiency across load current and output
voltage levels. The efficiency drops noticeably at 600 mV
because the gate drive voltage of M3 is reduced. The simulated
resistance of M3 is found to be 234 m at VOUT = 900 mV and
587 m at VOUT = 600 mV, versus 130 m for M1 and M2 .
Fig. 20 shows a micrograph of the fully integrated SIC
voltage regulator. The fabricated prototype chip has an area
of 1.3 mm × 0.5 mm, excluding the pads. Because the
inductor is placed above the capacitors, most of the chip area
is practically occupied by the capacitors. The chip could be
resistance and inductance. The extra inductance is estimated
more compact if it uses high-density capacitors, such as 200-
to be 100 pH based on the pin specification. Each pin has
fF/μm2 deep-trench capacitors [28].
a 100-nF decoupling capacitor. The load is implemented on
chip as a voltage-controlled current source. The controlling
IV. E XPERIMENTAL R ESULTS voltage is applied externally via a pin, and another pin is used
To validate the prototype, a 1.2-V input supply is applied to measure the actual loading current. The reference voltage
to the chip via five input pins, which is meant to reduce input is also applied externally via a pin.

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TANG et al.: FULLY INTEGRATED SIC VOLTAGE REGULATOR 9

TABLE III
C OMPARISON W ITH P REVIOUS F ULLY I NTEGRATED S TEP -D OWN V OLTAGE R EGULATORS

Fig. 21 shows the measured power efficiency (ηsw ) of the

fully integrated SIC regulator across different output voltages
and load currents. The power efficiency drops at light loads
due to switching loss and at high loads due to conduction loss.
Compared to the simulated results, the measured efficiency at
600 and 700 mV or at high loads is much lower. This could
be due to switch M3 having an actual threshold voltage higher
than modeled. Thus, at low output voltages, M3 is not fully
enhanced, resulting in a higher channel resistance. The dashed
lines (1)–(4) show the power efficiencies (ηlinear ) of an ideal
low-dropout (LDO) linear regulator at 0.6, 0.7, 0.8, and 0.9 V,
respectively. In practice, a switching regulator should only be
used if it provides better power efficiency than an LDO does.
At each output voltage level, there is a finite range of load Fig. 24. Measured output voltage ripple at different VOUT .
currents where the fully integrated SIC regulator outperforms
an ideal LDO. The efficiency enhancement factor, defined in
[7] as EFF = 1 – ηlinear /ηsw , is calculated for each output inductor and switches. For example, at the 900-mV output,
voltage level by taking the peak efficiency. The values range when load current increases, the duty cycle must increase to
from 0.04 at 900 mV to 0.22 at 600 mV. compensate for IR drop, which leads to lower inductor current
The transient response to a load step measured at the ripple, according to Fig. 6, and lower output voltage ripple.
700-mV output is shown in Fig. 22. The settling time is Table III summarizes the performance of the SIC voltage
less than 1 μs, and the overshoot is less than 20%. The regulator. In comparison with existing FIVRs that use on-chip
large overshoot can be attributed to the fast slew rate of the air-cored metal-tracked inductors, the SIC voltage regulator
load current and the small output capacitor. Fig. 23 shows achieves favorable power efficiency, but it is not easy to make
the transient response to a reference voltage step between a fair comparison due to different process technologies. We
600 and 900 mV. The 10%–90% rising time of the output expect that the power switches implemented in a 65-nm CMOS
voltage is about 40 ns, which is equivalent to a voltage process would be better than those in a 130-nm CMOS process
slew rate of 7.5 V/μs. The settling time is about 300 ns. and worse than those in a 22-nm CMOS process. Nevertheless,
Fig. 24 shows the measured output voltage ripple, which is the SIC voltage regulator achieves a significant improvement
below 56 mV for the entire range of output voltages and load in power density and current density due to the unique
currents. The ripple trend can be explained by the variation converter topology rather than the advantages of advanced
of duty cycle versus load current due to resistance of the fabrication technology. The capacitance density in our 65-nm

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10 IEEE JOURNAL OF SOLID-STATE CIRCUITS

CMOS process turns out similar to the value reported for the [6] T. Jia and J. Gu, “A fully integrated buck regulator with 2-GHz resonant
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TANG et al.: FULLY INTEGRATED SIC VOLTAGE REGULATOR 11

[27] S. Y. Bang, D. Blaauw, and D. Sylvester, “A successive-approximation Zhiyuan Zhou (Member, IEEE) received the M.S.
switched-capacitor DC-DC converter with resolution of V-IN/2(N) for a degree in electrical engineering from The University
wide range of input and output voltages,” IEEE J. Solid-State Circuits, of Texas at Dallas, Richardson, TX, USA, in 2013.
vol. 51, pp. 543–556, Feb. 2016. He is currently pursuing the Ph.D. degree with
[28] S. Sanders, E. Alon, H.-P. Le, M. Seeman, M. John, and V. Ng, “The Washington State University, Pullman, WA, USA.
road to fully integrated DC-DC conversion via the switched-capacitor His research interests include on-chip power man-
approach,” IEEE Trans. Power Electron., vol. 28, no. 9, pp. 4146–4155, agement system and energy-harvesting system for
Sep. 2013. Internet-of-Things (IoT) devices.
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Dec. 2019.
[33] R. W. Erickson and D. Maksimovic, Fundamentals of Power Electronics,
2nd ed. Norwell, MA: Kluwer, 2001. Jong-Hoon Kim received the Ph.D. degree in bio-
[34] C. P. Yue and S. S. Wong, “On-chip spiral inductors with patterned mechatronics engineering from Sungkyunkwan Uni-
ground shields for Si-based RF ICs,” IEEE J. Solid-State Circuits, versity, Seoul, South Korea, in 1997.
vol. 33, no. 5, pp. 743–752, May 1998. He is currently a Principle Researcher of smart
distribution system with the Korea Food Research
Institute, Jeollabuk, South Korea.

Nghia Tang (Member, IEEE) received the B.S. and

the Ph.D. degrees in electrical engineering from
Washington State University, Pullman, WA, USA,
in 2009 and 2016, respectively. His doctoral research
primarily focuses on power management integrated
circuits.
He has been involved in the design of enve-
lope tracking supply modulators for power ampli-
fiers, fully integrated voltage regulators, and energy-
harvesting systems. He has served as an IC Design
Intern at several companies, including Tagore Tech-
nology, Silicon Labs, and Texas Instruments.

Wookpyo Hong (Member, IEEE) received the B.S.

degree in electrical and computer engineering from
Chungbuk National University, Cheongju, South Deukhyoun Heo (Senior Member, IEEE) received
Korea, in 2006. He is currently pursuing the Ph.D. the B.S.E.E. degree in electrical engineering from
degree in electrical engineering with Washington Kyoungpuk National University, Daegu, South
State University, Pullman, WA, USA. Korea, in 1989, the M.S.E.E. degree in electrical
His research interests include power management engineering from the Pohang University of Science
circuits, emphasizing on fully integrated voltage and Technology (POSTECH), Pohang, South Korea,
regulators, single-input–multiple-output voltage reg- in 1997, and the Ph.D. degree in electrical and
ulators, energy-harvesting systems, and sensor net- computer engineering from the Georgia Institute of
works. Technology, Atlanta, GA, USA, in 2000.
In 2000, he joined National Semiconductor Cor-
poration, where he was a Senior Design Engineer
involved in the development of silicon RFICs for cellular applications. Since
Bai Nguyen (Member, IEEE) received the B.S. 2015, he has been a Professor with the Electrical Engineering and Computer
degree in electronics and telecommunication from Science Department, Washington State University, Pullman, WA, USA. He
Vietnam National University, Hanoi, Vietnam, has primary been interested in RF/microwave/opto transceiver design based
in 2005, and the M.S. degree in electrical and com- on CMOS, SiGe BiCMOS, and GaAs technologies for wireless and wire-
puter engineering from Chungbuk National Univer- line data communications, batteryless wireless sensors and intelligent power
sity, Cheongju, South Korea, in 2008. He is currently management systems for sustainable energy sources, adaptive beamformer
pursuing the Ph.D. degree in electrical engineering for phased-array communications, low-power high-date-rate wireless links for
with Washington State University, Pullman, WA, biomedical applications, and multilayer module development for system-in-
USA. package solutions.
He was a Research Assistant with the Institute Dr. Heo has been a member of the Technical Program Committee of the
of Material Science, Vietnam Academy of Science IEEE Microwave Theory and Techniques Society (IEEE MTTS-S) Inter-
and Technology (VAST), a Design Engineer at Emerson Network Power, national Microwave Symposium (IMS) and the International Symposium
a Hardware Manager with Innova Electronics, and a Senior Researcher at of Circuit and Systems (ISCAS). He received the 2009 National Science
Viettel Research and Development Institute, Viettel Group. His research Foundation (NSF) CAREER Award. He has served as an Associate Editor for
interests include analog integrated circuit design for power conversion and the IEEE T RANSACTIONS ON C IRCUITS AND S YSTEMS —PART II: E XPRESS
management, emphasizing on high-efficiency switching regulator, fully inte- B RIEFS from 2007 to 2009 and the IEEE T RANSACTIONS ON M ICROWAVE
grated dc/dc converter, wireless power transfer, and energy harvesting. T HEORY AND T ECHNIQUES .

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