TMP 1826

TMP1826
SBOSA45B – FEBRUARY 2022 – REVISED DECEMBER 2022
TMP1826 1-Wire®, ±0.3°C Accurate Temperature Sensor With 2-kbit EEPROM
1 Features 3 Description
• 1-Wire® interface with multi-drop shared bus and The TMP1826 is a high-accuracy, 1-Wire compatible
CRC digital output temperature sensor with integrated 2-
• Bus powered with operating voltage from 1.7 V to kbit EEPROM and a wide operating temperature
5.5 V range from –55°C to +150°C. The TMP1826 provides
• IEC 61000-4-2 ESD for 8-kV contact discharge a high accuracy of ±0.1°C (typical)/±0.3°C (maximum)
• Functional Safety-Capable across the temperature range of –20°C to +85°C.
– Developed for functional safety applications Each device comes with a factory programmed 64-bit
– Documentation available to aid functional safety unique identification number for addressing and NIST
system design traceability. The TMP1826 supports both standard
• High-accuracy digital temperature sensor (DGK): speed for legacy application and overdrive mode
– ±0.1°C (typical)/±0.3°C (maximum) from –20°C with 90-kbps data rate for low latency communication
to +85°C across a wide voltage range of 1.7 V to 5.5 V.
– ±0.3°C (typical)/±0.5°C (maximum) from –55°C In the simplest mode of operation, the TMP1826 1-
to +150°C Wire interface, with an integrated 8-kV IEC-61000-4-2
• High-accuracy digital temperature sensor (NGR) ESD protection on the data pin, requires only a single
– ±0.1°C (typical)/±0.3°C (maximum) from –20°C connection and a ground return in bus powered mode,
to +85°C which simplifies and reduces cost by reducing the
– ±0.3°C (typical)/±0.5°C (maximum) from –55°C number of wires and external protection components.
to +125°C Additionally, there is the VDD power pin also available
– ±0.5°C (typical)/±1.0°C (maximum) from –55°C for applications that may want to have a dedicated
to +150°C power supply.
• 94-µA temperature measurement and 1.3 µA
shutdown current The 2-kbit EEPROM on the TMP1826 allows the host
• 16-bit temperature resolution: 7.8125 m°C (1 LSB) to store application data in increments of 64 bits. With
• Fast data rates of 90 kbps in overdrive speed user programmable 256-bit page size write protection
• Flexible user programmable short address modes to avoid accidental overwrite, the EEPROM can be
for faster device address used as non-volatile, read-only memory. The four
• 2-kbit EEPROM features: digital I/O pins are configurable for general purpose
functions, temperature alert, or provide host to identify
– Write operation in block size of 64-bits
the position of the device on a shared bus.
– Continuous read mode
– Read with write protection with page size of Package Information
256-bits PART NUMBER PACKAGE
(1)(2)
BODY SIZE (NOM)
– Read/write current of 95 µA/178 µA WSON (8)(3) 2.50 mm × 2.50 mm
• NIST traceable factory-programmed non erasable TMP1826
VSSOP (8) 3.00 mm × 3.00 mm
64-bit identification number for device addressing
• 4 configurable open-drain digital input-output and (1) For all available packages, see the orderable addendum at
temperature alert the end of the data sheet.
(2) These package options are compatible with 1-Wire® devices.
2 Applications 1-Wire is a registered trademark of Maxim Integrated
Products Inc.
• Factory automation and control (3) This package is preview only.
• Appliances VDD = 1.7V to 5.5V
• Medical accessories
• CPAP machine
RPU
• Battery packs
GPIO
VDD
• LED lighting MCU

SDQ VDD
TMP1826
SDQ VDD
TMP1826
• Cold chain GND GND
• Temperature transmitters GND
• EV charging infrastructure VDD Powered Bus Powered
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TMP1826
SBOSA45B – FEBRUARY 2022 – REVISED DECEMBER 2022 www.ti.com
Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................12
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................22
3 Description.......................................................................1 7.5 Programming............................................................ 37
4 Revision History.............................................................. 2 7.6 Register Map.............................................................42
5 Pin Configuration and Functions...................................3 8 Application and Implementation.................................. 53
6 Specifications.................................................................. 3 8.1 Application Information............................................. 53
6.1 Absolute Maximum Ratings........................................ 3 8.2 Typical Applications.................................................. 53
6.2 ESD Ratings............................................................... 4 8.3 Power Supply Recommendations.............................56
6.3 Recommended Operating Conditions.........................4 8.4 Layout....................................................................... 56
6.4 Thermal Information....................................................4 9 Device and Documentation Support............................58
6.5 Electrical Characteristics.............................................4 9.1 Receiving Notification of Documentation Updates....58
6.6 1-Wire Interface Timing...............................................6 9.2 Support Resources................................................... 58
6.7 EEPROM Characteristics............................................6 9.3 Trademarks............................................................... 58
6.8 Timing Diagrams......................................................... 7 9.4 Electrostatic Discharge Caution................................58
6.9 Typical Characteristics................................................ 9 9.5 Glossary....................................................................58
7 Detailed Description......................................................12 10 Mechanical, Packaging, and Orderable
7.1 Overview................................................................... 12 Information.................................................................... 58
7.2 Functional Block Diagram......................................... 12
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (September 2022) to Revision B (December 2022) Page
• Changed the DGK (VSSOP) package status from Advanced Information to Production Data.......................... 1
• Added Functional Safety information to the Features section............................................................................ 1
• Updated maximum accuracy for full range from ±1.0 °C to ±0.5 °C................................................................... 4
• Updated tREC in overdrive speed from 2 µs to 10 µs.......................................................................................... 6
• Added minimum EEPROM Endurance specification for 125 °C.........................................................................6
• Removed GPIO read and CRC byte from the GPIO WRITE section............................................................... 34
Changes from Revision * (February 2022) to Revision A (September 2022) Page

• Added WSON package option............................................................................................................................1
• Added pinout for WSON package.......................................................................................................................3
• Updated operating ambient temperature as –55°C to 150 °C............................................................................ 4
• Added long-term stability and drift specification................................................................................................. 4
• Added temperature cycling and hysteresis specification.................................................................................... 4
• Added response time specification..................................................................................................................... 4
• Updated standby current as 1.59 µA.................................................................................................................. 4
• Updated power-on reset threshold on rising supply from typical 1.25 V to minimum of 1.5 V............................4
• Updated power-on reset threshold on falling supply from typical 1.15 V to maximum of 1.3 V..........................4
• Added the Flexible Device Address section..................................................................................................... 15
• Added section on standard and overdrive bus speeds.....................................................................................21
• Added FLEXADDR address command.............................................................................................................26
• Added description of FLEXADDR address command...................................................................................... 30
• Updated reset value for TEMP_RESULT_L and TEMP_RESULT_H registers................................................ 42
• Added DATA_READY flag in STATUS_REG....................................................................................................44
• Added FLEX_ADDR_MODE bits in CONFIG_REG2 register.......................................................................... 46
• Updated STACKMODE_ADDR as SHORT_ADDR register............................................................................. 47
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Product Folder Links: TMP1826

TMP1826
www.ti.com SBOSA45B – FEBRUARY 2022 – REVISED DECEMBER 2022
5 Pin Configuration and Functions

VDD 1 8 IO2/ALERT
SDQ 2 7 IO1
Thermal
Pad
ADDR 3 6 IO0
GND 4 5 IO3
Note: This package is preview only
Figure 5-1. NGR 8-Pin WSON Top View
VDD 1 8 IO2/ALERT
SDQ 2 7 IO1
ADDR 3 6 IO0
GND 4 5 IO3
Figure 5-2. DGK 8-Pin VSSOP Top View
Table 5-1. Pin Functions

PIN
I/O DESCRIPTION
NAME WSON VSSOP
ADDR 3 3 I Resistor address select. If unused, TI recommends to connect pin to ground
GND 4 4 — Ground
General-purpose digital open-drain IO. If unused, TI recommends to connect pin to
IO0 6 6 I/O
ground
IO1 7 7 I/O
ground
General-purpose digital open-drain IO or configurable as temperature alert. If unused, TI
IO2/ALERT 8 8 I/O
recommends to connect pin to ground
IO3 5 5 I/O
ground
Serial bidirectional data. In bus power mode, the pin is used to power the internal
SDQ 2 2 I/O
capacitor
Supply voltage in VDD powered mode. In bus powered mode, must be connected to
VDD 1 1 I
ground
6 Specifications
6.1 Absolute Maximum Ratings
Over free-air temperature range unless otherwise noted(1)
MIN MAX UNIT
Supply voltage VDD 6.5 V
SDQ, Bus powered mode –0.3 6.5
I/O voltage V
SDQ, Supply powered mode –0.3 VDD + 0.3
I/O voltage IO0, IO1, IO2, IO3 –0.3 6.5 V
Input voltage ADDR –0.3 1.65 V
Operating junction temperature, TJ –55 155 °C
Storage temperature, Tstg –65 155 °C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

TMP1826
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) All pins ±2000 V
Electrostatic
V(ESD) Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2) All pins ±500 V
discharge
IEC 61000-4-2 Contact Discharge SDQ pin ±8000 V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VDD Supply voltage VDD powered mode 1.70 5.5 V
VPUR Supply voltage on SDQ in bus powered mode (VDD = GND) 1.70 5.5 V
All IO pins in VDD powered mode (except SDQ and ADDR(1)) 0 5.5 V
VI/O
SDQ pin in VDD powered mode 0 VDD + 0.3 V
TA Operating ambient temperature(2) -55 150 °C
(1) If ADDR pin is not used, it is recommended to be connected to GND

(2) In bus powered mode, overdrive speed supports the max operating temperature up to 150°C, while standard speed supports up to
125°C for full VPUR range and 150C for VPUR > 2.5V (See Figure 6-18)
6.4 Thermal Information

TMP1826
THERMAL METRIC(1) NGR (WSON) DGK (VSSOP) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 66.1 158.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.7 52.6 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 20.2 NA °C/W
RθJB Junction-to-board thermal resistance 26.3 79.0 °C/W
ψJT Junction-to-top characterization parameter 1.0 4.9 °C/W
ψJB Junction-to-board characterization parameter 26.1 77.5 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Electrical Characteristics

Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25 °C
and VDD = 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TEMPERATURE SENSOR
–20 °C to 85°C ±0.1 ±0.3
TERR Temperature accuracy (DGK) °C
–55 °C to 150°C ±0.3 ±0.5
–20 °C to 85°C ±0.1 ±0.3
TERR Temperature accuracy (NGR) –55 °C to 125°C ±0.3 ±0.5 °C
–55 °C to 150°C ±0.5 ±1.0
PSR DC power supply sensitivity ±0.03 °C/V
Temperature resolution (High Including sign bit 16 Bits

TRES
Precision Format) LSB 7.8125 m°C
Averaging enabled, Conversion Time = 5.5 ms,
TREPEAT Repeatability(1) 16-bit mode, ±2 LSB
1-Hz conversion rate, 300 acquisition

TMP1826
Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25 °C
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TLTD Long-term stability and drift 1000 hours at 150°C(2) 0.0625 °C
TSTART = –40°C
Temperature cycling and TFINISH = 150°C
THYST 4 LSB
hysteresis TTEST = 25°C
3 cycles
Response time (Stirred Single layer Flex PCB 0.77 s

τ = 63 %
tRESP_L Liquid) 2-layer 62-mil Rigid 25°C to 75°C 1.91 s
NGR Package PCB
Active Conversion time (No CONV_TIME_SEL = 0 2.54 3 3.37 ms

tACT (Figure 7-12)
Averaging) CONV_TIME_SEL = 1 4.69 5.5 6.12 ms
Start-up delay for temperature
tDELAY conversion and EEPROM 100 300 µs
programming
SDQ DIGITAL INPUT/OUTPUT
CIN SDQ pin capacitance 40 pF
VIL Input logic low level(3) –0.3 0.2 × VS V
VIH Input logic high level(3) 0.8 × VS VS + 0.3 V
VHYST Hysteresis 0.3 V
IIN Input leakage current VDD powered mode –0.1 0.3 1.05 μA
VOL Output low level IOL = –4 mA 0.4 V
IO CHARACTERISTICS
CIN Input capacitance 10 pF
VIL Input logic low level(3) –0.3 0.2 × VS V
VIH Input logic high level(3) 0.8 × VS VS + 0.3 V
IIN Input leakage current 0 ±0.12 µA
VOL Output low level IOL = –3 mA 0.4 V
RESISTOR ADDRESS DECODER CHARACTERISTICS
Load capacitance as seen
CLOAD on ADDR pin (includes PCB 100 pF
parasitics)
RADDR resistor range 6.49 54.9 kΩ
RADDR resistor tolerance TA = 25°C –1.0 1.0 %
RADDR resistor temperature
–100 100 ppm/°C
coefficient
RADDR resistor lifetime drift –0.2 0.2 %
tRESDET Resistor decoding time 2.8 ms
POWER SUPPLY
IPU Pullup current(4) Bus powered mode, serial bus idle 300 μA
Supply current during
IDD_ACTIVE Temperature Conversion, serial bus idle 94 154 μA
temperature conversion
Serial bus inactive, one TA = -55°C to 85°C 1.3 3.3

IDD_SD Shutdown current μA
shot conversion mode TA = -55°C to 150°C 23.15
Power-on reset threshold
Supply rising (Figure 6-4, Figure 6-5) 1.5 V
VPOR voltage
Brownout detect Supply falling 1.3 V
Time required by device to reset after power up
tINIT Reset Initialization Time 2.0 ms
(Figure 6-4, Figure 6-5)
(1) Repeatability is the ability to reproduce a reading when the measured temperature is applied consecutively, under the same conditions.
See Figure 6-12

TMP1826
(2) Long term stability is determined using accelerated operational life testing at a junction temperature of 150°C.
(3) In bus powered mode VS = VPUR. In supply powered mode VS = VDD.
(4) The pullup current parameter is required to size the bus pullup resistor (See Section 7.3.3) for active temperature conversion or
EEPROM read and program operations.
6.6 1-Wire Interface Timing

Over free-air temperature range and VDD = 1.70 V to 5.5 V (unless otherwise noted)
STANDARD MODE OVERDRIVE MODE
UNIT
MIN MAX MIN MAX
BUS RESET AND BIT SLOT TIMING
Host to device bus reset pulse width (Figure 6-1)
tRSTL (1) 480 560 48 80 µs
tRSTH Device to host response time (Figure 6-1)(2) 480 48 µs

Device turnaround time for bus reset
tPDH 15 60 2 8 µs
response (Figure 6-1)
tPDL Device to host response pulse width (Figure 6-1) 60 240 8 24 µs
tSLOT Bit slot time (Figure 6-2, Figure 6-3) 60 120 11 µs
tREC Recovery time (Figure 6-2, Figure 6-3) 2 10 µs
tGF Glitch filter width (Figure 6-6)(3) 0.48 0.025 µs
tF Fall time 100 100 ns
BIT WRITE TIMING
tWR0L Host write 0 width (Figure 6-2) 60 120 9 10 µs
tWR1L Host write 1 width (Figure 6-2) 2 15 1 2 µs
tRDV Device read data valid time (Figure 6-2) 15 2 µs
tDSW Device read data window (Figure 6-2) 15 45 2 7 µs
BIT READ TIMING
tRL Host drive read bit slot time (Figure 6-3) 2 5 2 3 µs
Host wait time before read data sampling
tRWAIT tRL+tRC tRL+tRC µs
window (Figure 6-3)(4)
tMSW Host read data sampling window (Figure 6-3) tRL+tRC 30 tRL+tRC 3 µs
(1) In bus powered mode, extending the tRSTL above 600 µs may cause the device to power on reset
(2) The tRSTH is the maximum time the host must wait to receive a response from the furthest device, taking into account the propagation
delay and recovery time for all the devices.
(3) The glitch filter timing applies only on the rising edge of the SDQ signal
(4) The tRC time is defined as the time taken for the bus voltage to rise from 0V to minimum VIH of the host. This is a function of the bus
pullup resistor and parasitic capacitance of the trace or cable.
6.7 EEPROM Characteristics

Over free-air temperature range and VDD = 1.7 V to 5.5 V (unless otherwise noted); Typical specifications are at TA = 25°C
MIN TYP MAX UNIT
Programming time for 8-byte data word in user EEPROM 13.2 21 ms
tPROG
Programming time for register copy to EEPROM 26.4 42 ms
tREADIDLE Idle bus time for EEPROM 8-byte data word fetch 400 µs
IDD_PROG Programming current 178 214 µA
at TA = 125°C 25 years
Data Retention
at TA = 150°C 10 years
at TA = 125°C 20000 cycles
Endurance
at TA = 150°C 1000 cycles

TMP1826
6.8 Timing Diagrams

Host drives SDQ
Device drives SDQ
High Impedance, external pullup
tPDL
VDD/VPUR
VIH
tPDH
tRSTL tRSTH
VIL
Figure 6-1. Bus Reset Timing Diagram

Host drives SDQ
tSLOT tREC tSLOT tREC
VDD/VPUR VDD/VPUR
VIH VIH
VIL VIL
tRDV tDSW tRDV tDSW

tWR1L
tWR0L
Host Write-1 Host Write-0
Figure 6-2. Write Timing Diagram

Host drives SDQ
Device drives SDQ

VDD/VPUR VDD/VPUR
VIH VIH
tRWAIT tRWAIT
VIL VIL
tRL tMSW tRL tMSW
Host Read-1 Host Read-0
Figure 6-3. Read Timing Diagram

TMP1826
VDD
VPOR
0V
VSDQ Bus Idle Bus Acve
SDQ Pin
tINIT
Figure 6-4. VDD Powered Initialization Timing Diagram
VPUR Bus Idle Bus Active
VPOR
0V
tINIT
Figure 6-5. Bus Powered Initialization Timing Diagram

TMP1826
Host drives SDQ

VPUR
VIH
VIL
tGF
Logic H
Input of
Logic L Glitch Filter
Logic H
Output of
Logic L Glitch Filter
Figure 6-6. Glitch Filter Timing Diagram
6.9 Typical Characteristics

1.2 0.6
DS Max
1 0.5
0.8 0.4
Temperature Error ( C)
Temperature Error ( C)
0.6 DS Max 0.3

0.4 0.2
0.2 0.1
0 0
-0.2 -0.1
-0.4 -0.2
1.7 V
-0.6 DS Min -0.3 3.3 V
5.5 V
-0.8 -0.4
-1 -0.5
DS Min
-1.2 -0.6
-55 -40 -25 -10 5 20 35 50 65 80 95 110 125 140 -55 -40 -25 -10 5 20 35 50 65 80 95 110 125 140
Temperature (C) Temperature (C)
Figure 6-7. Temperature Error vs Temperature (NGR Package) .
.
Figure 6-8. Temperature Error vs Temperature (DGK Package)

TMP1826
6.9 Typical Characteristics (continued)

140 10
1.7 V 1.7 V
3.3 V 9 3.3 V
130 5.5 V 5.5 V
8
120 7
Current ( A)
Current ( A)
6
110
5
100
4
90 3
2
80
1
70 0
-60 -40 -20 0 20 40 60 80 100 120 140 -60 -40 -20 0 20 40 60 80 100 120 140
Temperature (C) Temperature (C)
Figure 6-9. Temperature Conversion Current vs Temperature Figure 6-10. Shutdown Current vs Temperature
10 80%
1.7 V
9 3.3 V
5.5 V 70%
8
60%
7 Population (%)
50%
Current ( A)
5 40%
4 30%
3
20%
2
10%
1
0 0
-60 -40 -20 0 20 40 60 80 100 120 140 -5 -4 -3 -2 -1 0 1 2 3 4 5
Temperature (C) Normalized Data Distribution (LSB)
. TA = 25°C
Figure 6-11. Standby Current vs Temperature Figure 6-12. Data Distribution With 5.5-ms Conversion Time and
Averaging On in 16-bit format
80% 50%
70%
60% 40%
Population (%)
50%
Population (%)
40%
30%
30%
20%
20%
10%
10%
0
-5 -4 -3 -2 -1 0 1 2 3 4 5
Normalized Data Distribution (LSB)
TA = 25°C 0
-5 -4 -3 -2 -1 0 1 2 3 4 5
. Normalized Data Distribution (LSB)
. TA = 25°C
Figure 6-13. Data Distribution With 3-ms Conversion Time and Figure 6-14. Data Distribution With 5.5-ms Conversion Time and
Averaging On in 16-bit format Averaging Off in 16-bit format

TMP1826
6.9 Typical Characteristics (continued)

50% 80%
Bus Powered-Overdrive Mode
Bus Powered-Standard Mode
70% VDD Powered
40%
60%
Population (%)
Population (%)
50%
30%
40%
20% 30%
20%
10%
10%
0
0 -5 -4 -3 -2 -1 0 1 2 3 4 5
-5 -4 -3 -2 -1 0 1 2 3 4 5
Normalized Data Distribution (LSB) Normalized Data Distribution (LSB)
TA = 25°C, 5.5 ms Conversion Time, Averaging On, 16-bit
TA = 25°C
Format
Figure 6-15. Data Distribution With 3-ms Conversion Time and
Averaging Off in 16-bit format Figure 6-16. Data Distribution for Power Mode and Bus Speed
90 2.3
2-layer FR4 PCB Standard Speed Typical Operating Range .
85 Single Layer Flex PCB .
80 63% Response
2.2
75
70
Temperature ( C)
VPUR Supply (V)
2.1
65
60
55 2
50
45
1.9
40
35
1.8
30
25
20 1.7
-1 0 1 2 3 4 5 6 7 125 130 135 140 145 150
Time (sec) Temperature (C)
TSTART = 25°C, TFINISH = 75°C .
Figure 6-17. Thermal Response Time (NGR) Figure 6-18. VPUR Minimum Supply Voltage vs Temperature
(Standard Speed)

TMP1826
7 Detailed Description
7.1 Overview
The TMP1826 is a digital output temperature sensor designed for thermal-management and thermal-protection
applications. The TMP1826 is a 1-Wire device which can operate in either supply powered or bus powered
(parasitic powered) mode. The device features a 2-kbit EEPROM. Figure 7-1 shows a block diagram of the
TMP1826.
7.2 Functional Block Diagram
ADDR Internal IO3

thermal
BJT
Oscillator
Conguraon Temperature IO2/ALERT
1-Wire Interface EEPROM sensor circuit
VDD Power Control & Controller
Device Capacitor
ScratchPad-1 ADC IO1
SDQ 2 kbit User

ScratchPad-2
EEPROM
IO0
GND
Figure 7-1. Functional Block Diagram
7.3 Feature Description

7.3.1 Power Up
The device operates in both supply powered and bus powered mode. In both modes, when the supply voltage
reaches within the operating range, the device requires tINIT to initialize itself. After tINIT, the host MCU can begin
accessing the device.
During initialization, the device may not respond to any bus activity. When initialization is complete, the device
shall wait for the bus reset from the host. During the initialization for the device, the following events take place:
• The EEPROM content for short address, temperature alert low, temperature alert high and temperature offset
registers are restored.
• The EEPROM for the IO configuration register is read and contents of the IO configuration register is
restored.
• The EEPROM content for device configuration-1 and device configuration-2 registers are restored to the
respective registers.
– If the ARB_MODE bits is restored as '10b' or '11b', then the device will respond to the SEARCHADDR in
arbitration mode.
– If OD_EN bit is set to '1b', then the device shall communicate in overdrive speed, unless the first bus reset
pulse from the host is sent in standard speed.
• The user memory protection bits are restored and appropriate protection to the user EEPROM block applied.
7.3.2 Power Mode Switch
The device is designed to operate in supply powered or bus powered mode. The dual mode implementation
provides a unique method of redundancy that, even in cases where the power supply pin VDD becomes 0V, the
device can draw power from data pin, as long as the pullup resistor value used is as per the specification limit.
When the device switches from supply powered to bus powered mode, the device shall operate with the same
settings until the internal capacitor is able to provide the current draw required by the device for communication
and the external pullup resistor can keep SDQ voltage above 1.7V during ADC and EEPROM programming. If
the internal voltage on the capacitor drops below the brown-out threshold, the device shall switch itself off and

TMP1826
enter bus powered mode of communication on subsequent power up. When the device completes the power-up
initialization sequence, as described earlier, the device shall respond to first bus communication starting with the
bus reset sequence.
7.3.3 Bus Pullup Resistor
The bus pullup resistance value selected is important for communication as per the speed mode and ensuring
that minimal possible energy is consumed in the application. If the resistor value is too small, it may violate the
VOL limits on the SDQ pin.
The total SDQ pins and bus capacitance must be considered along with the bus leakage current when selecting
the pullup resistor. The pullup resistance value selected must also ensure that the signal level reaches VIH as
per the timing requirements for standard and overdrive mode.
In bus powered mode of operation, the device charges its internal capacitor through the SDQ pin and the pullup
resistor. This charge on the capacitor is used during bus communication, when the SDQ pin low. For other high
current functions like thermal conversion and EEPROM access, the bus is held idle to ensure that the device
can draw current through the pullup resistor. The SDQ pin voltage during the high current operation must be
maintained to ensure sufficient operating margins. For VPUR =< 2.0 V use Equation 1 and for VPUR > 2.0 V use
Equation 2 to calculate the pullup resistor value.
VPUR − VOL MAX V − 1.6

< RPUR < IPUR (1)
4 × 10−3 PU MIN
VPUR − VOL MAX VPUR − VIH MIN

< RPUR < IPU MIN (2)
4 × 10−3
When the device is used in VDD or supply powered mode, a larger pullup resistor value may be used, as the
SDQ pin is used only for communication. The user must ensure that the pullup resistor value selected must be
able to support the timing for the required bus speed of operation.
For low current consumption devices like the TMP1826, selecting the correct pullup resistor value allows
the application to avoid low impedance current path components for bus powered mode of operation while
maintaining communication speeds and device parameters as per its electrical specification.
7.3.4 Temperature Results
The conversion is initiated by the host MCU by sending the temperature conversion command. At the end of
every conversion, the device updates the temperature registers temperature result and the status register bits.
Figure 7-2 shows that the device supports a high precision and legacy format, which can be configured through
the TEMP_FMT bit in the device configuration-1 register. The default setting for the temperature result is legacy
format for software compatibility.
Temperature Result MSB Register Temperature Result LSB Register
High Precision Format

S 27 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4 2-5 2-6 2-7
Legacy Format
S S S S S 26 25 24 23 22 21 20 2-1 2-2 2-3 2-4
Figure 7-2. Temperature Format
If the format selected is the high precision 16-bit format, the data in the result registers is stored in two's
complement form and has a resolution of 7.8125m°C and a range of ±256 °C. If the format selected is the legacy
12-bit format, the data in the result register is stored in sign extended form and has a resolution of 62.5m°C
and a range of ±128°C. The temperature register reads as 0°C before the first conversion. Table 7-1 and Table
7-2 show examples of possible binary data that can be read from the temperature result registers and the
corresponding hexadecimal and temperature equivalents for both formats.

TMP1826
Table 7-1. Precision (16-Bit) Temperature Data Format

TEMPERATURE DIGITAL OUTPUT (PRECISION FORMAT)
(°C) BINARY HEXADECIMAL
150 0100 1011 0000 0000 4B00
127 0011 1111 1000 0000 3F80
100 0011 0010 0000 0000 3200
25 0000 1100 1000 0000 0C80
1 0000 0000 1000 0000 0080
0.125 0000 0000 0001 0000 0010
0.03125 0000 0000 0000 0100 0004
0.0078125 0000 0000 0000 0001 0001
0 0000 0000 0000 0000 0000
–0.0078125 1111 1111 1111 1111 FFFF
–0.03125 1111 1111 1111 1100 FFFC
–0.125 1111 1111 1111 0000 FFF0
–1 1111 1111 1000 0000 FF80
–25 1111 0011 1000 0000 F380
–40 1110 1100 0000 0000 FC00
–55 1110 0100 1000 0000 F480
Table 7-2. Legacy (12-Bit) Temperature Data Format

TEMPERATURE DIGITAL OUTPUT
(°C) BINARY HEXADECIMAL
140 0000 0111 1111 1111 07FF
128 0000 0111 1111 1111 07FF
127.9375 0000 0111 1111 1111 07FF
100 0000 0110 0100 0000 0640
25 0000 0001 1001 0000 0190
1 0000 0000 0001 0000 0010
0.125 0000 0000 0000 0010 0002
0 0000 0000 0000 0000 0000
–0.125 1111 1111 1111 1110 FFFE
–1 1111 1111 1111 0000 FFF0
–25 1111 1110 0111 0000 FE70
–40 1111 1101 1000 0000 FD80
–55 1111 1100 1001 0000 FC90
7.3.5 Temperature Offset

The temperature offset has the same format as the temperature result and is stored in the temperature offset
registers.
The device, after every temperature conversion, applies the offset value before the temperature is stored in the
temperature result register. The host write to the offset register can be stored in the configuration EEPROM of
the device, which removes the overhead for the host to reprogram the value or reapply in software at every
power up. The offset features allow the device to achieve better accuracy at the temperature range for the
application by performing a single point calibration.

TMP1826
7.3.6 Temperature Alert

The temperature alert feature uses the temperature alert low registers for low threshold comparison and
temperature alert high registers for high threshold comparison. The format of the register is the same as the
temperature results.
The device shall compare the result of the last conversion with the alert thresholds. If the temperature result
is less than the low limit, or more than the high limits, then the device shall set the appropriate alert status
flag, in the status register. The alert status flags are cleared based on the ALERT_MODE setting in the device
configuration-1 register.
Additionally, if the IO2/ALERT pin is configured as an alert pin, the alert status is reflected on the pin in supply
powered mode.
7.3.7 Standard Device Address
Every device comes with a unique 64-bit address that is factory programmed. This is described below.
7.3.7.1 Unique 64-Bit Device Address and ID
The device has a hard-coded, 64-bit address which is factory programmed and cannot be altered by the
customer application. The unique 64-bit device address is used for device addressing in the end application and
for NIST traceability. Figure 7-3 shows the format of the 64-bit address. When the host accesses the device or
when the device sends its address, the 64-bit unique address is sent least significant bit first. The unique 64-bit
address consists of 3 fields. The lower 8 bits consists of the device family code, followed by a 48-bit unique
number and 8-bit CRC checksum on the 56 bits preceding it.
The device family code for TMP1826 shall read as 26h.
MSb LSb MSb LSb MSb LSb
8-bit CRC 48-bit Unique Address 8-bit Device Family
Bit-63 Bit-0
Figure 7-3. 64-Bit Device Address
7.3.8 Flexible Device Address

Depending on the user application case, the TMP1826 provides for some user and application configurable
address modes, called flexible address mode. These modes exist alongside the standard device address, and is
extremely useful for applications that require a combination of faster access and device position identification.
When the flexible device address is used, the short address register is updated. The short address register shall
be updated by the host write when the FLEX_ADDR_MODE bits are '00b'. When these bits are changed from
the value '00b', the device decodes the address resistor connected on ADDR pin or IOs or both of them and
overlay on the short address register. This is helpful as the same set of 16 resistors or 16 IO combinations can
be used for up to 256 unique flexible address.
The FLEX_ADDR_MODE is not stored in the configuration EEPROM, therefore the host must copy the short
address register content into EEPROM configuration memory to make the short address values permanent
without the need to decode at every power up.
7.3.8.1 Non-Volatile Short Address
Figure 7-4 shows the user-programmable, 8-bit short address mode of the device. The host must copy the 8-bit
short address to the configuration EEPROM, so that at subsequent power up, the device loads the updated short
address and respond to the host.
MSb LSb
NV7 NV6 NV5 NV4 NV3 NV2 NV1 NV0
Bit-7 Bit-0
Figure 7-4. Non-Volatile Short Address

TMP1826
7.3.8.2 IO Hardware Address

Figure 7-5 shows the 8-bit IO hardware address mode of the device. This feature is available on packages
which have general-purpose pins (IO0-IO3) available. The 8-bit value consists of the lower 4 bits as read values
of the pins (IO3 to IO0) that is overlaid on the contents of the short address register to form a 8-bit address.
The application may connect the general-purpose pins to either VDD/SDQ for logic '1' or GND for logic '0'. TI
recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case
the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '01b' in the device configuration-2
register for the device to latch the state of the general-purpose pins.
MSb LSb
NV7 NV6 NV5 NV4 IO3 IO2 IO1 IO0
Bit-7 Bit-0
Figure 7-5. IO Hardware Address
Note
IO pins must be configured as input before using IO hardware address mode. If any of the IO0 to IO3
pins are used in output mode, then the respective value shall be latched as '0'.
7.3.8.3 Resistor Address

The resistor address modes uses E96-series (1% tolerance) standard resistor connected between the ADDR pin
and ground. Figure 7-6 shows the 8-bit address with the lower 4 bits decoded from the resistor connected, which
is overlaid on the contents of the short address register.
MSb LSb
NV7 NV6 NV5 NV4 RA3 RA2 RA1 RA0
Bit-7 Bit-0
Figure 7-6. Resistor Address
After having FLEX_ADDR_MODE as '00b', the host controller must set the bits as '10b' in the device
configuration-2 register which enables the device to decode the resistor connected. After writing the device
configuration-2 register, the host must place the device in shut down mode and idle the bus for tRESDET, for
the device to decode the resistor address. Table 7-3 shows the set value of the device address based on the
decoded resistor value. If the ADDR pin connected to GND or lower than 6.49 kΩ, then the address decoder
shall always decode as '0000b'. Similarly, if the ADDR pin is connected to a resistor higher than 54.9 kΩ, the
address decoder shall always decode as '1111b'.
Table 7-3. Resistor Address Decode
RESISTOR VALUE (kΩ) ADDRESS DECODE
< 6.49 0h
7.87 1h
9.31 2h
11.0 3h
13.3 4h
15.4 5h
17.8 6h
20.5 7h
23.7 8h
26.7 9h
30.1 Ah

TMP1826
Table 7-3. Resistor Address Decode (continued)

RESISTOR VALUE (kΩ) ADDRESS DECODE
33.2 Bh
37.4 Ch
42.2 Dh
47.5 Eh
> 54.9 or floating Fh
This mode is useful when the application requires placing the TMP1826 on multiple printed circuit boards
(PCBs). The Bill of Materials (BOM) component can be changed easily instead of having multiple PCBs
fabricated for individual pin connections, thereby reducing the cost of the system.
Note
If unused, the ADDR pin is recommended be connected to GND. The CLOAD for ADDR pin is due to
parasitic capacitance depending on the board layout.
7.3.8.4 Combined IO and Resistor Address

In the combined IO and resistor address mode, the IO0 and IO1 pins are used along with the resistor connected
between ADDR pin and ground. Figure 7-7 shows the 8-bit address with the lower 4 bits decoded from the
resistor connected, followed by 2 bits decoded from the IO0 and IO1 pins which may be connected to either
VDD/SDQ for logic '1' or GND for logic '0', which is overlaid on the contents of the short address register. TI
recommends to use a 20 KΩ resistor to be placed between the IO and VDD/SDQ to prevent a supply shot in case
the IO pin is accidentally set to zero in output mode.
After having FLEX_ADDR_MODE as '00b', the host must set the bits as '11b' in the device configuration-2
register which enables the device to sample the ADDR pin to identify the resistor connected, followed by
sampling of the IO0 and IO1 to configure the short address. If the bit field value has already been updated in the
non-volatile storage, then the device shall automatically latch the pins, run the resistor decoder, and update the
value in the short address register on power up.
The host controller must place the device in shut down mode and idle the bus for tRESDET, for the device to
decode the resistor address.
MSb LSb
NV7 NV6 IO1 IO0 RA3 RA2 RA1 RA0
Bit-7 Bit-0
Figure 7-7. Combined IO and Resistor Address
This mode is useful when the application requires placing up to 64 devices on a single PCB, as it allows for easy
expansion using a combined approach of IO and resistor decoding while enabling IO2 and IO3 to function as
general-purpose input and output pins. This mode may also be used for position identification as no two devices
may have the same short address.
Note
IO pins must be configured as input before using IO hardware address mode. If the IO0 or IO1 pins
are used in output mode, then the respective value shall be latched as '0'.
7.3.9 CRC Generation

The TMP1826 implements a cyclic redundancy check (CRC) mechanism for data integrity check and
communication robustness. Table 7-4 lists the properties of a 8-bit CRC.
Table 7-4. CRC-8 Rule
CRC-8 Rule Attributes
CRC width 8 bits

TMP1826
Table 7-4. CRC-8 Rule (continued)

CRC-8 Rule Attributes
CRC polynomial x8 + x5 + x4 + 1 (0x31)
Initial seed value 00h
Input data reflected Yes
Output data reflected Yes
XOR value 00h
When a new transaction is done, the shift register is initialized with the seed value of 00h and the data is shifted
in LSB first. The CRC result is always part of the 64-bit unique address and is computed on the 56-bits that
precede it. Additionally, when the host writes to the scratchpad-1 for the registers and scratchpad-2 for the
memory, the device sends the CRC computed on the data bytes to provide a data integrity check for the host
on the transaction. When the host reads the scratchpad-1 for reading the temperature register, the device shall
append the CRC after the 8 bytes of scratchpad are sent.
The host must recalculate the CRC and compare it against the received CRC from the device. This is done by
shifting the read data from the device along with CRC bits. If there is no bus error, then the shift register at the
end of the bit shift will result in 00h. When writing the data to the device, the host must check the CRC received
by processing the write data to ensure that there were no transmission errors and take appropriate corrective
action before performing the next function.
7.3.10 Functional Register Map
The scratchpad-1 region and the IO register region together are referred to as the functional register map
(see Figure 7-8). The scratchpad-1 region is 16 bytes deep, and has temperature result, device status,
device configuration, short address, temperature alert limits and temperature offset registers. The IO register
region has the IO read and IO configuration registers. Some of the registers can be committed to the
configuration EEPROM to ensure that the device settings are restored on power up without the host rewriting the
configuration.

TMP1826
Scratchpad-1
Byte-0 Temperature Register LSB
Byte-1 Temperature Register MSB Back up EEPROM

Byte-2 Status Register
Byte-3 Reserved = FFh
Byte-4 Device Conguraon-1 Register Device Conguraon-1 Register
Byte-5 Device Con guraon-2 Register Device Con

guraon-2 Register
Byte-6 Short Address Register Short Address Register
Byte-8 Temperature Alert Low LSB Temperature Alert Low LSB

Byte-9 Temperature Alert Low MSB Temperature Alert Low MSB
Byte-10 Temperature Alert High LSB Temperature Alert High LSB
Byte-11 Temperature Alert High MSB Temperature Alert High MSB
Byte-12 Temperature Oset LSB Temperature Oset LSB
Byte-13 Temperature O set MSB Temperature Oset MSB
IO Registers
IO Read Register
IO Congura on Register IO Conguraon Register
Figure 7-8. Functional Register Map (Scratchpad-1)
7.3.11 User Memory Map

The EEPROM memory is organized as 8 pages of 4 blocks each. Figure 7-9 shows that each block is 8 bytes or
64 bits. This results in a total user memory of 2048 bits. All memory access to the device shall be increments of
a block size of 8 bytes. Access to the memory for programming is done through the scratchpad-2 register. The
host writes to the scratchpad-2 register, which allows the device to perform a read before committing the content
to the memory.

TMP1826
00FFh Block 3 00F8h – 00FFh

Block 2 00F0h – 00F7h
Page 7
Block 1 00E8h – 00EFh
00E0h Block 0 00E0h – 00E7h
00DFh Block 3 00D8h – 00DFh
Block 2 00D0h – 00D7h
Page 6
Block 1 00C8h – 00CFh
00C0h Block 0 00C0h – 00C7h
00BFh Block 3 00B8h – 00CFh
Block 2 00B0h – 00B7h
Page 5
Block 1 00A8h – 00AFh
00A0h Block 0 00A0h – 00A7h
009Fh Block 3 0098h – 009Fh
Block 2 0090h – 0097h
Page 4
Block 1 0088h – 008Fh
256 bytes
0080h Block 0 0080h – 0087h

007Fh Block 3 0078h – 007Fh
Block 2 0070h – 0077h
Page 3
Block 1 0068h – 006Fh
0060h Block 0 0060h – 0067h
005Fh Block 3 0058h – 005Fh
Block 2 0050h – 0057h
Page 2
Block 1 0048h – 004Fh
0040h Block 0 0040h – 0047h
003Fh Block 3 0038h – 003Fh
Block 2 0030h – 0037h
Page 1
Block 1 0028h – 002Fh
0020h Block 0 0020h – 0027h
001Fh Block 3 0018h – 001Fh
32 bytes
Block 2 0010h – 0017h

Page 0
Block 1 0008h – 000Fh
0000h Block 0 0000h – 0007h
Figure 7-9. Address to EEPROM Page and Block Map
Note
The device shall return "1" for any device read if the address is outside the user memory map.
7.3.12 Bit Communication

The 1-Wire interface communication does not have a reference clock, therefore all communication is performed
asynchronously with fixed time slot (tSLOT) and variable pulse width to indicate logic '0' and '1'. In idle state, the
external pullup resistor holds the line high. All bit communication, whether it is a write or a read, are initiated by
the host by driving the data line low to generate a falling edge and the bit value is decoded as the time for which
the data line is held low or high after the falling edge.
Even though the communication is one bit at a time, the data exchanged between the host and device is
performed at byte boundary. Every byte is sent least significant bit first. The device behavior is not ensured when
incomplete bytes are sent.

TMP1826
7.3.12.1 Host Write, Device Read

A host write is the means by which the host sends the command, function, and data to the devices. A host write
starts by the host driving the data line low as shown in Figure 7-10. If the host intends to transmit a logic '1', the
line is released after tWR1L time. If the host intends to transmit a logic '0', the line is released after tWR0L. After
releasing the data, the pullup resistor causes the line to become high till the beginning of the next time slot. The
device samples the line after tRDV has elapsed from the falling edge, for a time frame indicated by tDSW. The host
must factor the rise time due to the pullup resistor and bus capacitance to determine the release of the data line
before the line is sampled by the device and the host drives the next write bit time slot.
Host drives SDQ
VDD/VPUR VDD/VPUR
VIH VIH
VIL VIL
tRDV tDSW tRDV tDSW

tWR1L
tWR0L
Host Write-1 Host Write-0
Figure 7-10. Host Write, Device Read
7.3.12.2 Host Read, Device Write

A host read is the means by which the hosts gets the data from the device or the CRC for data integrity check. A
host read starts by the host driving the data line low as shown in Figure 7-11. When the device detects the falling
edge, the device can drive the line low before the time tRL. The host can release the bus from the side after the
time tRL(MIN) elapses. If the device intends to transmit a logic '1', then the bus is released before tRL(MAX) elapses.
If the device intends to transmit a logic '0', then the bus is released after tSLOT(MIN). The host must sample the
line after the time tRWAIT, for a time frame indicated by tMSW. The host must factor the rise time due to the pullup
resistor and bus capacitance to determine the sampling window for the host to sample the bit level sent by the
device or to drive the next read bit time slot.
Host drives SDQ
Device drives SDQ

VDD/VPUR VDD/VPUR
VIH VIH
tRWAIT tRWAIT
VIL VIL
tRL tMSW tRL tMSW
Host Read-1 Host Read-0
Figure 7-11. Host Read, Device Write
7.3.13 Bus Speed

The device supports both standard speed (8.33 kbps) and overdrive speed (90 kbps) data rates. All devices
are factory programmed to start in overdrive speed to enable higher data throughput. If the host requires the
TMP1826
device to operate at standard speed, then the host can easily switch the device by issuing a standard speed bus
reset. The seamless switchover allows the host to leverage better data rates on new designs, while maintaining
backward compatibility for older design.
Additionally, the device also provides the flexibility to switch from standard to overdrive speed mode using
address phase commands of OVD SKIPADDR and OVD MATCHADDR.
• When host issues OVD SKIPADDR, then all devices capable to support the overdrive mode on the bus
switch, from standard speed to overdrive speed.
• When host issues OVD MATCHADDR, then the device whose 64-bit device address matches the address
that host sends will switch from standard to overdrive speed.
7.3.14 NIST Traceability
The accuracy of temperature testing is verified with equipment that is calibrated by an accredited lab that
complies with ISO/IEC 17025 policies and procedures. Each device is tested and trimmed to conform to its
respective data sheet specification limits.
7.4 Device Functional Modes
The TMP1826 device features flexible one-shot temperature conversion modes along with robust user EEPROM
architecture, which is described in the sections below.
7.4.1 Conversion Modes
The TMP1826 supports one-shot conversion modes. There are different methods for one-shot conversion
modes, that may be used based on single device or multiple device bus network. Each of the conversion modes
are with single temperature sample, but the host can enable 8 samples averages in the device for improved
accuracy. The conversion always result in a single temperature sample, but the host can enable 8 samples
averages in the device for reducing conversion noise and improving accuracy.
7.4.1.1 Basic One-Shot Conversion Mode
The basic one-shot conversion mode is the default conversion mode. The device goes through a bus reset,
address and function phase to initiate the temperature conversion. During the communication, the device is in
shutdown mode. When the conversion request is registered by the device, the device starts active conversion
and then goes back to low power shutdown mode as shown in Figure 7-12. If the device is in continuous
conversion mode, then the one-shot conversion mode request is ignored.
Bus Answer to SKIPADDR CONVERT
Reset
Communicaon Reset (CCh) TEMP (44h)
8 Samples
Start of Conversion
Averaging Enabled
Command startup delay (tDELAY)
Acve conversion me (tACT)
Shutdown Shutdown
Temperature
Conversion
Figure 7-12. One-Shot Conversion Mode
As shown in Figure 7-13, there is no change in how one-shot conversion is performed when there are multiple
devices on the bus. However, as there are multiple devices, the combined current drain in bus powered mode
of operation may cause the bus voltage to drop. In such use cases, it is required that the host implement a low
impedance current path using a FET/transistor switch activated before tDELAY. This path is switched on so as to

TMP1826
meet the current requirement of the bus during an active conversion and after the active conversion duration is
complete, it is switched off for bus communication.
Answer to
Bus Communicaon
SKIPADDR CONVERT TEMP
Reset (CCh) (44h)
Reset
Start of Conversion
Temperature
Conversion Sequence
Command startup delay (tDELAY) Acve conversion me (tACT)
Shutdown Shutdown
TMP18xx
Device 0
TMP18xx
Device 1
TMP18xx
Device 2
Figure 7-13. Multiple Device One-Shot Conversion Mode
7.4.1.2 Auto Conversion Mode

The auto conversion mode is a programmable feature in bus powered mode that can be enabled by setting the
CONV_MODE_SEL as '10b' in the device configuration-1 register. As shown in Figure 7-14, the host can skip
the issue of the temperature conversion request and directly read the temperature data from the device when
the auto conversion mode is enabled. This enables the application to speed up the temperature conversion
and read, because the request command is no longer required. As in the case for multiple device bus, a low
impedance current path is required to meet the current requirement of the bus during the active conversions.
Bus Answer to MATCHADDR 64-bit Device READ SCRATCHPAD-1
Reset
Communicaon Reset (55h) Address (BEh)
Start of Conversion
Command startup delay (tDELAY)

Acve conversion me (tACT)
Shutdown Shutdown
Temperature
Conversion
Figure 7-14. Auto Conversion Mode
7.4.1.3 Stacked Conversion Mode

The stacked conversion mode is a programmable feature in bus powered mode that can be enabled by setting
CONV_MODE_SEL as '01b' in the device configuration-1 register. As shown in Figure 7-15, the devices can
use the address programmed in the short address register to delay the temperature conversion for the devices
when the stacked conversion mode is enabled. No more than two devices are actively converting at any given

TMP1826
time, therefore the current drain in bus powered configuration is limited. This allows the application to avoid
simultaneous temperature conversion by multiple parts and reducing the user system maximal supply current.
Answer to SKIPADDR CONVERT
Bus Communicaon Reset
Reset (CCh) TEMP (44h)
Start of Conversion
Temperature Command startup delay (tDELAY)

Conversion Sequence
Shutdown
TMP18xx
STACKMODE ADDRESS = 0
TMP18xx
TMP18xx
Note
The host controller must program all the device with the same setting for CONV_TIME_SEL and
AVG_SEL to ensure that no more than two devices are actively converting to use the feature as it is
intended.
Figure 7-15. Stacked Conversion Mode
7.4.2 Alert Function

As described earlier, the built-in alert function can be used by the host to check if the temperature has crossed a
certain threshold. The alert status bits are available in both bus powered and VDD powered mode. The alert pin
is available only in VDD powered mode.
If the device is in VDD powered mode and IO2/ALERT is configured to function as an IO2/ALERT pin, then the
pin shall be driven active low when the threshold crossing occurs. The pin is open-drain, and therefore requires
a pullup resistor. The IO2/ALERT pin deassertion is based on the setting of the ALERT_MODE setting in the
device configuration-1 register.
7.4.2.1 Alert Mode
The device operates in alert mode, when the ALERT_MODE is set as '0b'. In the alert mode of operation, the
alert status flag and IO2/ALERT pin are asserted when the last temperature conversion is either higher than the
temperature alert high limit or when it is lower than the temperature alert low limit register.

TMP1826
The alert status flag and IO2/ALERT pin are deasserted only when the host reads the status register or performs
a successful ALERTSEARCH command as shown in Figure 7-16.
ALERT_HIGH
Temperature
ALERT_LOW
Temperature conversions
ALERT_HIGH
ALERT_LOW
ALERT pin
Alert Status Read
Figure 7-16. Alert Mode Timing Diagram
7.4.2.2 Comparator Mode

The device operates in comparator mode, when the ALERT_MODE is set as '1b'. In the alert mode of operation,
the alert status flag and IO2/ALERT pin are asserted when the last temperature conversion is either higher than
the temperature alert high limit or when it is lower than the temperature alert low limit register.
The alert status flag and IO2/ALERT pin are deasserted only when the result of the last temperature conversion
is less than the temperature alert high limit minus the hysteresis or above the temperature low limit plus the
hysteresis as shown in Figure 7-17. The hysteresis is selectable using the HYSTERESIS bit field in the device
configuration-2 register.
ALERT_HIGH
ALERT_HIGH-HYSTERESIS
Temperature
ALERT_LOW+HYSTERESIS
ALERT_LOW
Temperature conversions
ALERT_HIGH
ALERT_LOW
ALERT pin
Alert Status Read
Figure 7-17. Comparator Mode Timing Diagram

TMP1826
7.4.3 1-Wire Interface Communication

To leverage the features effectively, the device access consists of three distinct phases. As shown in Figure
7-18, any bus communication starts with a bus reset condition to which every device on the bus must respond.
This is followed by a highly configurable address phase, where the host selects the device it wants to access.
Finally, there is a function phase where the host provides the selected device(s) the action it wants to take.
Bus Reset Phase Address Phase Func on Phase
Write Data
Answer to
Reset Command Device Address Funcon CRC
Reset
Read Data
Figure 7-18. 1-Wire Bus Communication
In a 1-Wire bus, all write and reads are initiated by the host except for the answer to reset which is initiated by
the devices on the bus.
7.4.3.1 Bus Reset Phase
The bus reset phase is the beginning of the communication. The phase is initiated by the host by holding the
1-Wire data line low for a period tRSTL. All devices on the bus, irrespective of their current state shall respond
to the bus reset, by reinitializing their internal state and responding to the host initiated bus reset. The devices
respond after a minimum of tPDH, by holding the 1-Wire low for a time period of tRSTH as shown in Figure 6-1.
All devices when powered up are configured with the OD_EN bit set as '1' in the device configuration-2 and OD
flag set as '1' in status register. If the host sends a bus reset pulse of 48 µs to 80 µs, then only devices operating
in overdrive speed shall respond to the bus reset pulse, while devices operating in standard mode shall continue
to wait for a standard mode bus reset.
If the host sends a bus reset pulse of minimum tRSTL for standard mode, the device shall reset the OD_EN bit
to '0' and respond to the bus reset in standard mode. If the bus consists of mixed standard and overdrive speed
devices, then sending a bus reset pulse in standard mode shall reset all devices to standard mode speed of
operation.
It is illegal for the host to send the bus reset for a particular speed of operation and then communicate at the
other speed mode. Also, if a bus reset pulse is sent which is greater than 80 µs (but less than 480 µs), then the
device communication shall be reset, though the device operation is not ensured.
7.4.3.2 Address Phase
Figure 7-19 shows the address phase that follows the bus reset phase. During this phase, the host presents 8-bit
commands which may be followed by either host sending a 64-bit device address or skipping the address. Some
of the commands are used to discover the device address, while others are used to select the device.

TMP1826
Host Sends Reset

Pulse
Yes Is Reset pulse No

width for Standard
Speed?
Yes
Is device in
Standard Speed?
No
TMP18xx switches
TMP18xx Responds
to Standard Speed.
in Overdrive Speed
OD Flag = 0
Host Sends Address

Command
No No No No No No No No
69h 3Ch
33h (READADDR)? 55h (MATCHADDR)? F0h (SEARCHADDR)? ECh (ALERTSEARCH)? CCh (SKIPADDR)? 0Fh (FLEXADDR)?
(OVD_MATCHADDR)? (OVD_SKIPADDR)?
Yes Yes Yes Yes Yes Yes Yes

TMP18xx Sends FLAG
TMP18xx Sends FLAG
Host Sends 8 Bytes of Host Sends 8 Bytes of Host Sends 1 Byte of
Address, LSb to MSb Host Sends FLAG Address, LSb to MSb Short Address, LSb to MSb
TMP18xx Sends 8 Bytes of

Address, LSb to MSb OD Flag = 0
Yes TMP18xx with
No Address Search Algorithm No
Does TMP18xx Alert Flag Set? Does TMP18xx No
Address Match? Address Match? Does TMP18xx Short
Address Match?
OD Flag = 0
Yes Yes
Yes
OD Flag = 1
Host Sends Funcon
Figure 7-19. Address Phase Flowchart
7.4.3.2.1 READADDR (33h)

The command can be used by the host to read the 64-bit address of the device. This command must only be
used when there is one device on the bus, as this command will cause a collision if multiple devices are present
on the bus.
7.4.3.2.2 MATCHADDR (55h)
The command is used by the host and is followed by a 64-bit address that is used to select a single device on
the bus. The address for each device is unique, therefore only one device can be selected by the command
while all other devices continue to wait for a bus reset.
7.4.3.2.3 SEARCHADDR (F0h)
The command is used by the host to identify the 64-bit address of each of the devices on the bus after the
system is powered up (see Figure 7-20). Additionally, this command may be run by the host to discover any
new devices that may be added to the system later. When there is a single device bus, the host can skip the
command and instead use the SKIPADDR or OVD_SKIPADDR commands to access the device.
As shown in right side flow of Figure 7-20, when the fast arbitration mode is enabled by setting ARB_MODE
bits as '11b' in the device configuration-2 register, the devices check the bus for the transmitted bit. If the device
reads a bit value other than what they had transmitted, they no longer respond to the command until the next
bus reset. A device that wins the bus continues until the 64th bit, sets the ARB_DONE bit in its status register to
'1b' and stops responding to the next SEARCHADDR command. The arbitration function allows the host a fast
discovery of the devices without having to go through the complicated, memory intensive and longer discovery
method using traditional SEARCHADDR command. At the same time, if the host has an issue on the bus, then
it can simply perform a broadcast write to disable and enable the arbitration mode to restart the fast arbitration
mode.
The device also features an optimized arbitration mode which is enabled by setting ARB_MODE bits as '10b'.
The devices check the transmitted bit, and if the devices detect a logic '0' when they send a logic '1', they do not
participate in the SEARCHADDR command until the next SEARCHADDR command is sent. The device that is

TMP1826
able to send all 64 bits successfully, wins the bus and sets the ARB_DONE bit in its status register to '1b' and
stops responding to next SEARCHADDR command. As a result of the optimized arbitration mode, the host does
not have to manage the complex memory structure to identify devices on the bus and can still use the legacy
software search algorithm.
The host must top searching for devices when it receives "FFFFFFFFh". The host must disable the arbitration
mode bits to clear the ARB_DONE status and enable only when it wants to search for new devices added to the
existing bus.

TMP1826
No No No
Address Command = Address Command =
ECh (ALERTSEARCH)? F0h (SEARCHADDR)?
Yes Yes
No No
Is ARB_MODE = 10? Is ARB_MODE = 11?
Yes Yes
TMP18xx Sends Bit 0 TMP18xx Sends Bit 0 TMP18xx Sends Bit 0
TMP18xx Sends Bit 0
Host Sends Bit 0
No No TMP18xx TMP18xx No
Bit-0 Match? Tx Bit-0 = Rx Bit-0 Tx Bit-0 = Rx Bit-0
Match? Match?
Yes
Yes Yes
TMP18xx Sends Bit 1 TMP18xx Sends Bit 0
TMP18xx Sends Bit 1 Host Sends Bit 0
Host Sends Bit 1

LEGACY ADDRESS SEARCH
OPTIMIZED ARBITRATION
FAST ARBITRATION
Match? Match?
Yes Yes
TMP18xx Sends Bit 1

TMP18xx Sends Bit 63
Host Sends Bit 1
TMP18xx Sends Bit 63 Yes
Host Sends Bit 63
Match? Match?
Yes Yes
Yes
TMP18xx Sends Bit 63
Host Sends Bit 63
Winning TMP18xx Drops out of Next SEARCH
Host Sends a Reset Pulse to restart the

1-Wire Bus communicaon
Figure 7-20. Address Search Algorithm Flowchart
7.4.3.2.4 ALERTSEARCH (ECh)

The command is used by the host to identify if any of the devices have an alarm condition that must be serviced
in alert mode. An alarm condition is set by the device when the temperature conversion is performed and the
temperature result is higher than alert high temperature register or lower than alert low temperature register.
The command uses the same method as the SEARCHADDR command, except that only devices with an alarm

TMP1826
condition shall respond. If none of the devices have an alarm condition, then the host shall get '1' followed by '1'
on the bus. If the device sends a '1' followed by '0', the host shall interpret it as either one or more devices have
an alert condition, or all devices have an alert condition. If there is a bus noise, that causes the line to be sample
erroneously, but if no device has an alert condition, then the host shall get all '1' on the bus during the address
search phase. The ARB_MODE bit does not have an impact on how the subsequent address search algorithm
works.
Only devices that have an alert set shall participate when they receive an ALERTSEARCH address command
and shall respond by sending its 64-bit address. A device shall no longer participate in the send address phase
if it successfully transmits the device address, which automatically clears the internal alert flags, releases the
ALERT pin, until another temperature conversion results in the alert condition getting set. The host controller
must ensure that all parts on the bus are configured in alert mode to use the command.
7.4.3.2.5 SKIPADDR (CCh)
The host can issue this command to select all the devices on the bus. This is useful when the host wants to write
to the scratchpad-1 or trigger the temperature conversion for all the devices on the bus. Additionally, the host
can use the command to increase the overall bus data throughput when there is a single device on the bus.
The host must take care to not issue the command when there are multiple devices on the bus,. If the host
intended to read the devices with this command, it would cause a collision on the bus.
7.4.3.2.6 OVD SKIPADDR (3Ch)
The host can issue this command to select all devices which support overdrive speed in a mixed speed bus.
This is useful when the host wants to write to the scratchpad-1 or trigger the temperature conversion for all
the devices on the bus that support overdrive speeds. Additionally, the host can use the command to increase
the overall bus data throughput when there is a single device on the bus. When the command is issued, only
devices that support overdrive mode shall set the internal OD flag as '1'.
The host must take care to not issue the command when there are multiple devices on the bus which support
overdrive mode. If the host intended to read the devices with this command, it would cause a collision on the
bus.
If the host issues a standard mode bus reset at any time, all devices which have OD flag set as '1' shall clear the
same and revert back to standard mode speed.
7.4.3.2.7 OVD MATCHADDR (69h)
The command is used by the host and is followed by a 64-bit address that is used to select a single device on
the bus in overdrive speed. The address for each device is unique, therefore only one device can be selected by
the command while all other devices have to wait for a bus reset. The selected device shall set its internal OD
flag as '1', and start all further communication in overdrive speed.
If the host issues a standard mode bus reset at any time, or selects another device using the OVD
MATCHADDR, then all other devices which have OD flag set as '1' shall clear the same and revert back to
standard mode speed.
7.4.3.2.8 FLEXADDR (0Fh)
The host issues the command to access a device by its short address that is configured in the short address
register. Using the command does not affect the 64-bit unique address of the device. The FLEXADDR command
is followed by one byte, which is the short address of the device, the host wants to select for further
communication.
7.4.3.3 Function Phase
Figure 7-21, Figure 7-22 and Figure 7-23 show the function phase that follows the address phase. The host may
present different functions during this phase, which is followed by either the host sending data to the device,
reading device data, or starting a temperature conversion. Some of the functions may be broadcast to all the
devices on the bus using SKIPADDR or OVD SKIPADDR. Read functions must always be unicast with a device
selected during the address phase using MATCHADDR, FLEXADDR or OVD MATCHADDR. For cases, where
there is a single device on the bus, the device address selection may be skipped.

TMP1826
No No No No
Function = 44h Function = 4Eh (WRITE Function = 48h (COPY Function = BEh (READ
Host Sends Function (CONVERT TEMP)? SCRATCHPAD-1)? SCRATCHPAD-1)? SCRATCHPAD-1)?
Yes Yes Yes Yes

TMP18xx Sends
Host Sends Host waits for EEPROM
Host waits for conversion Scratchpad Byte starting
DEVICE_CONFIG1 Byte programming time. Line
time. Line held IDLE at Byte-0 (LSB First)
held IDLE
Host Sends
DEVICE_CONFIG2 Byte Yes
Host Sent Reset?
Host Sends SHORT_ADDR No

Byte
No Have first 8 bytes

Host Sends been read?
TEMP_ALERT_LOW LSB
Byte
Yes
Host Sends
TEMP_ALERT_LOW MSB TMP18xx Sends CRC Byte
Byte
Host Sends
TMP18xx Sends
TEMP_ALERT_HIGH LSB
Scratchpad Byte starting
Byte
at Byte-8 (LSB First)
Host Sends
TEMP_ALERT_HIGH MSB
Yes
Byte
Host Sent Reset?
Host Sends
TEMP_OFFSET_LSB Byte No
No Have last 8 bytes

Host Sends been read?
TEMP_OFFSET_MSB Byte
Yes
TMP18xx Sends CRC Byte TMP18xx Sends CRC Byte
Back to Start
Figure 7-21. Function Phase Flowchart for Register Space
7.4.3.3.1 CONVERTTEMP (44h)

The function is issued by the host when the host wants the temperature sensors on the bus to perform a
one-shot temperature conversion.
When the device is bus powered, the host must keep the bus idle for the duration of the active temperature
conversion. The active temperature conversion time is dependent on the conversion mode. After temperature
conversion has completed, the result is updated in temperature result LSB and temperature result MSB and
status registers.
When automatic temperature conversion mode is enabled in the device configuration-1 register, the command
will be ignored.
7.4.3.3.2 WRITE SCRATCHPAD-1 (4Eh)
The function is issued by the host to write the functional registers for the temperature sensor. Following the
function byte, the host transmits the device configuration registers, short address register, temperature alert
low limit registers, temperature alert high limit registers and temperature offset registers. After sending the 9
bytes, the device shall transmit the CRC computed on the 9 bytes and send the CRC back to the host for quick
verification of data integrity.

TMP1826
Additionally, the host can issue a bus reset at any time during the transfer, though it is advised that the same
may be done only at byte boundary to ensure that there is no register corrupted due to incomplete transfer.
When the FLEX_ADDR_MODE bits are updated as a non-zero value, the host must hold off on any
communication to keep the bus in idle state for either tRESDET or tDELAY, as per the requested flex mode, to allow
the device to decode and update the short address. Also when the FLEX_ADDR_MODE bits have a non-zero
value, the byte for short address register shall not be updated in the register scratchpad, for any subsequent
write scratchpad-1 operations, to avoid the overwrite of the decoded short address.
Note
When updating the OD_EN and/or LOCK_EN bit in the device configuration-2 register, the host
controller must send the 9 bytes and wait for the CRC transmission before the change of device speed
or write protection of the register scratchpad can take effect. If the host terminates the transfer before
the complete CRC transmission, then any update to OD_EN and/or LOCK_EN shall not take effect.
7.4.3.3.3 READ SCRATCHPAD-1 (BEh)

The function is issued by the host to read the temperature result, status bits, and functional registers from the
register scratchpad. The selected device transmits the first 8 bytes of the register scratchpad followed by CRC
of the 8 bytes. If the host wants to continue the read operation, the host will receive the next 8 bytes along with
CRC for the last 8 bytes. The host can terminate the function at any point by issuing a bus reset.
7.4.3.3.4 COPY SCRATCHPAD-1 (48h)
The function is issued by the host to copy the scratchpad-1 registers to the EEPROM configuration memory. As
shown in Figure 7-21, the temperature alert registers, configuration register, short address register, temperature
offset and IO pin configuration registers are stored in the configuration EEPROM. There are 9 bytes being
copied from the register space to the NVM, therefore the host must hold the bus in idle state for twice the
EEPROM programming time before it performs the next access.
No No No No
Funcon = 0Fh (WRITE Func on = 55h (COPY Funcon = AAh (READ Funcon = F0h (READ
SCRATCHPAD-2)? SCRATCHPAD-2)? SCRATCHPAD-2)? EEPROM)?
Yes Yes Yes Yes
Host Sends EEPROM Host sends A5h to commit Host Sends EEPROM Host Sends EEPROM
Address High Byte Scratchpad-2 to EEPROM Address High Byte Address High Byte
Host Sends EEPROM Host Sends EEPROM Host Sends EEPROM

Host waits for tPROG
Address Low Byte Address Low Byte Address Low Byte
Host Sends 8 Data Bytes TMP18xx Sends Data

Host waits for tREADIDLE
(LSB First) Bytes (LSB First)
Yes TMP18xx Sends Data

Host Sent Reset?
Bytes (LSB First)
No
Yes
No Host Sent Reset?
Has 8 bytes been
read?
No
Yes
No
Have 8 bytes
TMP18xx Sends CRC Byte TMP18xx Sends CRC Byte been read?
Yes
Back to Start
Figure 7-22. Function Phase Flowchart for Memory Access

TMP1826
7.4.3.3.5 WRITE SCRATCHPAD-2 (0Fh)

The function is issued by the host to prepare data write to the EEPROM using memory scratchpad.
Figure 7-22 shows that the host first sends 2 bytes for the EEPROM address, followed by 8 data bytes. On
receiving the 8 data bytes, the device computes the CRC for total of 10 bytes of address and data received
from the host for data integrity check. The function only copies the data to the memory scratchpad, to enable the
host to change data, before the final EEPROM erase and program. Additionally, the host may use the memory
scratchpad as a 8-byte volatile buffer.
The device does not support byte wise access for EEPROM. All access to the scratchpad are done in
increments of 8 bytes. Hence the host must send the address at the 8-byte block boundary. Figure 7-9 shows
that any attempt to write data at a non-block boundary will result in data corruption for the corresponding
EEPROM page and block.
7.4.3.3.6 READ SCRATCHPAD-2 (AAh)
The function is issued by the host to read the content of the memory scratchpad.
The host first sends the 2 bytes for the EEPROM address (see Figure 7-22). If the 2 bytes of address matches
the address sent during the last WRITE SCRATCHPAD-2, the device responds by sending the 8 bytes of data
that was written to the scratchpad-2 buffer earlier. The host can send a bus reset any time during the transfer. If
the device sends all 8 bytes and no bus reset is received,the device transmits the CRC computed on the 2 byte
of address sent by the host and 8 bytes of data sent by the device to the host for data integrity check.
If there is a mismatch in the EEPROM address, the device shall go back to the start and wait for a bus reset
to restart communication, and the host shall receive '1' on the bus for any subsequent read. This mechanism
ensures that the host can detect an address byte corruption during both WRITE SCRATCHPAD-2 and READ
SCRATCHPAD-2, as both the data bytes and CRC byte will read back as FFh.
7.4.3.3.7 COPY SCRATCHPAD-2 (55h)
The function is issued by the host to copy the contents of scratchpad-2 to the EEPROM. The EEPROM current
is higher during the erase and program, therefore the application must size the external pullup resistor to ensure
that there is sufficient current drawn by the one or more devices or implement a low impedance current path
using an external FET/transistor switch parallel to the bus pullup resistor.
The host application must ensure that only WRITE SCRATCHPAD-2 or READ SCRATCHPAD-2, with address of
the intended location in the user EEPROM, are issued before COPY SCRATCHPAD-2 is sent. The device stores
and uses the address sent during WRITE SCRATCHPAD-2 to identify the location in the user EEPROM where
the copy operation shall be performed. The host only needs to send one byte with A5h to initiate the copy of
the memory content from scratchpad-2 to the user EEPROM, at the address location already specified, when
performing the commit operation. The host must hold the bus in idle state for the EEPROM programming time
before starting any new access on the bus.
7.4.3.3.8 READ EEPROM (F0h)
The function is issued by the host to read the EEPROM memory directly.
The host sends 2 bytes for the address of the EEPROM location, that it wants to read. The device then
sends the data bytes starting from that location until the internal address pointer does not reach the end of
the EEPROM or host does not issue a bus reset. If the internal address pointer reaches end of the EEPROM
location, the device shall send 1's on the bus. After sending the 2 bytes for the address of the EEPROM location
to access, and when moving between block boundary, the host must idle the bus for tIDLE as specified in the
EEPROM characteristics. Additionally, there is no CRC provided in the response from the device during the
READ EEPROM function.

TMP1826
The device does not support byte wise access for EEPROM. All access to the memory is done in increments
of 8 bytes. Hence the host must send the address at the 8-byte block boundary. If the address is sent for a
non-block boundary, the device shall send data from the start of the corresponding block as shown in Figure 7-9.
No No
Funcon = F5h (GPIO Func on = A5h (GPIO
READ)? WRITE)?
Yes Yes
Host Sends GPIO

Conguraon Byte
TMP18xx Sends GPIO Host Sends Inverted GPIO

Read Register Conguraon Byte
No
Is GPIO Conguraon
TMP18xx Sends CRC Byte Byte transmission OK?
Yes
TMP18xx Sends OK Code TMP18xx Sends Fail Code

No AAh FFh
Host Sent Reset
Yes
Back to Start
Figure 7-23. Function Phase Flowchart for IO Access
7.4.3.3.9 GPIO WRITE (A5h)

The function is issued by the host to configure and read the GPIO.
The host sends the IO configuration byte, followed by the inverted IO configuration byte value. This enables the
device to check for bit error due to bus noise. If there errors detected, then the device shall transmit a fail code
of FFh to the host, for the host to retry. If there are no errors detected, then the device shall transmit the success
code of AAh.
7.4.3.3.10 GPIO READ (F5h)
The function is issued by the host to read the GPIO.
After issuing the function, the device sends a byte which has the corresponding IO status, followed by the CRC
for the IO status byte. The host may repeat the sequence to implement a polling loop.
7.4.4 NVM Operations
The TMP1826 device follows a common procedure for programming user data and enabling the memory
protection for user data.

TMP1826
7.4.4.1 Programming User Data

Programming of user data to the memory use the functions WRITE SCRATCHPAD-2, READ SCRATCHPAD-2
and COPY SCRATCHPAD-2 as described earlier. The application must use the address in the provided
functional memory map to write user data to the device.
1. Host issues a bus reset, then waits for the response and sends the address command for the specific
device.
2. Host issues a WRITE SCRATCHPAD-2 with the address as per the functional memory map and the 8 bytes
of data and 1 byte of CRC to verify the transfer.
device.
4. Host issues a READ SCARTCHPAD-2 with the address as per the functional memory map, then reads the 8
bytes of data and 1 byte of CRC to ensure that it is same as what was written in the earlier step.
device.
6. Host issues a COPY SCRATCHPAD-2 with the data bytes as A5h to commit the data to user EEPROM.
7.4.4.2 Register and Memory Protection
The TMP1826 provides user configurable protection for both the scratchpad-1 registers and the memory region
as described below.
7.4.4.2.1 Scratchpad-1 Register Protection
The device provides for a one-time write protection for the entire register map. All the writable registers, except
for IO configuration, can be write-protected. To enable the write protection permanently, the host controller must
set LOCK_EN bit in the device configuration-2 register, then copy the register to the configuration EEPROM.
When the configuration EEPROM is programmed, the change is permanent and irreversible.
Additionally, the device provides temporary write protection mechanism. If the LOCK_EN bit is not committed
to configuration EEPROM, the device shall prevent any write to the register scratchpad-1 region, except the IO
configuration register as long as power is applied. If the device goes through a POR, then the LOCK_EN bit shall
be cleared to allow the host to update the register scratchpad-1.
7.4.4.2.2 User Memory Protection
The device provides a configurable one-time memory protection mechanism. Memory protection is available at
page level of 32 bytes of 256 bits. There is one level of memory protection and two modes of memory operation
available on the TMP1826:
• Public Read and Write: This is default memory option for factory-programmed parts. The host controller can
read and write without any additional steps.
• Public Read with write protection: In this mode, the host controller can read the memory without any specific
steps, but write access is not allowed.
Each page can be protected using a special address described below:
Table 7-5. User Memory Protection
USER MEMORY PROTECTION ADDRESS
PROTECTION LEVEL COMMENTS
PAGE NUMBER FIELD
OPERAND
User memory page-0 cannot be erased and programmed in any mode.
80h 00h
Public mode read access is allowed.
80h 01h
80h 02h
80h 03h
80h 04h

TMP1826
Table 7-5. User Memory Protection (continued)

USER MEMORY PROTECTION ADDRESS
PROTECTION LEVEL COMMENTS
PAGE NUMBER FIELD
OPERAND
80h 05h
80h 06h
80h 07h
The memory protection bits can be programmed only one time. Hence after a page is locked, it cannot be
unlocked. The method to lock a user memory page in public read-only with write protection is described in the
following sequence:
device.
2. Host issues a WRITE SCRATCHPAD-2 with the address as 800Nh, where N is the page number, and data
byte as 55h.
device.
4. Host issues a READ SCRATCHPAD-2 with the address as 800Nh, where the N is the page number and
reads the data byte to ensure it is 55h.
device.
6. Host issues a COPY SCRATCHPAD-2 with the data byte as A5h to commit the protection for the page.
7. Host waits for the programming time before starting any new bus operation.

TMP1826
7.5 Programming
The TMP1826 has multiple methods in which an application can access the device functions for temperature
conversion and EEPROM programming. When accessing multiple device the MATCHADDR command along
with the 64-bit device address must be used. If the short address has been programmed uniquely, then the host
may use the FLEXADDR command along with the 8-bit short address.
The sections below describe the sequences that must be followed to access the device functions properly.
7.5.1 Single Device Temperature Conversion and Read
Table 7-6 shows the program flow that the host MCU must execute for temperature conversion and subsequent
read of the temperature result. As the temperature results are the first two bytes of the register scratchpad-1, the
host may optionally stop the read after the device transmits the first two bytes by performing a bus reset.
Table 7-6. Single Device Temperature Conversion and Read Scratchpad-1 Sequence
HOST TO DEVICE DEVICE TO HOST COMMENTS
Reset Host sends reset to initialize communication
Answer to Reset Device responds to initialization
SKIPADDR (CCh) Host sends address command to select all device(s)
CONVERTTEMP (44h) Host sends function command to start temperature conversion
Bus idle for tDELAY + tCONV Bus is held in idle state (high) during temperature conversion
READ SCRATCHPAD-1 Host sends function command to read register scratchpad-1
(BEh)
TEMP_RESULT_L Device sends temperature result LSB register
TEMP_RESULT_H Device sends temperature result MSB register
STATUS_REG (Optional read for host) Device sends status register
FFh (Optional read for host) Device sends reserved byte
CONFIG_REG1 (Optional read for host) Device sends configuration-1 register
CONFIG_REG2 (Optional read for host) Device sends configuration-2 register
SHORT_ADDR (Optional read for host) Device sends short address register
CRC (Optional read for host) Device sends CRC on first 8 bytes
TEMP_ALERT_LOW_L (Optional read for host) Device sends temperature alert low LSB register
TEMP_ALERT_LOW_H (Optional read for host) Device sends temperature alert low MSB register
TEMP_ALERT_HIGH_L (Optional read for host) Device sends temperature alert high LSB register
TEMP_ALERT_HIGH_H (Optional read for host) Device sends temperature alert high MSB register
TEMP_OFFSET_L (Optional read for host) Device sends temperature offset LSB register
TEMP_OFFSET_H (Optional read for host) Device sends temperature offset MSB register
CRC (Optional read for host) Device sends CRC on last 8 bytes
7.5.2 Multiple Device Temperature Conversion and Read

Table 7-7 shows the program flow that the host MCU must execute for temperature conversion and subsequent
read of the temperature result for multiple devices. The host must use the MATCHADDR command to address
each device on the bus, because the devices do not arbitrate on a read function.

TMP1826
Table 7-7. Multiple Device Temperature Conversion and Read Scratchpad-1 Sequence
CONVERTTEMP (44h) Host sends function command to start temperature conversion
Bus idle for tDELAY + tCONV Bus is held in idle state (high) during temperature conversion
MATCHADDR (55h) Host sends address command to select specific device
DEVICE-1 ADDRESS Host sends 8 byte device address for selecting device-1
(BEh)
TEMP_RESULT_L Device-1 sends temperature result LSB register
TEMP_RESULT_H Device-1 sends temperature result MSB register
(BEh)
TEMP_RESULT_L Device-2 sends temperature result LSB register
TEMP_RESULT_H Device-2 sends temperature result LSB register
7.5.3 Register Scratchpad-1 Update and Commit

Table 7-8 shows the sequence the host must execute to update the register scratchpad and commit to the
configuration EEPROM. The host must read the scratchpad to ensure it can perform the correct read modify
write to the registers, before it copies the same to the configuration EEPROM.
If the host has only one device, or if the application can guarantee no bus corruption, then it may use SKIPADDR
command to globally update and commit the register scratchpad region with the same settings. However once
committed and locked, it is not possible for the host to update the locations anymore, and hence TI strongly
advises that the host still read the locations before running the commit operation.
Table 7-8. Register Scratchpad-1 Update and Program Configuration EEPROM
DEVICE-1 ADDRESS Host sends 8 byte for selecting device-1
(BEh)
16 register bytes + 2 CRC Device sends first 8 register scratchpad-1 bytes followed by CRC byte and then
bytes last 8 register scratchpad-1 bytes followed by CRC byte
Reset
WRITE SCRATCHPAD-1 Host sends function command to write register scratchpad-1
(4Eh)
9 register bytes Host sends the updated 9 register scratchpad-1 bytes

TMP1826
Table 7-8. Register Scratchpad-1 Update and Program Configuration EEPROM (continued)
CRC Device sends CRC for the register bytes
COPY SCRATCHPAD-1 Host sends function command to write copy scratchpad-1 to configuration
(48h) EEPROM
Bus idle for tPROG for Bus is held in idle state (high) during configuration EEPROM erase-program
register
7.5.4 Single Device EEPROM Programming and Verify

Table 7-9 shows the correct procedure the host must execute to update the EEPROM. When communicating
with a single device, the host may use the SKIPADDR command. However when communicating with multiple
devices, the host must use the MATCHADDR command or the FLEXADDR command to address the correct
device. The host writes to the EEPROM scratchpad first, reads it back to verify the content before it copies the
same to the user EEPROM. The copy command is issued with the qualifier byte A5h and the bus is held idle for
the duration of erase and program of the EEPROM. The host shall repeat the sequence for every 8 byte page.
After the locations are programmed, the host may issue an READ EEPROM function with the start address to
read all the bytes. The device shall read back the bytes in page size and put a CRC byte after every page to
ensure that the host shall be able to identify bit corruption using the CRC over a smaller data packet.
As long as the host continues the read operation, the device shall read back 8 bytes of data followed by a CRC
byte. When the device reaches the end of the EEPROM block, the device shall return all 1's to the host.
Table 7-9. Single Device EEPROM Program and Verify Sequence
WRITE SCRATCHPAD-2 Host sends function command to write to scratchpad-2
(0Fh)
2-byte EEPROM Address Host sends 2-byte EEPROM address where data has to be written with MSB first
and LSB last
8-bytes data Host sends 8-byte data for the EEPROM address
CRC Device sends CRC for the address and data
READ SCRATCHPAD-2 Host sends function command to read from scratchpad-2
(AAh)
2-byte EEPROM Address Host sends 2-byte EEPROM address for which data has been written with MSB
first and LSB last
8-bytes data Device sends 8 bytes from scratchpad-2
CRC Device sends CRC for the 8 bytes
COPY SCRATCHPAD-2 Host sends function command to copy scratchpad-2 to EEPROM
(55h)
A5h Host sends qualifier byte for EEPROM program

TMP1826
Table 7-9. Single Device EEPROM Program and Verify Sequence (continued)
Bus idle for tPROG Bus is held in idle state (high) during EEPROM programming
READ EEPROM (F0h) Host sends function command to read EEPROM
2-byte EEPROM Address Host sends 2-byte address to the EEPROM to read data
Bus idle for tREADIDLE Bus is held in idle state (high) during read to prefetch the data
8-bytes data Device sends 8 bytes from EEPROM address
CRC Device sends CRC for the 8 bytes
Bus idle for tREADIDLE Bus is held in idle state (high) during read to prefetch the data
7.5.5 Single Device EEPROM Page Lock Operation

When the device EEPROM is successfully programmed as shown in Table 7-9, the host shall execute the
sequence, as shown in Table 7-10, to write-protect the EEPROM page.
Table 7-10. Single Device EEPROM Page Lock Sequence
WRITE SCRATCHPAD-2 Host sends function command to write to scratchpad-2
(0Fh)
80h Host sends page protection byte
0Nh Host sends page number to lock
55h Host sends lock code byte
CRC Device sends CRC
READ SCRATCHPAD-2 Host sends function command to read from scratchpad-2
(AAh)
80h Host sends page protection byte
0Nh Host sends page number to lock
55h Device sends lock code byte
COPY SCRATCHPAD-2 Host sends function command to lock the page
(55h)
A5h Host sends qualifier byte for EEPROM program
Bus idle for tPROG Bus is held in idle state (high) during EEPROM programming
7.5.6 Multiple Device IO Read

Table 7-11 shows the program flow that the host MCU must execute for reading the IO from a device. The host
selects the device it wants to communicate with and issues the GPIO READ function and the device returns the
IO read register value along with the CRC for the byte. The device at this point shall again sample the IOs. If the

TMP1826
host issues a bus reset during the sampling time, the device shall terminate the update process and it will hold
the last sampled value. If the host continues, then the new sampled values shall be sent back by the device.
Table 7-11. Multiple Device GPIO Read Sequence
GPIO READ (F5h) Host sends function command for GPIO read
IO Read Register Device samples the GPIO and sends the IO read register data
GPIO READ (F5h) Host sends function command for GPIO read
7.5.7 Multiple Device IO Write

Table 7-12 shows the program flow that the host MCU must execute for configuring the IO for a device. The
host selects the device it wants to communicate with and issues the GPIO WRITE function. The host shall
then send the IO configuration register followed by an inverted value, that allows the device to check for any
bus transmission error. If the host receives a return code any other than AAh, it must terminate the transaction
by sending a bus reset and again write to the IO configuration register. If the host plans to read the device
continuously, then it must send a bus reset and initiate a GPIO READ function.
Table 7-12. Multiple Device GPIO Write Sequence
GPIO WRITE (A5h) Host sends function command for GPIO write
IO configuration data Host sends IO configuration data
IO configuration data Host sends inverted IO configuration data
Return Code Device returns AAh for successful write and FFh for error
GPIO WRITE (A5h) Host sends function command for GPIO write
IO configuration data Host sends IO configuration data
IO configuration data Host sends inverted IO configuration data
Return Code Device returns AAh for successful write and FFh for error

TMP1826
7.6 Register Map

Table 7-13. Register Map
SCRATCHPAD-1
TYPE RESET REGISTER NAME REGISTER DESCRIPTION SECTION
BYTE
00h RO 00h TEMP_RESULT_L Temperature result LSB register Go
01h RO 00h TEMP_RESULT_H Temperature result MSB register Go
02h RO 3xh STATUS_REG Status register Go
03h RO FFh Reserved Reserved
04h R/W 70h CONFIG_REG1 Device Configuration-1 register Go
05h R/W 80h CONFIG_REG2 Device Configuration-2 register Go
06h R/W 00h SHORT_ADDR Short address register Go
07h RO FFh Reserved Reserved
08h R/W 00h TEMP_ALERT_LOW_L Temperature alert low limit LSB Go
09h R/W 00h TEMP_ALERT_LOW_H Temperature alert low limit MSB Go
0Ah R/W F0h TEMP_ALERT_HIGH_L Temperature alert high limit LSB Go
0Bh R/W 07h TEMP_ALERT_HIGH_H Temperature alert high limit MSB Go
0Ch R/W 00h TEMP_OFFSET_L Temperature offset LSB register Go
0Dh R/W 00h TEMP_OFFSET_H Temperature offset MSB register Go
0Eh RO FFh Reserved Reserved
0Fh RO FFh Reserved Reserved
— RO F0h IO_READ IO read register Go
— WO 00h IO_CONFIG IO configuration register Go
Table 7-14. Access Type Codes

Access Type Code Description
Read Type
R R Read
RC R Read
C to Clear
R-0 R Read
-0 Returns 0s
Write Type
W W Write
W0CP W W
0C 0 to clear
P Requires privileged access
Reset or Default Value
-n Value after reset or the default
value

TMP1826
7.6.1 Temperature Result LSB Register (Scratchpad-1 offset = 00h) [reset = 00h]
The register is part of the 16-bit temperature result readout that stores the least significant byte of the output
of the most recent conversion. Following a power up, the register has the value 00h until the first conversion is
complete.
Return to Register Map.
Figure 7-24. Temperature Result LSB Register
7 6 5 4 3 2 1 0
TEMP_RESULT[7:0]
R-00h
Table 7-15. Temperature Result LSB Register Field Descriptions

Bit Field Type Reset Description
7:0 TEMP_RESULT[7:0] R 00h Stores the LSB of the most recent temperature conversion
results.
7.6.2 Temperature Result MSB Register (Scratchpad-1 offset = 01h) [reset = 00h]
The register is part of the 16-bit temperature result readout that stores the most significant byte of the output
of the most recent conversion. Following a power up, the register has the value 00h until the first conversion is
complete.
Figure 7-25. Temperature Result MSB Register
7 6 5 4 3 2 1 0
TEMP_RESULT[15:8]
R-00h
Table 7-16. Temperature Result MSB Register Field Descriptions

7:0 TEMP_RESULT[15:8] R 00h Stores the MSB of the most recent temperature conversion
results.

TMP1826
7.6.3 Status Register (Scratchpad-1 offset = 02h) [reset = 3Ch]

This register provides status of the alert flags, data ready, power mode, arbitration completion, and device lock.
The lock flag is set after the device configuration EEPROM is locked by the application. The arbitration done
flag is set after the device successfully sends its device address and is cleared only when the ARB_MODE bits
in the configuration register are cleared. The power mode status flag value is decided based on the powering
technique used for the device detected at power up and updated during every bus reset.
The alert flags are set after the most recent conversion results are available and cleared when the status register
is read by the host application. In alert mode, the alert flag when set, cannot be cleared by the device even if the
result of the last conversion is between the alert limits.
The data ready flag is set after a conversion is completed. It is automatically cleared when the host controller
reads the status register.
Figure 7-26. Status Register
7 6 5 4 3 2 1 0
ALERT_HIGH ALERT_LOW Reserved DATA_READY POWER_MOD ARB_DONE LOCK_STATUS
E
RC-0b RC-0b R-11b RC-0b R-xb R-0b R-0b
Table 7-17. Status Register Field Description

7 ALERT_HIGH R/RC 0b Alert high status flag
0b = Last temperature conversion result is less than alert high
limit
1b = Last temperature conversion result is more than or equal to
alert high limit
Alert high status flag is available on the IO2 pin when the pin is
configured for alert function
6 ALERT_LOW R/RC 0b Alert low status flag

0b = Last temperature conversion result is more than alert low
limit
1b = Last temperature conversion result is less than or equal to
alert low limit
Alert low status flag is available on the IO2 pin when the pin is
configured for alert function
5:4 Reserved R 11b Reserved
3 DATA_VALD RC 0b Data valid status flag
0b = No update in temperature result register
1b = Temperature result register updated after conversion
The data valid flag is automatically cleared when the host
controller reads the status register
2 POWER_MODE R xb Device power mode flag.
0b = VDD powered mode
1b = Bus powered mode
1 ARB_DONE R 0b Arbitration complete flag
0b = Arbitration is not complete or not enabled
1b = Arbitration is complete
0 LOCK_STATUS R 0b Lock status flag.
0b = Device configuration registers can be updated
1b = Device configuration registers cannot be updated

TMP1826
7.6.4 Device Configuration-1 Register (Scratchpad-1 offset = 04h) [reset = 70h]

The register is used to configure the device functions like temperature data format, alert mode, and averaging
averaging, and conversion type (one-shot, auto and stacked conversion in bus powered mode and one-shot in
VDD powered mode). The host can store the updated setting to the configuration EEPROM using the COPY
SCRATCHPAD-1 function command. At power-on reset, the register setting is automatically restored from the
configuration EEPROM.
Figure 7-27. Device Configuration-1 Register
7 6 5 4 3 2 1 0
TEMP_FMT Reserved CONV_TIME_S ALERT_MODE AVG_SEL CONV_MODE_SEL[2:0]
EL
RW-0b RW-1b RW-1b RW-1b RW-0b RW-000b
Table 7-18. Device Configuration-1 Register Field Descriptions

7 TEMP_FMT RW 0b Selects the temperature format.
0b = 12-bit legacy format
1b = 16-bit high precision format
6 Reserved RW 1b Reserved. Host must always write this bit as 1b.
5 CONV_TIME_SEL RW 1b Selects the ADC conversion time
0b = 3 ms /
1b = 5.5 ms
4 ALERT_MODE RW 1b Alert pin function only available in VDD powered mode
0b = Alert pin works in Alert Mode
1b = Alert pin works in Comparator Mode
3 AVG_SEL RW 0b Conversion averaging selection
0b = No averaging
1b = Averaging of 8 back-to-back conversions
2:0 CONV_MODE_SEL[2:0] RW 000b Conversion mode selection bits.
When device is in bus powered mode:
000b = Default one shot conversion mode using CONVERT
TEMP function
001b = Stacked conversion mode is enabled. When enabled,
the short address is used to stagger the actual conversion start
with respect to the conversion request.
010b = Auto temperature conversion mode is enabled
011b - 111b = Reserved. Device behavior is unspecified.
When device is in VDD powered mode:
000b = Default one shot conversion mode using CONVERT
TEMP function
001b - 111b = Reserved

TMP1826
7.6.5 Device Configuration-2 Register (Scratchpad-1 offset = 05h) [reset = 80h]
This register is used to configure the overdrive enable, flexible address mode, arbitration mode during address
discovery, and the hysteresis for alert status. The register can be used to lock the writable registers for the
device. All register bits except FLEX_ADDR_MODE can be stored in the configuration EEPROM using the
COPY SCRATCHPAD-1 function command and restored at power-on reset.
Note
1. When setting the lock enable bits, the application must send all the scratchpad-1 data bytes and
read the CRC from the device before the change of overdrive bit takes effect.
2. When FLEX_ADDR_MODE is selected to decode resistor or IO pins, the bus must be put in idle
state after the device configuration-2 register byte is transmitted for tRESDET.

Figure 7-28. Device Configuration-2 Register
7 6 5 4 3 2 1 0
OD_EN FLEX_ADDR_MODE[1:0] ARB_MODE[1:0] HYSTERESIS[1:0] LOCK_EN
RO-1b RW-00b RW-00b RW-00b RW-0b
Table 7-19. Device Configuration-2 Register Field Description

7 OD_EN RO 1b Overdrive mode enable
0b = Overdrive speed is disabled
1b = Overdrive speed is enabled
The bit when set cannot be cleared by host write and will
automatically be cleared only by a standard speed reset signal.
6:5 FLEX_ADDR_MODE[1:0] RW 00b Flexible address mode selection.
00b = Short address register is updated by host
01b = Short address register is updated by IO pin decode
10b = Short address register is updated by Resistor decode
11b = Short address register is updated by combined IO and
resistor address decode
Flexible address mode selection takes effect only when there is
a change detected in the bit setting.
4:3 ARB_MODE[1:0] RW 00b Arbitration mode
00b = Arbitration by device is disabled
01b = Reserved
10bh = Arbitration by device is enabled in software compatible
mode
11b = Fast Arbitration mode is enabled
The arbitration feature is applicable only when address
command is SEARCHADDR. Other commands and functions
are not affected by the ARB_MODE bit.
2:1 HYSTERESIS[1:0] RW 00b Alert hysteresis selection
00b = 5 °C hysteresis
01b = 10°C hysteresis
0 LOCK_EN RW 0b Register protection enable bit
0b = The register protection is disabled
1b = The register protection is enabled.
When set, the bit cannot be cleared by writing to the
scratchpad-1 to unlock the register protection. The feature when
enabled, prevents application write to the temperature offset,
temperature alert low, temperature alert high, short address and
device configuration registers.
See Note-1 above.

TMP1826
7.6.6 Short Address Register (Scratchpad-1 offset = 06h) [reset = 00h]

The register is used to program the short address for the device. The host can store the updated setting to the
configuration EEPROM using the COPY SCRATCHPAD-1 function command. At power-on reset, the register
setting is automatically restored from the configuration EEPROM. As described in Flexible Device Address,
the specific short address decoded value is overlaid on the non-volatile memory content restored to the short
address register after decoding.
The short address register can be updated by the host when the FLEX_ADDR_MODE bits have the value '00b'.
Any write to register when the FLEX_ADDR_MODE bits are not '00b' shall be ignored by the device.
Figure 7-29. Short Address Register
7 6 5 4 3 2 1 0
SHORT_ADDRESS[7:0]
RW-00h
Table 7-20. Short Address Register Field Descriptions

7:0 SHORT_ADDRESS[7:0] RW 00h Stores the short address for the device which may be used to
access the device without sending the 64-bit Unique Device
Address. The short address is also used during stacked
conversion mode to stagger the active conversion.

TMP1826
7.6.7 Temperature Alert Low LSB Register (Scratchpad-1 offset = 08h) [reset = 00h]
This register provides the LSB for the low temperature alert threshold to compare with the latest temperature
conversion result. The register on the first power up has the alert threshold set in legacy format. If there is
a change of format, then the application must update the register in the new format. If the latest temperature
conversion result is less than the threshold set, then the device shall update the alert low status flag in the status
register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the alert
pin low if the device is in VDD powered mode.
The factory state format for the register is legacy mode. The host can store the updated setting to the
setting is automatically restored from the configuration EEPROM.
Figure 7-30. Temperature Alert Low LSB Register
7 6 5 4 3 2 1 0
ALERT_LOW[7:0]
RW-00h
Table 7-21. Temperature Alert Low LSB Register Field Descriptions

7:0 ALERT_LOW[7:0] RW 00h Stores the LSB of the alert low limit for comparison with the last
temperature conversion result
7.6.8 Temperature Alert Low MSB Register (Scratchpad-1 offset = 09h) [reset = 00h]
This register provides the MSB for the low temperature alert threshold to compare with the latest temperature
conversion result is less than the threshold set, then the device shall update the alert low status flag in the status
register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the alert
pin low if the device is in VDD powered mode.
Table 7-22. Temperature Alert Low MSB Register
7 6 5 4 3 2 1 0
ALERT_LOW[15:8]
RW-00h
Table 7-23. Temperature Alert Low MSB Register Field Description

7:0 ALERT_LOW[15:8] RW 00h Stores the MSB of the alert low limit for comparison with the last

TMP1826
7.6.9 Temperature Alert High LSB Register (Scratchpad-1 offset = 0Ah) [reset = F0h]
This register provides the LSB for the high temperature alert threshold to compare with the latest temperature
conversion result is more than the threshold set, then the device shall update the alert high status flag in the
status register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the
alert pin low if the device is in VDD powered mode.
Figure 7-31. Temperature Alert High LSB Register
7 6 5 4 3 2 1 0
ALERT_HIGH[7:0]
RW-F0h
Table 7-24. Temperature Alert High LSB Register Field Descriptions

7:0 ALERT_HIGH[7:0] RW F0h Stores the LSB of the alert high limit for comparison with the last
7.6.10 Temperature Alert High MSB Register (Scratchpad-1 offset = 0Bh) [reset = 07h]
This register provides the MSB for the high temperature alert threshold to compare with the latest temperature
conversion result is more than the threshold set, then the device shall update the alert high status flag in the
status register, respond with the status bit flagged for an alert during the ALERTSEARCH command, and set the
alert pin low if the device is in VDD powered mode.
Figure 7-32. Temperature Alert High MSB Register

7 6 5 4 3 2 1 0
ALERT_HIGH[15:8]
RW-07h
Table 7-25. Temperature Alert High MSB Register Field Description

7:0 ALERT_HIGH[15:8] RW 07h Stores the MSB of the alert high limit for comparison with the
last temperature conversion result

TMP1826
7.6.11 Temperature Offset LSB Register (Scratchpad-1 offset = 0Ch) [reset = 00h]
The register is used to store the LSB of the offset calibration for the temperature sensor. The register on
the first power up has the temperature offset set in legacy format. If there is a change of format, then
the application must update the register in the new format. After every temperature conversion, the offset
calibration is automatically applied to the temperature result, before being stored in the TEMP_RESULT_L and
TEMP_RESULT_H registers.
Figure 7-33. Temperature Offset LSB Register
7 6 5 4 3 2 1 0
TEMP_OFFSET_L[7:0]
RW-00h
Table 7-26. Temperature Offset LSB Register Field Descriptions

7:0 TEMP_OFFSET_L[7:0] RW 00h Stores the offset correction LSB for the temperature result
7.6.12 Temperature Offset MSB Register (Scratchpad-1 offset = 0Dh) [reset = 00h]
The register is used to store the MSB of the offset calibration for the temperature sensor. The register on
the first power up has the temperature offset set in legacy format. If there is a change of format, then
the application must update the register in the new format. After every temperature conversion, the offset
calibration is automatically applied to the temperature result, before being stored in the TEMP_RESULT_L and
TEMP_RESULT_H registers and compared with limits registers.
Figure 7-34. Temperature Offset MSB Register
7 6 5 4 3 2 1 0
TEMP_OFFSET_H[15:8]
RW-00h
Table 7-27. Temperature Offset MSB Register Field Descriptions

7:0 TEMP_OFFSET_H[15:8] RW 00h Stores the offset correction MSB for the temperature result

TMP1826
7.6.13 IO Read Register [reset = F0h]

The register is used to read the state of the IO0 to IO3 pin. The register values are updated when the GPIO
READ function is issued by the host. When IO2 is configured to function as an alert pin, it provides a status of
the alert pin.
Figure 7-35. IO Read Register
7 6 5 4 3 2 1 0
nIO3_STATE nIO2_STATE nIO1_STATE nIO0_STATE IO3_STATE IO2_STATE IO1_STATE IO0_STATE
R-1b R-1b R-1b R-1b R-0b R-0b R-0b R-0b
Table 7-28. IO Read Register Field Descriptions

7 nIO3_STATE R 1b Read inverted value of the IO3 pin when configured as a digital
input or output
input or output
input or output
input or output
3 IO3_STATE R 0b Read value of the IO3 pin when configured as a digital input or
output
output
output
output
7.6.14 IO Configuration Register [reset = 00h]

The register is used to select the IO function for the pins marked IO0-IO3 on the device. When selected to
function as a digital open-drain output, the pin shall be able to drive a 0 or 1 externally for controlling open
drain output on IO0 to IO3 pin. In bus powered mode, IOs tied to SDQ and used for short address must not be
configured as output as this may cause the SDQ line to be driven low. TI strongly recommends to use a 20 KΩ
resistor between IO pins and SDQ.
Figure 7-36. IO Configuration Register
7 6 5 4 3 2 1 0
IO3_SEL[1:0] IO2_SEL[1:0] IO1_SEL[1:0] IO0_SEL[1:0]
WO-00b WO-00b WO-00b WO-00b
Table 7-29. IO Configuration Register Field Descriptions

7:6 IO3_SEL[1:0] WO 00b Selects the function of the IO
00b = IO3 is configured as input buffer and can be read
01b = Reserved
10b = IO3 is configured as an output in open drain mode and
the IO is driven as '0'
11b = IO3 is configured as an output in open drain mode and the
IO is driven as Hi-Z

TMP1826
Table 7-29. IO Configuration Register Field Descriptions (continued)

01b = IO2 is configured as an open drain active low alert
01b = Reserved
01b = Reserved

TMP1826
8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information

The TMP1826 can operate as a 1-Wire half duplex bus, either in supply or bus powered mode. The TMP1826
features a thermal sensor with an integrated 2-kbit user EEPROM for applications requiring identification with
lesser number of components due to space constraints. The device also features an integrated CRC that may be
used for ensuring data integrity during communication.
The bus powered mode is designed for applications working without a dedicated power supply pin and can
reduce cabling costs. As the device current consumption during thermal conversion and EEPROM operations
is low, the device may not require a low impedance current path, thereby reducing the need for additional FET
or load switch and current limiting resistor to bypass the bus pullup resistor. The pullup resistor used during
bus powered mode must be correctly sized to ensure that sufficient current can be supplied during a thermal
conversion and EEPROM operation, and input pin voltage does not fall below the VIH(MIN).
Additionally, if the host needs to reset the device when operating in bus powered mode, the host must pull the
communication line low for at least 50 ms. This allows the internal capacitor of the device to discharge and
prepare the device for power on reset.
8.2 Typical Applications
8.2.1 Bus Powered Application

5.0 V
3.0 kΩ VDD
MCU GPIO SDQ TMP1826 Temperature

Source
GND GND
Figure 8-1. Bus Powered Application
8.2.1.1 Design Requirements

For this design example, use the parameters listed below:
Table 8-1. Design Parameters
PARAMETER VALUE
Power mode Bus Powered (VDD pin is connected to GND)
Supply (VDD) 5.0 V
Pullup resistor range (RPUR) 1.2 kΩ to 3.33 kΩ

TMP1826
8.2.1.2 Detailed Design Procedure

To reduce the wire count, the bus powered mode for TMP1826 is the primary mode of operation. The VDD pin of
the device must be connected to GND and the SDQ pin of the device must be connected to the host GPIO with a
pullup resistor.
To calculate the pullup resistor range, substitute the value for VPUR, VOL(MAX), VIH(MIN) and IPU(MIN) in Equation 2
as the VPUR > 2.0 V.
5.0 − 0.4 5.0 − 4.0

< RPUR < (3)
4 × 10−3 300 × 10−6
1.15 kΩ < RPUR < 3.33 kΩ (4)
The actual value of the pullup resistor can then be adjusted based on the speed of communication and bus or
cable parasitic capacitance.
When the VDD is activated, the TMP1826 draws current through the pullup resistor to charge its internal
capacitors. When the internal capacitor is charged to the pullup voltage, the host can start communication. The
bus idle state is high, which is maintained by the pullup resistor, when the host puts its GPIO in high impedance
state.
The TMP1826 uses the stored charge to operate when the SDQ pin is low and measures the low period to
decode bus reset, logic high and logic low sent by the host. Similarly, when the host reads data from the
TMP1826, it changes the state of the bus from high to low and releases the bus. Depending on whether
the device has to send a logic low or logic high, the device shall either hold the bus low or release the bus
immediately.
8.2.2 Supply Powered Application
1.8 V
0.1 µF
5.1 kΩ VDD
MCU GPIO SDQ TMP1826 Temperature

Source
GND GND
Figure 8-2. Supply Powered Application

PARAMETER VALUE
Power mode VDD Powered
Supply (VDD) 1.8 V
Pullup resistor (RPUR) 5.1 kΩ

The supply powered mode uses the VDD pin connected to the same supply rail as the host and pullup resistor. TI
recommends to put a 0.1-µF bypass capacitor close to the VDD pin of the TMP1826.

TMP1826
The pullup resistor value of 5.1 kΩ, is large enough to provide proper communication with standard speed and
avoid VOL violation when the device is sending data to the host. The user may change the value based on the
total bus load and application operating requirements.
The communication protocol for supply powered mode is same as that for bus powered mode, which allows the
entire software stack to be reused. This mode of operation is useful for onboard thermal sensing applications as
it provides alert function.
8.2.3 UART Interface for Communication
3.3 V
2.2 kΩ VDD
SN74LVC1G07
MCU UART.TX SDQ TMP1826 Temperature
Source
GND UART.RX GND
Oponal series
resistor
Figure 8-3. Using UART to interface TMP1826

PARAMETER VALUE
Power Mode Bus powered
Supply (VDD) 3.3 V
Pullup resistor range (RPUR) 750 Ω to 2.2 kΩ

If using GPIO for communication is not possible due to any reason, it is also possible to use UART peripheral
that is available on most host controllers to interface with the TMP1826. UART is a push-pull full duplex bus and
to interface with TMP1826, it requires a buffer with open-drain driver like the SN74LVC1G07.
The input of the buffer is connected to the UART transmit pin and the output of the buffer is connected to the
SDQ pin on the TMP1826. The output of the buffer is also connected to the UART receive pin on the host. As
the output is open-drain, it requires a pullup resistor which can be calculated in Equation 2 as VPUR > 2.0 V.
Substituting the value for VPUR = 3.3 V, VOL(MAX) = 0.4 V, VIH(MIN) = 2.64 V and IPU(MIN) = 300 µA, the RPUR value
selected must be greater than 725 Ω and less than 2.2 kΩ.
In software, the application must adjust its baud rate so that it can send bus reset to the device by sending
00h. The start bit of the UART frame which is always 0, provides the required falling edge for data sent to
the TMP1826. When sending a logic high to the device, the UART shall send FFh to the TMP1826 and, when
sending a logic low to the device, the UART shall send C0h. As UART is a full duplex bus, the host must flush its
receive buffers during a transmit operation.
When receiving data from the TMP1826, the host shall send FFh and the device when transmitting a logic high
will detect and release the bus, while when transmitting a logic low will detect and hold the bus low. As a result,
the host shall receive a FFh for a logic high and F0h for a logic low depending on the baud rate configured.

TMP1826
8.3 Power Supply Recommendations

The TMP1826 operates with a power supply in the range of 1.7 V to 5.5 V in both VDD powered and bus
powered modes. When operating in VDD powered mode, a power-supply bypass capacitor is required for
precision and stability. Place this power-supply bypass capacitor as close to the supply and ground pins of
the device as possible. A typical value for this supply bypass capacitor is 0.1 µF. Applications with noisy or
high-impedance power supplies can require a bigger bypass capacitor to reject power-supply noise.
In bus powered mode, the VDD pin must be connected to ground. The internal capacitor in the device is sufficient
to provide power during bus communication. The internal capacitor is recharged through the external pullup
resistor during the recovery period. In cases, where there is a long bus length or at higher temperatures, it may
be necessary for the host to provide additional time for bus recovery or to use the overdrive speed in which the
part uses the internal capacitor charge less.
When using IO pins to control external circuits, take care that currents to these pins do not heat the part and
offset temperature measurements.
8.4 Layout
8.4.1 Layout Guidelines
Place the power-supply bypass capacitor as close as possible to the supply and ground pins when in supply
powered mode. The recommended value of the capacitor is 0.1 µF. The open-drain SDQ pin requires an
external pullup resistor which must not be higher than RPUR.
When in bus powered mode, only the external pullup resistor is required for the open-drain SDQ pin. As shown
in Figure 8-5, it is recommended to put 20 KΩ pull up resistor when connecting IO to SDQ pin to avoid shorting
the SDQ to GND in case the IO is configured as an output and driven low. The ADDR pin resistor uses very low
current to decode the short address and should be placed close to the device if possible. Care must be taken to
avoid leakage currents to prevent incorrect decoding.
To achieve a high precision temperature reading for a rigid PCB, do not solder the thermal pad. For a flexible
PCB, the user may solder the thermal pad to the increase board level reliability. If the thermal pad is soldered,
then it should be connected to the ground.
8.4.2 Layout Example
Via from Top Layer to Boom Layer
Bo om Layer Trace
Top Layer Trace
Bus Powered Mode VDD Powered Mode
0.1 µF 0.1 µF
VDD IO2 VDD IO2 VDD IO2 VDD IO2
SDQ IO1 SDQ IO1 SDQ IO1 SDQ IO1
ADDR IO0 ADDR IO0 ADDR IO0 ADDR IO0
GND IO3 GND IO3 GND IO3 GND IO3
Figure 8-4. Layout Example

TMP1826
VDD IO2 VDD IO2
SDQ IO1 SDQ IO1 20 K
ADDR IO0 ADDR IO0
GND IO3 GND IO3
Figure 8-5. IO Hardware Address in Bus Powered Mode

TMP1826
9 Device and Documentation Support

9.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.2 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.3 Trademarks
TI E2E™ is a trademark of Texas Instruments.
1-Wire® is a registered trademark of Maxim Integrated Products Inc.
All trademarks are the property of their respective owners.
9.4 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
9.5 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.
10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

TMP1826
PACKAGE OUTLINE
NGR0008C SCALE 5.000
WSON - 0.8 mm max height
PLASTIC SMALL OUTLINE - NO LEAD
2.6 A
B
2.4
PIN 1 INDEX AREA
2.6
2.4
0.8 C
0.7
SEATING PLANE
0.05 0.08 C
0.00
0.88 0.1
SYMM (0.2) TYP

EXPOSED
THERMAL PAD
4 5
2X 9 SYMM
1.5
1.85 0.1
6X 0.5
8
1
0.3
8X
0.2
PIN 1 ID 0.5 0.1 C A B
8X
0.3
0.05 C
4227008/D 03/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com

TMP1826
EXAMPLE BOARD LAYOUT

NGR0008C WSON - 0.8 mm max height
(0.88)
8X (0.6) SYMM
8X (0.25) 1 8
9 SYMM
6X (0.5)
(1.85)
(R0.05) TYP
5
4
(2.3)
LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:30X
0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND
EXPOSED
EXPOSED
METAL
METAL
SOLDER MASK METAL METAL UNDER SOLDER MASK
OPENING SOLDER MASK OPENING
NON SOLDER MASK
DEFINED SOLDER MASK
(PREFERRED) DEFINED
SOLDER MASK DETAILS
4227008/D 03/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com

TMP1826
EXAMPLE STENCIL DESIGN

NGR0008C WSON - 0.8 mm max height
(0.85) METAL
TYP
SYMM
8X (0.6)
8X (0.25) 1 8
9
SYMM
6X (0.5)
(1.67)
(R0.05) TYP
4 5
(2.3)
SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD 9:
87% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:30X
4227008/D 03/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com

PACKAGE OPTION ADDENDUM
www.ti.com 27-Jan-2023
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
PTMP1826NGRR ACTIVE WSON NGR 8 3000 TBD Call TI Call TI -55 to 150 Samples
TMP1826DGKR ACTIVE VSSOP DGK 8 2500 RoHS & Green SN Level-2-260C-1 YEAR -55 to 150 1826 Samples
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 27-Jan-2023
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Dec-2022
TAPE AND REEL INFORMATION
REEL DIMENSIONS TAPE DIMENSIONS

K0 P1
B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers
Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2 Q1 Q2
Q3 Q4 Q3 Q4 User Direction of Feed
Pocket Quadrants
*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TMP1826DGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Dec-2022
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TMP1826DGKR VSSOP DGK 8 2500 366.0 364.0 50.0
Pack Materials-Page 2
GENERIC PACKAGE VIEW
NGR 8 WSON - 0.8 mm max height
2.5 x 2.5, 0.5 mm pitch PLASTIC SMALL OUTLINE - NO LEAD
This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.
4227146/A
www.ti.com
IMPORTANT NOTICE AND DISCLAIMER
TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
standards, and any other safety, security, regulatory or other requirements.
These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license
is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you
will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these
resources.
TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with
such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for
TI products.
TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2023, Texas Instruments Incorporated

TMP 1826

Uploaded by

TMP 1826

Uploaded by

TMP1826

SBOSA45B – FEBRUARY 2022 – REVISED DECEMBER 2022

TMP1826 1-Wire®, ±0.3°C Accurate Temperature Sensor With 2-kbit EEPROM

• LED lighting MCU

• Temperature transmitters GND

• EV charging infrastructure VDD Powered Bus Powered

Changes from Revision * (February 2022) to Revision A (September 2022) Page

2 Submit Document Feedback Copyright © 2022 Texas Instruments Incorporated

Product Folder Links: TMP1826

5 Pin Configuration and Functions

Note: This package is preview only

Figure 5-1. NGR 8-Pin WSON Top View

Figure 5-2. DGK 8-Pin VSSOP Top View

Table 5-1. Pin Functions

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3

6.2 ESD Ratings

6.3 Recommended Operating Conditions

(1) If ADDR pin is not used, it is recommended to be connected to GND

6.4 Thermal Information

6.5 Electrical Characteristics

Temperature resolution (High Including sign bit 16 Bits

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Response time (Stirred Single layer Flex PCB 0.77 s

Active Conversion time (No CONV_TIME_SEL = 0 2.54 3 3.37 ms

Serial bus inactive, one TA = -55°C to 85°C 1.3 3.3

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5

6.6 1-Wire Interface Timing

tRSTH Device to host response time (Figure 6-1)(2) 480 48 µs

6.7 EEPROM Characteristics

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6.8 Timing Diagrams

Figure 6-1. Bus Reset Timing Diagram

tRDV tDSW tRDV tDSW

Figure 6-2. Write Timing Diagram

tSLOT tREC tSLOT tREC

tRL tMSW tRL tMSW

Host Read-1 Host Read-0

Figure 6-3. Read Timing Diagram

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7

Figure 6-4. VDD Powered Initialization Timing Diagram

VPUR Bus Idle Bus Active

Figure 6-5. Bus Powered Initialization Timing Diagram

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Host drives SDQ

6.9 Typical Characteristics

Temperature Error ( C)

0.6 DS Max 0.3

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9

6.9 Typical Characteristics (continued)

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6.9 Typical Characteristics (continued)

VPUR Supply (V)

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11

ADDR Internal IO3

ScratchPad-1 ADC IO1

SDQ 2 kbit User

Figure 7-1. Functional Block Diagram

7.3 Feature Description

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VPUR − VOL MAX V − 1.6

VPUR − VOL MAX VPUR − VIH MIN

High Precision Format

Figure 7-2. Temperature Format

Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 13

Table 7-1. Precision (16-Bit) Temperature Data Format

Table 7-2. Legacy (12-Bit) Temperature Data Format

7.3.5 Temperature Offset

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7.3.6 Temperature Alert

7.3.8 Flexible Device Address

Byte-4 Device Conguraon-1 Register Device Conguraon-1 Register

IO Congura on Register IO Conguraon Register