HW and Layout Design Consideration For DDR3 SDRAM Memory Interfaces

Freescale Semiconductor Document Number: AN3940
Rev. 0, 01/2010
Application Note
Hardware and Layout Design

Considerations for DDR3 SDRAM
Memory Interfaces
by Networking and Multimedia Group
Freescale Semiconductor, Inc.
Austin, TX
The design guidelines presented in this application note Contents

1. Designer Checklist . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
apply to products that leverage the DDR3 SDRAM IP core, 2. Termination Dissipation . . . . . . . . . . . . . . . . . . . . . . . 7
and they are based on a compilation of internal platforms 3. VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
designed by Freescale Semiconductor, Inc. The purpose of 4. VTT Voltage Rail . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
these guidelines is to minimize board-related issues across 5. Layout Guidelines for the Signal Groups . . . . . . . . . . 8
6. Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
multiple memory topologies while allowing maximum 7. Further Reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
flexibility for the board designer. 8. Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Freescale highly recommends that the system/board designer

verify all design aspects (signal integrity, electrical timings,
and so on) through simulation before PCB fabrication.
© Freescale Semiconductor, Inc., 2010. All rights reserved.

Designer Checklist
1 Designer Checklist
In the following checklist, some of the items are phrased as question, others as requirements. In all cases,
we recommend that you consider the line item and check it off in the rightmost column of Table 1.
Table 1. DDR3 Designer’s Checklist
Item Description Yes/No
Simulation
1. Have optimal termination values, signal topology, trace lengths been determined through simulation for each
signal group in the memory implementation? If on-die termination is used at both the memories and the controller,
no additional termination is required for the data group.
The following unique groupings exist:
1. Data Group: MDQS(8:0), MDQS(8:0), MDM(8:0), MDQ(63:0), MECC(7:0)
2. Address/CMD Group: MBA(2:0), MA(15:0), MRAS, MCAS, MWE.
3. Control Group: MCS(3:0), MCKE(3:0), MODT(3:0)
4. Clock Group: MCK(5:0) and MCK(5:0)
These groupings assume a full 72-bit data implementation (64-bit + 8 bits of ECC). Some products may only
implement 32-bit data and may choose to have fewer MCS, MCKE, and MODT signals. Some products support
the optional MAPAR_OUT and MAPAR_ERR for registered DIMMs. In such cases, MAPAR_OUT should be
treated as part of the ADDR/CMD group and MAPAR_ERR can be treated as an asynchronous signal.
2. Does the selected termination scheme meet the AC signaling parameters (voltage levels, slew rate, and
overshoot/undershoot) across all memory chips in the design?
Termination Scheme
It is assumed that the designer is using the mainstream termination approach as found in commodity PC motherboards.
Specifically, it is assumed that on-die termination is used for the data groups and that external parallel resistors tied to VTT are
used for the Address/CMD and the control groups. Consequently, differing termination techniques may also prove valid and
useful. However, they are left to the designer to validate through simulation.
3. Is the worst case power dissipation for the termination resistors within the manufacturer’s rating for the selected
devices? See Section 2, “Termination Dissipation.”
4. If resistor packs are used, have data lanes been isolated from the other DDR3 signal groups?
Note: Because on-die termination is the preferred method for DDR3 data signals, external resistors for the data
group should not be required. This item would only apply if the ODT feature is not used.
5. Have VTT resistors been properly placed? The RT terminators should directly tie into the VTT island at the end of
the memory bus.
6. Is the differential terminator present on the clock lines for discrete memory populations? (DIMM modules contain
this terminator.) Nominal range => 100–120 Ω.
7. Recommend that an optional 5pF cap be placed across each clock diff pair. If DIMM modules are used, the cap
should be placed as closely as possible to the DIMM connector. If discrete devices are used, the cap should be
placed as closely as possible to the discrete devices.
VTT Related Items
8. Has the worst case current for the VTT plane been calculated based on the design termination scheme? See
Section 2, “Termination Dissipation.”
9. Can the VTT regulator support the steady state and transient current needs of the design?
Hardware and Layout Design Considerations for DDR3 SDRAM Memory Interfaces, Rev. 0
2 Freescale Semiconductor
Designer Checklist
Table 1. DDR3 Designer’s Checklist (continued)
10. Has the VTT island been properly decoupled with high frequency decoupling? At least one low ESL cap, or two
standard decoupling caps for each four-pack resistor network (or every four discrete resistors) should be used. In
addition, at least one 4.7-μF cap should be at each end of the VTT island.
Note: This recommendation is based on a top-layer VTT surface island (lower inductance). If an internal split is
used, more capacitors may be needed to handle the transient current demands.
11. Has the VTT island been properly decoupled with bulk decoupling? At least one bulk cap (100–220 μF) capacitor
should be at each end of the island.
12. Has the VTT island been placed at the end of the memory channel and as closely as possible to the last memory
bank? Is the VTT regulator placed in close proximity to the island?
13. Is a wide surface trace (~150 mils) used for the VTT island trace?
14. If a sense pin is present on the VTT regulator, is it attached in the middle of the island?
VREF
15. Is VREF routed with a wide trace? (Minimum of 20–25 mil recommended.)
16. Is VREF isolated from noisy aggressors? In addition, maintain at least a 20–25 mil clearance from VREF to other
traces. If possible, isolate VREF with adjacent ground traces.
17. Is VREF properly decoupled? Specifically, decouple the source and each destination pin with 0.1uf caps.
18. Does the VREF source track variations in VDDQ, temperature, and noise as required by the JEDEC specification?
19. Does the VREF source supply the minimal current required by the system (memories + processor)?
20. If a resistor divider network is used to generate VREF, are both resistors the same value and 1% tolerance?
Routing
21. The suggested routing order within the DDR3 interface is as follows:
1. Data address/command
2. Control
3. Clocks
4. Power
This order allows the clocks to be tuned easily to the other signal groups. It also assumes an open critical layer
on which clocks are freely routed.
22. Global items are as follows:

• Do not route any DDR3 signals overs splits or voids.
• Traces routed near the edge of a reference plane should maintain at least 30–40 mil gap to the edge of the
reference plane.
• Allow no more than 1/2 of a trace width to be routed over via antipad.
23. When routing the data lanes, route the outermost (that is, longest lane first) because this determines the amount
of trace length to add on the inner data lanes.
24. The max lead-in trace length for data/address/command signals, are not longer than 7 inches?
25. Are the clock pair assignments optimized to allow break-out of all pairs on a single critical layer?
Freescale Semiconductor 3
Designer Checklist
26. The DDR3 data bus consists of 9 data byte lanes (assuming ECC is used). All signals within a given byte lane
should be routed on the same critical layer with the same via count.
Note: Some product implementations may only implement a 32-bit wide interface.
Byte Lane 0—MDQ(7:0), MDM(0), MDQS(0), MDQS(0)
Byte Lane 8—MECC(7:0), MDM(8), MDQS(8), MDQS(8)
To facilitate fan-out of the DDR3 data lanes (if needed), alternate adjacent data lanes onto different critical layers.
See Figure 1 and Figure 2.
Note: If the device supports ECC, Freescale highly recommends that the user implement ECC on the initial
hardware prototypes.
27. DDR3 data group—impedance range and spacing

Option #1 (wider traces—lower trace impedance)
• Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.
• Utilize wider traces if stackup allows (7–8 mils)
• Spacing to other data signals = 1.5x to 2.0x
• Spacing to all other non-DDR signals = 4x
Option #2 (smaller traces—higher trace impedance)
• Single-ended impedance = 50 Ω.
• Smaller trace widths (5–6 mil) can be used.
• Spacing between like signals should increase to 3x (for 5 mil) or 2.5x (for 6 mil) respectively
28. Check the following across all DDR3 data lanes:

• For MPC8572 and MPC8536, are all the data lanes matched to within 0.1 inch?
• For all other devices, are all the data lanes matched to within 0.75 inch?
29. Is each data lane properly trace matched to within 20 mils of its respective differential data strobe? (Assumes
highest frequency operation.)
30. When adding trace lengths to any of the DDR3 signal groups, ensure that there is at least 25 mils between
serpentine loops that are in parallel.
Designer Checklist
31. MDQS/MDQS differential strobe routing

Note: Some product implementations may support only the single-ended version of the strobe.
• Match all segment lengths between differential pairs along the entire length of the pair. Trace match the MDQS/
MDQS pair to be within 10 mils.
• Maintain constant line impedance along the routing path by maintaining the required line width and trace
separation for the given stackup.
• Avoid routing differential pairs adjacent to noisy signal lines or high speed switching devices such as clock
chips.
• Differential 75–95 Ω
• Diff Gap = 4–5 mils (as DQS signals are not true differential...aka pseudo differential
• Single-ended impedance 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.
• Spacing to other data signals = 2x.
• If not routed on the same layer as its associated data, then 4x spacing
• Spacing between like signals (other data) should increase to 3x (for 5 mil) or 2.5x (for 6 mil) respectively.
• Do not divide the two halves of the diff pair between layers. Route MDQS/MDQS pair on the same critical layer
as its associated data lane.
32. DDR3 address/command/control group—impedance range and spacing

• Daisy chain from chip to chip. The routing should go from chip 0 to chip n, where chip 0 is the one that has the
lower data bits DQ[0:7]… and chip n has the upper data bits. The daisy chain should end at the termination
resistors that are after chip n.
• With regards to physical/spacing properties
• Single-ended impedance = 40 Ω. The lower impedance allows traces to be slightly closer with less cross-talk.
• Spacing to other like signals = 1.5x to 2.0x
• Spacing to all other non-DDR signals = 3–4x
• Spacing between like signals should increase to 3x (for 5 mil) or 2.5x (for 6 mil) respectively
• Spacing to all other non-DDR signals = 3–4x
• With regards to tuning
• Tune signals to 20 mil of the clock at each device.
33. DDR3 differential clocks

Route as diff pair. With regards to diff properties, recommendations are as follows:
• P-to-N tuning = 10 mils
• Target single-ended impedance 40–50 Ω. The lower impedance reduces cross-talk.
• Differential 75–95 Ω
• Diff Gap = set per stackup
• Attempt to utilize wider traces if stackup allows (7–8 mils)
• Spacing to other signals = 4x.
• Spacing to other signals = 4x.
Designer Checklist
34. Are all clock pairs routed on the same critical layer (one referenced to a solid ground plane)?
35. Are all clock pairs properly trace matched to within 25 mils of each other?
36. The space from one differential pair to any other trace (this includes other differential pairs) should be at least 25
mils.
37. If unbuffered DIMM modules are used, are all required clock pairs per DIMM slot connected?
Note: Single ranked DIMM requires 1 clock pair and dual ranked DIMM requires 2 clock pairs
MODT/MDIC Related Items
38. Are the MODT signals connected correctly?

• MODT(0), MCS(0), MCKE(0) should all go to the same physical memory bank.
39. Is MDIC0 connected to ground via an 40-Ω precision 1% resistor? Is MDIC1 connected to DDR power via an 40-Ω
precision 1% resistor?
Miscellaneous Items
40. Are the power-on reset config pins properly set for the correct DDR type?
Note: Not all Freescale products support external power-on reset configuration pins for selecting the DDR type.
Therefore, this item does not apply to all Freescale products.
Registered DIMM Topologies (All items above still apply)
41. For memory implementations that use registered DIMM modules, the board designer should attach a reset signal
to the DIMM sockets. This reset signal should be derived from a ‘power good’ monitor status circuit.
Note: The reset pin to the DRAM is 1.5 V LVCMOS.
42. Though registered DIMMs require only a single clock per bank, all DDR3 clock pairs at the DIMM connector
should be attached (analogous to unbuffered DIMMs) so the design can also support unbuffered DIMMs with
minimal changes.
43. If the controller supports the optional MAPAR_OUT and MAPAR_ERR signals, ensure that they are hooked up
as follows:
• MAPAR_OUT (from the controller) => PAR_IN (at the RDIMM)
• ERR_OUT (from the RDIMM) => MAPAR_ERR (at the controller)
44. MAPAR_ERR is an open drain output from registered DIMMs. Ensure that a 4.7K pull-up to 1.5 V is present on
this signal.
Discrete Memory Topologies (All items above still apply with exception of registered DIMM items)
45. Construct the signal routing topologies for the groups like those found on unbuffered DIMM modules (that is,
proven JEDEC topologies).
46. When placing components, optimize placement of the discretes to favor the data bus (analogous to DIMM
topologies).
Optional: Pin-swap within a given byte lane to optimize the data bus routes further.
Caution: Do not swap individual data bits across different byte lanes.
Termination Dissipation
47. If a single bank of x16 devices is used, let the DDR3 clocks be point-to-point. Place the series damping resistor
(RS) close to the source and the differential terminator (RDIFF) at the input pins of the discretes.
If more than five discretes are used, construct the clocks like those on unbuffered DIMM modules. Alternatively,
place an external PLL between the controller and the memory to generate the additional clocks.
48. If multiple physical banks are needed, double stack (top and bottom) the banks to prevent lengthy and undesirable
address/cmd topologies.
49. Properly decouple the DDR3 chips per manufacturer recommendations. Typically, five low ESL capacitors per
device are sufficient. For further information, see article entitled Decoupling Capacitor Calculation for a DDR
Memory Channel, located on Micron’s web site.
50. To support expandability into larger devices, ensure that extra NC pins (future address pins) are connected.
51. Ensure access/test points are available for signal integrity probing. This is especially critical if using blind and
buried vias within the memory channel. If through-hole vias are used under the BGA devices, then generally these
sites can be used for probing.
52. Ensure RT, resistors on the address and control groups are located after the last DRAM chip in the-fly-by topology.
53. Ensure the reset pin has been considered and connected to the proper reset logic.
Note: The reset pin to the DRAM is 1.5V LVCMOS.
2 Termination Dissipation
Sink and source currents flow through the parallel RT resistors on the address and control groups. The
worst case power dissipation for these resistors is as follows:
Power = I2 * RT = (13 mA)2 * (47 Ω) = 7.9 mW.
Small resistors that provide dissipation of up to 1/16 W are ideal. See Section 4, “VTT Voltage Rail,” for
assumptions made for current calculations.
3 VREF
The current requirements for VREF are relatively small, at less than 3 mA. This reference provides a DC
bias of 0.75 V (VDD/2) for the differential receivers at both the controller interface and the DDR devices.
Noise or deviation in the VREF voltage can lead to potential timing errors, unwanted jitter, and erratic
behavior on the memory bus. To avoid these problems, VREF noise must be kept within the JEDEC
specification. As such, VREF and the VTT cannot be the same plane because of the DRAM VREF buffer
sensitivity to the termination plane noise. However, both VREF and VTT must share a common source
supply to ensure that both are derived from the same voltage plane. Proper decoupling at each VREF pin (at
the controller, at each DIMM/discrete, and at the VREF source) along with adhering to the simple layout
considerations enumerated in the checklist in Table 1 prevents potential problems.
Numerous off-the-shelf power IC solutions are available that provide both the VREF and VTT from a
common source. Regardless of the generation technique, VREF must track variations in VDDQ over voltage,
temperature, and noise margins as required by the JEDEC specifications.
VTT Voltage Rail
4 VTT Voltage Rail

For a given topology, the worst case VTT current should be derived. Assuming the use of a typical RT
parallel termination resistor and the worst case parameters given in Table 2, sink and source currents can
be calculated.
Table 2. Worst Case Parameters for VTT Current Calculation
Parameter Values Comment

VDDQ(max) 1.575 V From JEDEC spec
VTT(max) 0.798 V From JEDEC spec
VTT(min) 0.702 V From JEDEC spec
RDRVR 20 Ω Nominally, full strength is ~ 20 Ωs
RT 47 Ω Can vary. Typically 25–47Ωs.
VOL 0V Assumes driver reaches 0 V in the low state.
The driver sources (VTT plane would sink) the following based on this termination scheme:
(VDD_max – VTT_min)/(RT + RDRVR) = (1.575–0.702 V)/(47 + 20) = 13 mA
The driver sinks (VTT plane would source) the following based on this termination scheme:
(VTT_max – VOL / (RT + RS + RDRVR) = (0.798–0 V)/(47 + 20) = 12 mA
A bus with balanced number of high and low signals places no real demand on the VTT supply. However,
a bus with all DDR address/command/control signals low (~ 28 signals) causes a transient current demand
of approximately 350 mA on the VTT rail. The VTT regulator must provide a relatively tight voltage
regulation of the rail per the JEDEC specification. Besides a tight tolerance, the regulator must also allow
VTT along with VREF (if driven from a common IC), to track variations in VDDQ over voltage, temperature,
and noise margins.
5 Layout Guidelines for the Signal Groups

To help ensure the DDR interface is properly optimized, Freescale recommends the following sequence
for routing the DDR memory channel:
1. Route data
2. Route address/command/control
3. Route clocks
The data group is listed before the command, address, and control group because it operates at twice the
clock speed, and its signal integrity is of higher concern. In addition, the data group constitutes the largest
portion of the memory bus and comprises most of the trace matching requirements (those of the data
lanes). The address/command, control, and data groups all have a relationship to the routed clock.
Therefore, the effective clock lengths used in the system must satisfy multiple relationships. The designer
should perform simulation and construct system timing budgets to ensure that these relationships are
properly satisfied.
Layout Guidelines for the Signal Groups
5.1 Data—MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7]

The data signals of the DDR interface are source-synchronous signals by which memory and the controller
capture the data using the data strobe rather than the clock itself. When transferring data, both edges of the
strobe are used to achieve the 2x data rate.
An associated data strobe (DQS and DQS) and data mask (DM) comprise each data byte lane. This 11-bit
signal lane relationship is crucial for routing, and Table 3 depicts this relationship. When length matching,
the critical item is the variance of the signal lengths within a given byte lane to its strobe. Length matching
across all bytes lanes is also important and must meet the tDQSS parameter as specified by JEDEC. This is
also commonly referred to as the write data delay window. Typically, this timing is considerably more
relaxed than the timing of the individual byte lanes themselves.
Table 3. Byte Lane to Data Strobe and Data Mask Mapping
Data Data Strobe Data Mask Lane Number
MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0
MECC[0:7] MDQS8, MDQS8 MDM8 Lane 8
NOTE
When routing, each row (that is, the 11-bit signal group) must be treated as
a trace-matched group.
5.2 Layout Recommendations

Freescale strongly recommends routing each data lane adjacent to a solid ground reference for the entire
route to provide the lowest inductance for the return currents, thereby providing the optimal signal
integrity of the data interface. This concern is especially critical in designs that target the top-end interface
speed, because the data switches at 2x the applied clock. When the byte lanes are routed, signals within a
byte lane should be routed on the same critical layer as they traverse the PCB motherboard to the
memories. This consideration helps minimize the number of vias per trace and provides uniform signal
characteristics for each signal within the data group.
To facilitate ease of break-out from the controller perspective, and to keep the signals within the byte group
together, the board designer should alternate the byte lanes on different critical layers (see Figure 1 and
Figure 2).
Data Lane 7
Data Lane 5
Data Lane 3
Data Lane 1
Figure 1. Alternating Data Byte Lanes on Different Critical Layers —Part 1
Data Group 6
Data Group 4
Data Group 8
Data Group 2
Data Group 0
Figure 2. Alternating Data Byte Lanes on Different Critical Layers—Part 2
Simulation
6 Simulation
This application note provides general hardware and layout considerations for hardware engineers
implementing a DDR3 memory subsystem.The rules and recommendations in this document can serve as
an initial baseline for board designers to begin their specific implementations. The fly-by memory
topology and many interface frequencies are possible from the DDR3 interface, so it is highly
recommended that the board designer verify that all aspects (signal integrity, electrical timings, and so on)
are addressed through simulation before board fabrication.
In tandem with memory vendors, Freescale provides IBIS models for simulation. The board designer can
realize a key advantage in the form of extra noise and timing margins by taking the following actions:
• Optimizing the clock to signal group relationships to maximize setup and hold times
• Optimizing termination values. During board simulation, verify that all aspects of the signal eye
are satisfied, which includes at a minimum the following:
— A sufficient signal eye opening meeting both timing and AC input voltage levels
— Vswing max not exceeded (or alternatively max overshoot/max undershoot)
— Signal slew rate within specifications
Figure 3 shows the SSTL signal waveform.
Figure 3. SSTL Signal Waveform
Further Reading
7 Further Reading
Following is a list of documentation that may be useful:
• DDR3 chapter of the corresponding PowerQUICC or QorIQ processor reference manual
• Micron web site: http://www.micron.com. For example, Design Guide for DDR3-1066 UDIMM
systems: TN_41_08
• JEDEC web site: http://www.jedec.com. For example, the DDR3 SDRAM specification
8 Revision History
Table 4 provides a revision history for this application note.
Table 4. Document Revision History
Rev.
Date Substantive Change(s)
Number
0 01/2010 Initial public release
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Freescale Semiconductor Document Number: AN3940

Hardware and Layout Design

The design guidelines presented in this application note Contents

Freescale highly recommends that the system/board designer

© Freescale Semiconductor, Inc., 2010. All rights reserved.

Item Description Yes/No

VTT Related Items

Table 1. DDR3 Designer’s Checklist (continued)

Item Description Yes/No

22. Global items are as follows:

Table 1. DDR3 Designer’s Checklist (continued)

Item Description Yes/No

27. DDR3 data group—impedance range and spacing

28. Check the following across all DDR3 data lanes:

Table 1. DDR3 Designer’s Checklist (continued)

Item Description Yes/No

31. MDQS/MDQS differential strobe routing

32. DDR3 address/command/control group—impedance range and spacing

33. DDR3 differential clocks

Table 1. DDR3 Designer’s Checklist (continued)

Item Description Yes/No

MODT/MDIC Related Items

38. Are the MODT signals connected correctly?

Registered DIMM Topologies (All items above still apply)

Table 1. DDR3 Designer’s Checklist (continued)

Item Description Yes/No

4 VTT Voltage Rail

Parameter Values Comment

VTT(max) 0.798 V From JEDEC spec

VTT(min) 0.702 V From JEDEC spec

RDRVR 20 Ω Nominally, full strength is ~ 20 Ωs

RT 47 Ω Can vary. Typically 25–47Ωs.

VOL 0V Assumes driver reaches 0 V in the low state.

5 Layout Guidelines for the Signal Groups

5.1 Data—MDQ[0:63], MDQS[0:8], MDM[0:8], MECC[0:7]

Data Data Strobe Data Mask Lane Number

MDQ[0:7] MDQS0, MDQS0 MDM0 Lane 0

MDQ[8:15] MDQS1, MDQS1 MDM1 Lane 1

MDQ[16:23] MDQS2, MDQS2 MDM2 Lane 2

MDQ[24:31] MDQS3, MDQS3 MDM3 Lane 3

MDQ[32:39] MDQS4, MDQS4 MDM4 Lane 4

MDQ[40:47] MDQS5, MDQS5 MDM5 Lane 5

MDQ[48:55] MDQS6, MDQS6 MDM6 Lane 6

MDQ[56:63] MDQS7, MDQS7 MDM7 Lane 7

MECC[0:7] MDQS8, MDQS8 MDM8 Lane 8

5.2 Layout Recommendations

Figure 1. Alternating Data Byte Lanes on Different Critical Layers —Part 1

Figure 2. Alternating Data Byte Lanes on Different Critical Layers—Part 2

Figure 3. SSTL Signal Waveform

0 01/2010 Initial public release

Document Number: AN3940

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