Design and Implementation of Sychronous 4-Bit Up Counter Using Cmos 90Nm Technology

A MINI PROJECT REPORT ON
DESIGN AND IMPLEMENTATION OF SYCHRONOUS 4-

BIT UP COUNTER USING CMOS 90NM TECHNOLOGY
A Mini project report submitted in partial fulfillment of the requirement for the award
of the degree of
BACHELOR OF TECHNOLOGY
IN
ELECTRONICS AND COMMUNICATION ENGINEERING
Submitted
By
KRISHNAVENI 20S15A0410
N.PRABHAS 20S15A0415
B.RAJASHEKAR REDDY 20S15A0420
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

MALLA REDDY INSTITUTE OF TECHNOLOGY AND SCIENCE
Permanently affiliated to JNTUH and approved by AICTE, New Delhi
NBA and NAAC Accredited, ISO 9001:2015 certified, Approved by U.K Accreditation centre,
Granted status of 2(f) and 12(b) under UGC act 1956, Govt. of India.
MAISAMMAGUDA, DHULAPALLY, SECUNDERABAD-500100
2020-2023
MALLA REDDY INSTITUTE OF TECHNOLOGY AND SCIENCE
Permanently affiliated to JNTUH and approved by AICTE, New Delhi
NBA and NAAC Accredited, ISO 9001:2015 certified, Approved by U.K Accreditation center,
Granted status of 2(f) and 12(b) under UGC act 1956, Govt. of India.
MAISAMMAGUDA, DHULAPALLY, SECUNDERABAD-500100
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
CERTIFICATE
This is to certify that the mini project report entitled “DESIGN AND
IMPLEMENTATION OF SYCHRONOUS 4-BIT UP COUNTER CMOS 90NM
TECHNOLOGY“beingsubmittedKRISHNAVENI(20S15A0410),P R A B H A S (20S
15A0415),B.RAJASHEKARREDDY (20S15A0420), in partial fulfillment of the
degree of Bachelor of Technology in Electronics and Communication Engineering
during the academic year 2022-2023.
Certified further, to the best of our knowledge, the work reported here is not a
part of any other project on the basis of which a degree or an award has been given on
an earlier occasion to any other candidate. The results have been verified and found to
be satisfactory.
Head of the Department External Examiner
Mr. K.Y. SRINIVAS

Associate Professor
ACKNOWLEDGMENT
We express a whole-hearted gratitude to Dr. K. RAVINDRA, Principal and

Professor of Electronics and Communication Engineering Department, Malla Reddy
Institute of Technology and Science for providing us the conducive environment for
carrying my academic schedules and projects with ease.
We thank Mr. K. Y. SRINIVAS Associate Professor and Head of Department of
Electronics and Communication Engineering for providing seamless support and
knowledge over the past one year and also for providing right suggestions every phase of
the development of our project
We sincerely thank all staff members, friends and parents without whose support
project would have been deferred.
ii
ABSTRACT
Design of synchronous 4-bit up counter is proposed using master-slave negative pulse-triggered D

flip-flops. The master slave D flip-flop is implemented using 8 nand gates and an inverter. The
counter is provided with additional synchronous clear, and count enable inputs. The main objective is
to optimize the layout of the synchronous 4-bit up counter in terms of area. The design is implemented
using Cadence Virtuoso schematic editor and simulated using Cadence Virtuoso analog design
environment at 90nm CMOS process technology. The optimized layout of the counter is designed
using Cadence Virtuoso Layout Suite. The counter has transistor count of 210. The estimated power
of the counter is 97.90μW and delay is 20.39ns.
.
iii
CONTENTS
TOPIC PAGE NO.

ACKNOWLEDGEMENT ii
ABSTRACT iii
LIST OF FIGURES vii
LIST OF TABLES ix
ABBREVIATIONS x
CHAPTER 1: OVERVIEW OF THE PROJECT 1-3
1.1 Introduction 1
1.2 Problem Statement 2
1.3 Objective 2
1.4 Methodology Adopted 2
1.5 Motivation 2
1.6 Tools Required 2
CHAPTER 2: LITERATURE SURVEY 3-4

2.1 Introduction 3
2.2 Literature survey 4
CHAPTER 3:COUNTERS 5-7
3.1 Introduction 5
3.2 Introduction of counters 5
3.3 Types of counters 5-6
3.3.1 Asynchronous counter 5
3.3.2 Synchronous counter 6
3.4 Based on counting 7
3.4.1 Up counter 7
3.4.1 Down counter 7
3.4.3 Up/Down counter 7
CHAPTER 4:FLIP-FLOP
4.1 Introduction 8
4.2 Flip-Flop 8
4.3 Types of Flip-Flop 8-11
4.3.1 SR Flip-Flop 8
4.3.2 JK Flip-Flop 9
4.3.3 D Flip-Flop 10
4.3.4 T Flip-Flop 11
iv
CHAPTER 5: DESIGN OF SYCHRONO-BIT UP
COUNTERUUSING 12-15
LOGIC GATE
5.1 Introduction 12
5.2 Basic logic gate 12
5.3 4-Bit up counter using logic gate 13
CHAPTER 6 : SYCHRONOUS 4 BIT UP COUNTER 16-24
USING CMOS
6.1 Introduction 16
6.2 MOS as switch 16
6.3 CMOS Inverter 17
6.4 CMOS XOR 19
6.5 D Flip-Flop 20
6.6 Synchronous 4-bit up counter using CMOS 21
transistors
CHAPTER 7 : COMPARISON BETWEEN GATE & 25
TRANSISTER LEVEL
Comparison between gate level and transistor 25
level
CHAPTER 8: APPLICATIONS 26
Applications of Synchronous 4-bit up counter
CHAPTER 9: CONCLUSION AND FUTURE SCOPE 27
9.1 Conclusion 27
9.2 Future scope 27
REFERENCES 28
APPENDIX 29-38
v
LIST OF FIGURES
Figure no. Description Page no.
Fig no 3.1 Asynchronous counter 5
Fig no 3.2 Timing diagram of Asynchronous counter 6
Fig no 3.3 Synchronous counter 6

Fig no 3.4 Timing diagram of Synchronous counter 7
Fig no 4.1 Circuit diagram of SR flip-flop 8
Fig no 4.2 Circuit diagram of JK flip-flop 9
Fig no 4.3 Circuit diagram of D flip-flop 10
Fig no 4.5 Circuit diagram of T flip-flop 11
Fig no 5.1 Synchronous counter using logic gate 13
Fig no 5.2 Synchronous 4-bit up counter schematic 14
using DSCH
Fig no 5.3 Synchronous 4-bit up counter counter layout 14
using Micro wind
Fig no 5.4 Synchronous 4-bit up counter counter timing 15
diagram using
Micro wind
Fig no 6.1 MOS transistors symbol 16
Fig no 6.2 CMOS Inverter 18
Fig no 6.3 XOR schematic using DSCH 19
Fig no 6.4 XOR layout using Micro wind 19
Fig no 6.5 XOR timing diagram 20
Fig no 6.6 D Flip-Flop using NAND Gates 20
Fig no 6.7 D Flip-Flop using NAND Gates schematic layout 21
Fig no 6.8 Synchronous 4-bit up counter counter using CMOS 22
Schematic Using DSCH
Fig no 6.9 Synchronous4-bit up counter counter layout using 23
Micro win
Fig no 6.10 Synchronous 4-bit up counter counter transistor level 24
Timing diagram
Fig no 7.1 Synchronous 4 bit counter of Bar graph comparison 25
Between gates & transistors
vi
LIST OF TABLES
Table no. Description Page no.
Table 4.1.1 SR flip-flop truth table 8
Table 4.2.2 JK flip-flop truth table 9
Table 4.3.3 D flip-flop truth table 10
Table 4.4.4 T flip-flop truth table 11
Table 5.1 Basic logic gate symbols 12
Table 7.1 Synchronous 4-bit up counter
25
of results comparisonbetween
gate & transistor
vii
ABBREVIATIONS
CMOS : Complementary Metal Oxide Semiconductor
D : Delay or Data
DC : Direct Current
DSCH : Digital Schematic
MOS : Metal Oxide Semiconductor
NMOS : N- Channel Metal- Oxide Semi conductor
PDP : Power Delay Product
PMOS : P- Channel Metal- Oxide Semi conductor
viii
DESIGN AND IMPLEMENTATION OF SYNCHRONOUS 4-BIT UP COUNTER
CHAPTER 1
OVERVIEW OF THE PROECT
In this chapter introduction, problem statement, motivation, objective
methodology adopted, tools required, organisation report and conclusion reports are
discussed.
1.1 Introduction
As CMOS technology growing towards nano meter scale, the performance of any
electronics devices become challenging task because there are several parameters gets
affected due to scaled down the devices, researchers have developed various types of
logic circuits to increase the performance of electronic systems. One of the most
important categories of the logic family which is required for design any types of
electronics system is sequential logic circuits.
Counting is a fundamental function of digital circuits. A digital counter consists of a
collection of flip-flops that change state (set or reset) in a prescribed sequence. The
primary function of a counter is to produce a specified output pattern sequence. For
this reason, it is also a pattern generator. This pattern sequence might correspond to the
number of occurrences of an event, or it might be used to control various portions of a
digital system. In this latter case each pattern is associated with a distinct operation that
the digital system must perform. There are tremendous applications of a counter in the
digital consumer electronics market. A counter can play a vital role in several circuits
ranging from a simple display to complex microcontroller circuits. Some of the
apparent applications of a counter are frequency divider in phase-locked loops,
frequency synthesizers, signal generation and processing circuits, microcontrollers,
digital memories and in digital clock and timing circuits. A counter is another example
of a register.
As in the case of a register each of the 0-1 combinations that are stored in the
collection of flip-flops that comprise the counter, that is the output pattern, is known as
a state of the counter. The total number of states is called its modulus. Thus, if a
counter has „m‟ distinct states, then it is called a modulus-m counter or mod-m
counter. The order in which the states appear is referred to as its counting sequence.
The proposed synchronous 4-bit up counter is implemented using Cadence EDA tool.
The tool provides sophisticated features such as Cadence Virtuoso schematic editor
which provides sophisticated capabilities which speed and ease the design, Cadence
Virtuoso Visualization and Analysis which efficiently analyzes the performance of the
design, Cadence Virtuoso Layout Suite that speeds up the physical layout of the design
and Cadence Assura Physical Verification reduces overall verification time because it
incorporates a fast and intuitive debug capability integrated within the Virtuoso custom
design environment. It helps to easily recognize, fix, extract and compare errors.
Several counter circuits have been proposed targeting on design accents such as power,
delay, and area. Among those designs synchronous counters using master-slave D
flipflops have been widely used. The paper is organized as follows: in section 2, the
design of the proposed counter is presented. In section 3, the schematic and layout are
presented. In section 4, the simulation results are given and discussed. The area, power
and delay of the counter are estimated.
Department of ECE, MRITS 1

1.2 PROBLEM STATEMENT
Power and delay are the two parameters which are considered primarily in VLSI
domain. The main objective is to optimize the layout of the synchronous 4-bit up
counter in terms of area
1.3 MOTIVATION
The main motive of this research is to achieve less power dissipation and better
performance in the field of VLSI applications. CMOS VLSI design is like a modular
approach to creating ICs. Small circuit blocks are connected into larger circuit blocks
which are then connected at the system level to create a complete integrated circuit
These smaller circuit blocks can be analog, digital, or mixed-signal circuits. , CMOS
circuit has simple structure, low power consumption, large noise tolerance and strong
temperature stability, which is conducive to high integration. In addition, due to the
high degree of integration, the entire circuit is integrated in the chip
1.4 OBJECTIVE
The main objective of the project is to design and implementation of synchronous

4-bit up counter
1.5 METHODOLOGY ADOPTED

Power, delay and area are the two important parameters. So, we need to have
designs which take these two parameters into account. Technology like CMOS is a
step towards achieving this goal by having the Capability to have benefits of both
static CMOS and dynamic CMOS architectures in the same design.
1.6 TOOLS REQUIRED
“DSCH” design suite is a software suite produced “Micro Wind” for schematic
and layout design
Department of ECE, MRITS 2

CHAPTETR 2
LITERATURE SURVEY
2.1 INTRODUCTION
Electronic devices have been widely used in many different fields and the size of these
devices has been gradually reduced. An example of this is the mobile phone which is made
smaller to enhance user’s mobility and usage time. These are the contribution of integrated
circuit (IC) technology. With this technology, the modern devices have been reduced to
convenient sizes. Besides that mass production of IC has lowered the cost of production and
made most electronic devices affordable. Today, an IC is smaller than a coin and can hold
millions of transistors. Hence, further research in the design of IC is important to enhance the
production of a more efficient and viable IC.
2.2 LITERATURE SURVEY
Gordon. E. Moore [1] in 1965 predicted that the numbers of components on the chip will
double every 18 months. Initially he predicted only for 10 years but due to growth in the
integrated-circuit technology his prediction is valid till today. His work is widely recognized
as the Moore's law. The effect of Moore's law was studied carefully and researchers have come
to the conclusion that as the number of components in the chip increases the power dissipation
will also increase tremendously. It is also predicted that the amount of power dissipated will be
equal to the heat dissipated by the rocket nozzle. Hence power minimization has become an
important factor for today's VLSI engineers.
Lindauer [2] determined that the amount of energy dissipated to erase each bit of
information is at least kTln2 (where k is the Boltzmann constant and T is the room temperature)
during any computation the intermediate bits used to compute the final result are erased. This
erasure of bits is one of the main reasons for the power dissipation. ISSN (Print): 2320 – 3765
ISSN (Online): 2278 – 8875 International Journal of Advan
C. H. Bennett [3] in 1973 discovered that the power dissipation in any device can be made
zero or negligible if the computation is done using reversible model. He proved his theory with
the help of the truing machine which is a symbolic model for computation introduced by
Turing. Bennett also showed that the computations that are performed on irreversible or
classical machine can be performed with same efficiency on the reversible machine. Based on
the above concept the research on the reversibility was started in 1980's.
Shor [4] did a remarkable research work in creating an algorithm using reversibility for
factorizing large number with better efficiency when compared to the classical computing
theory. After this the work on reversible computing was started by more people in different
fields such as nanotechnology, quantum computers and CMOS VLSI.
Department Of ECE, MRITS 3

Edward Fredkin and Tommaso Toffoli [5, 6] based on the concept of reversibility they
introduced new reversible gates known as Fredkin and Toffoli reversible gates. These gates
have zero power dissipation and are used as universal gates in the reversible circuits. These
gates have three outputs and three inputs; hence they are known as 3*3 reversible gates.
Peres [7] introduced a new gate known as peres gate. Peres gate is also a 3*3 gate but it
is not auniversal gate like the Fredkin and Toffoli gate. Even though this gate is not universal
gate itis widely used in many applications because it has less quantum cost when compared to
the universal gate. The quantum cost of the Peres gate is 4.
H Thalpliyal and N Ranganathan [8] invented a reversible gate known as TR gate. The
main objective of introducing this reversible TR gate was to reduce the garbage output in a
reversible circuit
2.3 CONCLUSION
In this chapter introduction, research papers has been discussed

CHAPTER 3
COUNTERS
3.1 INTRODUCTION
In this chapter, the introduction of Counters, its various types, how it is works.
3.2 INTRODUCTION OF COUNTERS

A special type of sequential circuit used to count the pulse is known as a counter, or a
collection of flip flops where the clock signal is applied is known as counter.The counter is
one of the widest applications of the flip flop. Based on the clock pulse, the output of the
counter contains a predefined state. The number of the pulse can be counted using the output
of the counter.
3.3 TYPES OF COUNTERS
3.3.1 Asynchronous or ripple counters.
3.3.2 Synchronous counters
3.3.1 ASYCHRONOUS COUNTER:

Transition one from state to another state happens independent of clock. It works with
preset and clear.
In asynchronous counter, only the first flip-flop is externally clocked using clock pulse
while the clock input for the successive flip-flops will be the output from a previous flip-
flop.
This means that only a single clock pulse is not driving all the flip-flops in the
arrangement of the counter. The circuit diagram of Asynchronous counter shown in below Fig
3.1
Fig. 3.1: Block diagram of Asynchronous counter

3.4 Timing diagram of Asynchronous counter
3.3.2 SYCHRONOUS COUNTER

Transition from one state to another state happens in synchronism with clock. In
synchronous counter, the clock input across all the flip-flops use the same source and
create the same clock signal at the same time. So, a counter which is using the same clock
signal from the same source at the same time is called Synchronous counter.The circuit
diagram of Synchronous counter shown in Fig 3.3.
Fig 3.3 Block diagram of Synchronous counter

Fig 3.4 Timing diagram of Synchronous couter
3.4 BASED COUNTING

3.4.1 Up Counter
3.4.2 Down Counter
3.4.3 Up/ Down
3.4.1 UP COUNTER:
Counts in increasing order.
3.4.2 DOWN COUNTER
Counts in decreasing order
3.4.3 UP/DOWN
Counts in both directions, increasing order

CHAPTER 4
FLIP-FLOPS
4.1 INRODUCTION
In this chapter, introduction of flip-flops, various types flip flop, comparison between
flip- flops.
4.2 FLIP-FLOP
A flip-flop is a sequential digital electronic circuit having two stable states that can be
used to store one bit of binary data. Flip-flops are the fundamental building blocks of all
memory devices.
4.3 TYPES OF FLIP-FLOPS
4.3.1 SR Flip-Flop
4.3.2 JK Flip-Flop
4.3.3 D Flip-Flop
4.3.4 T Flip-Flop
4.3.1 SR Flip-Flop
This is the most common flip-flop among all. This simple flip-flop circuit has a set input (S)
and a reset input (R). In this system, when you Set “S” as active, the output “Q” would be
high, and “Q” would be low. Once the outputs are established, the wiring of the circuit is
maintained until “S” or “R” go high, or power is turned off.The cicuit diagram of SR Flip-
Flop shown in below Fig 4.1
Fig 4.1 Circuit diagram of SR Flip-Flop

Fig 4.1.1 Truth Table of SR Flip-Flop
The JK Flip-Flop is used to remove the drawback of the S-R flip flop, i.e., undefined
states. The JK flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is
improved in order to construct the J-K flip flop. When S and R input is set to true, the SR flip
flop gives an inaccurate result. But in the case of JK flip flop, it gives the correct output. The
circuit diagram of JK Flip-Flop shown Fig 4.4
Fig 4.2 Circuit diagram of JK Flip-Flop

In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge is
taken by the output Y. If both of its input is low, then no change occurs, and if high at the
clock edge, then from one state to the other, the output will be toggled. The J-K Flip Flop is a
Set or Reset Flip flop in the digital system.Truth table of j-k flip-flop shown in Fig 4.3.1
Table 4.2.2 J-K flip-flop truth table

4.3.3 D Flip-Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in shift-
registers, counters, and input synchronization.
4.3 Fig Circuit diagram of D Flip-Flop

The D flip-flop tracks the input, making transitions with match those of the input D.
The D stands for "data"; this flip-flop stores the value that is on the data line. It can be thought
of as a basic memory cell. A D flip-flop can be made from set/reset by tying the set to the reset
through an inverter. The result may be clocked.
Table: 4.3.3 D Flip- Flop truth table
4.4.3 T FLIP-FLOP
The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find the
complement of its state.The circuitdiagram of flip-flop shown in Fig 4.6
Fig 4.4 Circuit diagram of T Flip-Flop

The T flip-flop is also called toggle flip-flop. It is a change of the JK flip-flop. The T flip
flop is received by relating both inputs of a JK flip-flop. The T flip-flop is received by
relating the inputs ‘J’ and ‘K’. When T = 0, both AND gates are disabled. Therefore, there is
no changein the output. When T= 1, the output toggles.
Table 4.4.4 Truth Table of T Flip-Flop

CHAPTER 5
SYCHRONOUS 4 BIT UP COUNTER USING LOGIC GATES
In this chapter basic in this chapter, basic logic gates description and designing
Synchronous up counter using gates are discussed
5.1 Basic logic gates

Below table gives the corresponding symbol to each basic gate as it appears in the logic
editor window as well as the logic description. In this description, the symbol & refers to the
logical AND, | to Or, ~to INVERT, and ^ to XOR.
Table 5.1: Basic gates logic symbol with Boolean expression

5.3 4-Bit Up Counter using Logic gates

The circuit diagram of logic gate level 4-bit up counter shown in Fig 5.1
Fig 5.1 Synchronous 4-bit up counter

The proposed synchronous 4-bit up counter has 3 AND gates, 4 XOR gates and 4 master-slave
D flip-flops. Same clock pulse is given to each flip-flop. So with every clock pulse the counter
counts one step up. It is an up counter and starts from 0000. Then with clock pulse counts like
0001, 0010, 0011, 0100 up to 1111. Then it starts from 0000 again. Q0 is the LSB and Q3 is
the MSB. The master-slave D flip-flop actually works at the falling edge of the clock. But
because it is a master slave configuration [8], it actually stores the input at rising edge and it is
given to the output at the falling edge of the clock. So, change in counter output is observed in
the falling edge of the clock.
 There are 2 additional inputs in the counter, count enable (CE) and clear (clr). 1. Count
Enable (CE) input: If CE=0, then counter stops counting. IF CE=1, each clock pulse
results in a counting action.
 Clear (clr) input: If clr=1, then the counter output clears to 0000. If clr=0, each clock
pulse results in a counting action.

The control logic of the counter is as follows: The XOR gate complements each bit. The
AND chain causes complement of a bit if all the bits toward LSB from it equal 1. The Count
Enable forces all outputs of AND chain to 0 to “hold” the state
The Fig 5.2 represents schematic diagram of synchronous 4-bit up counter schematic
Fig 5.2 Conventional Synchronous 4-bit up counter schematic
Fig 5.3 Conventional Synchronous 4-bit up counter layout

Fig.5.4: Conventional Synchronous 4-bit up counter timing diagram

CHAPTER 6
SYCHRONOUS 4 BIT UP COUNTER USING CMOS
6.1 Introduction
In this chapter, CMOS description and designing demultiplexer using CMOS transistors
are discussed.
6.2 MOS as a switch

Complementary metal–oxide–semiconductor, abbreviated as CMOS is a technology for
constructing integrated circuits. CMOS technology is used in, Microcontroller, static RAM, and
other digital logic circuits. CMOS technology is also used for several analog circuits such as
image sensor (CMOS sensor), data converter, and highly integrated transceivers for many types
of communication. words "complementary-symmetry" refer to the typical design style with
CMOS using complementary and symmetrical pairs of p-type and n-type metal oxid
semiconductor field effect transistors (MOSFETs) for logic functions.
The MOS transistor is basically a switch. When used in logic cell design, it can be ON
or OFF. During ON state, current can flow between drain and source. During OFF state, no
current flow between drain and source. The MOS is turned ON or OFF depending on the gate
voltage. In CMOS technology, both n-channel (or nMOS) and pchannel MOS (or pMOS)
devices exist.
pMOS nMOS
Fig. 6.1: MOS transistors symbol

The n-channel MOS device requires a logic value 1 (or a supply VDD) to be on. In
contrary, the p-channel MOS device requires a logic value 0 to be on. When the MSO device
is on, the link between the source and drain is equivalent to a resistance. The order of range of
this ‘ON’ resistance is 100Ω-5KΩ. The ‘OFF’ resistance is considered infinite at first order,
as its value is several MΩ. The MOS size (width and length of the channel situated at the
intersection of the polysilicon gate and the diffusion) has a strong influence on the value of
the current
Within CMOS cells, metal and polysilicon are used as interconnects for signals.
Metal is a much better conductor than polysilicon. Polysilicon is rarely used for long
interconnects, except if a huge resistance value is expected. Polysilicon bridge links the gate
of the n-channel MOS with the gate of the p-channel MOS device. The polysilicon serves as
the gate control andthe bridge between MOS gates.
The main Advantages of CMOS over NMOS and BIPOLAR technology is the much
smaller power dissipation. Unlike NMOS or BIPOLAR circuits, a Complementary MOS
circuit has almost no static power dissipation. Power is only dissipated in case the circuit
actually switches
6.3 CMOS Inverter

The MOS configuration of inverter greatly reduces power consumption since one of
the transistors is always off in both logic states. Processing speed can also be improved due to
the relatively low resistance compared to the NMOS-only or PMOS-only type devices. In
MOS inverter circuits, both the input variable and the output variable are represented by node
voltages, referenced to the ground potential. Using positive logic convention, the logic value
of "1" can be represented by a high voltage of VDD, and the logic value of "0" can be
represented by a low voltage of 0.Here the p-channel MOS and the n-channel MOS transistors
function as switches. The fan out corresponds to the number of gates connected to the inverter
output. Physically, a large fan out means a large number of connections, that is a large load
capacitance. If we simulate an inverter loaded with one single output, the switching delay is
small. The circuit topology is complementary push-pull in the sense that for high input, the
nMOS transistor drives (pulls down) the output node while the pMOS transistor acts as the
load, and for low input the pMOS transistor drives (pulls up) the output node while the nMOS
transistor acts as the load. In other words, when the input signal is logic 0, the nMOS

switched off while PMOS passes VDD through the output. When the input signal is logic 1,
the pMOS is switched off while the nMOS passes VSS to the output. Consequently, both
devices contribute equally to the circuit operation characteristics.
Fig 6.2 CMOS Inverter

In CMOS design, the NAND gate consists of two nMOS in series connected to
two pMOS in parallel. T he nMOS in series tie the output to the ground for one single
combination A=1, B=1. For the three other combinations, the nMOS path is cut, but a least X-
OR gate using CMOS .In all three methods the basic building blocks are NMOS and PMOS.
The difference is in their arrangement and number. The circuit diagram and layout design of
respectively. One pMOS ties the output to the supply VDD. Notice that both nMOS and
pMOS devices are used in their best regime: the nMOS devices pass “0”, the pMOS pass “1”.
In CMOS design, the NAND gate consists of two nMOS in series connected to two
pMOS in parallel. The schematic diagram of the NAND cell is reported below. The nMOS in
series tie the output to the ground for one single combination A=1, B=1. For the three other
combinations, the nMOS path is cut, but a least one pMOS ties the output to the supply VDD.
Notice that both nMOS and pMOS devices are used in their best regime: the nMOS devices
pass “0”, the pMOS pass “1”.

6.3 CMOS XOR
X-OR gate using CMOS .In all three methods the basic building blocks are NMOS and
PMOS. The difference is in their arrangement and number. The circuit diagram and layout
design of XOR using CMOS technique is shown in Fig. 6.3 & 6.4
Fig 6.3 XOR using transistors schematic
Fig 6.4 XOR layout schematic

The timing diagram of Sychronous 4-bit up counter using shown in Fig 6.5
Fig. 6.6 XOR timing diagram
6.4 D Flip-Flop
D flip flop, also called Data flip flop or Delay flip flop is constructed from a gated SR-flip
flop with an inverter added between S & R inputs to allow for a single D (Data) input. This
single data input is used to replace “SET” signal and the inverter is used to generate the
complimentary “RESET” input there by making a level sensitive D type flip flop. The block
diagram of D flip flop using NAND and NOR gate is shown in Fig 6.6
Fig 6.6 D Flip-Flop Using NAND Gates

D flip flop has been designed by using all three mentioned techniques. D flip flop’s
module was formed and simulated so that it can be used for designing counter circuit. The
circuit design of CMOS D flip flop is shown in Fig.6.7
Fig 6.6 D Flip-Flop using transistors schematic
6.5 Synchronous 4-bit up counter using CMOS
The counter module consist of four XOR gates, three AND gates and four D FFs. Output
of each XOR gate act as an input to the cascaded D Flip-Flop. Output of the module cam be
observed by hexadecimal display. To reduce the circuit complexity XOR gate and D FF
module has been used which is designed by the CMOS technique only. The circuit diagram of
4-bit synchronous counter by CMOS technique is shown in Fig. 6.7 & 6.8

Fig 6.7 Synchronous 4-bit up counter using transistors schematic

Fig 6.8 Synchronous 4-bit up counter using transistors layout

Fig 6.9 Synchronous 4-bit up counter using transistors timing diagram

CHAPTER 7
RESULTS & COMPARISON BETWEEN
DIFFERENT LOGICS
The main area of analysis in this paper is power consumption by the de-multiplexer
circuit. In any digital CMOS circuit, the main reasons of power dissipation are gate leakage
currents, short circuit currents while both transistors are partially on and dynamic power
dissipation due to charging and discharging of the load capacitance.
From the analysis of both the designs of the de-multiplexer circuits it is evident that the
new designed Synchronous 4-bit up counter with transmission gates consumes less power than
the conventional Synchronous 4-bit up counter
Properties Power Area Time delay
Synchronous 4bit 33.2 µw 649µm2 0.1704ns
counter using Logic
Gate
Synchronous4bit 10.8 µw 156µm2 0.05ns
counter using Logic
Gate
Chart Title
700
600
500
400
Sychronous 4 bit up counter
300 using logic gate
Sychronous 4 bit up counter

200 using CMOS
100
0
1 2 3 4

CHAPTER 8
APPLICATIONS OF SYCHRONOUS 4 BIT UP COUNTER
 Frequency counter
 Digital clock
 Time measurement
 A to D converter
 Frequency divider circuits
 Digital triangular wave generator.

CHAPTER 9
CONCLUSION AND FUTURE SCOPE
9.1 Conclusion
The conclusion we obtained is that proposed design of Synchronous 4 bit up counter
circuit design using different logic styles that shows improved performance than the existing
Synchronous 4 bit up circuit. The power dissipation of the circuit using transmission gates is
2.190µW which is lower than that consumed by conventional de-multiplexer designed with
gates.. The new circuit provides an innovative method of designing Synchronous 4 bit up
circuit using transmission gates which consume lesser power than conventional Synchronous 4
bit up.
9.2 Future scope
The future scope is that can have number of input and output lines. The designs of basic
Synchronous 4 bit up counter can be designed used 65nm, 45nm technologies which can
further reduce the power consumption and also better performance.

REFERENCES
[1] E. Moore in 1965 predicted that the numbers of components on the chip will double every
18 months
[2] Lindauer determined that the amount of energy dissipated to erase each bit of information
is at least kTln2
[3] C. H. Bennett in 1973 discovered that the power dissipation in any device can be made
zero or negligible if the computation is done using reversible model
[4] Shor did a remarkable research work in creating an algorithm using reversibility for
factorizing large number with better efficiency when compared to the classical
computing theory.
[5, 6] Edward Fredkin and Tommaso Toffoli based on the concept of reversibility they
introduced new reversible gates known as Fredkin and Toffoli reversible gates
[7] Peres introduced a new gate known as peres gate. Peres gate is also a 3*3 gate but it is
not a universal gate like the Fredkin and Toffoli gate
[8] H Thalpliyal and N Ranganathan invented a reversible gate known as TR gate.

APPENDIX
SOFTWARE DSCH AND MICROWIND
DSCH
The DSCH program is a logic editor and simulator. DSCH is used to validate the
architecture of the logic circuit before the microelectronics design is started. DSCH
provides a user-friendly environment for hierarchical logic design, and fast
simulation with delay analysis, which allows the design and validation of complex
logicstructures.DSCH also features the symbols, models and assembly support for
8051 and PIC16F84 controllers. Designers can create logic circuits for interfacing
with these controllers and verify software programs using DSCH.
MICROWIND
The MICROWIND software allows the designer to simulate and design an integrated
circuit at physical description level. Born in Toulouse (France), Microwind is an
innovative CMOS design tool for educational market.Microwind is developed as
comprehensive package on windows platform to enable students to learn smart design
methods and techniques with more practice. With inbuilt layout editing tools, mix-
signal simulator, MOS characteristic viewer and more, it allows students to learn
complete design process with ease.Microwind unifies schematic entry, pattern based
simulator, SPICE extraction of schematic, Verilog extractor, layout compilation, on
layout mix-signal circuit simulation, cross sectional & 3D viewer, netlist extraction,
BSIM4 tutorial on MOS devices and sign-off correlation to deliver unmatched design
performance and productivity.With its approach for CMOS design educati on,
Microwind has gained lot followers worldwide. Universities across the globe are
using Microwind for budding engineers to teach CMOS concepts with ease. Paving
their path for more skilled softwares to be used at later stage of their course work.

Fig : DSCH
Fig : MICROWIND

Highlights
 User-friendly environment for rapid design of logic circuits.

 Supports hierarchical logic design.
 Added a tool on fault analysis at the gate level of digital. Faults: Stuck-at- 1,stuck-at-
0.The technique allows injection of single stuck-at fault at the nodes of the circuit.
 Improved interface between DSCH and Winspice.
 Handles both conventional pattern-based logic simulation and intuitive on
screen mouse-driven simulation.
 Built-in extractor which generates a SPICE netlist from the schematic diagram
(Compatible with PSPICE and WinSpice).
 Generates a VERILOG description of the schematic for layout conversion.
 Delay re-computation in DSCH with change of technology.
 Display of power results in DSCH are improved.
 Immediate access to symbol properties (Delay, fanout).
 Model and assembly support for 8051 and PIC 16F84 microcontrollers.
 Sub-micron, deep-submicron, nanoscale technology support.
 Supported by huge symbol library.
A specific command in DSCH creates the Verilog description of the logic

design, including the list of primitives and some stimulation information. This verilog
text file is understood by Microwind to construct the corresponding layout, with
respect to the desired design rules. The supply properties and most stimulation
information are added to the layout automatically, according to the logic simulation.
Finally, the analog simulation permits to validate the initial design and verify its
switching and power consumption performances.

Fig : Design flow from logic design to layout implementation
Lambda Units
The Microwind software works is based on a lambda grid, not on a micro grid.
Consequently, the same layout may be simulated in any CMOS technology.
The value of lambda is half the minimum polysilicon gate length. Table Axxx gives the
correspondence between lambda and micron for all CMOS technologies supported by
Microwind.The software can handle various technologies. The process parameters are stored
in files with the appendix '.RUL'. The default technology corresponds to a generic 6-metal

0.12 μm CMOS process. The default file is CMOS012.RUL. In order to select a new foundry,
click on File -> Select Foundry and choose the appropriate technology in the list.
Table : Correspondence between technology and the value of lambda in µm
Technology file available Minimum gate length Value of lambda

in the CD Rom
Cmos12.rul 1.2µm 0.6µm
This size in nm is the gate length of the transistor for clarity,the gate length is also an
approximate measure of transistor speed and of how densely you can pack transistors
together in a hand-crafted layout.

Procedure
 Open the DSCH software from the folder where you have saved in the computer.
 Go to file menu select New option.

 Again go to the file menu ,click on Save As option.Specify the project path and give a
file name and click on save.
 Now create /connect the circuit by dragging the necessary components from symbol
library or palatte.
 Modify the connections using the commands from edit menu.


 Properties of a symbol can change by double clicking on the symbol.Diaglog box

appears, make the changes and click on ‘OK’.
 To simulate/run the connected schematic,click on start simulation option from Simulate

menu.
 The following window appears, adjust the speed of simulation.

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A MINI PROJECT REPORT ON

DESIGN AND IMPLEMENTATION OF SYCHRONOUS 4-

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING

Head of the Department External Examiner

Mr. K.Y. SRINIVAS

We express a whole-hearted gratitude to Dr. K. RAVINDRA, Principal and

Design of synchronous 4-bit up counter is proposed using master-slave negative pulse-triggered D

TOPIC PAGE NO.

CHAPTER 2: LITERATURE SURVEY 3-4

Fig no 3.3 Synchronous counter 6

Department of ECE, MRITS 1

1.2 PROBLEM STATEMENT

The main objective of the project is to design and implementation of synchronous

1.5 METHODOLOGY ADOPTED

Department of ECE, MRITS 2

Department Of ECE, MRITS 3

In this chapter introduction, research papers has been discussed

Department Of ECE, MRITS 4

3.2 INTRODUCTION OF COUNTERS

3.3 TYPES OF COUNTERS

3.3.1 Asynchronous or ripple counters.

3.3.2 Synchronous counters

3.3.1 ASYCHRONOUS COUNTER:

Fig. 3.1: Block diagram of Asynchronous counter

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3.4 Timing diagram of Asynchronous counter

3.3.2 SYCHRONOUS COUNTER

Fig 3.3 Block diagram of Synchronous counter

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Fig 3.4 Timing diagram of Synchronous couter

3.4 BASED COUNTING

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Fig 4.1 Circuit diagram of SR Flip-Flop

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Fig 4.1.1 Truth Table of SR Flip-Flop

Fig 4.2 Circuit diagram of JK Flip-Flop

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4.3 Fig Circuit diagram of D Flip-Flop

Fig 4.4 Circuit diagram of T Flip-Flop

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Table 4.4.4 Truth Table of T Flip-Flop

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5.1 Basic logic gates

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5.3 4-Bit Up Counter using Logic gates

Fig 5.1 Synchronous 4-bit up counter

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Fig 5.2 Conventional Synchronous 4-bit up counter schematic

Fig 5.3 Conventional Synchronous 4-bit up counter layout

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Fig.5.4: Conventional Synchronous 4-bit up counter timing diagram

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6.2 MOS as a switch

Fig. 6.1: MOS transistors symbol

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6.3 CMOS Inverter

Department Of ECE, MRITS 17