VLSI Technology

Lecture 1

Semiconductor Overview and Moore’s Law

Dr. Brajendra Singh Sengar (PhD, IIT Indore)

Assistant Professor
Department of Electronics and Communication Engineering
National Institute of Technology Srinagar
Email id: [email protected]
 Syllabus
CONTENTS
Clean room Technology and safety requirements, Wafer cleaning processes and wet chemical
etching techniques, Solid State diffusion modeling and technology; Ion Implantation modeling,
technology and damage annealing; characterization of Impurity profiles, Oxidation: Kinetics of
Silicon dioxide growth both for thick, thin and ultra-thin films. Oxidation technologies in VLSI
and ULSI; Characterization of oxide films; High k and low k dielectrics for ULSI,
Photolithography, E-beam lithography and newer lithography techniques for mask generation,
CVD techniques for deposition of polysilicon, silicon dioxide, silicon nitride and metal films;
Epitaxial growth of silicon; modeling and technology, Metal film deposition : Evaporation and
sputtering techniques. Failure mechanisms in metal interconnect; Multi-level metallization
Syllabus
schemes, Plasma and Rapid Thermal Processing: PECVD, Plasma etching and RIE techniques;
RTP techniques for annealing, growth and deposition of various films for use in ULSI. Process
integration for NMOS, CMOS, Bipolar and BICMOS circuits
References:
1. S. K. Gandhi, VLSI Fabrication Principles: Silicon and Gallium Arsenide, Second Edition, Wiley.
2. G. S. May and S. M. Sze, Fundamentals of Semiconductor Fabrication, Wiley.
3 J. D. Plummer, M. D. Deal and P. B. Griffin, Silicon VLSI Technology: Fundamentals, Practice and Modeling, Pearson/PH.
4. P. Van Zant, Microchip Fabrication: A Practical Guide to Semiconductor Processing, Fifth Edition.
5. C. Y. Chang and S. M. Sze, ULSI Technology, McGraw-Hill.
6. Fabrication Engineering at the Micro- and Nanoscale, 4th edition, Campbell
2
7. S. M. Sze, VLSI Technology, McGraw-Hill.
 History of Electronic
Devices Low Power
2000 ULSI High speed
High integration
VLSI CMOS
Low Power
High speed
70 LSI LSI 10 years High integration
Si-MOSFET Silicon Technology
60 IC High Integration
IC 30 years
50 bipolar 1st Transistor Solid-State Circuits

High reliability
30 MOSFET Transistor
MISFET Concept Low Power
20 20 years
10 Triode 1st Electronic circuits
Vacuum tube
Diode
1900
Iwai Hiroshi
1906: Vacuum Tube : Triode

Lee De Forest

Iwai Hiroshi
 J. E. LILIENFELD
DEVICESFORCONTROLLEDELECTRICCURRENT
Filed March 28, 1928

J.E.LILIENFELD

Iwai Hiroshi
 J. Bardeen, W. Bratten,
1947: 1st transistor
W. Shockley

Iwai Hiroshi
First Bipolar Ge
Transistor
1958: 1st Integrated Circuit Jack S.
Kilby

Iwai Hiroshi
 3

1958 - Integrated circuit invented

September 12th 1958 Jack Kilby at
Texas instrument had built a
simple oscillator IC with five integrated
components (resistors, capacitors,
distributed capacitors and transistors)
In 2000 the importance of the IC was
recognized when Kilby shared the Nobel
prize in physics with two others. Kilby
was sited by the Nobel committee "for his
part in the invention of the integrated
circuit

a simple oscillator IC

University of southern Alabama

1959: 1st Planar Integrated
Circuit
Robert N. Noyce

Iwai Hiroshi
 Electronics Evolution
Monolithic Integration: On one Single substrate, components are made and
connected as well.

Discrete vs Monolithic Circuit

A discrete circuit is constructed of components which are manufactured separately. Later, these components are
connected together by using conducted wires on a circuit board or a PCB. Each component have to be that size so
that we can handle.

11
 1960: First MOSFET
by D. Kahng and M. Atalla
Top View

Al
SiO2
Si
Si/SiO2 Interface is
extraordinarily good
 Electronics Evolution

Vacuum Triode

Integration

13
 Electronics Evolution
Vacuum tubes were also revolutionary but integration was limited.

ENIAC: 1946
30×50 feet room

1 ENIAC = 17468 vacuum tubes + 7000 resistors + 10000 capacitors + 1500

relays + 6000 manual switches + 5 million soldered joints. Consumed 160
KW power.
Around 19000 vacuum tubes replaced in 1952 (50 tubes a day)
14
 Electronics Evolution

Transistor: 1948

530 germanium transistors and 2300 diodes.

25 Kg

90 Watts of Power
15
Electronics Evolution

16
 Electronics Evolution

With the Invention of IC, The

innovation begins……….

Moore’s Law

17
1970,71: 1st generation of LSIs

DRAM Intel 1103 MPU Intel 4004

In 2012
Most Recent SD Card

128GB (Byte)
=128G X 8bit
=1T(Tera)bit

1T =1012 = １ Trillion

World Population ： 7 Billion

Brain Cell ： 10 ～ 100 Billion
Stars in Galaxy ： 100 Billion
Iwai Hiroshi
 128 GB =1Tbit
2.4cm X 3.2cm X 0.21cm
Volume ： 1. 6cm³ Weight ： 2g

Voltage ： 2.7 3.6V

Old VacuumTube ：
5cmX 5cmX 10cm, 100g, 50W

What are volume, weight, power consumption for

1Tbit

Iwai Hiroshi
 Old VacuumTube ： 1Tbit =10,000 X 10,000 X 10,000 bit
5cmX 5cmX 10cm
Volume =(5cmX 10,000) X (5cmX 10,000)
X (10cmX 10,000)
=0.5kmX 0.5kmX 1km
500 m

m
1,000
1Tbit

Iwai
Hiroshi
Old Vacuum Tube ： 1Tbit =1012bit
50W
Power = 0.05kWX1012=50TW
Nuclear Power Generator
1MkW=1BW We need 50,000Nuclear Power Plant for just one
128 GB memory

In Japan we have only 54Nuclear

Power Generator

Last summer Tokyo Electric Power

Company (TEPCO) can supply only
55BW.

We need 1000 TEPCO just one 128

GB memory
Imagine howmany memories are used in
the world! Iwai
Hiros
 So progress of integrated
circuits is extremely
important for power saving.
Today, silicon device is the indispensable and
most important devices for our human society.

Everything has to be controlled by Si device.

Si realized extremely high-frequency (speed)

operation with extremely low cost, low power,
small size, high reliability.
Today’s IT -- such as internet, i-mode, cellular
phone, GPS navigation, game machine,
Entertainment robot – could not be realized
Without Si integrated circuit development.
INTEL
INTEL
1900 “Electronics”started.
Device: Vacuumtube
Device feature size: Several cm
Major Appl.: Amplifier (Radio, TV, Wireless etc.)

Technology Revolution

1970 “MicroElectronics”started.
Device: Si MOS integrated circuits
Device feature size: 10 m
Major Appl.: Digital (Computer, PC, etc.)

Technology Revolution
 Technology Scaling
GATE
SOURCE Xj
GATE DRAIN

D Tox
SOURCE DRAIN
BODY
BODY
Leff

Dimensions scale down by Doubles transistor density

30%
Oxide thickness scales down Faster transistor, higher
performance
Vdd &Vt scaling Lower active power

Technology has scaled well, will it in the future?

Scaling Evolution

Iwai Hiroshi
 MICRO to NANO Journey
Milestones

J.L.Hoyt
MIT
 Scaling
: of Downsizing
Importance

Downsizing:

Power reduction
Capacitance reduction
Speed increase

High integration Function increase

Parallel processing
Speed increase

Iwai Hiroshi
Demand for future VLSI:
Much higher performance
Much lower power consumption

Thus, downsizing of Si devices is

the most important and critical issue.

Iwai Hiroshi
 Prediction of Scaling limit
Vacuum tube era ： even m size could not be imagined
Since Si IC started
Period Expected Cause
limit(size)
Late 1970’s 1m: SCE
Early 1980’s 0.5m: S/D resistance
Early 1980’s 0.25m: Direct-tunneling of gate SiO2
Late 1980’s 0.1m: ‘0.1m brick wall’(various)
Today 50nm: ‘Red brick wall’ (various)
Today 10nm: Fundamental?
Transistor Integration Capacity
1000

100 1 Billion
Transistors (Million)

10

0.1

0.01

0.001
10 5 2 1 0.5 0.25 0.13 0.07
Technology ()

On track for 1B transistor integration capacity INTEL

J.L.Hoyt
MIT
 Limits of Moore’s
Law?

• Growth expected until 30 nm gate

length ( 180 nm)
– size halved every 18 mos. - reached in
– 2001 + 1.5 log2((180/30)2) = 2009
– what then?
• Paradigm shift needed in fabrication
process
 Technological Background of the Moore’s Law

• To accommodate this change, the size of the silicon

wafers on which the integrated circuits are fabricated
have also increased by a very significant factor – from
the 2 and 3 in diameter wafers to the 8 in (200 mm) and
12 in (300 mm) diameter wafers
• The latest catch phrase in semiconductor technology (as
well as in other material science) is nanotechnology –
usually referring to GaAs devices based on quantum
mechanical phenomena
• These devices have feature size (such as film thickness,
line width etc) measured in nanometres or 10-9 metres
 Recurring Costs
Variable Cost = {Cost of (Die + Die test + packaging)}/ Final Test Yield

Cost of Die = {Cost of wafer}/[ Dies per wafer x Die Yield]

Die per wafer = ∏ x [wafer diameter/2]2 - ∏ x wafer diameter

Die area 1.414 x Die area

Die yield= [1+(defects per unit area x Die area)/ − 

❑

Example
wafer size of 12 inches, die size of 2.5 cm2, 1 defects/cm2,
 = 3 (measure of manufacturing process complexity)
252 dies/wafer (remember, wafers round & dies square)
die yield of 16%
❑ 252 x 16% = only 40 dies/wafer die yield !

Die cost is strong function of die area

● proportional to the third or fourth power of the die area
PROCESS STEPS
Is Transistor a Good
Switch
I≠0
? I=0
On

I=∞ I = 1ma/u

I=0 I≠0

Off

I=0 I≠0
Sub-threshold Leakage
 What is a Semiconductor?

•A material whose conductivity can be varied by many orders of

magnitude
•Temperature
•Light
•Doping
Can be applied locally
•Electric Field Syllabus

•Can be made into a switch

•Current-controlled switch (e.g., bipolar transistor)
•Voltage-controlled switch (e.g., MOSFET)

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 Semiconductor Processing

•Creating small, interconnected 3D structures of insulators,

semiconductors, and conductors (called patterning)

•Allows manipulation of local electric field and current

Syllabus
•Selectively doping semiconductor regions to create p-n junctions and
other electrical components

•Allows manipulation of local charge carrier concentration

46
 Patterning

•Subtractive patterning
–Deposition
–Lithography
–Etch
•Additive patterning Syllabus
–Lift-off
–Damascene
From IBM website

47
 Patterning Example
•Patterning Sequence (example)
–Deposit polysilicon (for example) on wafer
–Deposit photoresist layer on top of polysilicon
–Expose and develop photoresist to create pattern
–Etch pattern into polysilicon using resist as
mask
–Strip away the resist Syllabus Top-down

–Repeat 20 – 60 times to make a chip

photomask

photoresist
polysilicon
Wafer
Cross-section
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 Patterning Techniques

Patterning Deposition Techniques

–Physical Vapor Depostion (PVD)
•Sputtering
•Evaporation
–Chemical Vapor Deposition (CVD)
–Oxidation
•Etch techniques Syllabus
–Dry (plasma, reactive ion etching)
–Wet
•Patterning is used to make wires, insulators, and
regions of selective doping

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 Localized Doping
• Patterning

• Ion Implantation

• Annealing (diffusion)
B Ion accelerated with hundreds of
KeV

SiO2 SiO2

N Type

Si

50
We are making…

• Transistors
• Chips
• Wafers

(this is mass production!)

Moore’s Law
 Moore’s Law
1965: Moore’s Observation
100000
65000 transistor
10000
Components per chip

1000

100

10
64 transistor
1
1959 1961 1963 1965 1967 1969 1971 1973 1975
Year

G. E. Moore, “Cramming More Components onto Integrated

Circuits,” Electronics Vol. 38, No. 8 (Apr. 19, 1965) pp. 114-117.
53
Moore’s Law
How Small?
 Dennard’s MOSFET Scaling Rules

Device/Circuit Parameter Scaling Factor*

Device dimension/thickness 1/

Doping Concentration 
Voltage 1/
Current 1/
Robert Dennard
Capacitance 1/
* Constant electric field scaling
Delay time 1/
Transistor power 1/2
Power density 1

There are no trade-offs. Everything gets better when you shrink a transistor!
 The Golden Age 1975 - 2000

•Dennard Scaling: as transistor shrinks it gets

–Faster

–Lower power (constant power density)

–Smaller/lighter

•Moore’s Law

–Keep the cost/area about constant while shrinking

–More transistors/chip & lower cost/transistor

 Two Versions of Moore’s Law
•Moore’s Law 1.0: scaling up

–Doubling the number of transistors every 1–2 years

–More powerful chip for the same price

•Moore’s Law 2.0: scaling down

–Shrinking transistor area lowers the cost of a transistor by about 30%/year

•Same chip for lower price

•Both versions enable many new applications

•Results in a large increase in chip volumes

 Problems with Dennard Scaling

•Voltage has always shrunk more slowly (~1/ λ)

•Voltage essentially stopped shrinking 10 years ago

–Thermal noise (kT/q = 25 mV at room temperature)

–Subthreshhold leakage current

•Power is at a wall, dominates shrink issues

•Clock speed is stuck – we can’t make our transistors

faster

•Today, shrinking a transistor makes it worse

 Dennard + Moore Today

•The only benefits of shrinking a transistor today are more

functions/chip and/or lower cost/function

•Moore’s Law cost: despite rising fab, equipment and material

costs, and increasing process complexity, the cost/cm2 of
finished silicon has remained about constant (or risen only
slowly) over the years.

– Result: lower cost per transistor each year

 Moore’s Law 3.0
•Moore’s Law 1.0: Scaling up

–Only applies to Flash and supercomputers today

•Moore’s Law 2.0: Scaling down

–Higher costs are putting this version in danger

•Moore’s Law 3.0: Scaling Out (Innovation through Integration)

–New materials (e.g., HkMG)

–3D integration

–Silicon photonics

–Memory on microprocessor

–Smart sensors and actuators, MEMS

–More… (More than Moore)

 Conclusions

•All three versions of Moore’s Law have always been present

–A shift in emphasis over time

•The Golden Days of Moore + Dennard are over

•Moore’s Law is primarily an economic law

–It is getting harder to keep costs down, putting the future of Moore’s
Law in danger

•Moore’s Law 3.0 is the most exciting version yet

Thanks

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