1.code Generation PDF

Module 11
Code Generation
Contents
●
Issues in the design of code generator
●Code generaton algorithm.
●Basic block and fow graph

Issues in the design of a code
generator
The following issues arise during the code generation
phase:
• Input to code generator
• Target program
• Instruction selection
• Register allocation
• Choice of Evaluation order
Issue of Code generator
Input to the code generator :-
Input consists of intermediate representaton of the source program produced by front
end, together with informaton in the symbol table to determine run-tme addresses of
the data objects denoted by the names in the intermediate representaton.
Intermediate representaton can be:

➢ Linear representaton such as postix notaton
➢ Three address representaton such as quadruples
➢ Virtual machine representaton such as stack machine code
➢ Graphical representatons such as syntax trees and DAGs.
Input to the code generator
Prior to code generaton:-

● The front end must be scanned, parsed and translated into intermediate
representaton
● Type checking has to be done. Therefore, input to code generaton is assumed to be
error-free
● The source program must be translated into a reasonably detailed intermediate
representaton
● Example:
● a: = b * - c + b * - c
Postix Notaton:-
a b c uminus * b c uminus * + assign (Correct Input)
a b c * uminus b c * uminus + assign (Incorrect Input)
Target Program
● Absolute machine language: It can be placed in a fxed memory locaton and can be
executed immediately.
● Relocatable machine language: It allows subprograms to be compiled separately.
A set of relocatable object modules can be linked together and loaded for executon
by a linking loader.
Example:
Error can occur during loading of relocatable object modules.
● Assembly language: Code generaton is made easier using Assembly Language
program. We can generate symbolic instructons and use Macro facilites of
assembler to help in code generaton.
Example:
Error can occur for undefned symbol
Instructon Selecton
● The instructons of target machine should be complete and uniform.

● The quality of the generated code is determined by its speed and size.
● The former statement can be translated into the later statement as shown below:
Register Allocaton
● Instructons involving register operands are shorter and faster than those involving
operands in memory.
● The use of registers is subdivided into two sub problems:
– Register allocaton – the set of variables that will reside in registers at a point
in the program is selected.
– Register assignment – the specifc register that a variable will reside in is
picked.
Evaluaton Order
● The order in which the computatons are performed can afect the efciency of
the target code.
● Some computaton orders require fewer registers to hold intermediate results
than others.
● The problem can be avoided by generatng code for three address statement in
the order in which they have been produced by ICG
Basic Blocks
A basic block is a sequence of consecutive statements in which flow of
control enters at the beginning and leaves at the end without any halt or
possibility of branching except at the end
Basic Block Construction Algorithm
Basic Blocks
Example:- Consider the following code for dot product of two vectors a
and b of length 20
begin
prod := 0;
i := 1;
do begin
prod := prod + a[i] * b[i];
i := i + 1;
end
while i <= 20
end
Basic Blocks
TAC
Basic Blocks
TAC
Block
Block11
Block
Block22
Flow Graph
●
Flow graph is a directed graph containing the flow-of-control
information for the set of basic blocks making up a program.
●
The nodes of the flow graph are basic blocks. It has a distinguished
initial node.
Code Generation Algorithm
The algorithm takes as input a sequence of three-address statements
constituting a basic block.
For each statement x := y op z
• Invoke a function getReg to determine the location L where the result of the
computation y op z should be stored.
• Consult the address descriptor for y to determine y’, the current location of
y. Prefer the register for y’ if the value of y is currently both in memory and a
register. If the value of y is not already in L, generate the instruction MOV y’, L
to place a copy of y in L.
• Generate the instruction OP z’, L where z’ is a current location of z. Prefer a
register to a memory location if z is in both. Update the address descriptor of x
to indicate that x is in location L. If x is in L, update its descriptor and remove x
from all other descriptors.
• If the current values of y or z have no next uses, are not live on exit from
the block, and are in registers, alter the register descriptor to indicate that, after
execution of x: = y op z, those registers will no longer contain y or z.
Code Generation Algorithm
The assignment d: = (a-b) + (a-c) + (a-c) might be translated into the following three- address
code sequence:
t: = a – b
u: = a – c
v: = t + u
d: = v + u
with d live at the end.
Code Sequence

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Module 11

●Basic block and fow graph

Intermediate representaton can be:

Prior to code generaton:-

● The instructons of target machine should be complete and uniform.

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