Lee 2020

Download as pdf or txt
Download as pdf or txt
You are on page 1of 2

Efficient PWM Waveform Generation Using Rotary

Encoder on Spartan-6E Starter Kit


Kyungnam Lee and Ho Young Hwang Youngmin Kim
Dept. of Computer Engineering, Kwangwoon University, 2
School of Electronic and Electrical Engineering,
Seoul 01897, Korea Hongik University, Seoul 04066, Korea
[email protected] [email protected]

Abstract— In this paper, an efficient pulse width modulation


(PWM) waveform generator with variable frequency and duty
cycle is designed and implemented. An ISIM simulator from Xilinx
is used to verify the simulation, and the reference clock and system
clock required to generate the PWM waveforms are based on a
rotary encoder signal and an oscillator on Spartan-6E FPGA
Starter Kit. A starter kit is used to implement the logic proposed
in this paper. The logic configuration is designed so that the duty Fig. 1. Duty cycle and frequency of PWM signal.
cycle of the PWM waveform can be changed from 0% to 100%
and there are no problems in PWM waveform generation even if
the rotary encoder pulse period is changed. The FPGA used to
construct the application logic provides a reconfigurable output voltage, and the lower the ratio, the lower the output
architecture and is economically useful, while also providing the voltage. Thus, it is possible to adjust the magnitude delivered to
best flexibility to replace a microcontroller. the load power by adjusting the pulse width.
Keywords— PWM generator, Duty Cycle; FPGA; Rotary The main advantage of PWM is very low power loss in
encoder; Spartan 6; Verilog; Xilinx. switching devices and at high frequencies. In digital circuits,
PWM waveform generation only provides the signal, while
I. INTRODUCTION FPGA-based PWM waveform generation provides a flexible
Pulse width modulation (PWM) is widely used in many design. Since FPGAs are economically useful with the
applications. It is used in many fields such as generating fixed numerous features of low cost, fast design time, and easy
DC voltage with unstable power [1], inverter control, AC and debugging available in a small design, they are replacing
DC motors [2], AC machine drives [3], analog-to-digital microcontrollers for many control system applications [8].
converters, and communication and control applications. A
The technique proposed in this paper describes the principle
PWM inverter is used to control the magnitude and frequency of
of variable duty cycle and PWM waveform generation using a
the applied voltage and current of the motor in AC motor
rotary encoder. In addition, the Spartan-6E FPGA starter kit is
operation [4].
used as an implementation tool, and simulation and synthesis are
Voltage-controlled switching devices in PWM include validated by Xilinx using the ISE WEB pack 14.7.
trigger thyristors, insulated-gate bipolar transistors (IGBTs), and
In this paper, Section II describes the operation of the
metal oxide semiconductor field effect transistors (MOSFETs)
proposed PWM waveform generator using a rotary encoder and
[5]. Today, PWM generation is more widely controlled using
Section III describes the simulation and results. Finally, Section
multiple converters [6]. PWM waveforms can output a
IV draws a conclusion.
modulated signal to a fixed waveform by varying the pulse width
of a time period that is typically kept constant. II. ROTARY ENCODER SIGNAL AND IMPLEMENTATION OF THE
In this paper, variable duty cycles and PWM waveforms are PROPOSED DESIGN
generated using the Spartan-6E FPGA starter kit and rotary The position sensor that converts the mechanical
encoder with an on-board clock signal. The FPGA has a flexible displacement in the rotational direction into a digital quantity is
architecture and can respond quickly to rotary encoder pulse called a rotary encoder. Originally designed as a detector for
cycle conditions. The FPGA with a reconfigurable architecture measuring rotation angle, it is recently used in positioning of
provides application convenience meeting user requirements [7]. information equipment in a robot or high precision position
control environment.
A typical PWM signal is shown in Fig. 1. As shown in Fig.
1, the duration of on pulse is “T”, the duration of off pulse is “t- Fig. 2 shows the pulse generated when the rotary encoder
T” where “t” is the entire cycle of the signal. Here, the state that rotates. The rotary encoder generates signals along the direction
the digital signal is “1”, which corresponds to “T/t”, is called a of rotation in the order of A, B phase or B, A phase with 90-
duty cycle. The higher the ratio of the “T” section, the higher the degree phase difference of 1/4 cycle [9].
(a) (a)

(b) (b)
Fig. 2. (a) Forward rotation and (b) reverse rotation of rotary encoder [9].

(c)
Fig. 4. Various duty cycles of the PWM output with 10 kHz frequency; (a)
10%, (b) 50%, and (c) 80%.

Fig. 3. Block Diagram of PWM Waveform generator IV. CONCLUSION


In this paper, an efficient PWM waveform generator that
uses a rotary encoder to change the PWM waveform from 0% to
100% duty cycle was designed. The proposed design was
The block diagram of the proposed design is shown in Fig. implemented in the Spartan-6E starter kit and was able to
3. The rotary encoder’s PHASE_A, PHASE_B signals and 100 generate a PWM frequency corresponding to the rotary encoder
MHz on-board clock are separated by inputs to FPGA Logic. It signal cycle. The proposed PWM waveform generation logic is
is also used as a system clock for “clk” signal and which can be easy to implement and requires minimal hardware and resources.
output variable duty cycles and PWM waveform signals using The proposed design can also be used to control DC motors, AC
that. also computed output is delivered to the device via motors, power inverters, converters. Different PWM waveforms
“clk_out”. Equations for calculating PWM frequency and duty can be generated using different approaches depending on the
cycle are as follows; application requirements.
PWM Freq =
1 (1)
Rotary Encoder Cycle / 2 ACKNOWLEDGMENT
This work was supported by the NRF of Korea funded by the MSIT under Grant
Duty Cycle = PWM signal cycle × Reserved value (%) (2) NRF-2019M3F3A1A02072093 (Intelligent Semiconductor Technology
Development Program).
Equation (1) shows the equation for conversion to PWM
frequency according to the rotary encoder signal cycle. At this REFERENCES
time, whenever the pulse edge of rotary encoder changes occurs, [1] R. Miftakhutdinov et al., “Modified Asymmetrical ZVS half-bridge DC–
1/2 is performed every 1 cycle per rotary encoder pulse to DC converter,” Applied Power Electronics Conference and Exposition, vol.
1, pp. 567–574, 1999.
calculate the PWM cycle. The FPGA internal logic [2] S. Shrivastava, J. Rawat, and A. Agrawal, “Controlling DC Motor using
configuration increases or decreases the signal period depending Microcontroller (PIC16F72) with PWM,” International Journal of
on the rotary encoder rotation speed. This is checked by a timer, Engineering Research, vol. 1, no. 2, pp. 45-28, 2012.
which is FPGA internal logic. It is checked in real time, and the [3] Y. Ito and S. Kawauchi, “Microprocessor –Based Robust Digital control
for UPS with three phase PWM Inverter,” IEEE Transactions on Power
encoder pulse cycle is calculated as the PWM signal cycle. As Electronics, vol.10, no.2, pp. 197-198, 1995.
shown in equation (2), it is calculated with the reserved value, [4] R. K. Pongiannan et al., “Dynamically Reconfigurable PWM Controller
reflected in the next PWM pulse cycle, and output as a duty cycle. for Three-Phase Voltage-SourceInverters”, IEEE Transactions on Power
Electronics, vol. 26, no. 6, pp. 1790-1799, 2011.
III. EXPERIMENTL RESULT [5] N. A. Rahim and Z. Islam, “Field Programmable Gate Array-Based Pulse-
Width Modulation for Single Phase Active Power Filter”, American
In this paper, the simulation was performed using the Xilinx Journal of Applied Sciences, vol. 6, pp. 1742-1747, 2009.
ISE 14.7 webpack tool. The functionality was designed in [6] Ó. López et al., “Multilevel Multiphase Space Vector PWM Algorithm,”
Verilog HDL code. Fig. 4 (a), (b), and (c) show PWM IEEE Trans. on Industrial Electronics, vol. 55, no. 5, pp. 1933-1934, 2008.
waveforms that change at 10%, 50%, and 80% duty cycle using [7] A. M. Joshi et al., “Design and implementation of real-time image
watermarking,” ICSPCC, pp. 1-5. 2011.
an ISIM simulator. For hardware implementation, the Spartan-
[8] A. M. Joshi, and A. Darji, “Efficient dual domain watermarking scheme
6E FPGA starter kit was used to generate the UCF file, and the for secure images,” International Conference on Advances in Recent
actual output pins identified the PWM waveforms that connect Technologies in Communication and Computing, pp. 909-914, 2009.
to the oscilloscope. [9] “Rotary Encoder Interface for Spartan-6E Starter Kit”, [Online]. Available:
https://www.xilinx.com.

You might also like