CD40718, CD40728, CD40758 Typ s

COS/MOS OR Gates Features: VOD

• Nledium-Speed Operation-tpLH'
High-Voltage Types (20-Volt Rating) tpHL = 60 ns (typ.) at VDD = 10 V
• 100% tested for quiescent current at 20 V 3 J
CD40718 Quad 2-lnput OR Gate
CD40728 Dual 4-lnput OR Gate • Maximum input current of 1 J.1.A at 18 V
over full package-temperature range; 100 nA at 4 K
CD40758 Triple 3-lnput OR Gate 18 V and 25 0 C
F B
• Standardized, symmetrical output characteristics '0 L
E 9
The RCA-C04071 B, C04072B, and • Noise margin (over full package temperature
H 12
CD4075B OR gates provide the system range) II ..
G 13
designer with direct implementation of the 1 Vat VDD = 5 V
positive-logic OR function and supplement 2 V at VDD = 10 V
the existing family of COS/MaS gates. The 2.5 Vat VDD = 15 V
Vss
CD4071, CD4072, and C04075 types are • 5·V, 10-V, and 16-V parametric ratings
supplied in 14-lead dual-in-line ceramic CD4071B
packages (0 and F suffixes), 14-lead dual- • Meets all requirements of JEDEC Tenta·
FUNCTIONAL DIAGRAM
in-line plastic packages (E suffix), 14-lead tive Stilndard ~o. 13 A, "Standard
ceramic flat packages (K suffix), and in chip Specifications for Description of 'B' Series
form (H suffix). CMOS Devices"

RECOMMENDED OPERATING CONDITIONS

For maximum reliability, nominal operating conditions should be selected so that operation
is always within the following ranges:
CHARACTERISTIC LIMITS UNITS o
MIN. I MAX. E
F 10
Supply· Voltage Range (For T A = Full Package·Temperature
Range)
3 18
I V G "
H 12

STATIC ELECTRICAL CHARACTERISTICS

LIMITS AT INDICATED TEMPERATURES (OCI

CD4072B
CONDITIONS Valuesat-55,+25,+125 Apply to D:F,H Packages FUNCTIONAL DIAGRAM
CHARACTER- Values at -40, +25, +85 Apply to E Package
ISTIC UNITS
Vo VIN VDD +25
(VI (VI (VI -55 -40 +85 +125 Min. Typ. Max.
Quiescent Device - 0,5 5 0.25 0.25 7.5 7.5 - 0.Q1 0.25
Current, - 0,10 10 0.5 0.5 15 15 - 0.01 0.5
p.A
100 Max. -
- 0,15 15 1 1 30 30 0.01 1
- 0,20 20 5 5 150 150 - 0.02 5 9 J

Output Low 0.4 0,5 5 0.64 0.61 0.42 0.36 0.51 1 -

(Sink) Current 0.5 0,10 10 1.6 1.5 1.1 0.9 1.3 26 -
IOLMin.
1.5 015 15 4.2 4 2.8 2.4 34 6.8 -
4.6 0,5 5 -0.64 -0.61 -0.42 -0.36 -0.51 -1 - mA
Output High
(Source) 2.5 0,5 5 -2 -1.8 -1.3 -1.15 -1.6 -3.2 - 10 L

Current,
IOH Min.
9.5 0,10 10 -1.6 -1.5 -1.1 -0.9 -13 -2.6 -
13.5 0,15 15 -4.2 -4 -2.8 -2.4 -3.4 -;-68 -
Output Voltage: - 0,5 5 0.05 - 0 0.05
Low-Level,
VOL Max.
- 0,10 10 0.05 - 0 0.05 CD4075B
- 0,15 15 005 - 0 0.05 FUNCTIONAL DIAGRAM
V
Output Voltage: - 0,5 5 4.95 4.95 5 -
High-Level, - 0,10 10 9.95 9.95 10 -
VOH Min.
- 0,15 15 14.95 14.95 15 -
Input Low 0.5,4.5 - 5 1.5 - - 1.5
Voltage,
VI~ Max.
1,9 - 10 3 - - 3
1.5,13.5 - 15 4 - - 4
V
Input High 4.5 - 5 3.5 3.5 - -
Voltage, 9 - 10 7 7 - -
VIH Min. 13.5 - 15 11 11 - -
Input Current
liN Max.
0,18 18 to.l to.l tl tl - t10- 5 ±0.1 p.A

238 ________________________________________________________________________
 CD4071B, CD4072B, CD4075B Typ s
MAXIMUM IRATINGS, Absolute-Maximum Values:
DC SUPPLY-\'OLTAGE RANGE, (VDD'
(Voltages relerenced to VSS Terminal) -0.5 to +20 V
INPUT VOLT~GE RANGE, ALL INPUTS -0.5 to VDD +0.5 V
DC INPUT CURRENT, ANY ONE INPUT ±10mA
POWER DISSIPATION PER PACKAGE (POl:
Fcn TA -40 to +60 o C (PACKAGE TYPE EI
C .. ...... 500mW
Fc)r T A +60 to +85 0 C (PACKAGE TYPE EI
C Derate Linearly at 12 mWf'C to 200 mW
For T A -!15 to +1000 C (PACKAGE TYPES D,FI
C .. ..... 500mW
For T A c +t 00 to +125 0 C (PACKAGE TYPES 0, FI Derate Linearly at 12 mW/oC to 200 mW
DEVICE DISSIPATION PER OUTPUT TRANSISTOR
FOR T A = fULL PACKAGE·TEMPERATURE RANGE (All Package Typesl 100mW
OPERATING·TEMPERATURE RANGE (TAl
PACKAGE TYPES 0, F, H -55 to +125 0 C
INPUT VOLTAGE (V,N' - v
PACKAGE TYPE E . -40 to +85 0 C
STORAGE TE.MPERATURE RANGE (Tstgl -65 to +1500 C Fig. 1 - Typical voltage transfer
LEAD TEMPE"RATURE (DURING SOLDERINGI characteristics.
At d'stance 1/16 ± 1/32 Inch (1.59 ± 0 79 mml from case fOI 10 s max.

DYNAMIC ELECTRICAL CHARACTERISTICS at T A = 25°C, Input t r , tf = 20 ns,

and CL = 5(] pF, RL =; 200 kn

ALL TYPES
TEST CONDITI or ~S
LIMITS
CHA RACTERISTIC ,- UNITS
v DO
,Ie ILTS
TYP. MAX.

Propagat Ion Delay Time, 5 125 250

10 60 120 ns
':PHl' tplH
'15 45 90

Transltio n Time, 5 100 200

lOAD CAPACITANCE (ClI-.F
'10 50 100 ns
tTHl' tTlH Fig. 2 - TYPical propagation delay time
'15 40 80
as a function of/oad capacitance.
Input Ca~,acitance, CIN Any Input ,- 5 7.5 pF

VDD

"ss

* All
NETWORK

a
INPUTS ARE PROTECTED
BY COSIMOS PROTECTION - ---
DD

"ss
92CS·29114

Fig. 3 - Schematic diagram for CD40118 (1of 4 Identical gates).

,
DRAIN-TO-SOURCE VOLTAGE IVDSI-v

FIg. 4 - Typical output low (sink) current

character/stics.

1(6'8'131~r--~ ~ l/~ ~3(4,IO,1I1

A
2 (5,9,121
92CIi-291l9
DRAIN-TO-SOURCE VOLTAGE lVosl-V

Fig. 6 - Minimum output low (sink) current

Fig. 5 - Logic diagram for CD40118 (1of 4 Identical gates). characteristics.

__________________---------------------------239
CD4071B, CD4072B, CD4075B Typ s
DIIAIN-lD-SOURCE VOLTAGE IVoS)-V
INV I ·

Vss

,5
YOO
'1'U-l4.J201.)

--- * BY
ALL INPUTS ARE PROTECTEO
COS'MOS PROTECTION
Fig. 8 - Typical output high (source) current
NETWORK
characteristics.

VSS
DRAIN-lO-SOURCE VOLTAGE IVDSI-V

Fig. 7 - Schematic diagram for CD40728 (1 of 2 identical gates).

2 (12)

3 (11)

11131
6 (9)

4 (10)

Fig. 9 - Logic diagram for CD40728 (1 of 2 identical gates). Fig. 10 - Minimum output high (source) current
charactf!,istics.

.,. ,,,:-1
2 (4,'2)0----4-..

1 (3,11)O*---+---~

* BY
VS:

ALL INPUTS ARE PROTECTEO

COS 'MOS PROTECTION
,5-- Yoo

.-
Fig. 12 -

00":
Typical transition tim.e as a function
of loed capacitance.

_£NT TlIll'EllATUII[ IT A -25·C

·
...
NETWORK VSS
T ~IV VI-'

- .
~2C" ·2911~ I I ,,~ V /1;
:- 10".
Fig. 11 - Schematic diagram for CD40758 (1 of 3 identical gates). ~ I7l,.?oIY~ ~
~ -
I ","'~V
~IQ! h //
~ !
i
III()2 · IV1//
1//

'0-.
I
i CL·~ p'

Fig. 13 - Logic diagram for CD40758 (1 of 3 identical gates).

--'!l ·- V

'0 10'
'NPUT fREQU[NCY (0 1 ' - .H,
CL'15 of ---
II
i'
IQ!
I
I
I
••

Fig. 14 - Typical dyanamic power dissipation . ,

as a function o( frequency.

240 _____________________________________________________________________
 CD4071B, CD4072B, CD4075B Typ s

TERMINAL ASSIGNMENTS (TOP VIEW)

INPUTS
o

'[
Vss
14 VOO J"A+B+C+O I. 14 Voo VOO
B- 2 13 H 2 13 K"E+I'+II+H o
J-A+B- 3 12 0 12 H
K"C+O- 4 II ""O+H 0
C- :I 10 L"E+F 10 F
L"O+H+X
o 6 9 XC 6 9 E K"O+E+F J "A+B+C
VSS- Vss 7 B XC
VSS -"'L..-_.llr-C DO
C04CI7IB CD4072B CD4D7!18
.2CS-24"'4 92CS-l""96RI 92CS-244'"
XC" INTERNAL CONNECTION Vss
DO NOT USE 9ZCS-zr4l0IAI

FIg. 15 - OUlescent device current test circuIt.

V~.P(JU'
,~ :::;".,,~
o """"'..::.,r- SEOUENTIALLY.
Vss TO BOTH VOO AND VSS
CONNECT ALL UNUSED
INPUTS TO EITHER
VOO CRVSS
VSS 92C5-27402

Fig. 16 - Input current test circuit.

vs.~UT·O·
,~ '~'~
v 1L • .J
NOTE
92CS-Z144" I Vss ~srN'p~~0M8INATI()N

Fig. 17 - Input-voltage test circuit.

D,menslollS .n parentheses are .n mll.',meters and

are deflved from the baSIC .nch d""e.1slOns as .n.
d,cated Gfld graduatIons are .n mils (10- 3 .nch)

The photographs and d,menSIons of t~ach CDSIMDS

chIp represent a chIp when It IS part of the wafer
When the w~fer IS cut Into" ChIP~, the cleavage '2eS-2'1I1
angles are 57 Instead of 90 with respect to the
face of the chIp Therefore, the nola ted chIp IS DImensions and pad layout for CD4071 B.
actually 7 mils (0 17 mm) larger In both dImenSIons

.aU-HI 10

Dimensions and pad layout for CD4072B. DimensIons and pad layout for CD4075B.

___________________________________________ 241