EE6008 Notes Rejinpaul

www.rejinpaul.
com
UNIT I
INTRODUCTION TO PIC MICROCONTROLLER
Introduction to PIC Microcontroller–PIC 16C6x and PIC16C7x Architecture–
PIC16cxx–- Pipelining -Program Memory considerations – Register File Structure
- Instruction Set - Addressing modes –Simple Operations.
1. PIC Microcontrollers
PIC stands for Peripheral Interface Controller coined by Microchip Technology to
identify its single chip microcontrollers. These devices have been phenomenally
successful in 8-bit microcontroller market.The main reason is that Microchip
Technology has constantly upgraded the device architecture and added needed
peripherals to the microcontroller to ’suit customers’ requirements. The development
tools such as assembler and simulator are freely available on the internet at
www.microchip.com
1.1Low-end Architectures
Microchip PIC microcontrollers are available in various types. When PIC −
MicroMCU first became available from General Instruments in early 1980’s, the
microcontroller consisted of a very simple processor executing 12-bit wide
instructions with basic I/O functions. These devices are known as low-end
architectures.
Some of the low-end device past numbers
are 12C5XX, 16C5X, and 16C505
1.2Mid-range Architectures
Mid-range Architectures are built by upgrading low-end architecture with more
number of peripherals,more numbers of register and more data memory. Some of the
mid-range devices are16C6X16C7X, 16F87X ↑Program memory type
C = EPROM
F = Flash
Get useful study materials from www.rejinpaul.com

www.rejinpaul.com
RC = Mask ROM
Popularity of PIC microcontrollers is due to the following factors-
1. Speed: Harvard Architecture, RISC Architecture
1 instruction Cycle = 4 clock cycles.
For 20 MHz clock, most of the instructions are executed in 0.2μs or five instructions
per microsecond.
2. Instruction Set Simplicity:
The instruction set consists of just 35 instructions (as opposed to 111 instructions for
8051)
3. Power on reset
Power-out reset
Watch-dog timer
Oscillator Options
• low-power Crystal
• Mid-range Crystal
• High-range Crystal
• RC Oscillator
4. Programmable timer options on chip ADC
5.Up to 12 independent interrupt sources
6. Powerful output pin control25mA (max.) current sourcing capability.
7. EPROM/OTP/ROM/Flash memory options.
1.3PIC16C7X Peripheral Features:

• Timer0: 8-bit timer/counter with 8-bit prescaler
• Timer1: 16-bit timer/counter with prescaler,can be incremented during sleep
via external crystal/clock
• Timer2: 8-bit timer/counter with 8-bit period register, prescaler and postscaler
• Capture, Compare, PWM module(s)
• Capture is 16-bit, max. resolution is 12.5 ns,Compare is 16-bit, max. resolution
is 200 ns,PWM max. resolution is 10-bit

www.rejinpaul.com
• 8-bit multichannel analog-to-digital converter

• Synchronous Serial Port (SSP) with SPI and I2C
• Universal Synchronous Asynchronous ReceiverTransmitter (USART/SCI)
• Parallel Slave Port (PSP) 8-bits wide, with external RD, WR and CS controls
• Brown-out detection circuitry for Brown-out Reset (BOR)

www.rejinpaul.com
Fig 1.1 PIC Microcontrollers Architectures

www.rejinpaul.com
Memory
The memory in a chip used to store the data and program temporary or permanently
.As like normal microcontrollers, the PIC chip also has certain amount of RAM,
ROM, EEPROM, other flash memory, etc. A PIC chip normally contains a certain
amount of Flash memory
ALU
Perform Operations on temporary working register and register file. It is 8 bit wide
ALU. One of the operand is normally in W register and the other one is either a fine
register or an immediate constant. Effect various flags, namely, carry, digit carry,
zero in status register
BUS
Bus is the communication or data transmission /reception path in a microcontroller
unit. In a normal microcontroller chip, two types of buses are normally available
Data Bus
Data bus is used for memory addressing. The function of data bus is interfacing all
the circuitry components inside the PIC chip
Address bus
Address bus mostly used for memory addressing. The function of address bus is to
transmit the address from the CPU to memory locations.
Power On Reset task
The task of POR is ensuring that the processor starts at known address when power is
first on. The reset function will set the program counter to the starting address.
Power Up timer
A special timer that delays the start of program execution after the PIC has been rest
on Power. This time delay allows Vdd to rise to the required level.
Brown Out delay
When the power supply drops below a certain voltage (4V in case of PIC), it causes
PIC to reset

www.rejinpaul.com
WDT
A Watch dog timer is a simple timer circuit that performs a specific operation after a
certain period of time if something goes wrong. Suppose we have written a program
which is compiled successfully and when we simulate if every time seems to work
fine. Then we program the PIC. However after a long period of time the program gets
stuck somewhere. What needs it this case is some kind of reset if the program is gets
stuck. This is a purpose of a watchdog timer circuit. When the WDT is enable counter
starts at 00 and increment by 1 unit until it reaches FF.When it goes from FF to 00 the
PIC will be reset, irrespective of what it is doing. The only way we can stop the
WDT, from resetting the WDT back to 00 throughout the program which is done by
the processor. Which indicates that the processor functioning is going on. Watch dog
timer is thus increase the system reliability.
CPU registers (registers commonly used by the CPU)

W, the working register, is used by many instructions as the source of an operand.
This is similar to accumulator in 8051. It may also serve as the destination for the
result of the instruction execution. It is an 8 - bit register.
Fig1.2 : W register
STATUS Register
The STATUS register is a 8-bit register that contains the arithmetic status of the
(ALU) , the reset status and the bank select bits for the data memory.
Fig1.3 : STATUS register

Carry bit ( c )
When two 8-bit operands are added, a 9 bits result occurs, because the result of
th
addition may be exceeds 256(FFH). The 9 bit is copied in the Carry bit.

www.rejinpaul.com
Bit 0 (c): Carry /borrow bit (ADDWF, ADDLW, SUBLW, SUBWF instructions)
1= A carry-out from the Most Significant bit of the result occurred
0= No carry-out from the Most Significant bit of the result occurred
Digit Carry (DC)
This bit indicates a carry from the lower 4 bits during 8 bit addition. If set, it means
rd th
there is a carry from the 3 bit to 4 bit position. Bit 1 DC: Digit carry/borrow bit
(AADWF, ADDLW, SUBLW, SUBWF instructions) for borrow, the polarity is
reversed.
th
1= A carry-out from the 4 low order bit of the result occurred
th
0= No carry-out from the 4 low order bit of the result
Zero (Z)
Many arithmetic and logic instruction affects the zero flag.
Decf Instruction can be used to decrement a variable in RAM, and if result is zero, Z
bit is set, otherwise cleared. Bit 2,(z) : Zero bit
1=the result of an arithmetic or logic operation is zero
0= the result of an arithmetic or logic operation is not Zero.
TO and PD (active low)
 Used along with SLEEP mode of PIC.

 During the sleep mode the Microcontroller save lots of power

 After coming out of this mode, the CPU can check these two status bit to
determine which kind of event is responsible to bring it out of the SLEEP
Mode.
 Bit 4 , (TO): This is a time –out bit used for timing and counting , Sleep and
reset functions.

1= after power-up , CLRWDT instruction or SLEEP
instruction 0=A WDT time-out Occurred

 Bit 3, (PD) : power – down bit
1=after power-up or by the CLRWDT instruction
0= by execution of the SLEEP instruction

www.rejinpaul.com
RPO and RP1

There are four memory banks each of 128 bytes in size. For bank selection
2 bits are needed, making the effective address 9- bit wide
FSR Register
(FileSelectionRegister,address=04H,84H)
FSR is an 8-bit register used as data memory address pointer. This is used in indirect
addressing mode.
INDF Register
(INDirectthroughFSR,address=00H,80H)
INDF is not a physical register. Accessing INDF access is the location pointed to by
FSR in indirect addressing mode.
PCL Register
(ProgramCounterLowByte,address=02H,82H)
PCL is actually the lower 8-bits of the 13-bit program counter. This is a both readable
and writable register.
PCLATH Register
(ProgramCounterLatch,address=0AH,8AH)
PCLATH is a 8-bit register which can be used to decide the upper 5bits of the
program counter. PCLATH is not the upper 5bits of the program counter. PCLATH
can be read from or written to without affecting the program counter. The upper 3bits
of PCLATH remain zero and they serve no purpose. When PCL is written to, the
lower 5bits of PCLATH are automatically loaded to the upper 5bits of the program
counter, as shown in the figure.
Fig1.4 : Schematic of how PCL is loaded from PCLATH

www.rejinpaul.com
Program Counter Stack

An independent 8-level stack is used for the program counter. As the program
counter is 13bit, the stack is organized as 8x13bit registers. When an interrupt occurs,
the program counter is pushed onto the stack. When the interrupt is being serviced,
other interrupts remain disabled. Hence, other 7 registers of the stack can be used for
subroutine calls within an interrupt service routine or within the mainline program.
Register File Map
It can be noted that some of the special purpose registers

are available both in Bank-0 and Bank-1. These registers
have the same value in both banks. Changing the register
content in one bank automatically changes its content in
the other bank.
Port Structure and Pin Configuration of PIC 16C74A
As mentioned earlier, there is a large variety of PIC
microcontrollers. However, the midrange architectures
are widely used. Our discussion will mainly confine to
PIC16C74A whose architecture has most of the required
features of a mid-range PIC microcontroller. Study of
any other mid-range PIC microcontroller will not cause
much variation from the basic architecture of PIC
16C74A ..
PIC 16C74A has 5 I/O Ports. Each port is a bidirectional I/O port In addition, they
have the following alternate functions.

www.rejinpaul.com
PARALLEL I/O Ports
Most of the PIC16cx/7x family controllers have 33 I/O lines and five I/O ports They are PORT A,
PORT B, PORT C , PORT D and PORT E.
PORT A:
Port A is a 6-bit wide bi-directional port. Its data direction register is TRISA
setting TRISA bit to 1 will make the corresponding PORT A Pin an input. Clearing a
TRIS a bit will make the corresponding pin as an output.
PORT B:
Port B is an 8-bit wide, bi-directional port. Four of the PORT B pins RB7 –
RB4 have an interrupt-on- change feature. Only the pins configured as inputs can
cause this interrupt to occur.
PORT C:
Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register

determine the function of its pins. Similar to other ports, a logic one 1 in the TRISC
Register configures the appropriate port pin as an input.
PORT D:
Port D is an 8-bit wide bi-directional port. In addition to I/O port, Port D also
works as 8-bit parallel slave port or microprocessor port. When control bit
PSPMODE (TRISE:4) is set.
PORT E:
It is a 3-bit bi-directional port. Port E bits are multiplexed with analog inputs of
ADC and they serve as control signals (RD , WR, CS) for parallel slave port mode of
operation.

www.rejinpaul.com
1.5 Harvard Architecture
The high performance of the PIC16CXX family can be attributed to a number of

architectural features commonly found in RISC microprocessors. To begin with, the
PIC 16CXX uses a Harvard architecture, in which, program and data are accessed
from separate memories using separate buses. This improves bandwidth over
traditional Von Neumann architecture where program and data may be fetched from
the same memory using the same bus.
Fig 1.5 CPU Architecture of PIC Microcontroller

As the PIC 16c6x/7x family of micro-controllers uses Harvard Architecture it enables
the devices exceptionally fast execution speed for a given clock rate. In the Harvard
Architecture separate buses are used for Data and Instruction as shown in the
diagram.
Instructions are fetched from program memory using buses that are distinct from the
buses used for accessing variables in data memory, I/O ports etc. Every instruction is
coded as a single 14-bit word and fetched over a 14-bit wide bus.
Separating program and data buses further allows instructions to be sized differently
than 8-bit wide data words. Instruction op-codes are 14-bits wide making it possible
to have all single word instructions. A 14-bit wide program memory access bus
fetches a 14-bit instruction in a single cycle

www.rejinpaul.com
1.6Pipelining
Fig 1.6 Pipelining of instruction fetch successive addressing
The CPU executes each instruction during the cycle following its fetch, pipelining
instruction fetches and instruction executions to achieve the execution of one
instruction every cycle. This is illustrated in Figure 1.6 . It can be seen that while
each instruction requires two cycles (a fetch cycle followed by an execute cycle), the
overlapping of the execute cycle of one instruction with the fetch cycle of the next
instruction leads to the execution of a new instruction every cycle.
This lockstep progression is broken whenever an instruction includes a branch
operation, as illustrated on Figure In this example, an instruction is fetched during the
second cycle, goto New Address, whose job it is to change the normal flow of
instruction fetches from one address to the next address. During the third cycle, the CPU
carries out the sequential fetch from address n+2. At the end of that third cycle, the CPU
executes the goto New Address instruction by changing the program counter to New
Address instead of simply incrementing it to n+3. On the fourth cycle while it is fetching
the instruction at New Address , ilt ignores the instruction automatically fetched from
th
address n+2. While this (n+2) instruction is located in the program immediately after
th
the (n+1) goto New Address instruction, it is never executed

www.rejinpaul.com
th
immediately after the execution of that (n+1) goto New Address instruction.
Fig 1.6 Introduction of extra cycle for a jump/goto Instruction
1.6PROGRAM MEMORY CONSIDERATIONS

Each member of the PIC16C6x/7x family of microcontrollers included in this
text has either 2K(i.e., 2048) or 4K(i.e., 4096) addresses of program memory. As
shown in Figure a, a program memory of 2K addresses needs only an 11 –bit
^
program counter to access any address (2 11=2048=2K). A program memory of 4K
addresses needs a 12-bit program counter, as shown in Figure b. This PIC family
actually uses a 13-bit program counter, allowing for extending the family to an 8K
program memory without changing the CPU structure. For 4K and 2K parts, the
upper bit or bits are simply ignored during fetches from program memory.

www.rejinpaul.com
Fig 1.7 Program Memory accesses

www.rejinpaul.com
Two addresses in the program memory address space are treated in a special way by
the CPU. When the CPU starts up from its reset state, its program counter is
automatically cleared to zero. This is illustrated in Figure . with the content of
address H'000'1 being a go to Mainline instruction. The second special address H'004'
, is automatically loaded into the program counter when an interrupt occurs. As
shown in Figure , a goto IntService instruction can be assigned to this address, to
cause the CPU to jump to the beginning of the interrupt service routine, located
elsewhere in the memory space.
The program memory map of PIC16C74A is shown in Fig. On reset, the program
counter is cleared and the program starts at 00H. Here a 'goto' instruction is required
that takes the processor to the mainline program. When a peripheral interrupt, that is
enabled, is received, the processor goes to 004H. A suitable branching to the interrupt
service routine (ISR) is written at 004H.

www.rejinpaul.com
The mainline program begins execution when the PIC comes out of reset. It continues
’
running until one of the PIC s interrupt sources requests service. At that point the
execution of the mainline code is temporarily suspended. The CPU begins the
execution of the interrupt service routine by automatically loading the program
counter with H'004'. At the completion of the interrupt service routine, the CPU
returns to where it left off in the mainline program. Program writing is somewhat
simplified if all the program code for the tables, the mainline program and its
subroutines, and the interrupt service routine and its subroutines take up less than 2K
words of instruction

www.rejinpaul.com
As shown in Figure, bits 10…0 of the call instruction are loaded into the program
counter. At the same time, bits 4 and 3 of a special register called PCLATH
(“program counter latch ”) are loaded into bits 12 and 11 of the program counter. As
long as the program memory is less than 2048(i.e.,2K) words, bits 4 and 3 of
' ' ' '
PCLATH can be left initialized to H 00 , and then the 11 address H 7FF .
For the programs larger than this, it is necessary to ensure that bit 3 of PCLATH is
set or cleared appropriately each time a subroutine is called. The goto instruction,
which also has an 11-bit address field, requires an identical treatment
1.7REGISTER FILE STRUCTURE
In PIC Microcontrollers the Register File consists of two parts namely

1. General Purpose Register File
2. Special Purpose Register File

www.rejinpaul.com
a) General Purpose Register File:
The general purpose register file is another name for the microcontroller’s
RAM . Data can be written to each 8-bit location updated and retrieved any number
of times.
b) Special Purpose Register File:
The special function register file consists of input, output ports and control
registers used to configure each 8-bit port either as input or output. It contains
registers that provide the data input and data output to a chip resources like Timers,
Serial Ports and Analog to Digital converter and also the registers that contains
control bits for selecting the mode of operation and also enabling or disabling its
operation.
Fig1.8 Register bank

www.rejinpaul.com
1.8 INSTRUCTION SET

Each microcontroller family has its own set of instructions, which carry out
essentially the same set of operations, but using different syntax. The PIC uses a
minimal set of instructions, which makes it a good choice for learning. While writing
the instructions the following guidelines are followed.
a) Write the instructions mnemonics in lower case (example: xorwf)
b) Write special Register names, RAM variable names and bit names in upper case
(example: STATUS, RPO….)
c) Write instruction and subroutine labels in mixed case (example: Mainline,
LoopTime..)
The instruction set of PIC is divided into Three basic categories. They are
(a) Byte oriented Instructions
(b) Bit oriented Instructions
(c) Literal and Control Instructions
Byte Oriented Instructions
In a byte oriented Instructions f represents a file register and d represents destination
register.The destination specifies where the result of operation is to be placed. If D=
0 the result is placed in W register(Accumulator) and if d = 1 , the
result is placed in the file register specified in the instruction.
ADDWF f, d ; Add W and f
CLRF f ; Clear f
MOVWF f ,d ; Move f
NOP ; No operation
SUBWF f ,d ; Subtract W from f
Bit Oriented Instruction

In bit oriented instructions, b represents a bit field designator which selects the
number of the bit affected by the operation and f represents the number of the file in

www.rejinpaul.com
which the bit is located.
BCF f , b ; Bit clear f

BSF f, b ; Bit set f
BTFSC f,b ; Bit test f ,skip if set
Literal and Control Instrucrtions
In literal and control instructions K represents an 8 or 11 bit constant or literal value.
ADDLW k ; Add literal and W

ANDLW k ; AND literal with W
CALL k ; Call subroutine
MOVLW k ; Move literal to W
SUBLW k ; Subtract W from literal
Based on the type of operation PIC supports various Instructions. They are explained
below.
CLASSIFICATION OF INSTRUCTIONS
All the instructions of the PIC microcontroller are classified into nearly 9 groups.
They are given below with examples.
(i).Arithmetic Operations :
ADDLW k ; Add literal value k to W
ADDWF f, d ; The contents of the W register are added with the register f.
SUBWF f ,d ; the contents of W register are subtracted from register f
(ii).Logical Instructions :
ANDLW k ; The contents of W register are ANDED with the 8-bit literal k .The
result is stored in the W register.
IORLW k ;Inclusive OR the literal value into W register
XORWF f,d ; The contents of W register are XORed with register f and the result is
stored in W or f.

www.rejinpaul.com
COMF f, d ; Complement f .
(iii).Increment/Decrement Instructions
INCF f ,d ; Increment contents of f register by 1
DECF f , d ; Decrement f by 1
(iv).Data Transfer instructions
MOVF f,d ; Move f to W i.e The contents of register f is moved to a destination
depending on d
MOVLW k ; Move literal k to W
MOVWF f ; Move W to f
(v) Clear Instructions
CLRF ;Clear file f
CLR W ; Clear the contents of W register and zero bit is set
CLRWDT ; Clear Watch dog timer
BCF ; Clear bit b of register f.
(vi)Rotate Instructions
RLF ; Rotate Left f through carry
RRF ; Rotate Right f through carry
(vii). Branch Instructions : There are two types of Branch

instructions. (i)Conditional Branch
(ii) Un conditional Branch instructions.
(i) Conditional Branch Instructions

BTFSC f , b ; Bit Test skip if clear
BTFSS f , b ; Bit test f , skip if set
If bit B in register f is zero ,then the next instruction is executed, otherwise next
instruction is discarded and a NOP is executed.
DECFSZ f,d ; Decrement f ,skip if zero.
INCFSZ f,d ; Increment f ,skip if zero

www.rejinpaul.com
(ii) Unconditional Instructions

CALL k ; Call the subroutine k unconditionally
GOTO k ; Unconditional k branch
RETURN ; Return from subroutine
REETLW k ; Return with literal in W register.
viii Miscellaneous
BSF f,b ; Set bit b of register f
SLEEP ; Go into stand by mode
NOP ; No operation i.e Do nothing , wait one clock cycle.

www.rejinpaul.com
1.9ADDRESSING MODES.
The PIC microcontrollers support only TWO addressing modes .They are
Direct Addressing Mode

Indirect Addressing mode
Direct Addressing: Using this method we are accessing the registers directly by
detecting location inside Data Memory from Opcode and by selecting the bank using
bits RP1 and RP0 of the STATUS register.
Example of direct addressing:
1. TEMP Equ 0x030
2. Movlw 5
3. Movwf TEMP

www.rejinpaul.com
It's easy to understand, that direct addressing method means working directly with
the variables. In the second line we put the number 5 into the working register W,
and in the line 3, the content of the W passes to the TEMP variable
Fig 1.9 Addressing modes
Indirect Addressing: To implement indirect addressing, a File Select Register (FSR)

and indirect register (INDF) are used. In addition, when using this method we choose
bank using bit IRP of the STATUS register. Indirect addressing treated like a stack
pointer, allowing much more efficient work with a number of variables. INDF
register is not an actual register (it is a virtual register that is not found in any bank).
Example of indirect addressing:
TEMP Equ 0x030
Movlw 0x030
Movwf FSR
Movlw 5
Movwf INDF

www.rejinpaul.com
In the second line, we put a value into the W register. In the third line, the value
passes to the FSR register, and from this moment FSR points to the address of the
TEMP variable. In the fourth line, the number 5 passes to the W register, and in the
fifth line, we move the contents of W register (which is 5) to the INDF. In fact INDF
performs the following: it takes the number 5 and puts it in the address indicated by
FSR register
Simple Operations
Either –or Sequence
Assume that an instruction that affects the Z bit has just been executed. Then
depending on the result one instruction sequence or another is to be executed,
continuing on after either case.

www.rejinpaul.com
Decrement a 16- bit counter
Assume that the upper byte of the counter is called COUNTH and the lower byte is
called COUNTL
Note how the movf instruction is first used to test COUNTL for zero without
changing it, and even without having to move it into W
Test a 16 – bit variable for zero
Using same COUNTH,COUNTL variable as previously , the following sequence

will either branch to an instruction labeled both zero if the variable equals zero or to
an instruction labeled carryon otherwise

www.rejinpaul.com

www.rejinpaul.com
UNIT II
INTERRUPTS AND TIMER
PIC micro controller Interrupts- External Interrupts-Interrupt Programming–
Loop time subroutine – Timers-T7imer Programming– Front panel I/O-Soft
Keys– State machines and key switches– Display of Constant and Variable
strings.
PIC Microcontroller Interrrupts:
Introduction:
There are 2 methods for communicating between the microcontroller and

the external system:
 POLLING
 INTERRUPTS
POLLING
Using this method, the microcontroller accesses at the exact time interval
the external device, and gets the required information. The user is the one
who determines the time intervals in which micro “contacts” the device.
In the Polling method, the PIC microcontroller must "access by himself" the
device and “ask” for the information it needs for processing. In fact we see
that in the Polling method the external devices are not independent systems;
they depend on the microcontroller, and only the micro is entitled to obtain
access to the information it needs. The main drawback of this method when
writing program is waste of time of microcontroller, which needs to wait and
check whether the new information has arrived.
INTERRUPTS
Interrupt is the signal sent to the micro to mark the event that requires
immediate attention. Interrupt is “requesting" the processor to stop to
perform the current program and to “make time” to execute a special code.
In fact, the method of interrupt defines the option to transfer the
information generated by internal or external systems inside the micro by
them self! Once the system has finished the task imposed on it, the
processor will be notified that it can access and receive the information and
use it.
The “request” for the microcontroller to “free itself” to execute the interrupt
could come from several sources:
1
www.rejinpaul.com
 External hardware devices. Common example is pressing on the key

on the keyboard, which causes to the keyboard to send Interrupt to
the microcontroller to read the information of the pressed key.
 The processor can send interrupts to itself as a result of executing the

program, to report an error in the code. For example, division by 0 will
causes an interrupt.
 In the multi-processor system, the processors can send to each other

interrupts as a way to communicate.
There are two types of PIC interrupts:
Software interrupts - come from a program that runs by the processor and
“request” the processor to stop running the program, go to make an
interrupt and then to return to continue to execute the program.
An example: Procedure - when there is a procedure call, the processor stops
the execution of the program, jumps to the place in memory that reserved
for a procedure – executes the procedure and only then returns back to the
program and continues to execute.
Hardware interrupts -these are sent to microcontroller by hardware devices

as a third-party; some of them can be blocked - (masking) by Interrupt
Enable bit (IE). When the interrupt is “blocked”, the PIC microcontroller does
not "see" the request for the interrupt and will not execute it. In fact the
blocked interrupt will not be executed until it will be unblocked.
For example: The processor is in the middle of a calculation, and we do not
want to write into memory until the micro did not finish the calculation. In
this situation, we will “block” the "write to the memory" interrupt. We will
“unblock” the interrupt only after the processor finished the calculation,
thus preventing him to write into the memory as long as it is in the middle
of the action. There are some interrupts that can not be “masked”/”blocked”
- NMI - Non Mask able Interrupts. They are used to report on critical
hardware issues, such as the drop of voltage. In this situation we are
interested in immediate response from the processor without the ability to
ignore them.
Interrupts in PIC16C6X:
The PIC16C6X family has up to 11 sources of interrupt. The interrupt

control register (INTCON) records individual interrupt requests in flag bits. It
also has individual and global interrupt enable bits.
PICmicro MCUs can have many sources of interrupt. These sources

generally include one interrupt source for each peripheral module, though
2
www.rejinpaul.com
some modules may generate multiple interrupts (such as the USART

module). The current interrupts are:
• INT Pin Interrupt (external interrupt)
• TMR0 Overflow Interrupt
• PORTB Change Interrupt (pins RB7:RB4)
• Comparator Change Interrupt
• Parallel Slave Port Interrupt
• USART Interrupts
• Receive Interrupt
• Transmit Interrupt
• A/D Conversion Complete Interrupt
• LCD Interrupt.
• Data EEPROM Write Complete Interrupt
• Timer1 Overflow Interrupt
• Timer2 Overflow Interrupt
• CCP Interrupt
• SSP Interrupt
There is a minimum of one register used in the control and status of the
interrupts. This register is: INTCON
Global interrupt enable bit, GIE (INTCON) enables (if set) all un-masked
interrupts or disables (if cleared) all interrupts. When bit GIE is enabled,
and an interrupt flag bit and mask bit are set, the interrupt will vector
immediately. Individual interrupts can be disabled through their
corresponding enable bits in the INTCON register. GIE is cleared on reset.
The “return from interrupt” instruction, RETFIE, exits the interrupt routine
as well as sets the GIE bit, which re-enable interrupts. The RB0/INT pin
interrupt, the RB port change interrupt and the TMR0 overflow interrupt
flag bits are contained in the INTCON register. The peripheral interrupt flag
bits are contained in special function registers PIR1 and PIR2. The
corresponding interrupt enable bits are contained in special function
registers PIE1 and PIE2 and the peripheral interrupt enable bit is contained
3
www.rejinpaul.com
in special function register INTCON. When an interrupt is responded to, bit

GIE is cleared to disable any further interrupts, the return address is
pushed onto the stack and the PC is loaded with 0004h. Once in the
interrupt service routine the source(s) of the interrupt can be determined by
polling the interrupt flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid recursive interrupts. For
external interrupt events, such as the RB0/INT pin or RB port change
interrupt, the interrupt latency will be three or four instruction cycles. The
exact latency depends when the interrupt event occurs The latency is the
same for one or two cycle instructions. Once in the interrupt service routine
the source(s) of the interrupt can be determined by polling the interrupt flag
bits. The interrupt flag bit(s) must be cleared in software before re-enabling
interrupts toavoid infinite interrupt requests. Individual interrupt flag bits
are set regardless of the status of their corresponding mask bit or the GIE
bit.
4
www.rejinpaul.com
Fig: INTERRUPT LOGIC FOR PIC16Cxx
INT INTERRUPT:
External interrupt on RB0/INT pin is edge triggered: either rising if edge

select bit INTEDG (OPTION) is set, or falling, if bit INTEDG is clear. When a
valid edge appears on the RB0/INT pin, flag bit INTF (INTCON) is set. This
interrupt can be disabled by clearing enable bit INTE (INTCON). The INTF bit
must be cleared in software in the interrupt service routine before re-
enabling this interrupt. The INT interrupt can wake the processor from
SLEEP, if enable bit INTE was set prior to going into SLEEP. The status of
global enable bit GIE decides whether or not the processor branches to the
interrupt vector following wake-up. See Section 13.8 for details on SLEEP
mode.
TMR0 INTERRUPT:
An overflow in the TMR0 register will set flag bit T0IF. The interrupt can
be enabled/disabled by setting/clearing enable bit T0IE.
PORTB INTERRUPT ON CHANGE:
An input change on PORTB sets flag bit RBIF. The interrupt can be
enabled/disabled by setting/clearing enable bit RBIE.
WATCH DOG TIMER (WDT):
The Watchdog Timer is a free running on-chip RC oscillator which does
not require any external components. This RC oscillator is separate from the RC
5
www.rejinpaul.com
oscillator of the OSC1/CLKIN pin. That means that the WDT will run, even if
the clock on the OSC1/CLKIN and OSC2/CLKOUT pins of the device has been
stopped, for example, by execution of a SLEEP instruction. During normal
operation, a WDT time-out generates a device reset. If the device is in SLEEP
mode, a WDT time-out causes the device to wake-up and continue with normal
operation. The WDT can be permanently disabled by clearing configuration bit
WDTE.
WDT PERIOD:
The WDT has a nominal time-out period of 18 ms, (with no prescaler).
The time-out periods vary with temperature, VDD and process variations from
part to part (see DC specs). If longer time-out periods are desired, a prescaler
with a division ratio of up to can be assigned to the WDT under software
control by writing to the OPTION register. Thus, time-out periods up to seconds
can be realized.
The CLRWDT and SLEEP instructions clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from timing out and generating a device
RESET condition.
The TO bit in the STATUS register will be cleared upon a WDT time-out.
WDT PROGRAMMING CONSIDERATIONS:
It should also be taken in account that under worst case conditions (VDD =
Min., Temperature = Max., max WDT prescaler) it may take several seconds
before a WDT time-out occurs.
ADC Interrupt
This interrupt is generated when the analog-to-digital conversion ends. This is
only to 16 C7X parts in general. ADIE is the bit that enables this interrupt in
INTCON register. Apart from this the master control bit GIE must be enabled.
The end of the conversion interrupt flag (ADIF) bit is in ADCON0 register.
i. On reset all interrupts are disabled
6
www.rejinpaul.com
ii. Programmer Sets/Clears INTEDG bit in OPTION register if Interrupts

are to be recognized on rising/ Falling edge of pulse
iii. Programmer sets in INTCON register GIE and the desired interrupts;
external Interrupt (INT), Timer 0 interrupt ( TOIE), or Port B Change (
RBIE).
iv. On setting the corresponding flag GIE gets disabled (to avoid further
occurrence of interrupt till ISR is executed) and program enters the ISR,
as the program come out of ISR, GIE get enabled automatically.
v. Before RETF the programmer has to disable the corresponding flag of the
interrupt source.
INTCON Register
The INTCON Register is a readable and writable register which contains

various enable and flag bits. Interrupt flag bits get set when an interrupt
condition occurs regardless of the state of its corresponding enable bit or the
global enable bit, GIE (INTCON<7>).This feature allows for software polling.
bit 7 GIE: Global Interrupt Enable bit
1 = Enables all un-masked interrupts
0 = Disables all interrupts
bit 6 PEIE: Peripheral Interrupt Enable bit
1 = Enables all un-masked peripheral interrupts
0 = Disables all peripheral interrupts
bit 5 T0IE: TMR0 Overflow Interrupt Enable bit
1 = Enables the TMR0 overflow interrupt
0 = Disables the TMR0 overflow interrupt
bit 4 INTE: INT External Interrupt Enable bit
1 = Enables the INT external interrupt

7
www.rejinpaul.com
0 = Disables the INT external interrupt
bit 3 RBIE (1): RB Port Change Interrupt Enable bit
1 = Enables the RB port change interrupt
0 = Disables the RB port change interrupt
bit 2 T0IF: TMR0 Overflow Interrupt Flag bit
1 = TMR0 register has overflowed (must be cleared in software)
0 = TMR0 register did not overflow
bit 1 INTF: INT External Interrupt Flag bit
1 = The INT external interrupt occurred (must be cleared in software)
0 = The INT external interrupt did not occur
bit 0 RBIF (1): RB Port Change Interrupt Flag bit
1 = At least one of the RB7:RB4 pins changed state (must be cleared

in software)
0 = None of the RB7:RB4 pins have changed state
OPTION_REG Register
The OPTION_REG Register is a readable and writable register, which contains
various control bits to configure the TMR0 prescaler/WDT postscaler (single
8
www.rejinpaul.com
assignable register known also as the prescaler), the external INT interrupt,
TMR0 and the weak pull-ups on PORTB.
PIE Register(s)
Depending on the number of peripheral interrupt sources, there may be

multiple Peripheral Interrupt Enable registers (PIE1, PIE2). These registers
contain the individual enable bits for the Peripheral interrupts. These
registers will be generically referred to as PIE. If the device has a PIE
register, The PEIE bit must be set to enable any of these peripheral
interrupts.
Although, the PIE register bits have a general bit location with each register,
future devices may not have consistent placement. Bit location
inconsistencies will not be a problem if you use the supplied Microchip
Include files for the symbolic use of these bits. This will allow the
Assembler/ Compiler to automatically take care of the placement of these
bits by specifying the correct register and bit name.
Interrupt Latency
9
www.rejinpaul.com
Interrupt latency is defined as the time from the interrupt event (the
interrupt flag bit gets set) to the time that the instruction at address 0004h
starts execution (when that interrupt is enabled). For synchronous
interrupts (typically internal), the latency is 3TCY. For asynchronous
interrupts (typically external), such as the INT or Port RB Change Interrupt,
the interrupt latency will be 3 - 3.75TCY (instruction cycles). The exact
latency depends upon when the interrupt event occurs (Figure 8-2) in
relation to the instruction cycle. The latency is the same for both one and
two cycle instructions.
INT and External Interrupts
The external interrupt on the INT pin is edge triggered: either rising if the
INTEDG bit (OPTION<6>) is set, or falling, if the INTEDG bit is clear. When a
valid edge appears on the INT pin, the INTF flag bit (INTCON<1>) is set. This
interrupt can be enabled/disabled by setting/clearing the INTE enable bit
(INTCON<4>). The INTF bit must be cleared in software in the interrupt
service routine before re-enabling this interrupt. The INT interrupt can
wake-up the processor from SLEEP, if the INTE bit was set prior to going
into SLEEP. The status of the GIE bit decides whether or not the processor
branches to the interrupt vector following wake-up. See the “Watchdog
Timer and Sleep Mode” section for details on SLEEP and for timing of
wake-up from SLEEP through INT interrupt.
10
www.rejinpaul.com
Note: Any interrupts caused by external signals (such as timers, capture,

change on port) will have similar timing.
Context Saving During Interrupts
During an interrupt, only the return PC value is saved on the stack.

Typically, users may wish to save key registers during an interrupt e.g. W
register and STATUS register. This has to be implemented in software. The
action of saving information is commonly referred to as “PUSHing,” while the
action of restoring the information before the return is commonly referred to
as “POPing.” These (PUSH, POP) are not instruction mnemonics, but are
conceptual actions. This action can be implemented by a sequence of
instructions. For ease of code transportability, these code segments can be
made into MACROs (see MPASM Assembler User’s Guide for details on
creating macros).
Interrupt Constrain:
When an interrupt source sends an interrupt signal to CPU, it is saying that

it is ready to be serviced. It is also implying that this servicing needs to
occur in timely manner or else a system malfunction will occur. For
11
www.rejinpaul.com
example a PIC chip controlling the operation of a device may use it UART
serial port as an optional port from a personal computer so the PC can
control an arrray of such devices. Alternatively that device may be used in
sand alone mode, with nothing connected to its UART serial port.Give these
two modes of operation , the PIC must be able to rspond to each chracter
recives via the UART and its two-byte FIFO before another two character
arive to overrun the first character. On the other hand, the PIC cannot
dedicate itself solely to waiting for characters to arrive via UART interrupts
because it has ongoing control to do.
The problem posed by UART interrupts is illustrate in the below figure5.1,

show the CPU executing the mainline program (and its subroutine) until a
character is recived by UART. At that point CPU digresses from its execution
of mainline code to execute the UART’s interrupt service routine. Then the
CPU returns to the execution of mainline code. With no other interrupt
occuring, the URAT is serviced as soon as a characterhas been recived and
an interrrupt signal sent to CPU . if the serial data is being transferred at
9600Bd, then these interrupts occur roughly a milisecound apart ,
representedby TPURAT in the below figure 5.1 an deach one is handle
immediately by the CPU
12
www.rejinpaul.com
With other interrupt sources enable, the story changes, as illustrate in the
secound figure now the UARTcan recive a character and send an interrupt
signal to the CPU, only to have its service postponed temporarily while the
CPU finishes servicing another interrupt. As can be seen in the figure , an
error may be occasionally occur if care is not taken to keep interrupt service
routines short
For the more general case with multiple interrupt sources, the worst case
sequencing of interrupts must be examined to determine whether a problem
will ever arise. Each interrupt source I, must be characterized by two
parameters
1. The minimum time intervel between interrupts from source I, denoted

by TP
2. The maximum time it takesthe CPU to execute the interrupt sources

handeler subroutine and its call from Intservice denoted by Ti
The minimum time interval between interrupts for a given interrupt source
is determine by the application for example in the case of the 9600Bd UART,
each 8-bit character is farmed between a start bit and a stop bit with a bit
time of 1/9600 secound, each 10-bit frame can arive 10/9600 secound
apart
TPURAT = 10/9600 Secound = 10,000,000/9600 = 1042μs
INTservice Interrupt Service Routine:
When ever an interrupt occurs the CPU automatically pushed the return
address in the program counter onto the stack and clear the GIE(global
interrupt enable) bit, disabling further interrupts. No other register or W are
automatically set aside. Consequently the first job of Intservice is to set
aside the content of W and the SATAUS. Then they can be restored at the
end of the interrupt service routine to exactly the same state they were in
when the interrupt occurred, as required for the proper execution of the
mainline code
This setting aside of W and the SATAUS is illustrated in the first three
instruction of below figure. The assumption is made that the mainline
program will not be switched for direct access of Bank 1 register of RAM
variables at the moment that the interrupts occurs. Once the interrupts
have been enable Bank 1 register and RAM should only be accessed by
indirect addressing.
13
www.rejinpaul.com
Fig: IntService interrupt service routine
The three instructions for setting aside W and the SATAUS use
Swapf SATATUS, W
To move the content of SATAUS to W instead of the expected instruction
Movf SATATUS,W
Note that swapf instruction doesnot ever affect the Z bit in the SATATUS
register when it makes this move (even though it copies the upper 4 bits of
SATATUS to the lower 4 bits of W and the lower 4 bits of SATATUS to the
upper 4 bits of W)in contrast the movf instruction corrupt the Z bit restoring
SATATUS and W again the instruction
Swapf W_TEMP,W
Copies W_TEMP to W without affecting the Z bit. It is preceded by
Swapf W_TEMP,F
14
www.rejinpaul.com
Which swaps the two halves of W_TEMP so that the following swapf
instruction will swap them again, ending up with every bit of W just where it
was when the interrupt occurred.
The central code of intservice is a sequence of btfsc, call instruction pair.

Each pair test the flag of each enable interrupt source. If the fklag is set, the
source’s interrupt service routine is called that provides the desired
response and clears the flag. If a tested flag is not set, the call is skipped .
this sequence is called polling routine, and quickely get the CPU to the
service routine for the source that requested service
Loop Time Subroutine:
The loop time subroutine is called from the mainline loop,in the case of LED
blink program actually the loop time subroutine to work correctly,the worst
case execution of the remainder of the code in the mainline loop plus the
worst case execution time for all the interrupt service routine that should
request the service. As a consequence successive execution of some task
may occur less than the predefine time like in the Les blinking program. On
the other hand even if this mainline overrun condition dose occur the long
range timing provided by the loop time subroutine will still be accurate
aslong as no counts of scalar are ever lost.
Example:
15
www.rejinpaul.com
Looptime
Btfsc SCLAER ,7
Goto looptime
Movlw 5
Addwf SCALER,F
return
External interrupts:
The PIC microcontroller has one pin, RBO/INT that serves as its primary
external interrupt input. This pin is bit 0 of PORTB before initializing the
interrupt circuitry PORTB itself should be initialized. The bit of bank 1
register TRISB set up the corresponding bits of PORTB as either inputs or
outputs. All of the pins that are setup as input pinas optional a weak pullup
resistor is added by clearing the NOT_RBPU bit of OPTION_REG as show in
the figure 6.1b this provides a useful input for a pushbutton switch or for a
array of keyswitches such as keypad show in 6.2a the internal pull-ups of
the circuit in figure 6.2b hold each input pin high until any of the key
switches are pressed, if any of the keyswitch are pressed then the
corresponding column driver drive the output to low.
16
www.rejinpaul.com
For example bit 7 of PORTB will be driven low if the key switch labeled “1”
is pressed and if the bit 3 output from PORTB is driven low otherwise the
internal pullup resistor pulls the bit 7 input high
Figure 6.2b also illustrate the use of bit 0 of PORTB as an interrupt input
that can be used independently of the manner in which the other pins of
PORTB are used. the setup for this independent interrupt input show in the
figure 6.3. the presence or absence of the weak pullup resistor on allPORTB
input is irrelevant to this bit0 input since the device that derives this
interrupt pin will override the weak pullup. The INTEDG bit of
OPTION_REG permits us to setup this input to generate an interrupt on
either a rising edge or falling edge. In addition , when used as an interrupt
input, this PB0/INT pin is automatically configured as a Schmitt-trigger
input . Triggering on the input edge regardless of its rise(or fall) time
17
www.rejinpaul.com
The INTCON register must be initialized with a one in its INE(RB0/INT

interrupt enable ) bit as well as in its GIE(global interrupt enable) bit . when
the interrupt occure there is no need to read PORTB rather ,just poll the
INTF (Interrupt flag) bit in INTCON to determine if an edge occurring on this
pin is the source of the interrupt if so , then clear the flag with
bcf INTCON,INTF
then service the interrupt and go back to INtservice’s polling routine to look
for any other pending interrupts
18
www.rejinpaul.com
OVERVIEW OF TIMER MODULES
The PIC16C72, PIC16C73/73A, PIC16C74/74A, PIC16C76/77 each have

three timer modules. Each module can generate an interrupt to indicate that
an event has occurred (i.e. timer overflow). Each of these modules is
explained in full detail in the following sections.
TIMER MODULES:
There are three completely independent Timers available in PIC 16F8XX

Microcontrollers. They are
 Timer 0
 Timer1
19
www.rejinpaul.com
 Timer2
Timer 0:
The Timer 0 module is a simple 8-bit overflow counter. The clock

source can be either the internal system clock (Fosc/4) or an external clock.
When the clock source is an external clock, the Timer0 module can be
selected to increment on either the rising or falling edge.
The Timer 0 module also has a programmable prescaler option. This

prescaler can be assigned to either the Timer0 module or the Watchdog
Timer. Bit PSA assigns the prescalerand bits PS2:PSO determine the
prescaler value. TMR0 can increment at the following rates: 1:1 when the
prescaler is assigned to Watchdog Timer, 1:2, 1:4, 1:8, 1:16, 1:32, 1:64,
1:128 and 1:256.
Synchronization of the external clock occurs after the prescaler. When

the prescaler is used, the external clock frequency may be higher then the
device’s frequency. The maximum frequency is 50 MHz, given the high and
low time requirements of the clock.
Timer 1
Timer1 is the most versatile and can be used to monitor the time
between signal transition occuringon an input pin or control the precise
time of transitions on an output pin. It is a 16-bit timer/counter. The clock
source can be either the internal system clock (Fosc/4), an external clock, or
an external crystal. Timer1 can operate as either a timer or a counter. When
operating as a counter (external clock source), the counter can either
operate synchronized to the device or asynchronously to the device.
Asynchronous operation allows Timer1 to operate during sleep, which is
useful for applications that require a real-time clock as well as the power
savings of SLEEP mode.
Timer 1 also has a prescaler option, which allows TMR1 to increment

at the following rates: 1:1, 1:2, 1:4 and 1:8 TMR1 can be used in
conjunction with the Capture/Compare/PWM module. When used with a
CCP module, Timer1 is the time-base for 16-bit capture or 16-bit compare
and must be synchronized to the device.
Timer 2
Timer 2 is an 8-bit timer with a programmable prescaler and a

programmable postscaler, as well as an 8-bit Period Register (PR2). Timer 2
can be used with the CCP module (in PWM mode) as well as the Baud Rate
20
www.rejinpaul.com
Generator for the Synchronous Serial Port (SSP). The prescaler option allows
Timer2 to increment at the following rates: 1:1, 1:4 and 1:16.
The post scaler allows TMR2 register to match the period register
(PR2) a programmable number of times before generating an interrupt. The
postscaler can be programmed from 1:1 to 1:16 (inclusive).
2.2 Overview of Timer Modules :
PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0
and Timer-2 are 8-bit timers. Timer-1 is a 16-bit timer. Each timer module
can generate an interrupt on timer overflow.
Timer-0 Overview:.
The timer-0 module is a simple 8-bit counter TMR0. Which can be written
to or read from. The counter sets a flag,T0IF, when it overflows and can
causes an interrupt at that time if that interrupt source has been
enable(T0IF=1) Timer0 can be assigned an 8 bit prescaler that can divide
the counter’s input by 2,4,8,16,….256 writing to TMR0 resets the prescaler
assigned to it.
Timer0 or prescaler cab be connected to either of two input sources
1. OSC/4, the PIC’s internal clock
2. RA4/T0CK1, the input connected to bit 4of PORTA
If the prescaler is bypassed and the internal clock used, the circuit is show
in figure6.5 results. The two cycles delay is a result of the need to
synchronize the external clock, TCK1. The internal clock. is write to TMR0
will reset the delay circuit, causing the two cycles that follow the write not to
be counte. Because of these two cycle delay if 256-10 = 246is written to the
TMR0, the T0IF flag will bw set in 12 cycles, no the 10 cycles expected
The use of the prescaler is illustrate in the figure6.6 when OPTION_REG is

initilized as show in the figure timer0 will overflow every 2.048ms (given
OSC=4MHz).
If using INTERNAL crystal as clock, the division is performed as follow:
21
www.rejinpaul.com
Fout– The output frequency after the division.

Tout– The Cycle Time after the division.
4- The division of the original clock (4 MHz) by 4, when using internal
crystal as clock (and not external oscillator).
Count- A numeric value to be placed to obtain the desired output frequency
- Fout.
(256 - TMR0)- The number of times in the timer will count based on the
register TMR0.
If using EXTERNAL clock source (oscillator), the division is performed

as follow:
OPTION Register Configuration :
Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock
source. The following OPTION register configuration is for clock source =
fosc /4 and no Watchdog timer.
22
www.rejinpaul.com
Fig: Timer - 0 operation
Timer - 1 Module
Timer 1 module is a 16-bit timer/counter

consisting of two 8-bit registers (TMR1H
and TMR1L) which are readable and writable. The TMR1 register pair
(TMR1H:TMR1L) increments from 0000H to FFFFH and rolls over to 0000H.
The TMR1 interrupt, if enabled, is generated on overflow, which sets the
interrupt flag bit TMR1IF (bit-0 of PIR1 register). This interrupt can be
enabled/disabled by setting/clearing TMR1 interrupt enable bit TMR1IE
(bit-0 of the PIE1 register). The operating and control modes of Timer1 are
dete rmined by the special purpose register T1CON. Various bits of T1CON
register are given as follows:-
TMR1 ON : Timer1 ON bit

0 = stops Timer 1; 1 = Enables Timer 1
TMR1CS : Timer 1 Clock source Select Bit

1 = External Clock (RCO/T1OSO/T1CKI)
0 = Inte2rnal Clock ( )
: Timer 1 External Clock Input Synchronization Bit

(Valid if TMR1CS = 1)
23
www.rejinpaul.com
1 - Do not synchronize
0 – Synchronize
T1OSCEN: Oscillator enable control bit

1 = Oscillator is enabled
0 = Oscillator is shut off
Timer 1 Input Clock Prescaler
Select Bit Prescaler

T1CKPS1 T1CKPS0 Value
1 1 1:8
1 0 1:4
0 1 1:2
0 0 1:1
Timer 1 can operate in one of the two modes
24
www.rejinpaul.com
 As a timer (TMR1CS = 0). In the timer mode, Timer 1 increments in

every instruction cycle. The timer 1 clock source is . Since the
internal clock is selected, the timer is always synchronized and there
is no further need of synchronization.
 As a counter (TMR1CS = 1). In the counter mode, external clock input

from the pin RCO/T1CKI is selected.
Reading and writing Timer 1
Reading TMR1H and TMR1L from Timer 1, when it is running from an

external clock source, have to be done with care. Reading TMR1H or TMR1L
for independent 8 - bit values does not pose any problem. When the 16-bit
value of the Timer is required, the high byte (TMR1H) is read first followed
by the low byte (THR1lL). It should be ensured that TMR1L does not
overflow (that is goes from FFH to 00H) since THR1H was read. This
condition is verified by reading TMR1H once again and comparing with
previous value of TMR1H.
Calculating Count, Fout, and Timer1 values
If using INTERNAL crystal as clock, the division is performed as follow:
Fout– The output frequency after the division.

Tout – The Cycle Time after the division.
4- The division of the original clock (4 MHz) by 4, when using internal
crystal as clock (and not external oscillator).
Count - A numeric value to be placed to obtain the desired output frequency
- Fout.
(65 536 - TMR1)- The number of times in the timer will count based on the
register TMR0.
If using EXTERNAL clock source (oscillator), the division is performed as

follow:
25
www.rejinpaul.com
Timer 1/CCP Programmable Period Scaler
Timer 1 and one of the CCP module can be used as a scaler. This takes
advantage of thr CCP module’s tiggers special events mode. When the
comparetakes place between TMR1 and the compare register (CCPR1 or
CCPR2). TMR1 is reset to zero giving a period of one greater than the value
loaded into CCPR1 (or CCPR2) the register ans circuit are shown in the
figure 6.11 using CCP1 module
Example:
Reading 16 bit of free running timer 1
movf TMR1H; reaf high byte
movwf TMPH ;store in TMPH
movf TMRL; readlow byte
movwf TMPL; store in TMPL
movf TMR1H,W; read hye byte in W
subwf TMPH ,W; subract1st read with 2nd read

26
www.rejinpaul.com
btfsc STATUS,Z; and check for equality
goto next;
: if high bytes differ, then there is an overflow
:read the high byte again followed by the low byte
movf TMR1H; reaf high byte
movwf TMPH
movf TMR1L,W; read low byte in W
movwf TMPL
net:nop
Timer 1 External Event Counter
Timer 1 like timer0, can be used to count external events. When used with
one of the CCP modules, it can generate a CCP interrupt after every Nth
input edge , for any integer value of N upto 65536 with timer1 prescaler,
this can be extended to every multiple of 8 up to 524288.
This basic counter is show in the figure 6.12 this is all that is need to count
N events with T1CON setr to H’02 the prescaler is bypassed and the input
from the pin0 of PORTC, the external clock input to timer1 (T1CK1) is
blocked by TMR1ON = 0 to count N input rising edges TMR1 is preset to
65536-N, the TMR1IF flag in the P1R! register is cleared , and the TMR1IE
interrupt enable bit in the PIE1 register is set . finally counting is begun by
setting TMR1ON bit in the T1CON register ,after N raising edges on the
input pin RC0/T1CK1, Timer 1 will generate an interrupt, permitting the
desired action to be taken at that time.
The synchronizer in the figure 6.12 synchronizes the input to the internal
clock. It is an optional feature, control by the NOT_T1SYNC (bit 2 ) of the
T1CON register. Synchronizing the external input clock. It is an optional
feature, controlled by thr NOT_T1SYNC bit of T1CON register.
Synchronizing the external input to the internal clock permits TMR1 to be
read from and write to. Even as the counter is counting , synchronization is
27
www.rejinpaul.com
also vital to proper operation when timer 1 is used with one of the CCP
modules while counting external events. The state of the NOT_T1SYNC bit is
ignored, and the synchronizer bypassed, when TMR1CS=0 select the
internal clock OSC/4
Timer1 and Sleep Mode:
One option that PIC chips make available to uses is the ability to stop the
internal clock(OSC/4) reducing power consumption significantly, and yet
have an accurate internal time base. Timer1 includes the pins and the
oscillator circuit to allow 32768 Hz crystal to save as its external clock
source. Since the synchronizer of figure6.12 will not produce output pluses
with the OSC/$ internal clock stopped, the synchronizer must be bypassed
TMR1 will overflow at 2-secound , 4-secound, 8-secpund, or 16-secound
intervals, depending on which prescaler value is used. The circuit is show in
the figure6.13
Each time tahat a TMR1 overflow occurs, the CPU initiates the startup of
the internal clock which may take as long as 1000 internal clock cycle
before the next instruction executed. If GIE bit had been cleared before the
Sleep instruction had been executed, then about a millisecound after TMR1
overflows, the CPU will countine execution with the code that follows the
Sleep instruction . if GIE=1 then about a millisecound after TMR1
overflows, the CPU will execute the one instruction that follows the sleep
instruction and then vector to the interrupt service routine at address
H’004’
28
www.rejinpaul.com
Timer 2 Overview
 Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can

be used as the PWM time base for PWM mode of capture compare
PWM (CCP) modules. The TMR2 register is readable and writable and
is cleared on device reset.
 The input clock ( ) has a pre-scaler option of 1:1, 1:4 or 1:16

which is selected by bit 0 and bit 1 of T2CON register respectively.
 The Timer 2 module has an 8bit period register (PR2). Timer-2

increments from 00H until it is equal to PR2 and then resets to 00H
on the next clock cycle. PR2 is a readable and writable register. PR2 is
initailised to FFH on reset.
 The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16)
to generate a TMR2 interrupt by setting TMR2IF.
Timer Clock Source
The Timer2 module has one source of input clock, the device clock
(FOSC/4). A prescale option of 1:1, 1:4 or 1:16 is software selected by
control bits T2CKPS1:T2CKPS0 (T2CON<1:0>).
Timer (TMR2) and Period (PR2) Registers
29
www.rejinpaul.com
The TMR2 register is readable and writable, and is cleared on all device
resets. Timer2 increments from 00h until it matches PR2 and then resets
to 00h on the next increment cycle. PR2 is a readable and writable
register. TMR2 is cleared when a WDT, POR, MCLR, or a BOR reset
occurs, while the PR2 register is set.
Timer2 can be shut off (disabled from incrementing) by clearing the

TMR2ON control bit(T2CON<2>). This minimizes the power consumption
of the module.
TMR2 Match Output
The match output of TMR2 goes to two sources:
1. Timer2 Postscaler
2. SSP Clock Input (Synchronous Serial Port module)
There are four bits which select the postscaler. This allows the postscaler
a 1:1 to 1:16 scaling(inclusive). After the postscaler overflows, the TMR2
interrupt flag bit (TMR2IF) is set to indicate the Timer2 overflow. This is
useful in reducing the software overhead of the Timer2 interrupt service
routine, since it will only execute once every postscaler # of matches.
The match output of TMR2 is also routed to the Synchronous Serial Port
module, which may software select this as the clock source for the shift
clock
Clearing the Timer2 Prescaler and Postscaler
The prescaler and postscaler counters are cleared when any of the
following occurs:
• a write to the TMR2 register
• a write to the T2CON register
• any device reset (Power-on Reset, MCLR reset, Watchdog Timer Reset,
Brown-out Reset,or Parity Error Reset)
Sleep Operation
During sleep, TMR2 will not increment. The prescaler will retain the last
prescale count, ready for operation to resume after the device wakes from
sleep.
30
www.rejinpaul.com
T2CON: TIMER2 CONTROL REGISTER (ADDRESS 12h)
Capture / Compare /PWM (CCP) Modules:
PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit
register (two 8-bit registers) and can operate in one of the three modes, viz.,
16-bit capture, 16-bit compare, or up to 10-bit Pulse Width Modulation
(PWM). The details of the two modules (CCP1 and CCp2) are given as
follows.
CCP1 Module:
31
www.rejinpaul.com
CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and
CCPR1H (high byte). The CCP1CON register controls the operation of CCP1
Module.
CCP2 Module:
CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and
CCPR2H (high byte). The CCP1CON register controls the operation of CCP2
Module.
Both CCP1 and CCP2 modules are identical in operation with the exception
of the operation of special event trigger.
The following table shows the timer resources for the CCP Mode.
CCP1CON Register (Address 17H )
CCP2CON Register is exactly similar to CCP1CON register. CCP2CON

Register address is 1DH. CCP1CON controls CCP module1 where as
CCP2CON controls CCP Module2.
Bit 5-4:
CCP1X CCP1Y: PWM least significant bits. These bits are of no use in
Capture mode. In PWM Mode, these bits are the two Lsbs of the PWM duty
cycle. The eight Msbs are found in CCPR1L. Thus the PWM mode operates
in 10-bit mode.
Bit 3-0:
CCP1M3:CCP1MO (CCP1 Mode select bits)
32
www.rejinpaul.com
0000=Capture/Compare/PWM Mode off
0100=Capture mode, every falling edge
0101=Capture mode, every rising edge
0110=Capture mode, every 4 th rising edge
0111=Capture mode, every 16 th rising edge
1000=Compare mode, set output on match (CCP1IF bit is set)
1001=Compare mode, clear output on match (CCP1IF bit is set)
1010=Compare mode, generate software interrupt on match (CCP1IF bit is

set, CCP1 pin unaffected)
1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets

Tmr1; CCP2 resets TMR1 and starts A/D conversion if A/D module is
Enabled)
11XX=PWM mode.
Capture Mode (CCP1):
Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1L

register pair in response to an event occurring on RC2/CCP1 pin. Capture
Mode for CCP2 is exactly similar to that of CCP1.
An event on RC2/CCP1 pin is defined as follows:
 Every falling edge
 Every rising edge.
 Every 4 th rising edge.
 Every 16 th rising edge.
As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register.
The combination of Timer1 and either the CCP1 or the CCP2 module
permits a PIC chip tot be used to determine the time of occurance of an
input edge. Timer1 can be used with its prescaler to let its 16-bit count
range measure longer intervals directly. How ever the finiest resolution in
the measurement result will occure if the prescaler is bypassed. Thus with
OSC=4MHz and bypassing the prescaler, the time of occurance of an input
edge will be ascertained to within 1µs
33
www.rejinpaul.com
Figure 6.9 shows the registers and circuity involved with the use of CCP1
module. The time between two input edges is determine by making two
captures and subtracting the one time from the other.
Schematic diagram for capture mode of operation
34
www.rejinpaul.com
Required condition for capture mode:
1. RC2/CCP1 pin should be configured as an input by setting TRISC

(bit 2).
2. Timer 1 should be operated from the internal clock (fosc/4), i.e.,

timer mode or in synchronized counter mode.
Compare Mode (CCP1)
Compare mode for CCP2 is similar to that of CCP1, except that in special
event trigger mode, CCP1 resets TMR1 only, whereas CCP2 resets TMR1
and starts A/D conversion if A/D module is enabled.
In compare mode, the 16-bit CCPR1 register value is compared against

TMR1 register pair (TMR1H and TMR1L) value. When a match occurs, the
RC2/CCP1 pin is driven high or driven low or remains unchanged as
decided by CCP1CON<3:0> bits.
Required conditions for compare mode
1. RC2/CCP1 pin must be configured as an output by clearing

TRISC<2> bit.
2. Timer-1 should be operated in timer mode (i.e., internal clock

source of fosc/4) or in synchronized counter mode.
35
www.rejinpaul.com
Timer1 is 16 bit counter that together with a CCP module can derive a pin
high or low at a precisely controlled time,independent of what the CPU is
doing at that time. Of the seven PIC family members considered all have two
CCP modules except PIC16C62A, PIC16C64A, and the PIC16C72, ehich
has only one. Consequently, they can all control the RC1/CCP2 pin. These
pin disgnation indicate the alternative role played by these pins as general
purpose I/O pins of PORTC.
While timer1 includes a prescaler to divide the internal clock by 1,2,4,or 8,

the choice of divide by one gives the finest resolution in setting the time of
an output edge. That is with OSC = 4 MHz, the timing of the edges of a pulse
can be controlled with a resolution of 1µs. the initialization for the CCP1
compare mode is show in the figure 6.7
For the PIC chips having two CCP modules, if both modules are being used
for either a compare funcation or for a capture funcation, they will share
TMR1. In this TMR1 should never be changed by writing to it. How ever if
TMR1 is being in one role only, its use is simplified by being able to stop its
clocking by clearing the TMR1ON bit in the T1CON register, clearing TMR1
setting up CCPR1, and then starting the clocking of TMR1 again
In software interrupt mode, CCP1IF bit is set but CCP1 pin in unaffected.
As shown in the figure, in special event trigger mode, both CCP1 and CCP2
initiates an A/D conversion.PWM mode (CCP1)Both CCP1 and CCP2 have
similar operation in PWM mode. Here we will discuss PWM with respect to
CCP1.
36
www.rejinpaul.com
Pulse width Modulation:

In PWM mode, the CCP1 pin produces up to a 10-bit resolution Pulse
Width Modulation (PWM) output. RC2/CCP1 pin should be configured in
the output mode by clearing TRISC<2> bit.
A pulse width modulation(PWM) output from a PIC chip is show in the

figure6.14a. for many application, the shorter the period the better.for
example in figure 6.15a, is a variable duty cycle of PWM output to generate
a dc voltage between oV and 5V by using low pass filter to form the
waveform average value. The shorter the PWM period, the faster the average
value can change. If the changes in the PWM signal are characterized by a
maximum frequency fmaxsignal as show in the figure 6.14b
37
www.rejinpaul.com
Fmaxsignal <<Fcutofffilter << FPWM

That is the filter’s cutoff frequency needs to be below the frequency of yhe
PWM waveform, Fpwm to remove its fundamental component and its
harmonics at 3 Fpwm, 5 Fpwm, 7 Fpwm etc. And to leave just the relatively
slowly varying DC component. The shorter the period of the PWM waveform
the easier it is to accommodate the signal frequencies with a filter that
passes them unharmedand that essentially removes the effect of pulse width
modulation.
The heart of the PIC’s PWM circuit is a 10bit counter formed from timer2’s
8-bit TMR2 counter for its upper bits and whatever 2 bit counter drives it.
As show in the figure 6.16a, these latter 2 bits depend on the prescaler
setting. If the prescaler is bypassed(ie set to divide by 1) as in the figure
6.16b, then the PWM circuity actually reaches into the 2 bit Q counter
which divides the crystal clock frequency by four to obtain the internal clock
frequency. This is the choice that leads to shortest period of the PWM
waveform.
The period of the waveform is controlled by the circuit of figure 6.17. this
figure shows that the period is controlled by two things: (i) the value
initialized for the Timer2 prescaler and (ii) the value initialized by PR2.
In addition to controlling the PWM frequency the value loaded to PR2
controls the duty cycle resoluation. Thus the circuity in figure 6.17a turns
on the PWM output , other circuitry will turn it off at any desired count of
the 10-bit counter in this figure. Consequently ,if PR2 is initialized to 63, the
full 10-bit counter will count with a scale of 64*4=256, or 8 bit resoluation
For OSC=4MHz, some choices of duty cycle resoluation and prescaler

divider lead to the PWM frequency value show in the figure 6.18.if Timer2 is
also to control the looptime, then the PWM circuity will have almost full 10
bit resoluation. The divide-by-four prescaler choice sets the PWM frequency
to 1KHz. Actually for OSC=4MHz, the stepup of Timer2 can achive the
same looptime performancewith divided by one prescaler and a divided by
eight postscaler this change quadruples the PWM frequency to 4KHz
The circuitry that controls the ontime of the PWM waveform is contained
entirely in the CCP circuitry. For the RC2/CCP1 output, this CCP1 circuitry
is show in the figure 6.19a. this circuit illustrates how the 10bit value is
formed that turns off the PWM output, thus controlling the duty cycle whose
value is given by figure 6.19b.
The upper 8 bits of the 10bits value arre loaded under program control into
CCPR1L.the PWM circuitry automatically transfers this value to CCPR1H as
38
www.rejinpaul.com
TMR2 is reset to start each PWM period. This double buffering of the value
that isactually used in the comparison is designed to help prevent the glitch
that would occure in CCPR1H were changed from H’50’ to H’40’. In this
event, the PWM output would not go low at all until the next period
The lower 2 bits of the 10bit value are loaded under program control into
bits 5 and 4 of CCP1CON. If a 10 bit valueis loaded into a 2 byte RAM
variable PWM (made upof PWMH and PWML) then the code will transfer it
to CCPR1L and CCP1CON appropriately to vary the output over the full
duty cycle range from zero to one.
39
www.rejinpaul.com
PWMupdate
Rrf PWMH,F ;rotate bit8
Rrf PWML,F ;into PWML[7]
Rrf PWMH,F ;rotate bit 0 into PWML[7]
Rrf PWML,F ;and bit 9 into PWML[7]
Rrf PWMH,F ;and bits 1,0 into PWMH[7:6]
;upper 8 bits are now in PWML
;lower 2 bits are in PWML[7:6]
Rrf PWMH,F ;move bits 1,0 to align with CCP1CON
Rrf PWMH,W ;and move to W
Xorwf CCP1CON,W ;toggle if CCP1X;CCP1Y differ
Andlw B’00110000’ ;force other bits to zero
Xorwf CCP1CON,F ;chane bits that differ
Movf PWML,W ;move upper 8 bit
Movwf CCPR1l
Return ;fourteen cycles
The schematic block diagram of CCP1 module in PWM mode is shown in the
figure.
40
www.rejinpaul.com
It can be noted that PR2 (Period Register, 8 bit) decides the PWM period
where CCPR1L (8-bits) and CCP1CON <5:4> (2-bits) decide the PWM duty
cycle. When TMR2 equals PR2, the SR latch is set and RC2/CCP1 pin is
pulled high. In the same time, TMR2 is cleared and the duty cycle value
available in CCPR1L is latched to CCPR1H. CCPR1H, CCP1CON <5:4>
decide the duty cycle and when this 10-bit equals the TMR2+2 prescaler or
Q-bits, the SR latch is set and RC2/CCP1 pin is driven low.
A PWM output as shown has a time period. The time for which the output
stays high is called duty cycle.
PWM Period
The PWM period is specified by writing to PR2 register. The PWM period can
be calculated using the following formula:
41
www.rejinpaul.com
PWM period = [( PR 2) + 1] × 4 × T osc × (TMR2 prescale value)

PWM frequency = 1/ PWM period
When TMR2 is equal to PR2, the following events occur on the next
increment cycle.
 TMR2 is cleared
 the CCP1 pin is set (if PWM duty cycle is 0
 The PWM duty cycle is latched from CCPR1L into CCPR1H
 PWM duty cycle
The PWM duty cycle is specified by writing to the CCPR1L register and to
CCP1CON < 5 : 4 >bits. Up to 10-bit resolution is available where CCPR1L
contains the eight MSBs and CCP1CON < 5 : 4 > contains the two LSB's.
The 10-bit value is represented by CCPR1L : CCP1CON < 5 : 4 >.
The PWM duty cycle is given by

PWM duty cycle = (CCPR1L : CCP1CON < 5 : 4 > ). T osc . (TMR2 prescale
value) To understand the 10-bit counter configuration from Timer-2, let us
first see the counting mechanism of Timer-2, as shown in Fig
42
www.rejinpaul.com
Although CCPR1L and CCP1CON < 5 : 4 > can be written to at anytime, the
duty cycle value is not latched into CCPR1H until a match between PR2 and
TMR2 occurs. In PWM mode, CCPR1H is a read-only register.
The CCPR1H register and a 2-bit internal latch are used to double buffer the
PWM duty cycle. This double buffering is essential for glitch less PWM
operation. When the CCPR1H and 2-bit latch match TMR2 concatenated
with an internal 2-bit Q clock or 2-bits of prescaler, the CCP1 pin is cleared.
Maximum PWM resolution (bits) for a given PWM frequency can be
calculated as
Application of PWM using CCP module:
The DC motor drive circuit use a number expressed in sign-plus-magnitude

for control purpose. The sign of the number, emited on bit 7 of PORTD,
determines the direction of current through the motor . when bit 7 is high
and the PWM output is turned on , the driver on the left is switched on to
Vmotor while the driver on the right is switched on to 0 volts and current
flows from left to right through the motor. When bit 7 is low and the PWM
output is turned on just the opposite is true and current flows from right to
left through motor. When the PWM output is off, the current in the dc motor
coasts through the diodes built into half H drivers. By controlling the duty
cycle of the PWM output , the average current in the dc motor is controlled.
Application of PWM to drive a Load:
43
www.rejinpaul.com
For other application such filtering is unnecessary figure 6.15b show a

driver circuit that can be used to control the temperature of aheater winding
or the intensity of a light source. The tiny power MOSFET is an almost ideal
driver. Its high impedance input is easy to derive and has an unusually low
input threshold of 3V. that is for an input voltage about 4V. the drain-
source equivqlent circuit is a very low resistance. For an input voltage 0V,
the drain source resistance is in the meghaohms.
Front-Panel I/O :
Design of instruments and other devices that requires intractions often an

LCD alphanumeric display plus either keyswitches or a rotary pulse
generator(RPG) in their design of front panel. The display serves to display
measurements , or other outputs, results. The also combines with the
keyswitchs or the RPG for the entry of stepup parameters. For example, so
the user can see successive digit entires combine and form the desired
amplitude. An RPG offers the desirable feature of being able to increment or
decriment the value of sttepup parameter being displayed on the LCD
Soft Keys:
A multiple line LCD display presents the opportunity, show in the figure 8.1
of being used with miniature pushbutton switches that are aligned to the
right of each line of the display. The label for each switch can be displayed,
and change at the right edge of row corresponding to that switch.
The circuit in the figure 8.2 illustrate how the four soft keys figure 8.1 can
be treated in the same manner as the 12keys of keypad. Infact , keyswitchs
are generally grouped into array such as this whether or not they are
physically grouped together in a keypad . figure 8.2 shows a pin from a
seprate port (bit 7 of PORTD) being used to derive the coloum of softkeys. If
bit 0 of PORTB is not used as an interrupt input. Then it actually makes
sense to use that pin to drive the column of softkeys.
44
www.rejinpaul.com
45
www.rejinpaul.com
State machines and keyswitches:
Keyswitches are not changed very fast, they can be checked once each time
around the mainline loop in a keySwitch subroutine. Recall that a looptime
of 10ms was selected because the maximum keybounce time of most of the
mechanical keyswitches is less than 10ms. Consequently , if keyswitch
detects that a key is newly pressed, it can be assured that the next time is
called, 10ms later, any erratic bouncing of the key contacts will have settled
out, with the contacts firmly closed.
The press and relese of a keyswitch occurs over an interval of many tens of
millisecounds. For example, if a keyswitch is pressed and released at the
relatively fast rate of four timesa second. The switch may be closed for 12
looptimes, open for 12 looptimes, closed for 12 looptimes, etc. the
keyswitch subroutine will use a state variable call KEYSTATE to keep track,
from one call to the next , of the sequencing of the following task
1. Debounce the keyswitch

2. Determined which key is pressed
3. Take appropriate action once for that press of the key
4. Wait for the relese of that key
46
www.rejinpaul.com
A flow chart of the keyswitch subroutine algorithm is show in the figure 8.3
each time keyswitch is called, if no key has been pressed during the last
several calls, then KEYSTATE will equal zero. The job of the keyswitch
subroutine in this case is to determine whether any key us newly pressed
The keyswitch algorithm of figure 8.3 test the STATUS register Z bit upon
returning from the AnyKey subroutine if Z=1, a return from the keyswitch
subroutine occurs. On the other hand if Z=0, a key is newly pressed , so
KEYSTATE is incremented to H’01’ before returning from the subroutine
Ten milisecound later the keyswitch subroutine is reentered, this time

KEYSTATE = H’01’ if a key is press was detected lastime. By now any
keybounce has settled out. A scankey subroutine is called it returns with
Z=1 and a KEYCODE RAM variable loaded with a value that identifies the
pressed key. If for any reson it cound not identifiy the press key. It returns
with Z=0 in the satus register.
A table driven implementation of the scankey subroutine is listed in the

figure 8.4. it test the 16 keys in the order of their keycode value
0,1,2,3….15 for ach value, a corresponding table entry is taken from
Scankeys_table. The lower 4 bits of table entry are used to drive the column
of the selected key low and the other columns high. In this way the only
keys that can drive one of the 4 upper bits of PORTB low are the four keys
in the selected column. The scankeys subroutine matches what is read back
from the upper 4 bits of PORTB against the upper 4 bits of the table entry.
Ifa match does occur, the next key is checked. If a match does not occur for
any of the 16 keys, the subroutine returs with Z=0.
The 220Ω resistors in figure 8.2 are there to product the PIC,s output
drivers during the execution of scankeys if two key switchs in the same row
are pressed simultaneously. In this abnormal case, two output drivers will
be shorted together. A high output will be shorted to a low output during the
testing of half of the keys, the 220Ωresistors limit the current to less than
10mA when this happens.
Upon the return from the scankeys subroutine, the keyswitch subroutine
tests the STATUS register Z bit if Z=1 it increments KEYSTATE and
returns, prepard to act on the pressed key in 10ms. If Z=0 then somehow
scankeys failed to identify a pressed key. This might occur if , for example,
two keys in the same column are pressed simultaneously. In that case, there
will be no entry in scankey_table that matches what is read from PORTB,
however this failure occurs, KEYSTATE is cleared to zero, starting over
again in the hunt for pressed key
47
www.rejinpaul.com
When KeySwitch is called with KEYSTATE=H’02’, it increments KEYSTATE.

If it then does a instruction, the job of this KeyAction subroutine is to carry
out the proper response for the pressedkey. The return from KeyAction will
pop the return address and actually execute a return from KeySwitch(if
KeyAction was accessed with a goto instruction instead of call instruction).
The last two states of the KeySwitch algorithm require the pressed key to be
released during two successive passes around the mainline loop. This
overcomes any potential problem with keybounce time during the relese key
;;;;;;;;;;;;;ScanKeys subroutine;;;;;;;;;;;;;;;;;;
ScanKeys
clrf KEYCODE ;Startby checking the “0” key
ScanKeys_1
call ScanKeys_Table ;get next table entry
movwf TEMP
bcf PORTD,7 ;PD7<- bit 0 of table entry
btfsc TEMP,0
bsf PORTD,7
movwf PORTB ;PB3,2,1 fromtable entry
xorfwf PORTB,W ;compare upper 4 bitsor PORTB with table entry
andlw B’11110000’ ;z=1 if a match
btfsc STATUS,Z
goto ScanKeys_done
incf KEYCODE,F ;try next key
btfsc KEYCODE,4 ;stop with Z=0 when KEYCODE =B’XXX1XXXX’
goto ScanKeys_1
ScanKeys_done
Return
;;;;;;;; ScanKeys_Table subroutine;;;;;;;;;;;;;;;;;;;
ScanKeys_Table
Movf KEYCODE,W
Addwf PCL,F ;Change PC with PCLATH=H’00’
retlw B’11101011’ ; Test “0” Key
retlw B’11101011’ ; Test “*” Key
retlw B’11101011’ ; Test “#” Key
retlw B’11101011’ ; Test SK1
Figuer8.4 ScanKey subroutine and its table subroutine
Display Pus RPG use:
48
www.rejinpaul.com
A popular display plus input device combination is show in the figure 8.5.
the grayhill rotary pulse generator its feature is 24 detented position per
revoluation so it clicks from one position to the next, giving the feel of rotary
switch . it is also features an integral momentary action push button switch.
When used with an alphanumeric display such as show in the figure 8.5
the RPG’s knob can be pushed and released to cycle the display among an
instruments setup parameters as well as its measurements results.

Stopping at specific setup parameters (ex: voltage amplitude of function
generator) the RPG can then be rotate to increase or decreasethe value of
parameter. Detents support this funcation by helping a user to avoid
inadvertently changing setup parameters while cycling among them with
successive pushes of knob
The PIC interface for grayhill RPG show in the figure 8.6b. The momentary
action push button switch can be treated in the same way as one of the soft
keys figure 8.2. then it will be checked, debounce, and handled at regular
intervals of time.
The twoRPG output must be treated differently from keyswitches since trhe
information they convey is represented by two output levels and their
changes. They must also treated differently from RPG interface. Any one
RPG output as in PB0/INT intrreput input. In the case of grayhilll RPG,
action is needed whenever either output change, not just when one of the
output riseing edge. The two RPG output can be checked in an RPG
49
www.rejinpaul.com
subroutine, called from the mainline loop[. The two inputs are compared
with their values 10ms ago. The selected parameter be inceremented or
decremented if the input have change
Display of variable
string:
When entering setup paramenter with either a keypad or an RPG and when
displaying the results of an instrument measurement, it is necessary to
write a string of ASCII-code characters to display. Since the character vary,
they are taken from the RAM
The assignment of a string variable VSTRING, to RAM with microchip’s

MPASM assembler is illustrate in fig 8.7. assume that a display string has
the formate as show in figure 8.7c:
1. Cursor position code (Figuer 7.8)

2. ASCII string of characters to be displayed
3. Endof string designator,H’00’
50
www.rejinpaul.com
Given string having this formate, a DisplayV subroutine can be written to

send the first character to the LCD display as a command (RS=0) and
subsequent characters as displayable characters (RS=1) and to stop when
H’00’ is accessed. If the maximum number of character evere to be send to
the display from the string is 10, then 12 RAM location must be reserved for
the 10 displayable characters, the leading cursor position code, and the
trailing end of string designator. This reservation of RAM for a string called
VSTRING is illustrate in the figure 8.7a and 8.7b. the MPASM assembler
permits code writers to creat error message to warn of error producing
condition.
VSTRINGlenght equ 12 ; maximum number of characters in VSTRING

Fig 8.7 (a) Equates section of code
cblock Bank0RAM
.
.
.
VSTRING: VSTRINGlength
Marker
endc
if marker>H'80'
error “ RAM use exceeds bank 0”
endif
Fig 8.7 (b) Assigning a variable string to RAM
Address RAM Content comments
VSTRING H'E4' Cursor – positioning code
VSTRING+1 H'33'
VSTRING+2 H'31'
VSTRING+3 H'32' four digit number 3126
VSTRING+4 H'36'
VSTRING+5 H'00' End of string designator
Fig 8.7 (c)Display string example
51
www.rejinpaul.com
Figuer 7.9 : Display of Character and its ASCII Code
Display of Constant string:
Constant string arise in seven ways. The labels associated with softkeys
represent one application. The units(kHz) associate with the variable
represent another. In this section a DisplayC subroutine that makes use of
display string stored in program memory will be developed. Each byte of
eachstring is accessed via retlw instruction in the process of returning from
52
www.rejinpaul.com
DisplayC_table subroutine. In PIC ay of storing tables and string in program

memory and subsequently accessing them with a variable poiinter
The source code form of display string store in program memory can be
illustrate by the following example used to display the string
ROW4Coll
Being in the first character position of the fourth row of the LCD display
_ROW4Coll
retlw H’D4’ ;cursor postioning code (figure 7.8)
dt “ROW4Coll” ;Character to be displayed
retlw 0
He dt assembler directive provides a convenient way of creating ASCII string,

the MPASM assembler converts dt “ROW4Coll” to
retlw A’R’
retlw A’O’
retlw A’W’
retlw A’4’
retlw A’C’
retlw A’o’
retlw A’l’
retlw A’l’
where A’R’ represented the ASCII code for the letter R the label for this
sequence of retlw instruction
uses the initial underline character to serves as a remainderthat entities

such as this represented label for constant string display. In fact the
constant string itself can be used as its own label
Figuer 8.8 shows the DisplayC_Table subroutine to be locate in the first

256 address of the program area along with the other table subroutine. It
include every constant string display needed for an application, one right
after another. To get the specific display string , the DisplayC subroutine
needs to have passed to it the offsert from the instruction following addwf
PCL,F this instruction to start of the specific display string of intrest.
The offset in the code is loaded to W before DisplayC subroutine is called .
ehen the DisplayC_Table subroutine is called by the DisplayC subroutine,
it will add W to the address represented by CDS, loading the program
counter with the results. Consequently it will return with W loaded by select
retlw instruction there by passing back to DisplayC the first byte from the
selected display string
53
www.rejinpaul.com
54
www.rejinpaul.com
55
www.rejinpaul.com
UNIT III PERIPHERALS AND INTERFACING
I2C Bus for Peripherals Chip Access– Bus operation-Bus subroutines– Serial EEPROM—
Analog to Digital Converter–UART-Baud rate selection–Data handling circuit–Initialization –
LCD and keyboard Interfacing -ADC, DAC, and Sensor Interfacing.
Introduction
Microprocessor based system design involves interfacing of the processor
with one or more peripheral device for the purpose of communication with
various input and output devices connected to it. During the early days of the
microprocessor revolution, these techniques required complex hardware
consisting of Medium scale integration devices, making the design highly
complex and time consuming. So, the manufacturers (INTEL) have developed a
large number of general and special purpose peripheral devices most of them
being single chip circuits. They are also programmable devices. Hence, these
peripheral devices are found to be of tremendous use to a system designer.
Peripheral devices, can broadly be classified into two categories.
(a) General purpose peripherals and
(b) Special purpose peripherals (Dedicated function peripherals)
General purpose peripherals are devices that perform a task, but may be
used for interfacing a variety of I/O devices to the microprocessor.
 Simple I/O -- (Non-programmable)
 Programmable peripheral Interface (PPI) – (8255)
 Programmable Interrupt Controller – (8259)
 Programmable DMA Controller – (8237/8257)
 Programmable Communication Interface – (8251)
 Programmable Interval Timer – (8253/8254)
Special function peripherals or devices that may be used for interfacing a
microprocessor to a specific type of I/O device. These peripherals are more
complex and therefore, relatively more expensive than general purpose
peripherals. The special function peripherals (Dedicated function peripherals)
are
 Programmable CRT Controller
 Programmable Floppy Disc Controller
 Programmable Hard Disc Controller
 Programmable Keyboard and display interface.
The functioning of these devices varies depending on the type of I/O
device they are controlling.
I2C Bus for Peripherals:
In the early 1980's, NXP Semiconductors developed a simple bi-
directional 2-wire bus for efficient inter-IC control. This bus is called the Inter-
IC or I2C-bus. At present, NXP's IC range includes more than 150 CMOS and
bipolar I2C-bus compatible types of performing communication functions
between intelligent control devices (e.g. Microcontrollers), general-purpose
circuits (e.g. LCD drivers, remote I/O ports, memories) and application-
oriented circuits (e.g. Digital tuning and signal processing circuits for radio and

www.rejinpaul.com
video systems). All I2C-bus compatible devices incorporate an on-chip interface

which allows them to communicate directly with each other via the I2C-bus.
This design concept solves the many interfacing problems encountered when
designing digital control circuits Today, the I2C bus is used in many other
application fields than just audio and video equipment. The bus is generally
accepted in the industry as a de-facto standard. The I2C bus has been adopted
by several leading chip manufacturers like Xicor, ST Microelectronics, Infineon
Technologies, Intel, Texas Instruments, Maxim, Atmel, Analog Devices and
others.
I2C Bus Protocol:
The I2C bus physically consists of 2 active wires and a ground
connection. The active wires, called SDA and SCL, are both bi-directional. SDA
is the Serial Data line, and SCL is the Serial Clock line. Every device hooked up
to the bus has its own unique address, no matter whether it is an MCU, LCD
driver, memory, or ASIC. Each of these chips can act as a receiver and/or
transmitter, depending on the functionality. Obviously, an LCD driver is only a
receiver, while a memory or I/O chip can be both transmitter and receiver.
The I2C bus is a multi-master bus. This means that more than one IC capable
of initiating a data transfer can be connected to it. The I2C protocol
specification states that the IC that initiates a data transfer on the bus is
considered the Bus Master. Consequently, at that time, all the other ICs are
regarded to be Bus Slaves.
As bus masters are generally microcontrollers, let's take a look at a general
'inter-IC chat' on the bus. Let's consider the following setup and assume the
MCU wants to send data to one of its slaves
First, the MCU will issue a START condition. This acts as an 'Attention'
signal to all of the connected devices. All ICs on the bus will listen to the bus
for incoming data. Then the MCU sends the ADDRESS of the device, it wants
to access, along with an indication whether the access is a Read or Write
operation had received the address, all IC's will compare it with their own
address. If it doesn't match, they simply wait until the bus is released by the
stop condition If the address matches, however, the chip will produce a
response called the ACKNOWLEDGE signal. Once the MCU receives the
acknowledge, it can start transmitting or receiving DATA. In our case, the MCU
will transmit data. When all is done, the MCU will issue the STOP condition.
This is a signal that the bus has been released and that the connected ICs may
expect another transmission to start any moment.

www.rejinpaul.com
We have had several states on the bus in our example: START, ADDRESS,
ACKNOWLEDGE, DATA, STOP. These are all unique conditions on the bus.
Before we take a closer look at these bus conditions we need to understand a
bit about the physical structure and hardware of the bus.
As explained earlier, the bus physically consists of 2 active wires called SDA
(data) and SCL (clock), and a ground connection.
Both SDA and SCL are initially bi-directional. This means that in a particular
device, these lines can be driven by the IC itself or from an external device. In
order to achieve this functionality, these signals use open collector or open
drain outputs (depending on the technology).
The bus interface is built around an input buffer and an open drain or open
collector transistor. When the bus is IDLE, the bus lines are in the logic HIGH
state (note that external pull-up resistors are necessary for this which is easily
Forgotten). To put a signal on the bus, the chip drives its output transistor,
thus pulling the bus to a LOW level. The "pull-up resistor" in the devices as
seen in the figure is actually a small current source or even non-existent.
The nice thing about this concept is that it has a "built-in" bus mastering
technique. If the bus is "occupied" by a chip that is sending a 0, then all other
chips lose their right to access the bus. More will be explained about this in the
section about bus arbitration.
However, the open-collector technique has a drawback, too. If you have a long
bus, this will have a serious effect on the speed you can obtain. Long lines
present a capacitive load for the output drivers. Since the pull-up is passive,
you are facing an RC constant which will reflect on the shapes of the signals.
The higher this RC constant, the slower you can go. This is due to the effect
that it influences the slew rate of the edges on the I2C bus. At a certain point,
the ICs will not be able to distinguish clearly between a logic 1 and 0.

www.rejinpaul.com
SDA (above) and SCL (below) with Rp = 10 kΩ and Cp = 300 pF. The SCL clock
runs with 100 kHz (nominal).
Bus Arbitration:
So far we have seen the operation of the bus from the master's point of view
and using only one master on the bus. The I2C bus was originally developed as
a multi-master bus. This means that more than one device initiating transfers
can be active in the system. When using only one master on the bus there is no
real risk of corrupted data, except if a slave device is malfunctioning or if there
is a fault condition involving the SDA / SCL bus lines. This situation changes
with 2 MCU's:
When MCU 1 issues a start condition and sends an address, all slaves will
listen (including MCU 2 which at that time is considered a slave as well). If the
address does not match the address of CPU 2, this device has to hold back any
activity until the bus becomes idle again after a stop condition.
As long as the two MCU's monitors what is going on on the bus (start and stop)
and as long as they are aware that a transaction is going on because the last
issued command was not a STOP, there is no problem.
Let's assume one of the MCU's missed the START condition and still thinks the

www.rejinpaul.com
bus is idle, or it just came out of reset and wants to start talking on the bus
which could very well happen in a real-life scenario. This could lead to
problems. Since the bus structure is a wired AND (if one device pulls a line low
it stays low), you can test if the bus is idle or occupied.
When a master changes the state of a line to HIGH, it MUST always check that
the line really has gone to HIGH. If it stays low then this is an indication that
the bus is occupied and some other device is pulling the line low.
Therefore the general rule of thumb is: If a master can't get a certain line to go
high, it lost the arbitration and needs to back off and wait until a stop
condition is seen before making another attempt to start transmitting. The
rule says that a master loses arbitration when it cannot get either SCL or SDA
to go high when needed, this problem does not exist. It is the device that is
sending the '0' that rules the bus. One master cannot disturb the other
master's transmission because if it can't detect one of the lines to go higher, it
backs off, and if it is the other master that can't do so, it will behave the same.
This kind of back-off condition will only occur if the two levels transmitted by
the two masters are not the same. Therefore, let's have a look at the following
figure, where two MCUs start transmitting at the same time:
The two MCU's are accessing a slave in writing mode at address 1111001. The
slave acknowledges this. So far, both masters are under the impression that
they "own" the bus. Now MCU1 wants to transmit 01010101 to the slave,
while MCU 2 wants to transmit 01100110 to the slave. The moment the data
bits do not match anymore (because what the MCU sends is different than
what is present on the bus) one of them loses arbitration and backs off.
Obviously, this is the MCU which did not get its data on the bus. For as long as
there has been no STOP present on the bus, it won't touch the bus and leave
the SDA and SCL lines alone (yellow zone). The moment a STOP was detected,
MCU2 can attempt to transmit again.
Clock Synchronization:
All masters generate their own clock on the SCL line to transfer messages to
the I2C-bus. Data is only valid during the HIGH period of the clock. A defined
clock is therefore needed for the bit-by-bit arbitration procedure to take place.
Clock synchronization is performed using the wired-AND connection of I2C

interfaces to the SCL line. This means that a HIGH to LOW transition on the
SCL line will cause the devices concerned to start counting off their LOW period
and, once a device's clock has gone LOW, it will hold the SCL line in that state
until the clock HIGH state is reached. However, the LOW to HIGH transition of

www.rejinpaul.com
this clock may not change the state of the SCL line if another clock is still
within its LOW period. The SCL line will therefore be held LOW by the device
with the longest LOW period. Devices with shorter LOW periods enter a HIGH
wait-state during this time.
Special Addresses and Exceptions:
In the I2C address, map there are so-called "reserved addresses". This section
contains some more details on these addresses and what they do. For
information about the Extended Addressing Mode, please refer to the
corresponding chapter.
Address R/W Designation
0000-000 0 General call address
0000-000 1 START byte (note
0000-001 x Reserved for the obsolete C-Bus format (note 3)
0000-010 x Reserved for a different bus format (note 4)
0000-011 x Reserved for future purposes (note 5)
0000-1xx x Reserved for future purposes
1111-1xx x Reserved for future purposes
1111-0xx x 10-bit slave addressing mode (note 6)

The general call address: This address is being used to access all devices on
the bus which are capable of handling the general call and need this data.
Devices which are capable of handling this general call, but do not need it will
not answer. All bytes transferred after this address may or may not be taken
by the slaves that are responding to it. If no slave is acknowledging a
transmitted byte, the operation is stopped by issuing a STOP on the bus. The
meaning of the general call address is specified in the 1st byte transmitted after
this "general call". This first byte can contain the following information: If the
LSB is set to 0:
Reset and write programmable part of slave address. All devices who
respond to this will reset and take in the programmable part of their
0000-
address. This is done by re-reading the levels on the address select
0110
pins of the device (if any). This command can be used to reset an
entire I2C system.
The same as above, but without the reset . This can be useful if the
0000-
state of the address select pins of a device is configurable. This way
0100
the device address will change.
If the LSB is set to 1:

www.rejinpaul.com
This is a Hardware Call. If a device needs urgent attention from a

master device without knowing which master it needs to turn to, it can
use this call. This is a call "to whom it may concern". The device then
xxxx-
embeds its own address into the message. This call means as much
xxx1
as: Please contact me, I need to be serviced. All masters will listen and
the master that knows how to handle the device with the address
transmitted will contact its slave and act appropriately.
The START address:
This can be used between masters. A master which does not have an I2C
interface in hardware but in software needs to monitor the bus all the time.
Since this can require a lot of processing time, the START address was
introduced. The masters can sample the bus at a low rate. As soon as they
detect that the SDA line is low (it is held low for over 7 clock periods) it can
switch to a higher sampling rate to detect the Start condition. This address is
not followed by a stop condition, but rather by a repeated start condition.
Reserved for the obsolete C-Bus format: These addresses are used when
data other than I2C data have to be transmitted over the bus.
Reserved for future purposes: These addresses are for further expansion and
are currently not allowed.
10-bit slave addressing mode: Due to the increasing popularity of the I2C bus
the 7-bit address space got exhausted. This started posing problems for people
currently in the phase of designing a new I2C compatible IC. Therefore the I2C
standard has been updated to implement a 10-bit addressing mode.
A chip that conforms to the new standard receives two address bytes. The first
consists of the extended addressing reserved address, including the 2 MSB's of
the device address and the Read/Write bit. The second byte contains the 8
LSB's of the address. This scheme ensures that the 10 bit addressing mode
stays completely transparent for the other devices on the bus. Any new design
should implement this new addressing scheme.
Enhanced I2C (FAST Mode)
In the FAST mode, the physical bus parameters are not altered. The protocol,
bus levels, capacitive load etc. remain unchanged. However, the data rate has
been increased to 400 Kbit/s and a constraint has been set on the level of
noise that can be present in the system. To accomplish this task, a number of
changes have been made to the I2C bus timing.
High-speed I2C (HS-Mode)
High-speed mode (Hs-mode) devices offer a quantum leap in I2C-bus transfer
speeds. Hs-mode devices can transfer information at bit rates of up to 3.4
Mbit/s, yet they remain fully downward compatible with Fast- or Standard-
mode (F/S-mode) devices for bi-directional communication in a mixed-speed
bus system. With the exception that arbitration and clock synchronization is
not performed during the Hs-mode transfer, the same serial bus protocol and
data format is maintained as with the F/S-mode system. Depending on the
application, new devices may have a Fast or Hs-mode I2C-bus interface,

www.rejinpaul.com
although Hs-mode devices are preferred as they can be designed-in to a greater

number of applications.
I2C Bus Events:
 Start and Stop Conditions
 Transmitting a Byte to a Slave Device
 Receiving a Byte From a Slave Device
 Getting Acknowledge from a Slave Device
 Giving Acknowledge to a Slave Device
 No Acknowledge ConditionS.3
Start and Stop Conditions:
Prior to any transaction on the bus, a START condition needs to be
issued on the bus. The start condition acts as a signal to all connected
IC's that something is about to be transmitted on the bus. As a result, all
connected chips will listen to the bus.
After a message has been completed, a STOP condition is sent. This is
the signal for all devices on the bus that the bus is available again (idle).
If a chip was accessed and has received data during the last transaction,
it will now process this information (if not already processed during the
reception of the message).
 The chip issuing the Start
condition first pulls the SDA
 Start
(data) line low, and next pulls
 the SCL (clock) line low.
 The Bus Master first releases the

 Stop
SCL and then the SDA line.

A few notes about start and stop conditions:
 A single message can contain multiple Start conditions. The use of this
so-called "repeated start" is common in I2C.
 A Stop condition ALWAYS denotes the END of a transmission. Even if it
is issued in the middle of a transaction or in the middle of a byte. It is
"good behavior" for a chip that, in this case, it disregards the information
sent and resumes the "listening state", waiting for a new start condition.
Transmitting a Byte to a Slave Device:
Once the start condition has been sent, a byte can be transmitted by the
MASTER to the SLAVE.
This first byte after a start condition will identify the slave on the bus (address)
and will select the mode of operation. The meaning of all following bytes
depends on the slave.

www.rejinpaul.com
A number of addresses have been reserved for special purposes. One of these
addresses is reserved for the "Extended Addressing Mode". As the I2C bus
gained popularity, it was soon discovered that the number of available
addresses was too small. Therefore, one of the reserved addresses has been
allocated to a new task to switch to 10-bit addressing mode. If a standard slave
(not able to resolve extended addressing) receives this address, it won't do
anything (since it's not its address).
If there are slaves on the bus that can operate in the extended 10-bit
addressing mode, they will ALL respond to the ACK cycle issued by the master.
The second byte that gets transmitted by the master will then be taken in and
evaluated against their address.
Note: Even in 10-bit extended addressing mode, Bit 0 of the first byte after the
Start condition determines the slave access mode ('1' = read / '0' = write).
Receiving a Byte From a Slave Device:

Once the slave has been addressed and the slave has acknowledged this, a
byte can be received from the slave if the R/W bit in the address was set to
READ(set to '1').
The protocol syntax is the same as transmitting a byte to a slave, except that
now the master is not allowed to touch the SDA line. Prior to sending the 8
clock pulses needed to clock in a byte on the SCL line, the master releases the
SDA line. The slave will now take control of this line. The The line will then go
high if it wants to transmit a '1' or, if the slave wants to send a '0', remain low.
(1)All the master has to do is generate a rising edge on the SCL line
(2) read the level on SDA
(3) and generate a falling edge on the SCL line

www.rejinpaul.com
(4). The slave will not change the data during the time that SCL is high.
(Otherwise a Start or Stop condition might inadvertently be generated.)
During (1) and (5), the slave may change the state of the SDA line.
In total, this sequence has to be performed 8 times to complete the data byte.
Bytes are always transmitted MSB first.
The meaning of all bytes being read depends on the slave. There is no such
thing as a "universal status register". You need to consult the data sheet of the
slave being addressed to know the meaning of each bit in any byte transmitted.
Getting Acknowledge from a Slave Device:
When an address or data byte has been transmitted onto the bus, then this
must be ACKNOWLEDGED by the slave(s). In case of an address: If the address
matches its own, then that slave and only that slave will respond to the
address with an ACK. In case of a byte transmitted to an already addressed
slave then that slave will respond with an ACK as well.
The slave that is going to give an ACK pulls the SDA line low immediately after
reception of the 8th bit transmitted, or, in case of an address byte, immediately
after evaluation of its address. In practical applications this will not be
noticeable.
This means that as soon as the master pulls SCL low to complete the
transmission of the bit
(1), SDA will be pulled low by the slave
(2). The master has now issued a clock pulse on the SCL line
(3). The slave will release the SDA line upon completion of this clock pulse
(4). The bus is now available again for the master to continue sending data or
to generate a stop condition.
In case of data being written to a slave, this cycle must be completed before
a stop condition can be generated. The slave will be blocking the bus (SDA kept
low by slave) until the master has generated a clock pulse on the SCL line.

www.rejinpaul.com
Giving Acknowledge to a Slave Device:

Upon reception of a byte from a slave, the master must acknowledge this to
the slave device.The master is in full control of the SDA and the SCL line.
After transmission of the last bit of the master (1) the slave will release the SDA
line.
(1). The SDA line should then go high

(2).The Master will now pull the SDA line low
(3).Next, the master will put a clock pulse on the SCL line
(4). After completion of this clock pulse, the master will again release the SDA
line
(5).The slave will now regain control of the SDA line
Note: The above waveform is slightly exaggerated. You will not notice SDA is
gone, high in (2) and (5). A small spike might barely be visible.
Note: An Acknowledge of a byte received from a slave is always necessary,
EXCEPT on the last byte received If the master wants to stop receiving data
from the slave, it must be able to send a stop condition. Since the slave regains
control of the SDA line after the ACK cycle issued by the master, this could
lead to problems. Let's assume the next bit ready to be sent to the master is a
0. The SDA line would be pulled low by the slave immediately after the master
takes the SCL line low. The master now attempts to generate a Stop condition
on the bus. It releases the SCL line first and then tries to release the SDA line -
which is held low by the slave. Conclusion: No Stop condition has been
generated on the bus This condition is called a NACK: Not ACKnowledge. Do
not confuse this with No
ACKnowledge:
Condition Can Only Occur...
Not acknowledge (NACK) After a master has read a byte from a slave
No acknowledge After a master has written a byte to a slave
No Acknowledge Condition:

www.rejinpaul.com
This is not exactly a condition. It is merely a state in the data flow between
master and slave. If, after transmission of the 8th bit from the master to the
slave, the slave does not pull the SDA line low, then this is considered a No
ACKcondition.
This means that either:

 The slave is not there (in case of an address)
 The slave missed a pulse and got out of sync with the SCL line of the
master.
 The bus is "stuck". One of the lines could be held low permanently.
In any case the master should abort by attempting to send a stop condition on
the bus.
A test for a "stuck bus" can be performed in the stop condition cycle.
I2C Bus Subroutine:
The SCL pin must have an open drain output while the SDA pin must be either
an input or have an open drain output, the I2C bus subroutine will repeatedly
access TRISC, the data direction register for PORTC. However, TRISC is located
at the bank 1 address, H‘87‘, which cannot be accessed by direct addressing
without first executing the instruction
Then changing the required bit of TRISC, and finally reverting back to Bank 0
with
Bcf STATUS,RP0
Instead of doing this, load the indirect pointer FSR, with the address of TRISC
and then do the required bit setting and bit clearing of TRISC bits indirectly.

www.rejinpaul.com
Figure: 9.5 I2C typical message string format
For example , with the following definition

SCL equ 3
And
SDA equ 4
Then
Bsf INDF,SDA
Will relese the SDA line, letting the external pullup resistor of figuer9.1b pull it
high or some other I2C chip pull it low.
The use of FSR raise two condition
1. If these I2C subroutines are executed from the mainline program, then
any interrupt service routine that also uses FSR must set it aside upon
entry and restore it upon exit
2. Any use of indirect addressing to access a sequence of addresses in the
PIC‘s RAM when used in conjunction with these I2C subroutines must
swap pointers in and out of FSR.
The timing requirements of figuer9.6 will be handled by inserting a number of
nop instructions between the instruction that change SDA and SCL. The
number of nop instruction required depends on the crystal clock rate. The
delay macro, define in figure 9.7a uses the equate of Freq to 4,10, or 20 to
insert a number of nop instruction equal tot the first,second, or third macro
parameters.

www.rejinpaul.com

www.rejinpaul.com
The equates and variables needed for the I2C subroutines are listed in Figuer
9.8 DEVADD is the selected peripheral chip‘s 7-bit address on the I2C bus
shifted left one place to align it for use as a control byte. INTADD is a selected
registered memory address inside the selected peripheral chip by an I2C output
subroutine, I2Cout.DATAIN is the repository for the byte of data retrived by an
I2C input subroutine, I2Cin, from the selected register in the selkected
peripheral chip.
The I2Cout subroutine of figuer9.9 call a start subroutine to generate the

START condation, and calls a TX subroutine three times to send DEVADD(plus
R/W = 0), IINTADD, and DATAOUT out on the I2C bus. Finally, it calls a stop
subroutine to generate the STOP condition. The TX subroutine takes the byte
passed to it in W, uses a TXBUF variable to extract the bits one by one, and
transmits each bit using a BitOut subroutine. TX reads the acknowledge bit by
calling a BitIn subroutine, setting Z if ACK occurs.
The I2Cin subroutine of figure 9.9 is similar to the I2Cout subroutine. It calls
the Start subroutine and then the TX subroutine twice to send DEVADD (Plus
R/W = 0) and INTADD. Then it calls the Start subroutine to send (plus R/W =
1), the RX subroutine to read back a byte(with NOACK), and finally the Stop
subroutine.
noexpand
delay macro freq4, ferq 10, freq20
if freq==4
fill (nop), freq4
endif
if freq==10
fill (nop), freq10
endif
if freq==20
fill (nop), freq20
endif
endm
Figuer 9.7 (a) macro definition
0 nop for OSC = 4MHz (i.e., for freq eqn 4),

1 nop for OSC = 10MHz (i.e., for freq eqn 10),
2 nops for OSC = 20MHz (i.e., for freq eqn 20),
Figuer 9.7 (b) example of macro invoication which will insert
Freq eqn 4 ;set to 4,10,20, for 4MHz,10Mhz,20MHz

SDA eqn 4 ;I2C serial data bit of PORTC
SCL eqn 3 ;I2C serial clock bit of PORTC

www.rejinpaul.com
Figuer: 9.8 I2C Equates
Cblock
.
.
.
DEVADD ;device I2C address X2
INTADD ;Internal address
DATAOUT ;Data to be written into INTADD during a writ
DATAIN ;Data to be read from INTADD during a read
TXBUF ;Buffer for each byte sent by TX
RXBUF ;Buffer for each byte received by RX
.
.
.
endc
Figuer: 9.8 I2C variables
;;;;;;;;;;I2C Subroutine;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;The I2Cout subroutine transfer out three bytes: DEVADD, INTADD and DATAOUT
I2Cout
Call start ; generate START condition
Movf DEVADD,W ;send peripheral address with R/W=0(write)
Call TX
Movf INTADD,W ;send the peripheral’s internal address
Call TX
Movf DATAOUT,W ;send data to write to peripheral
Call TX
Call STOP ; generate STOP condition
Return
; the I2Cin subroutine transfers out DEVADD(With R/W = 0) and INTADD,restarts,

;transfer out DEVADD(with R/W = 1) and reads one byte back into DATAIN
I2Cin
call START ;generat the START condition
movf DEVADD,W ;send peripheral address with R/W = 0
call TX
movf INTADD,W ;send peripherals internal address
call TX
call Restart ;Restart
movf DEVADD,W ;send peripheral address
iorlw B’00000001’ ; with R/W=1 (Read)
call TX
bsf TXBUFF,7 ;NOACK the following read of one byte
call RX ;Read byte
movf DATAIN ;into DATAIN
call STOP ;generate STOP condition
return
; the START subroutine initializes the I2C bus and then generate the START condition on the
;I2C bus
; the Restart entry point bypasses the initialization of the I2C bus
Start

www.rejinpaul.com
Movlw B’00111011’ ;enable I2C master mode

Movwf SSPCON
Bcf PORTC,SDA ;drive SDA low when it is an output
Bcf PORTC,SCl ;drive SCL low when it is an output
Movlw TRISC ;set indirect pointer to TRISC
Movwf FSR
Restart
Bsf INDF,SDA ;make sure SDA is high
Bsf IINDF,SCL ;make sure SCL is high
Delay 0,1,2
Bcf INDF,SDA
Delay 0,1,2 ;t : START
Bcf INDF,SCL
Return
; the stop subroutine generate the stop condition on the I2C bus
Stop
Bcf INDF,SDA ;return SDA low
Bsf INDF,SCL ;drive SCL high
Delay 0,1,2 ;t : STOP
Bsf INDF,SDA ; and then drive SDA high
Return
; The TX subroutine sends the byte passed to it in W and returns Z=1 if ACK occurs & Z=0 if
NOACK occurs
TX
Movwf TXBUFF ;save parameter inTXBUFF
Bsf STATUS,C ;rotate a one through TXBUFF to count bits
TX_1
Rlf TXBUFF,F ;rotate TXBUFF left,through carry
Movf TXBUFF,F ;set Z bit when all eight bits have been transferred’
Btfss STATUS,Z ;until Z=1
Call Bitout ;send carry bit, then clear carry bit
Goto TX_1 ; then do it again
Call Bitin ; read acknowledge bit into bit 0 of RXBUFF
Movlw B’0000001 ; read acknowledge bit
Andwf RXBUFF,W ;Z=1 if ACK; Z=0 if NOACK
Return
; the RX subroutine recives a byte from the I2C bus into W, using RXBUFF buffer
; call RX with bit 7 of TXBUFF clear for ACK
;Call RX with bit 7 of RXBUFF set for NOACK
RX
Movlw B’00000001’ ; rotate a one through RXBUFF to the carry bit to count bits
Movwf RXBUFF
RX_1
Rlf RXBUFF,F ;shift previous bits left
Call Bitin ; read a bit fromSDA in to bit 0 of RXBUFF
Btfss STATUS,C ;C=1 yet
Got to RX_1 ; no do it again
Rlf TXBUFF,F ;move bit 7 of TXBUFF to carry bit
Call Bitout ; and from there to SDA as acknowledgement
Movf RXBUFF,W ;put received byte in to W
Return

www.rejinpaul.com
; The Bitout subroutine transmit, then clears the carry bit
Bitout
Bdf INDF,SDA ;copy carry bit to SDA
Btfsc STATUS,C
Bsf INDF,SDA
Bsf INDF,SCL ;puls clock line
Delay 0,1,2
Bcf INDF,SCl
Bcf STATUS,C ;Clear carry bit
Return
; The Bitin subroutine recives one bit into bit0 of RXBUFF
bitin
bsf INDF,SDA ;release SDA line
Bsf INDF,SCL ;drive clock line high
Bcf RXBUFF,0 ;copy SDA to bit 0 of RXBUFF
Btfsc PORTC,SDA
Bsf INDF,SCl ;drive clock line low again
Return
;;;;;;;;;;;;;;;;;;; end of I2C subroutine;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
Figure: 9.9 I2C Subroutine
Figure 9.8,9.9,9.7,9.6,9.5 has to include
Serial EEPROM:
EEPROM technology supplies nonvolatile storage of variables to a PIC
controlled device or instruments. That is variables stored in an EEPROM will
remain there even after power has been turned off and then on again. Some
instruments use an EEPROM to store calibration data during manufacture. In
this way, each instrument is actually custom built, with customization that can
easily automate. Other instruments use an EEPROM to allow a user to store
several sets for setup information. For an instrument requiring a complicated
setup procedure, this permits a user to retrieve the setup for any one of several
very different measurements. Still other devices use an EEPROM in a way that
is transparent to a user, providing backup of setup parameters and thereby
bridging over power outages.
An EEPROM with I2C serial interface such as microchip technology‘s 24LC01B

provides designer with a convenient solution to a need for nonvolatile data
storage. It holds 128bytes of data . it is package in a tiny eight-pin DIP or
surface-mount package. It requires only a+5V supply and will operate on the
―fast mode‖ (400 kbits/s) I2C bus. It draws less than 3 mA of supply current
during programming, 1 mA during reading, and 0.1 mA during sandby. It times
its own write cycle and automatically erases a byte before writing into it. A
block of upto 8 bytes can be written to the chip at one time and the chip will
program them all simultaneously in less than 10ms. The manufacture
guarantees successful writes for up to 10,000,000 erase/write cycles and data

www.rejinpaul.com
retention beyond 200 years over an operating temperature range of 00C to

+700C or (-400C to +850C for industrial version)
The device with its interface circuit is illustrate in figure 9.15 the WP (write
protect) pin permits a manufacturer to program a part with calibration
constants ( with WP low) and then to permit only reads thereafter ( with WP
tied high).
The EEPROM makes use of an internal address pointer that is set during the
second byte of a ―write‖ message string, as show in the figure 9.16a and 9.16b.
if further bytes are transmitted before the STOP condition, as in figure 9.16b,
they will accept as the data to be write into the selected internal address. The
reception of the STOP condition triggers the programming of these bytes into
the select addresses.
While the EEPROM is doing its autonomous programming operation, it will
acknowledge another write command. Because of this, the acknowledge bit can
be used as a flag to determine when the programming operation has been
completed. Simply send out the slave address with the write bit low and check
whether the ACK bit is pulled low by the EEPROM. Until it does get pulled low
in acknowledgment, the START condition followed by the same byte can be
sent repeatedly and the ACK bit tested. With a typical programming time of
2ms,, programming of many bytes can take place as rapidly as possible, faster
than simply allowing the 10ms worst-case write time to expire.
This EEPROM includes a page write buffer for writing upto 8bytes
simultaneously with the single write message string show in the figure 9.16b.
within 10ms after the STOP condition is received by the EEPROM, all of the
transmitted bytes will be programmed. However, all eight addresses are
constrained to have the same upper 5 bits. That is, only the lower 3 bits of
EEPROM internal address counter are incremented when more than one data
byte is included in a write command sequence. For example, if the EEPROM
address sent in the second byte of the write command is B‘00010110‘ and if
that address byte is followed by three data bytes and the STOP condition, then
the first of the three data bytes will be written into address B‘00011000‘. The
second into B‘00010111‘, and the third into B‘00010000‘
Reading any number of bytes of data from selected EEPROM address requires
that a starting address first be sent to EEPROM with the write message string
of figure 9.16a. this string is followed by the message string of figure 9.16c,
consisting of the START condition, a read command, and than a read of data
from consecutive address sent back by the EEPROM. The PIC signals the
EEPROM to send no further bytes by not pulling the SDA line low during the
last acknowledge but time. The sending of the STOP condition by the PIC
completes the message string.

www.rejinpaul.com
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus is not busy.
• During data transfer, the data line must remain stable whenever the clock
line is high. Changes in the data line while the clock line is high will be
interpreted as a Start or Stop condition.
 When the bus is not busy both the data and the clock line remains high
 For data transfers high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All commands must be preceded
by a Start condition
 To stop the data transfer at low-to-high transition of the SDA line while the
clock(SCL) is high determines a Stop condition. All operations must be
ended with a Stop condition.
Each data transfer is initiated with a Start condition and terminated with a
Stop condition. The number of data bytes transferred between the Start and
Stop conditions is determined by the master device and is, theoretically,
unlimited (although only the last sixteen will be stored when doing a write

www.rejinpaul.com
operation). When an overwrite does occur, it will replace data in a first-in,

first-out (FIFO) fashion.
Device Addressing
A control byte is the first byte received following the Start condition from
the master device. The control byte consists of a four-bit control code. For
the 24XX01, this is set as ‗1010‘ binary for read and write operations. The
next three bits of the control byte are ‗don‘t care for the 24XX01. The last bit
of the control byte defines the operation to
be performed. When set to ‗1‘, a read operation is selected. When set to ‗0‘,
a write operation is selected. Following the Start condition, the 24XX01
monitors the SDA bus checking the device type identifier being transmitted.
Upon receiving a ‗1010‘ code, the slave device outputs an Acknowledge
signal on the SDA line. Depending on the state of the R/W bit, the 24XX01
will select a read or write operation.
Operation Control Code Block Select

R/W
Read 1010 Block Address 1

www.rejinpaul.com
Write 1010 Block Address 0
WRITE OPERATION
Byte Write
Following the Start condition of the master, the device code (4 bits), the
block address (3 bits, don‘t care) and the R/W bit, which is a logic low, is
placed onto the bus by the master transmitter. This indicates to the
addressed slave receiver that a byte with a word address will follow after it
has generated an Acknowledge bit during the ninth clock cycle. Therefore,
the next byte transmitted by the master is the word address and will be
written into the address pointer of the 24XX01.
Page Write
The write control byte, word address and first data byte are transmitted
to the 24XX01 in the same way as a byte write. However, instead of
generating a Stop condition, the master transmits up to 8 data bytes to the
24XX01, which are temporarily stored in the on- chip page buffer and will
be written into the memory once the master has transmitted a Stop
condition.

www.rejinpaul.com
i2c bus connection to EEPROM

EEPROMs are designed to interface with Inter-Integrated Circuit (I2C) buses
and hardware. Fairchild‘s electrically erasable programmable read only
memories (EEPROMs) offer valuable security features (write protection), two
write modes, three read modes and a wide variety of memory sizes.
Applications for the I2C bus and memories are included in SANs (small-area
networks), stereos, televisions, automobiles and other scaled-down systems
that don‘t require tremendous speeds but instead cost efficiency and design
simplicity.

www.rejinpaul.com
Connection of I2C bus with EEPROM and other Devices

The I2C bus configuration is an amalgam of microcontrollers and
peripheral controllers. By definition: a device that transmits signals onto the
I2C bus is the ―transmitter‖ and a device that receives signals is the
―receiver‖; a device that controls signal transfers on the line in addition to
controlling the clock frequency is the ―master‖ and a device that is
controlled by the master is the ―slave‖. The master can transmit or receive
signals to or from a slave, respectively, or control signal transfers between
two slaves, where one is the transmitter and the other is the receiver. It is
possible to combine several masters, in addition to several slaves, onto an
I2C bus to form a Multimaster system. If more than one master
simultaneously tries to control the line, an arbitration procedure decides
which master gets priority. The maximum number of devices connected to
the bus is dictated by the maximum allowable capacitance on the lines, 400
pF, and the protocol‘s addressing limit of 16k; typical device capacitance is
10 pF. Up to eight E2PROMs can be connected to an I2C bus, depending on
the size of the memory device implemented. The simplicity of the I2C system
is primarily due to the bidirectional 2- wire design, a serial data line (SDA)
and serial clock line (SKL), and to the protocol format. Because of the
efficient 2-wire configuration used by the I2C interface
START/STOP CONDITIONS
If both the data and clock lines are HIGH, the bus is not busy. To attain
control of the bus, a start condition is needed from a master; and to release
the lines, a stop condition is required.
Start Condition: HIGH-to-LOW transition of the data line while
the clock line is in a HIGH state.
Stop Condition: LOW-to-HIGH transition of the data line while the
clock line is in a HIGH state.
The master always generates the start and stop conditions. After the start
condition the bus is in the busy state. The bus becomes free after the stop
condition.
DATA BIT TRANSFER

After a start condition ―S‖ one data bit is transferred during each clock
pulse. The data must be stable during the HIGH-period of the clock. The
data line can only change when the clock line is at a LOW level. Normally,
each data transfer is with 8 data bits and 1 acknowledged bit (byte format to
acknowledge).
ACKNOWLEDGE

www.rejinpaul.com
Each data transfer needs to be acknowledged. The master generates the

acknowledge clock pulse. The transmitter releases the data line (SDA =
HIGH) during the acknowledge clock pulse. If there was no error detected,
the receiver will pull down the SDAline during the HIGH period of the
acknowledge clock pulse. If a slave receiver is not able to acknowledge, the
slave will keep the SDA line HIGH and the master can then generate a STOP
condition to abort the transfer. If a master receiver keeps the SDA line
HIGH, during the acknowledge clock pulse, the master signals the end of
data transmission and the slave transmitter release the data line to allow
the master to generate a STOP-condition.
FORMATS
There are three data transfer formats supported:
— Master transmitter writes to slave receiver; no direction change
— Master reads immediately after sending the address byte
— Combined format with multiple read or write transfers
ADDRESSING
The 7-bit address of an I2C device and the direction of the following data is
coded in the first byte after the start condition:
A ―0‖ on the least significant bit indicates that the master will write
information to the selected Slave address device; a ―1‖ indicates that the
master will read data from the slave.

www.rejinpaul.com
SERIAL EEPROM APPLICATIONS
Serial EEPROMS are ideal non-volatile cost effective memory solutions in

applications that require:
 Small footprint and board space as in cellular phone applications

 BYTE level ERASE, WRITE, and READ of data
 Low voltage and current for handheld battery applications as in a keyless
entry transmitter
 Multiple non-volatile functions in the same application such as a VCR
 Low availability of microcontroller I/O lines
Market Common Applications

Consumer TV tuners, VCRs, CD players,
cameras, radios, and remote
controls
Automotive Airbags, anti-lock brakes,
odometers, radios, and keyless
entry
Office Automation Printers, copiers, PCs, and portable
PCs
Telecom Cellular, cordless and full features
Phones, faxes, modems, pagers,
and satellite receivers
Industrial Bar code readers, point-of-sale
terminals,

www.rejinpaul.com
Smart cards, lock boxes,

Garage door openers, and test
measurement
Equipment
The typical functions that serial EEPROMs are utilized for being:
• Memory storage of channel selectors or analog controls (volume, tone, etc.) in
consumer electronics products
• Power down storage and retrieval of events such as fault detection or error
diagnostics in automotive products
• Electronic real time event or maintenance logs such as page counting in office
automation products. Also, configuration or DIP switch storage in office
automation products
• Last number redial storage and speed dial number storage in telecom
products
• User in-circuit reprogrammable look up tables such as bar code readers,
point-of-sale terminals, environmental controls and other industrial products
Temperature Sensor
The combination of an analog temperature transducer, an analog to digital

converter, and an I2C bus interface all ina tiny SO-8 surface mount package
represents a significant contribution to designers.
The analog voltage from the internal temperature passes to a converter

located in such close physical proximity that all of the potential problems of
noise and ground voltage offsets are handled inside the chip, once and for
all National semiconductor‘s LM75 chip converts temperature over the range
of -250 to +1000C with ±20C accuracy. The same part delivers ±30C accuracy
for temperature down to -550C and up to ±1250C. for many applications an
even more important feature is its fine 0.50C resolution. Obtained with the
support of a 9 bit ADC. Figure 9.11 illustrate the two‘s complement form of
the output. This 0.50Cresolution ,eans that small temperature difference are
measured with in 0.50C.

www.rejinpaul.com
The LM75 chip also include thermal watchdog that can be set up to
interrupt the PIC on its RB0/INT edge triggered interrupt input when the
temperature rises past a programmable setpoint. TOS ( os stands fot over
temperature shut down) . it includes programmable hysteresis so that the
temperature must dip down below the setpoint TOS threshold to a lower
THYST threshold before rising again past the TOS setpoint to generate another
output edge.

www.rejinpaul.com
The chip includes a power on reset circuit that defaults to the operation
show in the figure 9.12b. at the power on time the PIC may come out of the
reset first; therefore, it is necessary to insert a delay before initializing the
LM75‘s thermal watchdog circuitry. Otherwise the PIC‘s commands to the
LM&% may go unnoticed
The register structure of the LM75 is show in the figure 9.13. when a ―write‖
message string is transmitted to the chip, the first byte select the chip for a
write and then the second byte loads the pointer register. The write message
string can stop there( illustrate in figure 9.14a), or it can continue with a 2-
byt write of 1000F = 75.50C to the TOS register (illustrate infiguer9.14b). once
the pointer has been set, any of these register can be read, reading 2 bytes

www.rejinpaul.com
for temperature. TOS or THYST or reading just 1 byte for the configuration
registers.
If the thermal watchdog function of the LM75 is not use , then advantage
can be taken of the power-on default clearing of the poiinter and
configuration register. In this case the interaction with the chip need be no
more than successive reads of the temperature. As in the figure 9.14C
The OS output operates in either of two modes, comparator or interrupt.
The host controls the temperature at which the alarm is asserted (TOS) and
the hysteresis temperature below which the alarm condition is not valid
(THYST). Also, the LM75‘s TOS and THYST registers can be read by the
host. The address of the LM75 is set with three pins to allow multiple
devices to work on the same bus. Power-up is in comparator mode, with
defaults of TOS = +80°C and THYST = +75°C. The 3.0V to 5.5V supply

www.rejinpaul.com
voltage range, low supply current, and I2C interface make the LM75 ideal
for many applications in thermal management and protection.
Applications
 Thermal System Management
 Thermal Protection
 Test Equipment, Computers and Office Electronics
Analog to digital converter:
An analog-to-digital converter (ADC) converts an analog signal into an

equivalent digital number. PIC 16C74A has an inbuilt ADC with the following
features
 8-bit conversion
 8 analog input channels
 An analog multiplexer
 A sample and hold circuit for signal on the selected input channel
 Alternative clock sources for carrying out conversion
 Adjustable sampling rate
 Choice of an internal or external reference voltage

www.rejinpaul.com
 Interrupt to microcontroller on end of conversion
ADC Characteristic:
The PIC analog to digital converter has the idealized transfer funcation show in
the figure 10.1. it converts an input voltage to an 8 bit number. The input
voltage is scaled against a reference voltage,VRef
The reference voltage that is best suited for many application is the PIC supply
voltage VDD select as one option and connected to the ADC internally, there by
avoiding the need to dedicated a pin to this role. For a transducer whose
output is proportional to its own supply voltage and that uses the PIC supply
voltage as its own supply voltage, making VRef equal to VDD ia an ideal choice.

www.rejinpaul.com
For other applications, using VDDas the refrence voltage offers the largest
possible analog voltage input range, since proper ADC operation requires
0V ≤ VInput ≤ VRef and also 3V ≤ VRef ≤ VDD
Given this choice of VRef = VDD the PIc parts ca assign up to eight pins to serve
as analog inputs to the ADC, using the pins and the register initializations
show in the figure 10.2 any pin that is assigned to serve as an analog and
digital input to the ADC can be read as a digital input by reading the
appropriate port pin or used as an analog input by selecting it as the input
channel to the ADC

www.rejinpaul.com
The default power-on state of ADCON!(H‘00‘) powers down the digital I/O
circuitry for the five pins labeled ―analog input or digital I/O‖, there by making
them ―analog input only‖ pins
For some applications, the use of an external voltage reference of 3.0V provides
the greatest possible resolution in the output.. this is particularly useful for

www.rejinpaul.com
voltage difference measurement. Figure 10.3 illustrate the connection of an

external voltage reference to the PIC. The 10µF capacitor suppresses RF
switching transients.
The performance characteristic of the analog to digital converter are listed in

the figure 10.4 and expanded in figure 10.5. When a new input channel is
selected, the analog multiplexer sampling switch connects the input pin to
Chold, a sampling capacitor, show in the figure 10.5a. Vhold, the voltage on
reference must be allowed time to charge until it equals to Vsource to within one-

www.rejinpaul.com
half of one of the voltage steps of figure 10.1. The larger resistance of the
source being measured, the longer this charging time will become. The
relationship is shown in figure 10.5b. A high source resistance can be
converted to a low source resistance with the help of the op amp ―follower‖
circuit of figure 10.5c.
After waiting out the sample time, a conversion can be initiated. The ADC
circuit will open the sampling switch and carry out the conversion of the input
voltage as it was at the moment the switch was opened. Upon completion of the
conversion, the sampling switch is closed and Vhold again tracks Vsource.
If the ADC is used to sample a single channel at equally spaced intervals, this
can be done automatically under interrupt control. The timer‘s CCp module
can be used with Timer1 to initiate periodic ADC conversion of the select
channel. In addition, the ADC is set up to generate an interrupt when the
conversion has been completed. After this process has been setup and begun,
the CPU simply deals with each sample as it becomes available.
ADC USE:
Register ADCON1, TRISA, and TRISE must be initialized to select the refrence
voltage and the input channel desired, as described by figure 10.2 and 10.3.
then ADCON0 is initialized with the step listed in figure 10.6. the first step is
select the ADC clock source from among the four choices. The choice show in
the figure 10.6a provide the highest rate consistent with the constrain that the
ADC clock period must be 1.6µs or greater. The RC choice (made by setting

www.rejinpaul.com
ADCON0[7:6] to 11) is designed for use with PIC being clocked by a relatively
slow clock. It lets the ADC run at a nominal 250kHz rate.

www.rejinpaul.com
If just one analog input is to be used, it can be selected once and for all by
combining the channel selection of figuer10.6b with the ADC clock period
selection of figure 10.6a. if several analog channels are to be used, it is
important to remember to wait for the sample time discussed in conjunction
with figure 10.5. that is, select the channel, wait out the required sample time ,
and the initiate the conversion by setting the GO_DONE bit of ADCON0. When
GO_DONE =0 again, the result from ADRES(H‘1E‘), the ADC result register

www.rejinpaul.com
If one or more channel channels are to be periodically sampled, the

timer1/CCP2 combination can be used to initiate each conversion. The register
involved as shown in the figure 10.7

www.rejinpaul.com

www.rejinpaul.com
UART( Universal Asynchronous Receiver & Transmitter):
UART stands for Universal Asynchronous Receiver / Transmitter, is a module

include in the following parts: PIC16C63, PIC16C65A, PIC16C73A, and
PIC16C74A,
It is a serial communication interface which uses two lines for sending (TX) and
receiving (RX) data. As its name indicates it is an
asynchronous communication interface, which means it doesn‘t need to send
clock along with it as in synchronous communications. UART is the
communication standard of our old computer‘s RS-232 serial port. Most of the
Microchip‘s PIC Microcontrollers have built in USART Module. USART stands
for Universal Synchronous Asynchronous Receiver Transmitter. It can be
configured in the following Modes:
 UART – Asynchronous (Full Duplex)
 USRT Master – Synchronous (Half Duplex)
 USRT Slave – Synchronous (Half Duplex)
TXSTA – Transmit Status and Control Register:
 Bit 7 CSRC : Clock Source Select Bit, this bit has no application in the
Asynchronous mode operation of USART module. It is used to select
master or slave mode in Synchronous mode operation.
 Bit 6 TX9 : When this bit is set it enables the 9 bit transmission
otherwise 8 bit transmission is used. 9th bit in the 9 bit transmission
mode is commonly used as parity bit.
 Bit 5 TXEN : Setting this bit enables the transmission. In the

synchronous mode operation CREN and SREN bits of RCSTA register
overrides this bit.

www.rejinpaul.com
 Bit 4 SYNC : This is the USART Mode select bit. Setting this bit selects
Synchronous mode while clearing this bit selects Asynchronous mode.
 Bit 3 Unimplemented : This bit is unimplemented and will read as 0.
 Bit 2 BRGH : This is the High Baud Rate Select bit for Asynchronous
mode operation and is unused in Synchronous mode. Setting this bit
selects High Speed and clearing this bit selects Low Speed baud rates.
You will can see the baud rate calculation later in this article.
 Bit 1 TRMT : This is the Transmit Shift Register (TSR) status bit. This
can be used to check whether the data written to transmit register is
transmitted or not. When the TRS is empty this bit is set and when the
TSR is full this bit will be 0.
 Bit 0 TX9D : This is the 9th bit of data in the 9 bit transmission mode.
This is commonly used as parity bit.
RCSTA – Receive Status and Control Register :
 Bit 7 SPEN : Serial Port Enable bit. Setting this bit enables serial port
and configures RC7, RC6 as serial port pins.
 Bit 6 RX9 : Setting this bit enables 9 bit reception otherwise it will be in
8 bit reception mode.
 Bit 5 SREN : Single Receive Enable bit. This bit has no effect on
Asynchronous mode and Synchronous Slave mode. Setting this bit will
enables Single Receive. This bit will cleared after the reception is
complete.
 Bit 4 CREN : Continuous Receive Enable bit. Setting this bit will enable
Continuous Receive. In the Synchronous Mode CREN overrides SREN.
 Bit 3 ADDEN : Address Detect Enable bit. This bit is applicable only in
Asynchronous 9 bit mode. Setting this bit enables Address Detect.
 Bit 2 FERR : Framing Error bit. 1 at this bit stands for Framing Error
while 0 stands for No Framing Error.

www.rejinpaul.com
 Bit 1 OERR : Overrun Error bit. A high at this bit indicates that Overrun
error has occured.
 Bit 0 RX9D : This is the 9th bit of Received Data and is commonly used
as Parity Bit.
USART Baud Rate Generator (BRG)
Baud Rate Generator provides the required clock for the data transmission and
reception. USART module has a dedicated 8 bit baud rate generator which
supports both Synchronous and Asynchronous modes. The 8-
bit SPBRG register controls the time period of this free running timer. In
Asynchronous mode BRGH, 2nd bit of TXSTA register also controls the
generated baud rate but in Synchronous mode it is ignored. Baud Rate can be
calculated from the following equations, where FOSCis the clock frequency of the
microcontroller.
Waveform and BAUD-Rate Accuracy:
When a serial data is transmitted asynchronously, the data stream is

generated with the transmitter‘s clock. The receiver must synchronize the
incoming data stream to the receiver‘s clock.

www.rejinpaul.com
An example of the transmission of 4 bytes is show in the figure 11.1. each 8 bit
is framed by a START bit and STOP bit. For transmission at 9,600Bd, each of
these bits lasts for a bit time(BT) of 1/9,600 second. Before the first frame is
transmitted, the line from the transmitter‘s TX output to the recivers‘S RX
input idles high. The receiver monitors its RX input, waiting for the line to drop
low because of the transmission of the (low) START bit. The receiver
synchronizes on this high to low transition. Then the receiver reads the 8 bit of
serial data by sampling the RX input at 1.5BT,2.5BT, 3.5BT, 4.5BT, 6.5BT,
7.5BT, AND 8.5BT as show in the figure 1101. It checks that the framing of
The byte has been interpreted correctly by reading the high STOP bit at 9.5BT.
if the RX line is actually low at this time , for whatever the reason, the receiver
sets a flag to indicate a framing error. Regardless of whether or not a framing
error occurs, the receiver then begins again, resynchronizing upon the next
high to low transition of the RX line. Because of this resynchronization, the
receiver can generate its own baud-rate clock that only approximate the
transmitter‘s baud-rate clock and yet the reciver can recover the serial data
perfectly.

www.rejinpaul.com
The PIC‘s baud-rate clock operates at either of two ranges, called high
speedbaud rate and low speed baud rate. Using the low speed baud rate, the
reciver looks for STOP to START transition by sampling its RX input every
1/16th of one of its bit times, as show in the figure 11.2, then it counts six
more of these sample times to point where it reads a cluster of three closely
spaced samples of RX and votes among them to ensure that it is seeing the low
START bit. There after, it reads successive clusters of three samples spaced 16
sample time apart.in effect, the reciver is reading its input every 16 periods of
its sample clock.
BAUD-RATE Selection:
A desired baud rate can be approximated by the UART‘s baud rate generator. If
the crystal clock rate were selected to be carefully chosen multiple pf the
desired baud rate, then the baud rate generator would produce the desired
baud rate exactly. The clock rates used by microchip to characterized the three
speed grades of their parts
4MHz 10MHz 20MHz

www.rejinpaul.com
These speed grades do not provide exact multiples of the popular 9,600Bd and
19,200Bd rate commonly used by personal computer serial port. However, the
flexibility of the baud rate generator circuitry permits close approximation to
both 9,600 Bd and 19,200Bd with any of the standard clock rates. The baud
rate is derived from the crystal rate using an 8 bit presentable divider and a
fixed diver of either 16 or 64, as show in the figure 11.4b. the results are
tabulated in the figure 11.4a. even in the worst case , the percent error of the
approximate baud rate is only one-third of the percent error that cannot be
tolerated by the UART.
Nominal OSC =4MHz OSC = 10MHz OSC = 20MHz

Baud Rate BRGH SPBRG %error BRGH SPBRG %error BRGH SPBRG %error
9,600 baud 1 25 +0.16% 1 64 +0.16% 1 129 +0.16%
19,200 baud 1 12 +0.16% 1 32 -1.4% 1 64 +0.16%
Figure: 114.a Register contents and accuracy of approximated baud rate
For BRGH = 1(high speed baud rate)
For BRGH =0 (low speed baud rate)
Figure: 114.b Relation between OSC,BRGH, SPBRG, and Bayd Rate
UART Data Handling Circuitry:
The transmitted data circuit show in the figure 11.5a. to transmit a byte of
data serially from TX pin, the byte written to TXREG register. Assuming there
is not already data in TSR (transmit shift register), the content of TXREG will
be automatically transferred to the TSR, making TXREG available for a second
byte even as the first byte is being shifted out of the TX pin, framed by START
and STOP bits

www.rejinpaul.com

www.rejinpaul.com
The receiver data circuit is similar, with received data shifted into RSR(receiver
shift register) when it is in place, the STOP bit is checked and an error flag is
set if the STOP bit does not equal one. In any case, the receiver byte is
automatically transferred into a 2 byte FIFO. If the FIFO was initially empty,
the receiver byte will fall through to the RCREG (receiver register) virtually
immediately, where it is ready to be read by the CPU. If the CPU is slow in
reading the RCREG, a second byte can be received at the RX pin. When it is in
place in the RSR, it will follow the first byte into the 2 byte FIFO. At that point,
the FIFO is full. If the third byte enters the RX pin and is shifted all the way
across the RSR before at least one of the two bytes in the FIFO has been read,
then the new byte will be lost. An overflow error flag will be set, alerting the
receiver software of the loss of a byte of data
At 9600Bd, it takes 10/9600 second, or just a little longer than a millisecond,

to receive each byte. If the receiver bytes are handled under interrupt control,
each byte should be easily handled in a timely fashion, well before an overrun
error can even occur. No oher interrupt handler should be permitted to lock
out.
UART Initialization:
The register involved with UART is show in the figure 11.6. the data direction
bit associated with the RC6/TX pin and the RC7/RX pin must both be set up
as inputs, with ones in bits 6 and 7 of the TRISC register, the setting of these
two bits disable the general I/O port output circuitry associated with these two
pins( the handling of these bits of TRISC stands in contrast to the clearing of
bits 3 and 5 of TRISC in support of the serial peripheral interface output pins)
The UART‘s baud rate and its transmit and receive funcations are initialized by
writes to SPBRG, TXSTA, and RCSTA, as show in figures 11.4 and 11.6 at 9600
Bd, each transfer takes about a millisecond, so sending or receiving a string of
characters is best carried out under interrupt control. The flag and interrupt
enable bits of the PIR1,PIE1 and INTCOON register control the timing of CPU
interactions with the UART.
UART Use:
A major application for the PIC‘s UART is to provide a two-wire(plus ground)

serial interface to a personal computer. The circuit of figure 11.7 uses
mortorola chip to translate between the ov to a =5V logic level signal swings on
the PIC‘s RX and TX pins and ±10V signal swings that support the RS-232
interface requirement. Both the PIC and the PC should be setup for the same
baud rate and for one start bit, 8data bits, one stop bit, and no parity bit

www.rejinpaul.com

www.rejinpaul.com

www.rejinpaul.com
Given this setup, the PIC will respond to PCIF interrupts by reading each byte
from the RCREG register sent by the PC. The RCIF flag will clear itself when the
byte read from RCREG leaves the receive circuit‘s FIFO empty.
The PIC sends out a string of bytes by writing them, one by one under
interrupt control, to TXREG , the TXIF flag takes care of itself, clearing
automatically when TXREG is written to, and setting again as the data written
TXREG are automatically transferred to the transmit shift register, at the
completion of sending the string of bytes to the PC, the TXIE bit in the PIE1
register is cleared to disable further ‖transmit‖ interrupts until another string
needs to be sent to the PC

www.rejinpaul.com
Another application of the PIC UART is to couple two PIC‘s together. In this way
some of the work that would be done by one PIC is off loaded to a second PIC,
figure 11.8 show s this connection of two PIC‘s, using the maximum possible
baud rate to obtain fast coupling between the two PICs with in 40 internal
clock cycles, what is written into one PIC‘s TXREG register appears in the
other PIC‘s RCREG register.
Carrying out transfers at this fast rate calls for some precautions is need if
overrun error are to avoided, given PICs that are try to carry out the task in
additional to monitoring the UART‘s RCREG register. A given PIC can only
receive 2 bytes into its FIFO without reading them immediately. Any further
bytes received will be discard until the earlier bytes are read out of the FIFO,
making room for new bytes

www.rejinpaul.com
Keypad:
A keypad is a matrix of push-buttons aligned in rows and columns to provide
user input, a 3x4 keypad is basically formed like the following schematic:
it consists of 3 columns and 4 rows, hence the name, whenever the user taps
one button, the column and the row corresponding to that button are shorted,
for example, if a user chooses to tap the "5" button, col2 and row2 are shorted,
if a users picks "0" button, col2 and row4 are shorted, and so on. the method
used to read such input is called Scanning, you connect the rows and the
columns to the microcontroller, you set the columns as outputs, rows as
inputs (or vice versa) and you start feeding a pattern of inputs to the columns
while checking the readings of the rows.
For example, if you tied all rows through pull-up resistors to Vcc, all row
inputs are typically 1s (1111), now if you start feeding columns with the
following pattern, 011, 101, 110, you can check which row conducts the 0
signal to the controller, thus, you'll detect the shorted row and column.
example: if a user presses button "6", when I feed the columns by 011, the
rows output would be 1111, when I feed it by 101, the rows output would be
also 1111, but when I feed it by 110, button "6" will conduct the 0 signal, thus
my rows output would be 1011, Knowing that I used col3 to conduct the 0
signal, and I got the 0 signal at row2, I'll know the pressed button is "6".
Using PIC-C to Read a Keypad:

PIC-C provides a common library for reading keypads named kbd.c, all you
have to do is to include the kbd.c library in your code, and use the function
kbd_getc() to scan the keypad.

www.rejinpaul.com
kbd.c library uses either port D or port B to interface the keypad, you'll find the
schematic for the interface further below, but if you need to use other ports to
interface your keypad, you'll have to use a user defined library, you can find
those on ccsinfo.com forum, or you can write your own library (which is pretty
simple).
Note: the kbd_getc(); function returns the ASCII code of the pressed button
(returns a character).
The Alphanumeric LCD:

An alphanumeric LCD is a type of LCDs that only displays English letters,
numbers and some ASCII characters, those LCDs contains a controller unit
that processes the input and forms the displayed character on the LCD, most
alphanumeric LCDs have a parallel interface, some other LCDs have a serial
interface to minimize the construction complicity.
Alphanumeric LCDs comes in different sizes, the size describes the number of
characters an LCD can display, common sizes are 16x2, 20x2, 16x4, 20x4
..etc. a 16x2 has 2 rows and can display 16 characters on each row.
Parallel LCD Pinout:

Parallel LCDs typically have 16 pins as following:
- Power Supply Pins:
Vss : Ground reference (0V)
Vcc : +5V supply voltage
Vee : Contrast pin, typically connected to GND via a resistor (0Ω - 5kΩ),
change the value to change the contrast.
- Control Bus Pins:
RS : Register Select, used to set the LCD either to command mode or to data
mode.
R/W : Read/Write select, used either to read characters from LCD or to write
new characters.
E : Active low Enable signal.
- Data Bus Pins:
D0-D7 : used to pass 8Bit character data, you have the choice either to use
only 4Bit bus (D4-D7) or to use the whole data bus.
- Backlight Voltage Pins:
A : Anode (+5V)

www.rejinpaul.com
K : Cathode (0V)
used to turn ON/OFF the backlight LED of your LCD.
Using PIC-C to Write to LCD:

To write to an LCD you need a software library, you can either go with the
original lcd.c library that comes with your compiler's software bundle (which I
don't recommend), or you can use flex_lcd.c libraries written by PCM
programmer, here:
The flex_lcd.c library gives you the opportunity to select PIC pins to be
connected to the LCD by changing the definers at the top of the library.
After including the flex_lcd.c library in your code, you should initialize the LCD
at the beginning of your main code using the function lcd_init();
Then you can use the function lcd_putc("Your String"); to display your
strings.
The Schematic:
Click on the schematic to zoom in,

I've selected the LCD pinouts in flex_lcd as following:
#define LCD_DB4 PIN_B4

#define LCD_E PIN_B3

#define LCD_RS PIN_B1

www.rejinpaul.com
#define LCD_RW PIN_B2
and commented out

// #define USE_LCD_RW 1
The PIC-C Code:
/*
PIC16F877A interface to 3x4 Keypad and 16x2 LCD
Badr Ghatasheh
[email protected]
*/
#include <16f877a.h>
#fuses XT,NOLVP,NOWDT,NOPROTECT
#use delay(clock=4000000)
#include "flex_lcd.c"
#include <kbd.c>
void main()
{
char k=0; // Character k to store keypad input
delay_ms(1);
/* Peripherals Configurations */
lcd_init(); // Turn LCD ON, along with other initialization
commands
kbd_init(); // Initialize Keypad
lcd_gotoxy(1,1); // point LCD cursor to col1 row1

lcd_putc("Hello World !!"); // print on LCD
lcd_gotoxy(1,2); // point LCD cursor to col1 row2
while(1) // infinite loop

{
k = kbd_getc(); // read keypad input (if exists)
if(k!=0) // if key captured
{
lcd_putc(k); // print captured key to lcd
k=0; // reset k for another loop round
delay_ms(250); // delay between key presses
}
delay_ms(1); // delay_between read trials
}
}

www.rejinpaul.com

www.rejinpaul.com
UNIT IV
INTRODUCTION TO ARM PROCESSOR
ARM Architecture –ARM programmer‟s model –ARM Development tools-
Memory Hierarchy –ARM Assembly Language Programming–Simple
Examples–Architectural Support for Operating systems
ARM introduction:
The first ARM processor was developed at Acorn Computers Limited, of
Cambridge, England, between October 1983 and April 1985. At that time,
and until the formation of Advanced RISC Machines Limited (which later was
renamed simply ARM Limited) in 1990, ARM stood for Acorn RISC Machine.
Acorn had developed a strong position in the UK personal computer market
due to the success of the BBC (British Broadcasting Corporation)
microcomputer. The BBC micro was a machine powered by the 8-bit
6502microprocessor and rapidly became established as the dominant
machine in UKschools following its introduction in January 1982 in support
of a series of television programmers broadcast by the BBC. It also enjoyed
enthusiastic support in the hobbyist market and found its way into a number
of research laboratories and higher education establishments. Following the
success of the BBC micro, Acorn's engineers looked at various
microprocessors to build a successor machine around, but found all the
commercial offerings lacking. The 16-bit CISC microprocessors that were
available in 1983 were slower than standard memory parts. They also had
instructions that took many clock cycles to complete (in some cases, many
hundreds of clock cycles), giving them very long interrupt latencies. The BBC
micro benefited greatly from the 6502's rapid interrupt response, so Acorn's
Designers were unwilling to accept a retrograde step in this aspect of the
processor's performance. As a result of these frustrations with the
commercial micro processor offerings, the design of a proprietary
microprocessor was considered. The major stumbling block was that the
Acorn team knew that commercial microprocessor projects had absorbed
hundreds of man-years of design effort. Acorn could not contemplate an
investment on that scale since it was a company of only just over 400
employees in total. It had to produce a better design with a fraction of the
design effort, and with no experience in custom chip design beyond a few
small gate arrays designed for the BBC micro. Into this apparently impossible
scenario, the papers on the Berkeley RISCI fell like a bolt from the blue. Here
was a processor which had been designed by a few postgraduate students in
under a year, yet was competitive with the leading commercial offerings. It
was inherently simple, so there were no complex instructions to ruin the
interrupt latency. It also came with supporting arguments that suggested it
could point the way to the future, though technical merit, however well
supported by academic argument, is no guarantee of commercial success.
The ARM, then, was born through a serendipitous combination of factors,
and became the core component in Acorn's product line. Later, after a
judicious modification of the acronym expansion to Advanced RISC Machine,
it lent its name to the company formed to broaden its market beyond Acorn‟s
product range. Despite the change of name, the architecture still remains
close to the original Acorn design

www.rejinpaul.com
UNIT -4 INTRODUCTION TO ARM PROCESSOR
ARM Architecture:
Architectural overview
The ARM is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is
based on Reduced Instruction Set Computer (RISC) principles, and the
instruction set and related decode mechanism are much simpler than those
of micro programmed Complex Instruction Set Computers (CISC). This
simplicity results in a high instruction throughput and impressive real-time
2
www.rejinpaul.com

interrupt response from a small and cost-effective processor core. Pipeline
techniques are employed so that all parts of the processing and memory
systems can operate continuously. Typically, while one instruction is being
executed, its successor is being decoded, and a third instruction is being
fetched from memory. The ARM processor also employs a unique
architectural strategy known as Thumb, which makes it ideally suited to
high-volume applications with memory restrictions or applications where
code density is an issue. The key idea behind Thumb is that of a super-
reduced instruction set. Essentially, the ARM processor has two instruction
sets:
• The standard 32-bit ARM set.

• A 16-bit Thumb set.
The Thumb set‟s 16-bit instruction length allows it to approach twice the
density of standard ARM code while retaining most of the ARM‟s performance
advantage over a traditional 16-bit processor using 16-bit registers. This is
possible because Thumb code operates on the same 32-bit register set as
ARM code. Thumb code is able to provide up to 65 % of the code size of ARM,
and 160 % of the performance of an equivalent ARM processor connected to a
16-bit memory system. The particular flash implementation in the
LPC2141/42/44/46/48 allows for full speed execution also in ARM mode. It
is recommended to program performance critical and short code sections
(such as interrupt service routines and DSP algorithms) in ARM mode. The
impact on the overall code size will be minimal but the speed can be
increased by 30 % over Thumb mode.
ARCHITECTURE OF ARM PROCESSORS:

The ARM 7 processor is based on Von Neman model with a single bus for
both data and instructions.(The ARM9 uses Harvard model).Though this will
decrease the performance of ARM, it is overcome by the pipe line concept.
ARM uses the Advanced Microcontroller Bus Architecture (AMBA) bus
architecture. This AMBA include two system buses: the AMBA High-Speed
Bus (AHB) or the Advanced System Bus (ASB), and the Advanced Peripheral
Bus (APB).
The ARM processor consists of
 Arithmetic Logic Unit (32-bit)
  One Booth multiplier(32-bit)
 One Barrel shifter
 One Control unit
 Register file of 37 registers each of 32 bits.
In addition to this the ARM also consists of a Program status register of 32
bits, Some special registers like the instruction register, memory data read
and write register and memory address register ,one Priority encoder which is
used in the multiple load and store instruction to indicate which register in
the register file to be loaded or stored and Multiplexers etc.
Arithmetic Logic Unit (ALU)
The ALU has two 32-bits inputs. The first comes from the register File
while the other comes from the shifter. ALU outputs modify the status
register flags. The V-bit output goes to the V flag as well as the Cout goes to
3
www.rejinpaul.com

the C flag. While the most significant bit actually represents the S flag, the
ALU output is NORed to get the Z flag.
Booth multiplier
Booth„s Algorithm is a smart move for multiplying signed numbers. It initiate
with the ability to both add and subtract there are multiple ways to compute
a product . Booth„s algorithm is a multiplication algorithm that utilizes two„s
complement notation of signed binary numbers for multiplication.
Barrel shifter
The barrel shifter is a functional unit which can be used for shift a data word
by a specified number of bits. It provides five types of shifts and rotates
which can be applied to Operand
1. LSL – Logical Shift Left
2. LSR – Logical Shift Right
3. ASR – Arithmetic Shift Right
4. ROR – Rotate Right
5. RX – Rotate Right Extended
Control unit:
Control unit (CU) within the CPU that coordinates the actions of the CPU's
component. At the heart of the CU is a clock that emits a square wave of a
fixed frequency. Using the clock's output, the CU sends control signals to
various parts of the CPU. These signals cause various actions to take place at
specified times.
ARM Registers
ARM has a total of 37 registers .In which - 31 are general-purpose registers of
32-bits, and six status registers .But all these registers are not seen at once.
The processor state and operating mode decide which registers are available
to the programmer. At any time, among the 31 general purpose registers only
16 registers are available to the user. The remaining 15 registers are used to
speed up exception processing.
Data Registers- R0-R15
ARM architecture are inbuilt with register for data processing it has both
general purpose and special purpose register as follows R0-R12-General
Purpose Registers
R13-R15-Special function registers of which,R13
- Stack Pointer, refers to entry pointer of Stack.
R14 - Link Register, Return address is put to this when ever a subroutine is
called.
R15 - Program Counter
4
www.rejinpaul.com
In addition there are 2 status registers

CPSR - Current program status register, status of current execution
isstored.
SPSR - Saved program Status register, includes status of program as
wellas processor.
CPSR(Current program status register)

The ARM core uses the CPSR register to monitor and control internal
operations. The CPSR is a dedicated 32-bit register and resides in the register
file. The CPSR is divided into four fields, each of 8 bits wide: flags, status,
extension, and control. The extension and status fields are reserved for future
use. The control fields contain the processor mode, state, and interrupt mask
bits. The flags field contains the condition flags. The 32-bit CPSR register is
shown below.
Conditional Code Flags
N - Negative Result from ALU

Z - Zero result from ALU
5
www.rejinpaul.com

C - ALU operation carried out
V - ALU operation overflowed
Interrupt Enable Bits
I - IRQ, Interrupt Disable

F - FIQ, Disable Fast Interrupt
T- Bit
If
T=0, Processor in ARM Mode.
T=1, Processor in THUMB Mode
Mode Bits
Specifies the processor Modes.
M[4:0] Mode Accessible register set

10000 User PC, R14..R0 CPSR
10001 FIQ PC, R14_fiq..R8_fiq, R7..R0 CPSR, SPSR_fiq
10010 IRQ PC, R14_irq..R13_irq, R12..R0 CPSR, SPSR_irq
10011 Supervisor PC, R14_svc..R8_svc, R7..R0 CPSR, SPSR_svc
10111 Abort PC, R14_abt..R8_abt, R7..R0 CPSR, SPSR_abt
11011 Undefined PC, R14_und..R8_und, R7..R0 CPSR, SPSR_und
(1) User mode (usr: the normal program execution state

(2) FIQ mode (fiq) : designed to support a data transfer or channel process
(3) IRQ mode (irq): used for general-purpose interrupt handling
(4) Supervisor mode (svc): a protected mode for the operating system
(5) Abort mode (abt): entered after a data or instruction prefetch abort
(6) Undefined mode (und): entered when an undefined instruction is executed
SPSR ( Saved Program Status Register)

  All processor modes except system and user mode have an SPSR.
  
Records the pre-exception value of the CPSR.

Upon taking an exception, the CPSR
 is copied to the SPSR of the processor
mode the exception is taken to.
This is useful because the exception handler is able to restore the CPSR to
the value prior to taking the exception, as well as being able to examine the
CPSR in general.
Load Store Architecture

ARM can support for load store architecture, only load and store instructions
access the memory, all other instructions use registers as operands
 Load To load a value from memory, you copy the data from memory
 into a register.
 Store To store a value to memory, you copy the data from a register to
memory.
6
www.rejinpaul.com
ARM Buses:
Register Bank is connected to ALU via two data paths.
A bus
B bus
B bus goes via Barrel Shifter. It preprocesses data from source register by
shifting left or right or even rotating. The Program Counter is that part of
register Bank , that generate address. Registers in register bank are
symmetric i.e., they can have both data and address. Program counter
generates address for next function.
Address Incrementer block, increments or decrements register value
independent of ALU. There is an Instruction Decode and control block that
provides control signals.
Pipeline
Pipeline is the mechanism used by the RISC processor to execute
instructions at an increased speed. This pipeline speeds up execution by
fetching the next instruction while other instructions are being decoded and
executed. During the execution of an instruction, the processor fetches the
instruction .It means loads an instruction from memory. And decodes the
instruction i.e. identifies the instruction to be executed and finally Executes
the instruction and writes the result back to a register.
Fetch: the instruction is fetched from memory and placed in the instruction
pipeline.
Decode:the instruction is decoded and the datapath control signals prepared
for the next cycle. In this stage the instruction 'owns' the decode logic but not
the datapath.
Execute: the instruction 'owns' the datapath; the register bank is read, an
operand shifted,the ALU result generated and written back into a destination
register.
7
www.rejinpaul.com
Features of Arm Processors
The ARM processors are based on RISC architectures and this architecture
has provided small implementations, and very low power consumption.
Implementation size, performance, and very low power consumption remain
the key features in the development of the ARM devices.
The typical RISC architectural features of ARM are :
  A large uniform register file

 A load/store architecture, where data-processing operations only
operate on register contents, not directly on memory contents
 Simple addressing modes, with all load/store addresses being
determined from register contents and instruction fields only uniform
and fixed-length instruction fields, to simplify instruction decode.
 Control over both the Arithmetic Logic Unit (ALU) and shifter in most
data-processing instructions to maximize the use of an ALU and a
 shifter
 Auto-increment and auto-decrement addressing modes to optimize
program loops
 Load and Store Multiple instructions to maximize data throughput
 Conditional execution of almost all instructions to maximize execution
throughput.
ARM programmer’s model
Introduction
Our ARM has a 32-bit data bus and a 32-bit address bus. The data types the
Processor supports are Words (32 bits), where words must be aligned to four
Byte boundaries. Instructions are exactly one word, and data operations (e.g.
ADD) are only performed on word quantities. Load and store operations
can transfer words.
8
www.rejinpaul.com

Our ARM supports six modes of operation:
(1) User mode (usr): the normal program execution state

(2) FIQ mode (fiq): designed to support a data transfer or channel process
(3) IRQ mode (irq): used for general-purpose interrupt handling
(4) Supervisor mode (svc): a protected mode for the operating system
(5) Abort mode (abt): entered after a data or instruction prefetch abort
(6) Undefined mode (und): entered when an undefined instruction is executed
The ARM 7 architecture has a total of six different operating modes, as shown
below. These modes are protected or exception modes which have associated
interrupt sources and their own register sets
User: This mode is used to run the application code. Once in user mode the
CPSR cannot be written to and modes can only be changed when an
exception is generated.
FIQ: (Fast Interrupt reQuest) This supports high speed interrupt handling.
Generally it is used for a single critical interrupt source in a system
IRQ: (Interrupt ReQuest) This supports all other interrupt sources in a
system
Supervisor: A “protected” mode for running system level code to access
hardware or run OS calls. The ARM enters this mode after reset
Abort: If an instruction or data is fetched from an invalid memory region, an
abort exception will be generated
Undefined Instruction: If a FETCHED opcode is not an ARM instruction, an
undefined instruction exception will be generated
The User registers R0-R7 are common to all operating modes. However FIQ
mode has its own R8 –R14 that replace the user registers when FIQ is
entered. Similarly, each of the other modes have their own R13 and R14 so
that each operating mode has its own unique Stack pointer and Link register.
The CPSR is also common to all modes. However in each of the exception
modes, an additional register - the saved program status register (SPSR), is
added. When the processor changes the current value of the CPSR stored in
the SPSR, this can be restored on exiting the exception mode.
9
www.rejinpaul.com

Figure: Register used under different modes of operation
Entry to the Exception modes is through the interrupt vector table.
Exceptions in the ARM processor can be split into three distinct types.
(i) Exceptions caused by executing an instruction, these include software
interrupts, undefined instruction exceptions and memory abort exceptions
(ii) Exceptions caused as a side effect of an instruction such as a abort
caused by trying to fetch data from an invalid memory region.
(iii) Exceptions unrelated to instruction execution, this includes reset, FIQ
and IRQ interrupts.
The format of the Program Status Registers is shown in Figure (3-2). The N,
Z, C and V bits are the condition code flags. The condition code flags in the
CPSR may be changed as a result of arithmetic and logical operations in the
processor and may be tested by all instructions to determine if the
Instruction is to be executed The I and F bits are the interrupt disable bits.
The I bit disables IRQ interrupts when it is set and the F bit disables FIQ
interrupts when it is set. The M0, M1, M2, M3 and M4 bits (M [4:0]) are the
mode bits, and these determine the mode in which the processor operates.
The interpretation of the mode bits is shown in Table (3-1). Not all
combinations of the mode bits define a valid processor mode. Only those
explicitly described shall be used.
Exceptions

 ARM supports a range of interrupts, traps, and supervisor
 calls – all are
grouped under the general heading of exceptions

Exceptions arise whenever there is a need for the normal flow of
 
program execution to be broken, the processor can be diverted to
handle the interrupt from the peripherals

So the processor move to handle the exceptions exception routine has
completed so that the original program can be resumed. Many
exceptions may arise at the same time
FIQ Exceptions
The FIQ (Fast Interrupt reQuest) exception is externally generated by taking

the nFIQ input LOW. This input can accept asynchronous transitions, and is
delayed by one clock cycle for synchronization before it can affect the
processor execution flow
IRQ Exceptions

www.rejinpaul.com
10

www.rejinpaul.com

The IRQ (Interrupt ReQuest) exception is a normal interrupt caused by a
LOW
Level on the nIRQ input. It as a lower priority than FIQ, and is masked out
When a FIQ sequence is entered. Its effect may be masked out at any time by
Setting the I bit in the CPSR
Abort Exceptions
An ABORT can be signaled by the external ABORT input. ABORT indicates

that the current memory access cannot be completed. For instance, in a
virtual memory system the data corresponding to the current address may
have been moved out of memory onto a disc
(1) If the abort occurred during an instruction prefetch (a Prefetch Abort), the
prefetched instruction is marked as invalid but the abort exception does not
occur immediately
(2) If the abort occurred during a data access (a Data Abort), the action
depends on the instruction type.
(a) Single data transfer instructions (LDR, STR) will write back modified
base registers and the Abort handler must be aware of this.
(b) Block data transfer instructions (LDM, STM) complete. All register
overwriting is prevented after the Abort is indicated, which means in
particular that R15 (which is always last to be transferred) is preserved in an
aborted LDM instruction.
Software interrupt
The software interrupt instruction (SWI) is used for getting into Supervisor
mode, usually to request a particular supervisor function. When a SWI is
executed, ARM performs the following:
(1) Saves the address of the SWI instruction plus 4 in R14_svc; saves CPSR in
SPSR_svc
(2) Forces M[4:0]=10011 (Supervisor mode) and sets the I bit in the CPSR
(3) Forces the PC to fetch the next instruction from address 0x08
Undefined instruction trap
When the ARM comes across an instruction that it cannot handle, it offers it
to any coprocessors that may be present. If a coprocessor can perform this
instruction but is busy at that time, ARM will wait until the coprocessor is
ready or until an interrupt occurs. If no coprocessor can handle the
instruction then ARM will take the undefined instruction trap when ARM
takes the undefined instruction trap it performs the following:
(1) Saves the address of the Undefined or coprocessor instruction plus 4 in
R14_und; saves CPSR in SPSR_und.
(2) Forces M[4:0]=11011 (Undefined mode) and sets the I bit in the CPSR
(3) Forces the PC to fetch the next instruction from address 0x04
11
www.rejinpaul.com
Vector Summary
Address Exception Mode on entry

0x00000000 Reset Supervisor
0x00000004 Undefined instruction Undefined
0x00000008 Software interrupt Supervisor
0x0000000C Abort (prefetch) Abort
0x00000010 Abort (data) Abort
0x00000014 -- reserved -- --
0x00000018 IRQ IRQ
0x0000001C FIQ FIQ
Exception Priorities
When multiple exceptions arise at the same time, a fixed priority system
determines the order in which they will be handled:
(1) Reset (highest priority)
(2) Data abort
(3) FIQ
(4) IRQ
(5) Prefetch abort
(6) Undefined Instruction, Software interrupt (lowest priority)
ARM Assembly language Programming:

The ARM processor is very easy to program at the assembly level,
though for most applications it is more appropriate to program in a high-level
language such as C or C++. Assembly language programming requires the
programmer to think at the level of the individual machine instruction. An
ARM instruction is 32 bits long
37 registers
– 31 general 32 bit registers, including PC
– 6 status registers
– 15 general registers (R0 to R14), and one status registers and program
counter are visible at any time –when you write user-level programs
•R13 (SP)
•R14 (LR)
•R15 (PC)
•The visible registers depend on the processor mode
•The other registers (the banked registers) are switched in to support IRQ,
FIQ, Supervisor, Abort and undefined mode processing
12
www.rejinpaul.com
  R0 to R15 are directly accessible

  R0 to R14 are general purpose

  R13: Stack point (sp) (in common)

  
Individual stack for each processor mode
  R14: Linked register (lr)

  R15 holds the Program Counter (PC)


 CPSR - Current Program
 Status Register contains condition code flags and
the current mode bits
 
5 SPSRs (Saved Program Status Registers) which are loaded with CPSR
when an exceptions occurs
When writing user-level programs, only the 15 general-purpose 32-bit
registers (r0 to r14), the program counter (r15) and the current program
status register (CPSR) need be considered. The remaining registers are used
only for system-level programming and for handling exceptions (for example,
interrupt).
ARM INSTRUCTION SET

ARM instructions process data held in registers and only access memory with
load and store instructions. ARM instructions commonly take two or three
operands. For example ,the ADD instruction adds the two values stored in
registers r1 and r2 (the source registers). It stores the result to register r3
(the destination register). ADD r3, r1, r2
ARM instructions are classified into data processing instructions, branch

instructions, load-store instructions, software interrupt instruction, and
13
www.rejinpaul.com

program status register instructions. The instruction sets are majorly
classified in to
  Data Processing instruction

  Data transfer instruction

 
Control flow instruction
Data Processing instruction:

ARM data processing instructions enable the programmer to perform
arithmetic and logical operations on data values in registers. Data processing
instruction are the only instruction which modifies the data values. Data
processing instruction typically require two operands for produce a single
result.
Here are some rules which allply to ARM data processing instruction

 All operands are
 32 bits wide and come from registers or are specified as
literals values

The result, produce by the data processing instruction also has 32 bits
 wide and is placed in a register. long multiplyinstructions produce a
64-bit result;they are stored in the two register
 
Each of the operand registers and the result register are independently
specified in the instruction. That is, the ARM uses a '3-address' format
for these instructions
Simple Register operands:
A typical RAM data processing instruction written in assembly
language using register for example:
ADD r0, r1, r2 ; r0 = r1+ r2
The semi colon indicatres every thing right side to the semi colon is command
and it should be ignored by the assembler
The data processing instruction explain the data value in r1 and r2 is added
and the result is store in r0 register.
While eriting the assembly language source codecare must be need to write
the operands in the correct order that is result register in first followed by
first and second operands.
This instruction is executed and change the system state at the distination
register, optinally the N,Z,C 7 V flags in CPSR also change.
Arithmetic operations.
These instructions perform binary arithmetic (addition, subtraction and
reverse
subtraction, which is subtraction with the operand order reversed) on two
32-bit operands. The operands may be unsigned or 2's-complement signed
integers; the carry-in, when used, is the current value of the C bit in the
CPSR.

www.rejinpaul.com
14

www.rejinpaul.com
Bit-wise logical operations.

These instructions perform the specified Boolean logic operation on each bit
pair of the input operands
Register movement operations.

These instructions ignore the first operand, which is omitted from the
assembly language format, and simply move the second operand to the
destination.
Comparison operations.
These instructions do not produce a result but just set the condition code
bits (N, Z, C and V) in the CPSR according to the selected operation.
Immediate operands:
Instead of adding two registers, we simply wish to add a constant to a register
we can replace the second source operand with an immediate value, which is
a literal constant, preceded by '#':
ADD r3, r3, ; r3 := r3

#1 +1
AND r8, r7, ; r8 :=
#&ff r7[7:0]
The first example also illustrates that although the 3-address format allows
source and destination operands to be specified separately, they are not
15
www.rejinpaul.com

required to be distinct registers. The second example shows that the
immediate value may be specified in hexadecimal (base 16) notation by
putting '&' after the '#'.
Shifted register operands:

Shifts and rotates are specified as left or right, logical or arithmetic. A left
shift is one where the bits, as written on the page, are moved by one or more
bits to the left, i.e. towards the more significant end. Zero-valued bits are
shifted in at the right and the bits at the left are lost, except for the final bit
to be shifted out, which is stored in the carry flag.
A right shift is in the opposite direction, the bits moving from the more
significant end to the lower end, or from left to right on the page. Again the
bits shifted out are lost, except for the last one which is put into the carry. If
the right shift is logical then zeros are shifted into the left end. In arithmetic
shifts, a copy of bit 31 (i.e. the sign bit) is shifted in.
LSL #n Logical shift left immediate
n is the number of bit positions by which the value is shifted. It has the value
0..31. An LSL by one bit may be pictured as below:
After n shifts, n zero bits have been shifted in on the right and the carry is
set to bit 32-n of the original word.
LSR #n Logical shift right immediate
1..32. An LSR by one bit is shown below:
After n of these, n zero bits have been shifted in on the left, and the carry flag
is set to bit n-1 of the original word.
ASR #n Arithmetic shift right immediate
1..32. An ASR by one bit is shown below
16
www.rejinpaul.com
If ' sign' is the original value of bit 31 then after n shifts, n 'sign' bits have
been shifted in on the left, and the carry flag is set to bit n-1 of the original
word.
ROR #n Rotate right immediate
n is the number of bit positions to rotate in the range 1..31. A rotate right by
one bit is shown below:
after n of these rotates, the old bit n is in the bit 0 position; the old bit (n-1) is
in bit 31 and in the carry flag.
RRX Rotate right one bit with extend
This special case of rotate right has a slightly different effect from the usual
rotates. There is no count; it always rotates by one bit only. The pictorial
representation of RRX is:
he old bit 0 is shifted into the carry. The old content of the carry is shifted
into bit 31.
Setting the condition codes:
Any data processing instruction can set the condition codes. The instruction
is executed conditionally, according to the status flags in the APSR, in exactly
the same way as the comparison operations only set the condition codes, An
17
www.rejinpaul.com

arithmetic operation (which here includes CMP and CMN) sets all the flags
according to the arithmetic result. A logical or move operation does not
produce a meaningful value for C or V, so these operations set N and Z
according to the result but preserve V, and either preserve C when there is no
shift operation, or set C to the value of the last bit to fall off the end of the
shift.
Flag-Setting Example
ldr r1, =0xffffffff
ldr r2, =0x00000001
adds r0, r1, r2
The result of the operation would be 0x100000000, but the top bit is lost
because it does not fit into the 32-bit destination register and so the real
result is 0x00000000. In this case, the flags will be set as follows:
Flag Explanation
We lost some data because the result did not fit into 32 bits, so
C=1
the processor indicates this by setting C (carry) to 1.
The result is 0, which is considered positive, and so
N=0
the N (negative) bit is set to 0.
From a two's complement signed-arithmetic
viewpoint, 0xffffffff really means -1, so the operation we did was
V=0
really (-1) + 1 = 0. That operation clearly does not overflow,
so V (overflow) is set to 0.
Z=1 The result is 0, so the Z (zero) bit is set to 1.
Multiplies :
•A special form of the data processing instruction supports multiplication
•Some important differences
– Immediate second operands are not supported
–The result register must not be the same as the first source register
– If the „S‟bit is set, the C flag is meaningless
1. Multiplying two 32-bit integers gives a 64-bit result, the least

significant 32 bits of which are placed in the result register and the
rest are ignored.
2. multiplication in modulo 232 arithmetic and gives the correct result
whether the operands are viewed as signed or unsigned integers.
3. An alternative form, subject to the same restrictions, adds the product
to a running total. This is the multiply-accumulate instruction
MLA r4, r3, r2, r1 ; r4 := (r3 x r2 + r1)[31:0]
4. Multiplication by a constant can be implemented by loading the
constant into a register and then using one of these instructions
Data transfer instructions:
Data transfer instructions transfer data between registers and memory
 
Memory to register

www.rejinpaul.com
18

www.rejinpaul.com

 
Register to memory
There are three basic forms of data transfer instruction in the ARM
instruction set:
  Single register load and store instructions.

  Multiple register load and store instructions.

 
Single register swap instructions
Single register load and store instructions
These instructions provide the most flexible way to transfer single data
items between an ARM register and memory The data item may be a byte, a
32-bit word, or a 16-bit half-word.
Multiple register load and store instructions.
These instructions are less flexible than single register transfer
instructions, but enable large quantities of data to be transferred more
efficiently. They are used for procedure entry and exit, to save and restore
workspace registers, and to copy blocks of data around memory.
Single register swap instructions.
These instructions allow a value in a register to be exchanged with a
value in memory, effectively doing both a load and a store operation in one
instruction.
Register indirect addressing means that the location of an operand is held in

a register. It is also called indexed addressing or base addressing.
Register indirect addressing mode requires three read operations to access an
operand. It is very important because the content of the register containing
the pointer to the operand can be modified at runtime. Therefore, the address
is a variable that allows the access to the data structure like arrays.
  Read the instruction to find the pointer register
  Read the pointer register to find the operand address
 Read memory at the operand address to find the operand
Some examples of using register indirect addressing mode:
LDR R2, [R0] ; Load R2 with the word pointed by R0

-------------------------------------------------------------------------------------
STR R2, [R3] ; Store the word in R2 in the location pointed by R3
Register Indirect Addressing with an Offset
ARM supports a memory-addressing mode where the effective address of an
operand is computed by adding the content of a register and a literal offset
coded into load/store instruction. For example,
Instruction Effective Address
-------------------------------------------------------------------------------------
LDR R0, [R1, #20] R1 + 20 ; loads R0 with the word pointed at by R1+20
Single register load and store instructions

These instructions compute an address for the transfer using a base register,
which should contain an address near to the target address, and an offset
which may be another register or an immediate value.
the base registers are incremented by 4 (bytes), since this is the size of a
word. If the base register was word-aligned before the increment, it will be
word-aligned afterwards too. All load and store instructions could use just
this simple form of register-indirect addressing. However, the ARM

www.rejinpaul.com
19

www.rejinpaul.com

instruction set includes more addressing modes that can make the code more
efficient.
Multiple register data transfers
The ARM and Thumb instruction sets include instructions that load and
store multiple registers. These instructions can provide a more efficient way
of transferring the contents of several registers to and from memory than
using single register loads and stores.
Multiple register transfer instructions are most often used for block copy and
for stack operations at subroutine entry and exit. The advantages of using a
multiple register transfer instruction instead of a series of single data transfer
instructions include:
  Smaller code size.
 A single instruction fetch overhead, rather than many instruction
fetches.
 On uncached ARM processors, the first word of data transferred by a
load or store multiple is always a nonsequential memory cycle, but all
subsequent words transferred can be sequential memory cycles.
Sequential memory cycles are faster in most systems.
Stack Operations
•ARM use multiple load-store instructions to
operate stack
–POP: multiple load instructions
–PUSH: multiple store instructions
•Stack grows up or grows down
–Ascending, „A‟
–Descending, „D‟
•Full stack, „F‟: sp points to the last used address in the stack
•Empty stack, „E‟: sp points to the first unused address in the stack
20
www.rejinpaul.com
Block Copy addressing
Control Flow Instructions

•Determine which instructions get executed next
Branch and Link Instructions

•BL instruction save the return address into r14 (lr)
21
www.rejinpaul.com
•Problem
–If a subroutine wants to call another subroutine, the original return
address, r14, will be overwritten by the second BL instruction
•Solution
–Push r14 into a stack
–The subroutine will often also require some work registers, the old values in
these registers can be saved at the same time using a store multiple
instruction
22
www.rejinpaul.com
Supervisor Calls
•SWI: Software Interrupt
•The supervisor calls are implemented in system software They
are probably different from one ARM system to another
Most ARM systems implement a common subset of calls in addition to any
specific calls required by the particular application
Jump tables

Call one 
of a set of subroutines depending on a value computed by the
program
23
www.rejinpaul.com
4.5 Writing Simple Assembly language Programs
24
www.rejinpaul.com
4.6 Memory Hierarchy

4.6.1Memory size and speed
A typical computer memory hierarchy comprises several levels, each level
having a characteristic size and speed.
Memory Cost
Fast memory is more expensive per bit than slow memory, so a memory
hierarchy also aims to give a performance close to the fastest memory with an
average cost per bit approaching that of the slowest memory.
4.6.2 On-chip memory
On-chip RAM
25
www.rejinpaul.com

In many embedded systems simple on-chip RAM is preferred to cache for a
number benefits of reasons:
  It is simpler, cheaper, and uses less power.
 It has more deterministic behaviour.
The drawback with on-chip RAM cache is that it requires explicit
management by the programmer, whereas a cache is usually transparent to
the programmer.
One important advantage of on-chip RAM is that it enables the programmer
to allocate space in it using knowledge of the future processing load. A cache
left to its own devices has knowledge only of past program behaviour, and it
can therefore never prepare in advance for critical future tasks. Again, this
is a difference which is most likely to be significant when critical tasks must
meet strict real- time constraints.
The system designer must decide which the right approach for a particular
system is, taking all these factors into account. Whatever form of on-chip
memory is chosen, it must be specified with great care. It must be fast
enough to keep the processor busy and large enough to contain critical
routines, but neither too fast (or it will consume too much power) nor too
large (or it will occupy too much chip area).
4.6.3 Caches
Processor and memory speeds
In 2000 DRAM parts have a capacity of 256 Mbits per chip, with random
accesses operating at around 30 MHz. Microprocessors can request several
hundred million memory accesses per second. If the processor is so much
faster than the memory, it can only deliver its full performance potential with
the help of a cache memory.
A cache memory is a small, very fast memory that retains copies of recently
used memory values. It operates transparently to the programmer,
automatically deciding which values to keep and which to overwrite. These
days it is usually implemented on the same chip as the processor. Caches
work because programs normally display the property of locality, which
means that at any particular time they tend to execute the same instructions
many times (for instance in a loop) on the same areas of data (for instance a
stack).
Unified and Harvard caches

Caches can be built in many ways. At the highest level a processor can have
one of the following two organizations:
• A unified cache.
This is a single cache for both instructions and data, as illustrated in Figure
4.7
• Separate instruction and data caches.
This organization is sometimes called a modified Harvard architecture as
shown in Figure 4.8.
26
www.rejinpaul.com
Figure 4.7 A unified instruction and data cache
Figure 4.8 Separate data and instruction caches.

Both these organizations have their merits. The unified cache automatically
adjusts the proportion of the cache memory used by instructions according
to the current program requirements, giving a better performance than a
fixed partitioning. On the other hand the separate caches allow load and
store instructions to execute in a single clock cycle. Cache Performance
Metrics
Since the processor can operate at its high clock rate only when the memory
items it requires are held in the cache, the overall system performance
depends strongly on the proportion of memory accesses which cannot be
satisfied by the cache. An access to an item which is in the cache is called a
27
www.rejinpaul.com

hit, and an access to an item which is not in the cache is a miss. The
proportion of all the memory accesses that are satisfied by the cache is the
hit rate, usually expressed as a percentage, and the proportions that are not
is the miss rate.
The miss rate of a well-designed cache should be only a few per cent if a
modern processor is to fulfil its potential. The miss rate depends on a
number of cache parameters, including its size (the number of bytes of
memory in the cache) and its organization.
Cache organization
Since a cache holds a dynamically varying selection of items from main

memory, it must have storage for both the data and the address at which the
data is stored in main memory
The direct-mapped cache
  A line of data stored in a tag of memory

  Each memory location has a specific place in the cache.

  
Tag and data can be accessed at the same time.

Tag RAM smaller than data RAM and has a smaller access
 time allowing the
comparison to complete before accessing the data RAM
Figure 4.9 Direct-mapped cache organization.

The set associative cache
Moving up in complexity, the set-associative cache aims to reduce the
problems due to contention by enabling a particular memory item to be
stored in more than one cache location. A 2-way set-associative cache is
illustrated in Figure . As the figure suggests, this form of cache is effectively
two direct-mapped caches operating in parallel. An address presented to the
cache may find its data in either half, so each memory address may be stored
in either of two places. Each of two items which were in contention for a
single location in the direct-mapped cache may now occupy one of these
places, allowing the cache to hit on both.
The 8 Kbyte cache with 16 byte lines will have 256 lines in each half of the
cache, so four bits of the 32-bit address select a byte from the line and eight

www.rejinpaul.com
28

www.rejinpaul.com

bits select one line from each half of the cache. The address tag must
therefore be one bit longer, at 20 bits. The access time is only very slightly
longer than that of the direct-mapped cache, the increase being due to the
need to multiplex the data from the two halves.
When a new data item is to be placed in the cache, a decision must be taken
as to which half to place it in. There are several options here.
Random allocation. The decision is based on a random or pseudo-random

value.
Least recently used (LRU).The cache keeps a record of which location of a
pair was last accessed and allocates the new data to the other one. Round-
robin (also known as 'cyclic').The cache keeps a record of which location of a
pair was last allocated and allocates the new data to the other one
29
www.rejinpaul.com
30

www.rejinpaul.com
The Fully associative cache
address
tag CAM data RA M
mux
hit data
At the other extreme of associativity, it is possible to design a fully associative
cache in VLSI technology. Rather than continuing to divide the direct-mapped
cache ever smaller components, the tag store is designed differently using
content addressed memory (CAM). A CAM cell is a RAM cell with an inbuilt
comparator, so a CAM based tag store can perform a parallel search to locate
an address in any location. The organization of a fully associative cache is
illustrated in Figure Since there are no address bits implicit in the position of
data in the cache, the tag must store all the address bits apart from those used
to address bytes within the line.
Write strategies
There are more choices to make when the processor executes a write cycle. In
increasing order of complexity, the commonly used write strategies are: Write –
through
All write operations are passed to main memory
Write – through with buffered write
Write operations are passed to main memory through the write buffer
Copy – back (write – back)
Write operations update only the cache.
31

www.rejinpaul.com

www.rejinpaul.com
UNIT V
ARM ORGANIZATION
3-Stage Pipeline ARM Organization– 5-Stage Pipeline ARM Organization–ARM

Instruction Execution- ARM Implementation– ARM Instruction Set– ARM coprocessor
interface– Architectural support for High Level Languages – Embedded ARM Applications.
5.1 3-stage pipeline ARM organization

Register Bank which stores the processor state.it has 2 read ports, 1 write
ports, access any register ,1
additional read port, 1 additional write port for r15
,the program counter(PC)
 
 The barrel shifter, which can shift or rotate one operand by any number of bits.


The ALU, which performs the arithmetic and logic functions required by
 the instruction set.

The address register and incrementer, which select and hold all 
memory addresses and generate sequential addresses when required.
 
 The data registers, which hold data passing to and from memory.
 
The instruction decoder and associated control logic.
ARM processors up to the ARM7 employ a simple 3-stage pipeline with

the following pipeline stages:
• Fetch;
The instruction is fetched from memory and placed in the instruction pipeline.
• Decode;
The instruction is decoded and the datapath control signals prepared for the nextcycle. In
this stage the instruction 'owns' the decode logic but not the datapath.
• Execute;
The instruction 'owns' the datapath; the register bank is read, an operand shifted,the
ALU result generated and written back into a destination register.
At any one time, three different instructions may occupy each of these stages, so the
hardware in each stage has to be capable of independent operation.
1
www.rejinpaul.com
UNIT V - ARM ORGANIZATION
A[31:0] control
address register
P
C incrementer
PC
register
bank
instruction
decode
A multiply &
L register
U control
A B
b
u b b
s u u
s barrel s
shifter
ALU
data out register data in register
D[31:0]
Fig 5.1 3-stage pipeline ARM organization
When the processor is executing simple data processing instructions the pipeline
enables one instruction to be completed every clock cycle. An individual instruction
takes three clock cycles to complete, so it has a three-cycle latency, but the through-
2
www.rejinpaul.com
put is one instruction per cycle. The 3-stage pipeline operation for single-cycle
instructions is shown in Figure .
At any time slice, 3 different instructions may occupy each of these stages, so the
hardware in each stage has to be capable of independent operations
When the processor is executing data processing instructions , the latency = 3
cycles and the throughput = 1 instruction/cycle
Memory access (fetch, data transfer) in every cycle

Datapath used in every cycle (execute, address calculation, data transfer)
Decode logic generates the control signals for the data path use in next cycle
(decode, address calculation
3
www.rejinpaul.com
The simplest way to view breaks in the ARM pipeline is to observe that:
• All instructions occupy the datapath for one or more adjacent cycles.
• For each cycle that an instruction occupies the datapath, it occupies the decode
logic in the immediately preceding cycle.
• During the first datapath cycle each instruction issues a fetch for the next instruction
but one.
• Branch instructions flush and refill the instruction pipeline.
5.2 5-Stage Pipeline ARM Organization

The time,T , required to execute a given program
is given by:
T : The time that execute a given program

prog
N : The number of ARM instructions executed in the program
inst
CPI: Average number of clock cycles per instructions
f : frequency
clk
There are only two ways to increase performance:
1. Increase the clock rate, fclk.
2. Reduce the average number of clock cycles per instruction, CPI.
Separate instruction and Data memories => 5 stage pipeline

Used in ARM9TDMI
The 5-stage pipeline

The ARM processors which use a 5-stage pipeline have the following pipeline stages:
• Fetch
The instruction is fetched from memory and placed in the instruction pipeline.
4
www.rejinpaul.com
• Decode
The instruction is decoded and register operands read from the register file. There are
three operand readports in the register file, so most ARM instructions can source all
their operands in one cycle.
• Execute
An operand is shifted and the ALU result generated. If the instruction is a load or
store the memoryaddress is computed in the ALU.
• Buffer/data
Data memory is accessed if required. Otherwise the ALU result is simply buffered
for one clock cycle to give the same pipeline flow for all instructions.
• Write-back
The results generated by the instruction are written back to the register file, including
any data loaded from memory.
next
pc
+4
I-cache fetch
pc + 4
pc + 8
I decode
r15 instruction
decode
register read
immediate
fields
mul
LDM/
STM post -
+4 index reg
shift shift
pre-index
execute
ALU forwarding
paths
mux
B, BL
MOV pc
SUBS pc
byte repl.
D-cache buffer/
load/store
address data
rot/sgn ex
LDR pc
5

www.rejinpaul.com
register write write-back

www.rejinpaul.com
Figure 5.4 ARM9TDMI 5-stage pipeline organization
This 5-stage pipeline has been used for many RISC processors and considered to be
the classic way to design such a processor.
Data forwarding in the 5-stage pipeline

Instruction execution in the 3-stage pipeline is spread across 3 pipeline stages
(Execute,Buffer/Data, and Write-back) in the 5-stage pipeline. The only one way to
solve data dependencies without stalling the 5-stage pipeline is to introduce
forwarding paths.
Data dependencies arise when an instruction needs to use the result of one of its
predecessors before that result has returned to the register file.
Forwarding paths allow results to be passed between stages as soon as they are
available. The 5-stage ARM pipeline requires each of the 3 source operands to be
forwarded from any of 3 intermediate result registers.
There is a case where, even with forwarding, it is not possible to avoid a pipeline
stall. Consider the following code sequence:
LDRrN,[ .. ];loadrN from somewhere, N:

0~15 ADDr2, r1, rN; and use it immediately
Fig 5.5 Instruction cycle
The processor cannot avoid a one-cycle stall as the value loaded into rN only enters
6
www.rejinpaul.com
the processor at the end of the buffer/data stage, and it (rN) is needed by the
following instruction at the start of the execute stage.
The only way to avoid this stall is to encourage the C compiler (or assembly language
programmer) not to put a dependent instruction immediately after a load instruction.
Since the 3-stage pipeline ARM cores are not adversely affected by this code
sequence, existing ARM programs will often use it. Such programs will run correctly
on 5-stage ARM cores, but could probably be rewritten to run faster by simply
reordering the instructions to remove these dependencies.
5.3 ARM Instruction Execution

Data processing instructions
A data processing instruction requires two operands, one of which is always a
register and the other is either a second register or an immediate value. The second
operand is passed through the barrel shifter where it is subject to a general shift
operation, and then it is combined with the first operand in the ALU using a general
ALU operation. Finally, the result from the ALU is written back into the destination
register (and the condition code register may be updated).All these operations take
place in a single clock cycle as shown in Figure 5.5. Note also how the Program
counter (PC) value in the address register is incremented and copied back into both
the address register and r15 in the register bank, and the next instruction but one is
loaded into the bottom of the instruction pipeline (i. pipe).The immediate value, when
required, is extracted from the current instruction at the top of the instruction
pipeline. For data processing instructions only the bottom eight bits (bits [7:0]) of the
instruction are used in the immediate value.
7
www.rejinpaul.com
Data transfer instructions

A data transfer (load or store) instruction computes a memory address in a manner
very similar to the way a data processing instruction computes its result. A register is
used as the base address, to which is added (or from which is subtracted) an offset
which again may be another register or an immediate value. This time, however, a
12-bit immediate value is used without a shift operation. The address is sent to the
address register, and in a second cycle the data transfer takes place. Rather than leave
the data path largely idle during the data transfer cycle, the ALU holds the address
components from the first cycle and is available to compute an auto-indexing
modification to the base register if this is required. (If auto-indexing is not required
the computed value is not written back to the base register in the second cycle.)The
data path operations for the two cycles of a data store instruction (SIR) with an
immediate offset are shown in Figure 5.6.
8
www.rejinpaul.com
Figure 5.6 SIR (store register) data path activity.
When the instruction specifies the store of a byte data type, the 'data out' block
extracts the bottom byte from the register and replicates it four times across the 32-bit
data bus. External memory control logic can then use the bottom two bits of the
address bus to activate the appropriate byte within the memory system. Load
instructions follow a similar pattern except that the data from memory only gets as far
as the data in' register on the second cycle and a third cycle is needed to transfer the
data from there to the destination register.
9
www.rejinpaul.com
Branch instructions
1 Branch:B{<cond>}label
2 Branch with Link:BL{<cond>}sub_routine_label
Branch instructions compute the target address in the first cycle as shown in Figure 5.7. A
24-bit immediate field is extracted from the instruction and then shifted left two bit
positions to give a word-aligned offset which is added to the PC. The result is issued as an
instruction fetch address, and while the instruction pipeline refills the return address is
copied into the link register (r14) if this is required (that is, if the instruction is a 'branch
with link').The third cycle, which is required to complete the pipeline refilling, is also used
to make a small correction to the value stored in the link register in order that it points
directly at the instruction which follows the branch. This is necessary because r15 contains
pc + 8 whereas the address of the next instruction is pc +4 .
10
www.rejinpaul.com
5.4The ARM coprocessor interface

5.4.1Coprocessor architecture
The ARM supports a general-purpose extension of its instruction set through the
addition of hardware coprocessors, and it also supports the software emulation of
these coprocessors through the undefined instruction trap.
Its most important features are:
• Support for up to 16 logical coprocessors.
• Each coprocessor can have up to 16 private registers of any reasonable size; they
are not limited to 32 bits.
• Coprocessors use load-store architecture, with instructions to perform internal
Operations on registers, instructions to load and save registers from and to
Memory, and instructions to move data to or from an ARM register.
The ARM7TDMI coprocessor interface is based on 'bus watching' (other ARM cores
use different techniques). The coprocessor is attached to a bus where the ARM
instruction stream flows into the ARM and the coprocessor copies the instructions 11
www.rejinpaul.com
into an internal pipeline that mimics the behavior of the ARM instruction pipeline. As
each coprocessor instruction begins execution there is a 'hand-shake' between the
ARM and the coprocessor to confirm that they are both ready to execute it. The
handshake uses three signals:
cpi (from ARM to all coprocessors).
This signal, which stands for 'Coprocessor Instruction', indicates that the ARM
has identified a coprocessor instruction and wishes to execute it.
cpa (from the coprocessors to ARM).
This is the 'Coprocessor Absent' signal which tells the ARM that there is
no Coprocessor present that is able to execute the current instruction.
cpb (from the coprocessors to ARM).
This is the 'Coprocessor Busy' signal which tells the ARM that the coprocessor
cannot begin executing the instruction yet.
5.4.2Handshake outcomes
1.Once a coprocessor instruction has entered the ARM7TDMI and coprocessor pipe-
lines, there are four possible ways it may be handled depending on the handshake
signals: The ARM may decide not to execute it, either because it falls in a branch
shadow or because it fails its condition code test. (All ARM instructions are
conditionally executed, including coprocessor instructions.) ARM will not assert cpi,
and the instruction will be discarded by all parties.
2. The ARM may decide to execute it (and signal this by asserting cpi), but no present
coprocessor can take it so cpa stays active. ARM will take the undefined instruction
trap and use software to recover, possibly by emulating the trapped instruction.
3. ARM decides to execute the instruction and a coprocessor accepts it, but cannot
execute it yet. The coprocessor takes cpa low but leaves cpb high. The ARM will
'busy-wait' until the coprocessor takes cpb low, stalling the instruction stream at this
point. If an enabled interrupt request arrives while the coprocessor is busy, ARM will
12
www.rejinpaul.com
break off to handle the interrupt, probably returning to retry the coprocessor
instruction later.
4. ARM decides to execute the instruction and a coprocessor accepts it for immediate
execution, cpi, cpa and cpb are all taken low and both sides commit to complete the
instruction.
5.4.3Data transfers
If the instruction is a coprocessor data transfer instruction the ARM is responsible for
generating an initial memory address (the coprocessor does not require any
connection to the address bus) but the coprocessor determines the length of the
transfer; ARM will continue incrementing the address until the coprocessor signals
completion. The cpa and cpb handshake signals are also used for this purpose. Since
the data transfer is not interruptible once it has started, coprocessors should limit the
maximum transfer length to 16 words (the same as a maximum length load or store
multiple instruction) so as not to compromise the ARM's interrupt response.
5.4.4Pre-emptive execution
A coprocessor may begin executing an instruction as soon as it enters its pipeline so
long as it can recover its state if the handshake does not ultimately complete. All
activity must be idempotent (repeatable with identical results) up to the point of
commitment.
5.5 Architectural support for High Level Languages

 
Assemble-level abstraction
• A programmer who writes directly with the raw machine instruction set
• Expressing the program in terms of instructions, addresses, registers, bytes and
words
 
High-level languages
• Allows the programmer to think in terms of abstractions that are above the
machine level
13
www.rejinpaul.com
• The programmer may not even know on which machine the program will
ultimately run The RISC philosophy focusing instruction set design on flexible
primitive operations from which the complier can build its high level
operations
5.5.1Data types
ARM support for characters
• For handling characters is the unsigned byte load and store instruction
ANSI (American National Standards Institute) C basic data types
• Defines the following basic data types
– Signed and unsigned characters of at least eight bits
– Signed and unsigned short integers of at least 16 bits
– Signed and unsigned integers of at least 16 bits
– Signed and unsigned long integers of at least 32 bits
– Floating-point, double and long double floating-point numbers
– Enumerated types
– Bit fields (sets of Boolean variables)
• The ARM C complier adopts the minimum sizes for each of these types
• The standard integer uses 32-bit values
ANCI C derived data types

• Defines derived data types
Arrays, Functions, Structures, Pointers, Unions
• ARM pointers are 32 bits long and resemble unsigned integers
• The ARM C compiler aligns characters on byte boundaries, short integers at
even addresses and all other types on word boundaries
ARM architectural support for C data types
• Provides native support for signed and unsigned 32-bit integers and for
unsigned bytes, covering the C integer, long integer and unsigned character
types
• For arrays and structures: base plus scaled index addressing
14
www.rejinpaul.com
• Current versions of the ARM include signed byte and signed and unsigned 16-
bit loads and stores, providing some native support for short integer and signed
character types
5.5.2Expressions
 
Register use
• The key to the efficient evaluation of a complex expression is to get the
required values into the registers in the right order and to ensure that frequently
used values are normally resident in registers
• Optimizing this trade-off between the number of values that can be held in
registers and the number of registers remaining is a major task for the complier
 
ARM support
• The 3-address instruction format used by the ARM gives the compiler the
maximum flexibility
• Thumb instructions (generally 2-address)
– restricts the compiler‟s freedom to some extent
– smaller number of general registers also makes its job harder
 
Accessing operands
• A procedure will normally work with operands that are presented in one of the
following ways, and can be accessed as indicated as an argument passed
through a register
– The value is already in a register, so no further work is necessary as a
argument passed on the stack
– Stack pointer (r13) relative addressing with an immediate offset known at
compile-time allows the operand to be collected with a single LDR
• As a constant in the procedure‟s literal pool
– PC-relative addressing, again with an immediate offset known at compile-
time, gives access with a single LDR
• As a local variable
– Local variables are allocated space on the stack and are accessed by
• a stack pointer relative LDR
15
www.rejinpaul.com
• As a global variable
– Global (and static) variables are allocated space in the static area and are
accessed by static base (is usually in r9) relative addressing
 
Pointer arithmetic
• Arithmetic on pointers depends on the size of the data types that the pointers
are pointing to If a variable is used as an offset it must be scaled at run-time
• if p is held in r0 and i in r1, the change to p may be compiled as:

ADD r0, r0, r1, LSL #2 ; scale r1 to int
 
Arrays
• The declaration: int a[10];
– a reference to a[i] is equivalent to the pointer-plus-offset form *(a+i)
5.5.3Conditional statements
 
 if…else


The ARM architecture offers unusually efficient support for conditional
expressions when the conditionally executed statement is small
• More complex ‘if’ statements: more conventional solution
16
www.rejinpaul.com
 
switches
• ARM is to use a jump table
5.5.4Loops
for (i=0; i<10; i++) {a[i] = 0; }
17
www.rejinpaul.com
• It can be further improved by moving the test to the bottom of the loop
 
While loops
• The standard conceptual arrangement of a „while‟ loop is as follow
• One fewer branch is executed each time the complete „while‟ structure is
encountered
5.5.5FUNCTION AND PROCEDURES:

Procedure and function are a portion of code within a larger program that performs a
specific task and is relatively independent of the remaining code.
A Function procedure is a statement enclosed by the Function and End Function
statements. The Function procedure performs a task and then returns control to the
calling code. When it returns control, it also returns a value to the calling code.
18
www.rejinpaul.com
A procedure is a function which returns no value but has only side-effects. The C
language, for example, has no procedures, only functions. ANSI C even defines a
type, void, for the result of a function that has no result.
You can define a Function procedure in a module, class, or structure. It is Public by
default, which means you can call it from anywhere in your application that has
access to the module, class, or structure in which you defined it.
A Function procedure can take arguments, such as constants, variables, or
expressions, which are passed to it by the calling code. Both functions and
procedures can return values. Apart from this following are the differences:
Functions are used for computations where as procedures can be used for
performing business logic.
Functions must return a value, procedures need not be.

Function parameters are always IN, no OUT is possible.
Function returns 1 value only. Procedure can return multiple values(max. 1024).
A procedure may modify an object where a function can only return a value.
Program design:
Good programming practice requires that large programs are broken down into
components that are small enough to be thoroughly tested; a large, monolithic
program is too complex to test fully and is likely to have 'bugs' in hidden corners that
do not emerge early enough in the program's life to be fixed before the program is
shipped to users.
19
www.rejinpaul.com
Program hierarchy:
Fig 5.8 Typical hierarchical program structure
A typical hierarchy is illustrated in Figure 4. The top of the hierarchy is the program
called main. The remaining hierarchy is fairly informal; lower-level routines may be
shared by higher-level routines, calls may skip levels, and the depth may vary across
the hierarchy.
Leaf routines:
At the lowest level of the hierarchy there are leaf routines; these are routines which
do not themselves call any lower-level routines. In a typical program some of the
bottom-level routines will be library or system functions; these are predefined
operations which may or may not be leaf routines (that is, they may or may not have
internal structure).
Terminology:
20
www.rejinpaul.com
There are several terms that are used to describe components of this program
structure, often imprecisely. We shall attempt to apply terms as follows:
• Subroutine: a generic term for a routine that is called by a higher-level routine,
particularly when viewing a program at the assembly language level.
• Function: a subroutine which returns a value through its name. A typical invocation
looks like:
c = max (a, b);
• Procedure: a subroutine which is called to carry out some operation on
specified data item(s).
A typical invocation looks like:
printf ("Hello WorldXn");
C functions:
In C all subroutines are functions, but they can have side-effects in addition to
returning a
Value, and when the returned value is of type 'void' it is effectively suppressed and
only the side effects remain, giving a behaviour which looks just like a procedure.
Arguments and parameters:
An argument is an expression passed to a function call; a value received by the
function is a parameter.
A call by reference semantics would cause any change to a parameter within a
function to be passed back to the calling program, which clearly only makes sense
when the argument is a simple variable, but C does not support this.
ARM Procedure Call Standard
The APCS imposes a number of conventions on the otherwise 'vanilla' flavour of the
ARM architecture:
• It defines particular uses for the 'general-purpose' registers.
• It defines which form of stack is used from the full/empty,
ascending/descending Choices supported by the ARM instruction set.
• It defines the format of a stack-based data structure used for back-tracing
when Debugging programs.
21
www.rejinpaul.com
• It defines the function argument and result passing mechanism to be used by all
externally visible functions and procedures. ('Externally visible' means that the
procedure interface is offered outside the current programming module. A function
which is used only within the Current module may be optimized by deviating from
this convention.)
• It supports the ARM shared library mechanism, which means it supports a standard
way for shared (re-entrant) code to access static data.
APCS variants:
There are several (16) different variants of the APCS which are used to generate code
for a range of different systems. They support:
• 32-or 26-bit PCs
Older ARM processors operated in a 26-bit address space and some later versions
continue to support this for backwards compatibility reasons.
Implicit or explicit stack-limit checking
Stack overflow must be detected if code is to operate reliably. The compiler can
insert instructions to perform explicit checks for overflow.
Re-entrant or non-re-entrant code.
Code specified as re-entrant is position-independent and addresses all data indirectly
through the static base register (sb).
ARM efficiency:
Overall the ARM supports functions and procedures efficiently and flexibly. The
various flavours of the procedure call standard match different application
requirements well, and all result in efficient code. The load and store multiple register
instructions are exploited to good effect by the compiler in this context; without them
calls to non-leaf functions would be much more costly.
22
www.rejinpaul.com
5.5.6 USE OF MEMORY: An ARM system, like most computer systems, has its
memory arranged as a linear set of logical addresses.
Fig 5.9 The Standard ARM C program address Space model
The stack:
Whenever a (non-trivial) function is called, a new activation frame is created on the
stack containing a backtrace record, local (non-static) variables, and so on.
The heap:
The heap is an area of memory used to satisfy program requests (malloc ()) for more
memory for new data structures.
Address space model:
23
www.rejinpaul.com
Where an application can use the entire memory space (or where a memory
management unit can allow an application to think it has the entire memory space),
the application image is loaded into the lowest address, the heap grows upwards from
the top of the application and the stack grows downwards from the top of memory.
Chunked stack model:
Other address space models are possible, including implementing a 'chunked' stack
where the stack is a series of chained chunks within the heap.
Data storage:
The various data types supported in C require differing amounts of memory to store
their binary representations. The basic data types occupy a byte (chars), a half-word
(short ints), a word (ints, single precision float) or multiple words (double precision
floats).
Data alignment:
Therefore the ARM C compiler generally aligns data items on appropriate
boundaries:
• Bytes are stored at any byte address.
• Half-words are stored at even byte addresses.
• Words are stored on four-byte boundaries.
Packed structs:
Sometimes it is necessary to exchange data with other computers that follow different
alignment conventions, or to pack data tightly to minimize memory use even though
this will reduce performance.
5.6 Embedded ARM Applications

Trends in embedded system design

 Integrate allthe major system functions apart from some memory components into a
single chip
 
 Benefits in terms of component costs, reliability, and power-efficiency
 
 Advance in semiconductor process technology: millions of transistors built cheaply
 
The era of complex systems on a single chip
24
www.rejinpaul.com
 
Several examples of ARM-based „system on chips‟
5.6.1 The VLSI Ruby II Advanced Communication Processor
Fig 5.10. The VLSI Ruby II Advanced Communication

Processor Ruby II organization
1. Based on an ARM core
2. 2 Kbytes of fast (zero wait state) on-chip SRAM
3. Critical routines can be loaded to get the best performance and minimum power
consumption
4. Peripheral modules
5. PCMCIA interface
6. Four byte-wide parallel interfaces
25
www.rejinpaul.com
7. Two UARTs
8. Byte-wide FIFO buffers
9. Synchronous communications controller
10. Serial controller: I2C for battery-backed RAM, real-time clock, E2PROM,and audio
codec
11. External bus interface
12. 8-, 16-, and 32-bit data buses and flexible wait state generation
13. Counter/timer block
14. Three 8-bit counters connected to a 24-bit prescaler
15. Interrupt controller
16. Programmable control of all on- and off-chip interrupt sources
Ruby II power-management modes
1. On-line – all circuits are clocked at full speed
2. Command – the ARM core runs with 1 to 64 wait states but all other circuitry runs at full
speed. An interrupt switches the system into on-line mode immediately.
3. Sleep – all circuitry is stopped apart from the timers and oscillators. Particular interrupts
return the system to on-line mode.
4. Stopped – all circuits (including the oscillators) are stopped. Particular interrupts return
the system to on-line mode.
Packaging
1. 144- and 176-pin thin quad flat packs
2. Up to 32 MHz at 5 V.
3. At 20 MHz, 30 mA in on-line mode, 7.9 mA in command mode, 1.5 mA in sleep
mode, and 150 uA in stop mode.
5.6.2 The VLSI ISDN Subscriber Processor (VIP)

VIP
 Programmable engine for ISDN (Integrated Services Digital Network ,a digital
telephony standard) subscriber communications Developed by Hagenuk GmbH
Licensed to VLSI Technology for sale as ASSP (Application Specific Standard Part)

 Incorporates most of the circuitry required to implement a full feature ISDN
terminal, supporting voice, data, and video services
26
www.rejinpaul.com
 ISDN S0-interface, a numeric keypad, a number display, a microphone and an

earphone Applications

 ISDN terminal equipment: PABX telephones, H.320 videophones, integrated PC
communications

 ISDN to DECT (Digital European Cordless Telephone) controllers

 ISDN to PCMCIA communication cards.
Typical VIP system configuration
Fig 5.11 Typical VIP system configuration
27
www.rejinpaul.com
Fig 5.12 VIP Organization

Memory interface
1. Supports 8-, 16-, and 32-bit off-chip static RAMs and ROMs and 16- and32-bit
dynamic RAMs
2. Divided into 4 ranges, each with programmable number of wait states
3. 3 Kbyte on-chip RAM
S0-interface
1. Connection to an S0-interface bus via isolating transformers and surge
protection
2. PLL for data and clock recovery, framing, and low-level protocols
3. 192 Kbit/s raw data includes two 64 Kbit/s B channels (8-bit 8 KHz speech
samples)and one 16 Kbit/s D channel (control purposes)
Codec
1. G.711 codec
2. On-chip analog front end: Direct connection to a telephone handset and a
hands-free microphone and speaker
3. Input and output independent programmable gains
4. Amplification stages have power-down modes to save power.
28
www.rejinpaul.com
ADCs
1. Based on timing how long it takes to discharge a capacitor to theinput
voltage level
2. Very simple way to measure slowly varying voltages
3. Comparator and counter
4. Measure the voltage from a volume control potentiometer or tocheck
the battery voltage in a portable application
Keypad interface
1. Parallel output ports to strobe the columns of the keypad
2. Parallel input ports with internal pull-down resistors to sense the rows
3. Key press will generate an interrupt:
ARM can activate individual columns and sense rows.
Clocks and timers
1. 38.864 MHz and 460.8 KHz during power-down
2. Watchdog at every 1.28 sec
3.2.5 ms timer interrupts for DRAM refresh and multitasking.
5.6.3 The One C VWS22100 GSM Chip

 One C VW22100 Developed by VLSI Technology, Inc System-on-chip design
for GSM mobile telephone handset

 All the functions required in a handset with addition of external program and
data memory and a suitable radio module
Example: Samsung SGH2400, a dual-band (GSM 900/1800)handset with hands-free
voice activated dialing
29
www.rejinpaul.com
Fig 5.13 Samsung GSM Handset
Fig 5.14 Typical GSM handset architecture
30
www.rejinpaul.com
The One C VWS22100GSM Chip (III)

VWS22100organization
ARM7TDMI core
General purpose controller
GSM protocol layers
DSP core
Base band signal processing
DSP subsystem
Based on the 16-bit OakDSP core
Real-time signal processing
functions Voice coding
Equalization
Channel coding
Echo cancellation
Noise suppression
Voice recognition
Data compression
ARM7TDMI subsystem
Responsible for the system control functions
 The user interface software

 The GSM protocol stack

 Power management

 Driving the peripheral interface

 Running some data applications
On-chip debug
 Single JTAG interface

 ARM7TDMI Embedded ICE module
31
www.rejinpaul.com
 Debug technology on the Oak DSP core


 Other test and debug facilities
Power management
 Global and selective power-down modes

 The ability to slow down the system clock in idle mode

 The analog circuits also can operate at reduced power

 The on-chip pulse-width modulation outputs control battery charging

 The on-chip ADCs provide for the monitoring of the temperature and battery
voltage to give optimum operation.
5.6.4 The Ericsson-VLSI Bluetooth Baseband Controller
Bluetooth
 De-facto standard for wireless data communication for the 2.4GHz band

 Consortium of Ericsson, IBM, Intel, Nokia, and Toshiba

 Support short-range communication (to 10 m range) using radio
communication with 1 Mbit/s

 Robust communication in a noisy and uncoordinated environment
 For laptop, cellular telephone, printer, PDA, desktop, fax, keyboards, and so
on Provide bridge to existing networks
Bluetooth ‘piconet’
 Bluetooth units dynamically form ad hoc „piconets‟, which are groups of 2 to 8
units that operate the same frequency-hopping scheme

 One of the units will operate as master: Defines the clock and hopping
sequence.
32
www.rejinpaul.com
Fig 5.15 A typical Bluetooth system
Ericsson Bluetooth core

 Power-optimized hardware block

 Handles all the Link Controller functionality within the Bluetooth specification

 Interface logic to a Bluetooth radio communication

 Performs all the packet-handling functions for point-to-point, multislot, and
point-to-multipoint communications

 Combination of circuit and packet switching
Power management
 On-line: all blocks are clocked at their normal speed. TheARM7TDMI core
clock 13 to 40 MHz. 40 mA max.

 Command: The ARM7TDMI clock is slowed down by the insertion of wait
states

 Sleep: The ARM7TDMI click is stopped. 0.3 mA.

 Stopped: The clock oscillator is turned off.
33
www.rejinpaul.com
Fig 5.16 Bluetooth controller
5.6.5 The SA-1100

Features
 High-performance integrated system-on-chip

 Based on a modified version of SA-110 Strong ARM CPU core

 Intended for use in mobile phone handsets, modems, and other
handheld applications

 High performance with minimal power consumption.
34
www.rejinpaul.com
Fig 5.17 SA-1100 organization
CPU core
 SA-1 processor core

 Exception vector relocation mechanism (for Windows CE)

 16 Kbyte instruction cache using a 32-way associative CAM-RAM structure
with 8-word lines

 MMU with Process ID mechanism (for Windows CE)
35
www.rejinpaul.com
 8 Kbyte 32-way associative data cache in parallel with a512 byte 2-way set-
associative cache

Allow large data structures to be cached without causing major pollution
of the main data cache

 Addition of read buffer
 Addition of hardware breakpoint and watch point registers.
Memory controller
 Up to 4 banks of 32-bit off-chip DRAM
 PCMCIA interface

Two card slots are supported with some external „glue‟ logic
System control
On-chip
 
 A reset controller

A power management controller that handles low-battery warnings and
 switches the system between its various operating modes

  system timer block that supports general timing and watchdog
An operating
functions
 
 An interrupt controller
 
 A real-time clock that runs from a 32 KHz crystal source
 
28 general-purpose I/O pins.
Peripherals
LCD controller
Serial ports: USB, SDLC, IrDA, codec, and standard
UART 6-channel DMA
Bus structure
36
www.rejinpaul.com
Two buses connected through a bridge

The system bus: connects all the bus masters and the off-chip memory
The peripheral bus: connects all the slave peripheral
device Similar to AMBA ASB-APB split
Minimizes the bus width
Reduces the complexity and cost
Applications
 
 Off-chip memory: DRAM and ROM/flash
 
Necessary interface electronics for the various peripheral interfaces, display,
and so on
 
Very simple at the PCB level, yet very powerful processing capability and
sophisticated system architecture.
SA-1100 silicon ->
Characteristics
 Process 0.35 um

 Transistors2,500,000

 MIPS 220/250

 Metal layers 3

 Die area 75 mm2

 Power 330/550 mW

 Vdd 1.5/2V

 Clock 180/220 MHz

 MIPS/W 665/450
5.6.6The ARM7100
Features
 Highly integrated microcontroller

 Suited to a range of mobile applications
37
www.rejinpaul.com
 Smart mobile phones and palm-top computers
Fig 5.18 The Psion Series 5MX

Principal user input devices
Keyboard: parallel I/O
Stylus pointing device: transparent digitizing tablet overlaid on the LCD
display
Infrared via ADC
Communication
RS232C serial interface
IrDA compliant infrared interface for wireless connection to printers, modems,
and host PCs
Audio codec: microphone and speaker
38
www.rejinpaul.com
Fig 5.19 The Psion Series 5 hardware organization
ARM7100 organization
1. ARM710a CPU
2. ARM MMU
3. 8 Kbyte 4-wayassociative quadword line cache
4. 4-address 8-dataword write buffer
5. AMBA bus
6. Peripherals
 LCD controller

 Serial & parallel I/O ports

 Interrupt controller

 32-bit external bus interface
39
www.rejinpaul.com
 DRAM controller
Fig 5.20 ARM7100 organization
 Power management
 Levels
 Other features to enhance power-efficiency

Support for self-refresh DRAM.
40
www.rejinpaul.com
ARM7100 silicon ->

ARM7100 principal characteristics
 
 Process 0.6 um
 
 Transistor N/A
 
 MIPS 30
 
 Metal layers 2
 
 Die area N/A
 
 Power 14 mW
 
 Vdd 3.3 V
 
 Clock 18.432 MHz
 
MIPS/W 212
5.6.7 The ARM7500 and ARM7500FE

Features
 Highly integrated single-chip computer

 Combines the major components of the Acorn Risc PC

 Principal macrocells
 The ARM CPU core


 Contains most of the functionality of the ARM710
 Reduced cache 4 Kbytes (from 8 Kbytes)

4-way set-associative mixed instruction and data cache
 Memory management unit
41
www.rejinpaul.com
Based on a 2-level page table

64-entry translation look-aside buffer
 A write buffer

 The FPA10 floating-point unit
Up to 6 MFLOPS at 40 MHz
The video and sound macrocell
Video controller
1. Generate displays using a pixel clock of up to 120 MHz
2. 256-entry color palette with on-chip 8-bit DACs for RGB
3. Additional control bits for external mixing and fading
4. Support a separate hardware cursor
5. Can drive a high-resolution color monitor or single- or double-panel grey-scale
or color LCD
Sound controller
1. 8 independent channels of 8-bit analog stereo sound
2. Played through an on-chip exponential DAC
3. 16-bit sound samples through a serial digital channel and an external CD-
quality DAC
DMA controller for video/audio data channels
The memory and I/O controller
Memory controller
1. Direct connection of up to four banks of DRAM and two banks of ROM
2. Programmed to be 16 or 32 bits wide
3. Double access for 32-bit quantities in 16-bit banks
DRAM controller
1. Page mode accesses for sequential cycles in bursts of up to 256transfers
2. Supports a range of DRAM refresh modes
ROM controller
 Supports burst mode
42
www.rejinpaul.com
3 DMA controllers
 Handle data streams for video, cursor, and audio channels
I/O controller
 Manages 16-bit off-chip I/O bus

 Number of on-chip interfaces: 4 comparators, 2 serial ports, counter/timers, 8
general-purpose open-drain I/O lines, and programmable interrupt controller.
Fig 5.21 ARM7500 organization
Applications
 Low-cost versions of the Acorn Risc PC

 Online Media interactive video set-top box
 High-resolution displays
1280 x 1024 and above the number of colors become restricted due to
the bandwidth limitations of standard DRAM
43
www.rejinpaul.com
 Ideally suited
 Hand-held test equipment


 Multimedia applications.
ARM7500 silicon ->5% ARM core area
ARM7500characteristics
 
 Process 0.6 um
 
 Transistors 550,000
 
 MIPS 30
 
 Metal layers 2
 
 Die area 70 mm2
 
 Power 690 mW
 
 Vdd 5 V
 
 Clock 0-33 MHz
 
MIPS/W 43
44
www.rejinpaul.com
ARM Instruction SET
 
 All instructions are 32 bits long.
 
 Most instructions execute in a single cycle.
 
 Every instruction can be conditionally executed.
 
A load/store architecture
 
 Three operand format

 
Combined ALU and shifter for high speed bit manipulation
Specific memory access instructions with powerful auto-indexing addressing modes.
 
 32 bit and 8 bit data types
 
 and also 16 bit data types on ARM Architecture v4.
Flexible multiple register load and store instructions

 
Instruction set extension via coprocessors
Conditional Execution
 
 Most instruction sets only allow branches to be executed conditionally.

However by reusing the condition evaluation hardware, ARM effectively increases
 number of instructions.
-All instructions contain a condition field which determines whether the CPU

 will execute them.

 -Non-executed instructions soak up 1 cycle.

Still have to 
complete cycle so as to allow fetching and decoding of following
 instructions.

This removes the need for many branches, which stall the pipeline (3 cycles to refill).
 -Allows very dense in-line code, without branches.
-The Time penalty of not executing several conditional instructions is
frequently less than overhead of the branch or subroutine call that

would otherwise be needed.
45
www.rejinpaul.com
The ARM condition code field
31 28 27 0
cond
To execute an instruction conditionally, simply postfix it with the appropriate condition:

For example an add instruction takes the form:
ADD r0,r1,r2 ; r0 = r1 + r2 (ADDAL)
To execute this only if the zero flag is set:
ADDEQ r0,r1,r2 ; If zero flag set then…; ... r0 = r1 + r2
By default, data processing operations do not affect the condition flags (apart from the
comparisons where this is the only effect). To cause the condition flags to be updated, the S
bit of the instruction needs to be set by post fixing the instruction (and any condition code)
with an “S”.
46
www.rejinpaul.com
For example to add two numbers and set the condition flags:
ADDS r0,r1,r2 ; r0 = r1 + r2 ; ... and set flags
Branch instructions
Branch : B{<cond>} label
Branch with Link : BL{<cond>} sub_routine_label
Link bit 0 = Branch

1 = Branch with link
The offset for branch instructions is calculated by the assembler:

By taking the difference between the branch instruction and the target address minus 8 (to allow for
the pipeline).
This gives a 26 bit offset which is right shifted 2 bits (as the bottom two bits are always zero as
instructions are word – aligned) and stored into the instruction encoding. This gives a range of ± 32
Mbytes.
 
When executing the instruction, the processor:
-shifts the offset left two bits, sign extends it to 32 bits, and adds it to PC.
 
 Execution then continues from the new PC, once the pipeline has been refilled.

The "Branch with link" instruction implements a subroutine call by writing PC-4 into the
 LR of the current bank.
-i.e. the address of the next instruction following the branch with link (allowing for

the pipeline).
 
To return from subroutine, simply need to restore the PC from the LR:
-MOV pc, lr
-Again, pipeline has to refill before execution continues.
 
The "Branch" instruction does not affect LR.
47
www.rejinpaul.com
Branch, Branch with Link and exchange (BX, BLX)
 
 1: B{L}X{<cond>} Rm
 
 2: BLX <target address>

In the first format the branch target is specified in a register, Rm. Bit[0] of
Rm
 is copied into the T bit in the CPSR and bits[31:1] are moved into the PC:

If Rm[0] is 1, the processor switches to execute Thumb instructions and
begins executing at theaddress in Rm aligned to a half-word boundary by
 clearing the bottom bit.

 If Rm[0] is 0, the processor continues executing ARM instructions and begins 
executing at the address in Rm aligned to a word boundary by clearing Rm[l].
 
 Format (1) instructions may be executed conditionally or unconditionally, but format

 (2) instructions are executed unconditionally.

'<target address>' is normally a label in the assembler code; the assembler will
generate the offset (which will be the difference between the word address of the
target and the address of the branch instruction plus 8) and set the H bit if

appropriate.
48
www.rejinpaul.com
Software Interrupt (SWI )

The software interrupt instruction is used for calls to the operating system and is
often called a 'supervisor call'. It puts the 
processor into supervisor mode and begins
executing instructions from address 0x08.
 
 In effect, a SWI is a user-defined instruction.

It causes an exception trap to the SWI hardware vector (thus causing a change to
supervisor mode, plus the associated
 state saving), thus causing the SWI
 exception handler to be called.


The handler can then examine the comment field of the instruction to decide
 what operation has been requested.

By making use of the SWI mechansim, an operating system can implement a set 
of privileged operations which applications running in user mode can request.
Data processing Instructions
Largest family of ARM instructions, all sharing the same instruction format.
Contains:
Arithmetic operations
Comparisons (no results - just set condition codes)
Logical operations
Data movement between registers
Remember, this is a load / store architecture
These instruction only work on registers, NOT memory.
They each perform a specific operation on one or two operands.
First operand always a register - Rn
Second operand sent to the ALU via barrel shifter.
49
www.rejinpaul.com
The ARM data processing instructions are used to modify data values in registers.
www.rejinpaul.com
Multiplication Instructions
The Basic ARM provides two multiplication instructions.
Multiply
MUL{<cond>}{S} Rd, Rm, Rs ; Rd = Rm * Rs
Multiply Accumulate - does addition for free
MLA{<cond>}{S} Rd, Rm, Rs,Rn ; Rd = (Rm * Rs) + Rn
Restrictions on use:
 
 Rd and Rm cannot be the same register

 Can be avoid 
by swapping Rm and Rs around. This works because multiplication is
commutative.
 
Cannot use PC.
www.rejinpaul.com
Single word and unsigned byte data transfer
The pre-indexed form of the instruction:

LDRlSTR{<cond>}{B} Rd, [Rn, <offset>]{!}
The post-indexed form:

LDRlSTR{<cond>}{B}{T} Rd, [Rn], <offset>
A useful PC-relative form that leaves the assembler to do all the work:
LDRlSTR{<COnd>}{B} Rd, LABEL
52
www.rejinpaul.com
 
 P = 1 means pre-indexed, i.e. modify the address BEFORE use
 
 P = 0 means post-indexed, i.e. modify the address AFTER use
 
 B = 1 selects unsigned byte transfer (default is word transfer)
 
 <offset> may be #+/- 12-bit immediate value (i.e. constant)
 
 <offset> may also be +/- register
 
 write-back (or "!") = 1 if the base register is updated
 
All the shift parameters are the same as before
Half-word and signed byte data transfer instructions
53
www.rejinpaul.com
The S and H bits define the type of the operand to be transferred

The pre-indexed form:
LDR|STR{<cond>}H|SH| SB Rd, [Rn, <offset>] { ! }
The post-indexed form:
LDR|STR{<cond>}H|SH|SB Rd, [Rn], <offset>
Swap memory and register instructions (SWP)
SWP{<cond>}{B} Rd, Rm,[Rn]
Status register to general register transfer instructions
31 28 27 23 2221 1615 12 11 0
cond 00010 R 001111 Rd 000000000000
destination register
SPSR/CPSR
54
www.rejinpaul.com
MRS{<cond>} Rd,CPSR I SPSR
General Register to status register transfer instruction
55
www.rejinpaul.com
56
www.rejinpaul.com

EE6008 Notes Rejinpaul

Uploaded by

Copyright:

Available Formats

EE6008 Notes Rejinpaul

Uploaded by

Document Information

Original Description:

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

EE6008 Notes Rejinpaul

Uploaded by

Copyright:

Available Formats

www.rejinpaul.

Get useful study materials from www.rejinpaul.com

1.3PIC16C7X Peripheral Features:

Get useful study materials from www.rejinpaul.com

• 8-bit multichannel analog-to-digital converter

Get useful study materials from www.rejinpaul.com

Fig 1.1 PIC Microcontrollers Architectures

Get useful study materials from www.rejinpaul.com

Get useful study materials from www.rejinpaul.com

CPU registers (registers commonly used by the CPU)

Fig1.3 : STATUS register

Get useful study materials from www.rejinpaul.com

Get useful study materials from www.rejinpaul.com

RPO and RP1

Fig1.4 : Schematic of how PCL is loaded from PCLATH

Get useful study materials from www.rejinpaul.com

Program Counter Stack

It can be noted that some of the special purpose registers

Get useful study materials from www.rejinpaul.com

PARALLEL I/O Ports

Port C is an 8-bit wide, bidirectional port. Bits of the TRISC Register

Get useful study materials from www.rejinpaul.com

1.5 Harvard Architecture

The high performance of the PIC16CXX family can be attributed to a number of

Fig 1.5 CPU Architecture of PIC Microcontroller

Get useful study materials from www.rejinpaul.com

Fig 1.6 Pipelining of instruction fetch successive addressing

Get useful study materials from www.rejinpaul.com

Fig 1.6 Introduction of extra cycle for a jump/goto Instruction

1.6PROGRAM MEMORY CONSIDERATIONS

Get useful study materials from www.rejinpaul.com

Fig 1.7 Program Memory accesses

Get useful study materials from www.rejinpaul.com

Get useful study materials from www.rejinpaul.com

Get useful study materials from www.rejinpaul.com

1.7REGISTER FILE STRUCTURE

In PIC Microcontrollers the Register File consists of two parts namely

2. Special Purpose Register File

Get useful study materials from www.rejinpaul.com

a) General Purpose Register File:

b) Special Purpose Register File:

Fig1.8 Register bank

Get useful study materials from www.rejinpaul.com

1.8 INSTRUCTION SET

Bit Oriented Instruction

Get useful study materials from www.rejinpaul.com

which the bit is located.

BCF f , b ; Bit clear f

Literal and Control Instrucrtions

In literal and control instructions K represents an 8 or 11 bit constant or literal value.

ADDLW k ; Add literal and W

Get useful study materials from www.rejinpaul.com

(vii). Branch Instructions : There are two types of Branch

(i) Conditional Branch Instructions

Get useful study materials from www.rejinpaul.com

(ii) Unconditional Instructions

Get useful study materials from www.rejinpaul.com

Direct Addressing Mode

Example of direct addressing: