ISSCC2011Visuals T1

Integrated LC oscillators
Pietro Andreani
Dept. of Electrical and Information Technology
Lund University, Sweden
(also with ST-Ericsson, Lund, Sweden)
ISSCC 2011 Tutorial, S. Francisco, February 20th, 2011
© 2011 IEEE IEEE International Solid-State Circuits Conference © 2011 IEEE

Overview
• Popular LC (voltage-controlled) oscillators

– Oscillation frequency, tuning range, gain factor
• Passive components
– Inductors, varactors
• Phase noise
– Linear time-variant analysis
– Phase noise in popular LC oscillators
• Interface circuits
– Voltage regulator
– Buffers
2 2
Why bother about LC oscillators?
• LC VCO a truly fundamental analog block in radio

transceivers
• More and more bands are being added in cellular
communications  tougher demands on VCOs
• A large amount of total power consumed in VCOs 
attractive for optimization
• Bottlenecks in terms of noise performance and spur
sensitivity
3 3
Frequency synthesis with PLL
Reference frequency from crystal

oscillator (26MHz / 52MHz)
VCO
fXO PFD LPF fRF
/N
RF frequencies, perhaps over a very
large band (e.g. several GHz)
4 4
Building an LC oscillator
All losses compacted into a

LC tank
parallel resistance
C
L R ‒Ractive
Z tank ( jω0 ) = R
1 1
ωo ≈ fo ≈
R
LC 2π LC Q= = Rω0C
ω0 L
5 5
Colpitts oscillator
Classical embodiment with only one active device
L R
Vout
VB
C1
IB C2
6 6
Start-up conditions – linear analysis
Barkhausen’s criterion: oscillation

if loop gain (LG) is such that
LG ( jω ) = 1
L R
φLG ( jω ) = 0
− g mVs C1 Example: LG = β A
Vs
C2
+ A
7 7
Start-up conditions
1 C1C2
ωo = C=
LC C1 + C2
L R
Vs'
LG =
Vs 1 1
≡ gm =
Ractive R ⋅ n ⋅ (1 − n )
C1
Vs Vs'
C1
1 n=
g mVs C2 C1 + C2
gm
8 8
Large-signal regime
Very non-linear  operation in class C
VDD
Vout
L R
VDD
Vout
VB
Itank
C1
t
Itank IB C2
9 9
Describing function approach
I DS
Iω0
L R ≈ 2I B
t
Vout
Iω0
C1 1 Aout = Iω0 R (1 − n )
ωo =
LC ≈ 2 I B R (1 − n )
Fundamental
C2
C1C2 C1
current harmonic C= n=
C1 + C2 C1 + C2
T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, 2003

10 10
Cross-coupled differential-pair oscillator
Extremely popular family of oscillators
Operation in class B
VDD IB IB
t
V+ V- V-
VDD
V+
N1 N2
t
R 2 2
IB A+ = A− = I B Adiff = IB R
π 2 π
11 11
Oscillator with complementary switch pair
IB
t
-IB
VDD
V+ V- V+ V-
t
4
Adiff = IB R
π
IB Compared to single-switch-pair 
double amplitude, but also double VDD
12 12
Current bias – MOS source
• High-impedance source
• 1/f noise upconversion
V+ V-
N1 N2
“Tail” current source

VB IB
13 13
Current bias – resistor
• Low impedance source

V+ V- • 1/f noise absent
N1 N2
Ismail and Abidi, ISSCC ‘03

14 14
Two regions of operation
VDD
Vosc
Voltage (supply) limited
Current limited
2
A= IB R
IB π
IB
• Current-limited region  Vosc proportional to IB·R
• Peak oscillation amplitude cannot exceed VDD  voltage
limited  extra losses from MOS pair and tail source
• Operating at the limit between current-limited and voltage-
limited  best performance
15
Integrated inductors
Nguyen and Meyer, JSSC Aug. 1990 Nguyen and Meyer, JSSC March 1992
In standard nm CMOS, take advantage of the (relatively) thick top

metal layers needed by digital power supply routing!
State of the art: inductances up to a few nH, Q = 10-20 @ 2-5 GHz
16 16
Hollow coils
Craninckx and Steyaert, JSSC May ‘97
17 17
Ground shield
If Rp = 0 or ∞
 maximum Q
Conductive ground shield 
Rp very small
18 18
Patterned ground shield
Slot
Induced current
Ground strip
Ground strips Slots between strips
No closed loops in the ground shield
Yue and Wong, JSSC May ‘98

19 19
Effect of ground shield
Aluminum Polysilicon
Q Q
PGS = Patterned ground shield

SGS = Solid ground shield
NGS = No ground shield
20 20
Can you spot two differently-looking inductors?
M. Nilsson et al, “A 9-Band WCDMA/EDGE Transceiver Supporting HSPA Evolution”, ISSCC ’11, paper 21.2.
21 21
8-shaped coil
8-shaped  rejects common-

mode magnetic fields!
clover-shaped  even
higher rejection, but
higher losses
+-
0V
T. Mattsson, US patent #7,151,430 B2, Dec. ‘06
22 22
Improved robustness at chip level
• Possible to have 2 PLLs working at the same time and
at very similar frequencies (WCDMA)
• No pulling from TX PA
23
Frequency tuning
• Only one frequency is not enough  a more or less

wide frequency “tuning range” (TR) is needed to
sweep across the targeted communication bands
• Additionally, we need to take into account the
process variation on the value of L and C
• Look for a component having a variable inductance
or variable capacitance
• Variable capacitance  varactor  reverse-
biased diode, or MOS device
• MOS varactor by far the most popular
24 24
MOS varactors
PMOS device
CMOS
Strong inversion (p) Accumulation (n)
Moderate/weak
inversion (p)
Depletion (n)
VGB
25 25
NMOS in N-well
Avoided!
CMOS Cmax
Cmin
VGB
Soorapanth et al, VLSI Symp. ’98; Svelto et al, VLSI Symp. ’98; Andreani and Mattisson, JSSC June ‘00
26 26
Varactor trade-off
Cpar
2Cpar Cvar
L
G
Cvar ∝ W·L
D S W
Cpar ∝ W
Rvar ∝ L/W
 Maximum Q and minimum tuning range (TR)
with L=Lmin
L  Trade-off between Q and TR
Cmax/Cmin > 5 and Q > 50 @ 5GHz achievable
27 27
Discrete tuning
• Continuous tuning covers
only a small fraction of
overall TR
V+ V- • Decouples TR from VCO
gain factor KVCO
ON/ ON/ ∂ω
OFF OFF KVCO =
∂Vctr
• Crucial to keep impact of
thermal noise and spurs
fRF from PLL PFD and LPF
small  large R and
fXO PFD LPF relatively small C in LPF ok
 full PLL integration
/N • Needs calibration before
release in PLL
Kral et al, CICC ‘98
28 28
Example of discrete overlapping bands
• fosc =1.07-1.42GHz
Frequency [GHz]
• 28% TR
• KVCO only 75MHz/V
Tuning voltage (V)
Berny et al, CICC ‘03

29 29
Two approaches to discrete tuning
Vctr Vctr
CGD C
CDB
≈ CDB + CGD
Vctr,off Vctr,on Vctr,min Vctr,max
Sjöland, TCAS-II, May ‘02

30 30
Switched capacitor – trade-off
Vctr
CGD C
CDB
Cpar ∝ W
Rsw ∝ L/W
L  Maximum Q for L=Lmin
W  Trade-off between Q and TR
Berny et al, JSSC Apr. ‘05; Dal Toso et al, ISCAS ‘10
31 31
Avoiding parasitic switch conduction
Floating nodes must be avoided;

highest possible overdrive when “on”
1.8V
0V
Vth 0V Vth
1.2V
Maximum VGD and VDB 0V
must not be exceeded
Sjöland, TCAS-II, May ’02; Andreani et al, ESSCIRC ‘10

32 32
More levels of discrete tuning
.
.
• fosc =2.55-4.08GHz
Frequency [GHz]
. • 5-bit coarse tuning,

1 coarse
. 5-bit fine tuning
step
. • Small varactor for
continuous tuning
.
.
.
Fine step (5 bits)
Andreani et al, ESSCIRC ‘10

33 33
A digression – digitally-controlled oscillator (DCO)
DCO
fXO TDC FIR fRF
/N
• No analog tuning device in DCO, still needs
to tune fRF very finely  extremely small
switchable C needed
Example: for 2kHz resolution at 3.6GHz with

Ctank = 4.5pF and L = 500pH, ∆Ctank = 5aF
This and next two slides courtesy of Prof. A. Liscidini and Dr. Luca Fanori, Univ. Pavia, Italy
34 34
Small effective capacitances
• Capacitive divider
– Sensitive to mismatches and
parasitic caps
Chen et al, A-SSCC ‘07
Staszewski et al, JSSC Nov. ‘05

• Capacitive ∆Σ dithering
– Standard approach, but: spurs, large
high-frequency quantization noise
35 35
Very small effective capacitance without dithering
• A large Cs between the sources is

seen by the tank as very much
smaller
For 2ω0CS >> gm 

2
 gm 
Im (Y ) = −ω0CS  
 2ω0CS 
Cs is shrunk!
• Minimum capacitive step beyond
technology limitations!
Fanori, Liscidini, Castello, JSSC Dec. ’10

36 36
Why bother about phase noise?
Phase noise in transceiver is important for at least three

reasons:
1) in a receiver, it can downconvert a large nearby
signal on top of the desired signal
2) in a transmitter, it can increase the noise floor in the
receive band
3) in both, it can directly corrupt the phase information
in the signal
– Not seldom, the phase noise of the VCO is the bottleneck for the
whole radio performance
37
Phase noise
Phase noise, in dBc/Hz

dBc
f0 f
• The oscillation is modulated by unavoidable noise sources 

the LO signal displays skirts in the frequency domain
• Close to the f0 carrier, amplitude noise is rejected by the
amplitude-stabilizing mechanism intrinsic to the oscillator 
only phase noise is left
38
Example of phase noise requirements – GSM
RX TX
Hegazi and Abidi, JSSC May ‘03

39
Frequency down-conversion – ideal
fo
LO IF
Desired signal + Blocker
LO Blocker
Ideal down-
conversion @ BB
Desired
signal
fo fo+ f1 0 f1
40 40
Frequency down-conversion – real
fo fo+ f1 0 f1
Noise floor raised by mixing of LO phase noise

with blocker (“reciprocal mixing”)
41 41
Example of reciprocal mixing – GSM
−23dBm Noise floor due to

reciprocal mixing:
−23 −138 = −161 dBm Hz
−99dBm PN @ 3MHz
f f + Δf
3MHz
This should be compared to the RX thermal noise floor:
−174 + NF ≈ −171 dBm Hz
42 42
TX-to-RX leakage in WCDMA
Antenna
Duplexer
TX RX TX-to-RX = –40dBc
RX-to-TX = –50dBc
LNA
PA
43 43
WCDMA band VIII (GSM)
TX RX
880 915 925 960 f (MHz)
45MHz
44 44
Phase noise requirements – WCDMA
-40dB
-13dBm+PN
+27dBm
LNA
We accept only a very
PA marginal increase of
the RX NF
Margin for 0.5dB

PN at duplex deterioration of NF=3dB
frequency
−13 + PN < −174 + NF − 9 PN < −167 dBc/Hz

TX power leaked RX thermal @ 45MHz
3dB
to RX input noise floor
45 45
Phase noise in ideal LC oscillator – LTI approach
C
L R ‒Ract

Y (ω ) =  G + jωC +
1  (1 − ω 2 LC )
 − Gact =
 jω L  jω L
j (ω0 + Δω ) L ω0 L
Z (ω0 + Δω ) ≈ ≈−j
(
1 − (ω0 + Δω ) LC
2
2
Δω
) ω0
ω0 L ω0 L 1 ω0
Z ( ω 0 + Δω ) = = R⋅ ⋅ = R⋅
Δω R 2 Δω 2QΔω
2
ω0 ω0
46
Phase noise from tank losses
2
C
in L
2 2
v n2 in2 2  ω0   1 ω0 
= ⋅ Z (ω0 + Δω ) = 4k BTG ⋅  R ⋅  = 4 k B TR  ⋅ 
Δf Δf  2Q Δω   2Q Δω 
• Both amplitude and phase noise, but amplitude noise is rejected
• The phase noise is defined as half the above expression, normalized
to the output signal power (in dB below the carrier per Hertz, dBc/Hz):
 v2 2   2k TR  1 ω 2 
L ( Δω ) = 10 log10  2n  = 10 log10  2B  ⋅ 0  
 Apk 2   Apk 2  2Q Δω  
   
47
Leeson’s equation
 2k TR   1 ω 2    Δω1 f 3 
L ( Δω ) = 10 log10  F ⋅ 2B 1 +  ⋅ 0    ⋅ 1 + 
 Apk 2   2Q Δω     Δω 
 
L ( Δω )
Up-converted 1/f noise (30dB/dec, 1/f3 region)
Thermal noise (20 dB/dec, 1/f2 region)

Noise floor
Ideal L ( Δω )
Δω1 ω0 log ( Δω )
f3
2Q
48
Example of phase noise
Notch  artifact of the

measurement technique
1/f3 noise corner
49
Hajimiri and Lee’s theory of phase noise
The conversion of noise

δ (t −τ ) Vout ( t ) into phase noise is time-
dependent – LTV phase
noise analysis needed!
No phase noise Maximum phase noise
Vout Vout
δ (t −τ ) δ (t −τ )
Hajimiri and Lee, JSSC Feb. ‘98

50
Impulse sensitivity function (ISF, Γ)
• Current noise source in (φ ) is weighed by associated Γin (φ )

 effective current noise in ,eff (φ ) = in (φ ) ⋅ Γin (φ ) (φ = ω0t )
• ISF  dimensionless, frequency- and amplitude
independent, with period 2π:
c0 ∞
Γ (φ ) = +  cn cos ( nφ + φn )
2 n =1
• We define in2,eff ,rms as

2π
1
in2,eff ,rms  n,eff (φ ) dφ
2
= i
2π 0
51
ISF and phase noise
• If in (φ ) is a cyclo-stationary white current noise source, its
contribution to phase noise is
 in2,eff ,rms 
L ( Δω ) = 10 log  
 2 ( CA )2 ( Δω )2 
 pk 
• If in (φ ) is a cyclo-stationary 1/f current noise source, its

contribution is
 in2,eff ,0 
L ( Δω ) = 10 log  
 2 ( CA ) ( Δω )2 
2
 pk 
where in ,eff ,0 is the DC component of the Fourier series of in ,eff (φ )
52
Examples of ISFs
LC oscillator Ring oscillator

Vout = cos (φ )
φ φ
Γ = − sin (φ )
φ φ
Hajimiri and Lee, JSSC Feb. ’98; Andreani and Wang, JSSC Nov. ‘04
53
A particularly simple case
• Parallel RLC resonator again  stationary noise  contribution

of R to phase noise is:
 in2,eff ,rms   in2 Γi2n ,rms 
L ( Δω ) = 10 log   = 10 log  
 2 ( CA ) ( Δω )2 
2
 2 ( CA ) ( Δω )2 
2
 pk   pk 
 
4 k TG ⋅ 1 2
= 10 log  B 
C  2 ( CA ) ( Δω ) 
2 2
i n2 L  pk 
 2
k BTG  ω0  
= 10 log 
 ( Cω A )2  Δω  
 0 pk 
Leeson with F=1  2k TR  1 ω 2 
recovered without any = 10 log  2B  0
 
ad hoc assumptions!
 Apk 2  2Q Δω  
 
54
Phase noise from MOS pair
iN2 1 (φ ) = 4k BT γ n g m, N 1 (φ ) iN2 1,eff (φ ) = iN2 1 (φ ) ⋅ Γ 2N 1 (φ )
Γ N 1 (φ ) ≈ 1
IN2 I N1
V-
V+
N1 N2
IB
−Φ Φ
Two commutations in one oscillation period
55
Total phase noise – very simple expression
Tank MOS pair
 k BT 
L ( Δω ) = 10 log  2 2 2 (
1 + γ n )
 RAtank C ( Δω ) 
F = 1+ γ n
• Transistors appear only through channel noise factor γn
• Transistor phase noise always proportional to tank noise (60%
from tank, 40% from MOS pair, if γn = 2/3)
• This is because transistor noise is proportional to commutation
time, which is inversely proportional to the oscillation
amplitude, which is proportional to the tank parallel resistance
• A simple-minded LTI analysis would yield very wrong
predictions (i.e., MOS phase noise increases with MOS gm)
Andreani et al., JSSC May ‘05
56
MOS phase noise – invariance
1 2I B
i 2
N1 ( φ ) = 4 k BT γ n g m , N 1 ( φ ) Φn =
Atank βn 2 × βn
Two effects balance each other:
1) Larger MOS produces more

noise during current
commutation, and
2) Larger MOS allows a faster
commutation
Result: the two areas are identical
−Φ n −Φ n ,2 β Φ n ,2 β Φn
57
Phase noise from tail current source
η (Φ )
 k BT 
2 (
L ( Δω ) = 10 log  2 2 1 + γ + η ( Φ ) γ n g m ,bias R ) 
 RAtank C ( Δω ) 

58
Choice of inductor
 k BT 
L ( Δω ) = 10 log  2 2 2 (
1 + γ )
 RAtank C ( Δω ) 
• In the low GHz band, inductor loss dominates (although Q is

steadily increasing)
1 1 L2ind L2ind
L ( Δω ) ∝ 2 2
∝ 3 2 2∝ 3 2 = 3
RAtank C R C I B R I B R par , L I B2
• In terms of the series resistance of the inductor 

3
Rser
L ( Δω ) ∝ ,L
L4ind I B2
• The above expression should be minimized
59
Choice of inductor – II
3
Rser
L ( Δω ) ∝ ,L
L4ind I B2
3
Rser ,L
• 4
decreases with increasing Lind
Lind
• It would seem that Lind should be maximized  C is 100%
parasitic capacitance
• However, a large Lind forces the oscillator to enter the voltage-
limited region for a low I B  phase noise may be too high!
Vosc Voltage limited
Current limited
IB
• A few iterations are needed to find the optimal value of Lind
Approach borrowed from Ham and Hajimiri, JSSC June ‘01

60
Single-ended Colpitts oscillator
2
iMOS (φ )
Γ MOS (φ )
L R
Vout
VB
C1
IB C2
, eff (φ )
2
iMOS
Noise injected into tank when ISF is near zero  excellent!

Hajimiri and Lee, JSSC Feb. ‘98; Andreani et al., JSSC May ‘05
61
Phase noise of single-ended Colpitts oscillator
 k BT  1 − n 
L ( Δω ) ≈ 10 log  2 3 2 
1+ γ n 
 4 I B R (1 − n ) C ( Δω ) 
2 2
n  
Minimum for:
0.30 for γ n = 2 3

nopt = 1 3 for γ n = 1
0.36 for γ = 1.5
 n
• However, contrary to what was commonly (and

justifiably) believed, Colpitts is more noisy than
differential-pair LC oscillator!

62
Harmonic oscillators – a general result
1) Γ sinusoidal and in quadrature with tank voltage

2) Active devices work as transistors
3) Transistor current noise proportional to gm
Transistor effective noise depends only on

tank loss and topology
J. Bank, ”A harmonic oscillator design methodology based on describing functions”, PhD thesis, Gothenburg, Sweden, 2006
Mazzanti and Andreani, JSSC Dec. ‘08
63
Double-switch pair vs. single-switch pair
Double-switch-pair (DS) oscillator Single-switch-pair
(SS) oscillator
4 2
ADS = IB R ASS = IB R
π π
V+ V- V+ V-
What phase noise

difference should
we expect?
IB
IB
Andreani and Fard, JSSC Dec. ‘06

64
Phase noise of DS oscillator
 k BT  γn +γ p 
LDS ( Δω ) = 10 log  2 2  1+  
 A C ( Δω ) R 
2
2 
 DS
• pMOS and nMOS contribute equally

– Independently of relative strengths
– Assumptions: fast switching, no parasitic capacitances
• 60% from tank, 40% from transistors
– If γn = γp = 2/3
65
DS vs. SS – phase noise
 k BT  γn +γ p 
LDS ( Δω ) = 10 log  2 2  1+  
 A C ( Δω ) R 
2
2 
 DS
 k BT 
LSS ( Δω ) = 10 log  2 2 (1+ γ n )
 A C ( Δω ) R
2

 SS 
If IB,DS = IB,SS and γn = γp 
ADS = 2 ASS → LDS = LSS − 6dB
66
DS vs. SS – MOS noise
SS
Area (SS) = 2 · Area (DS)
4 DS transistors
make as much noise
as 2 SS transistors!
DS
−Φ n , SS −Φ n , DS Φ n , DS Φ n , SS
67
DS and SS – phase noise vs. IB
DS-VCO
SS-VCO
6dB
• 2.15 – 2.35 GHz

• Q ≅ 11
Andreani and Fard, JSSC Dec. ’06

68
DS and SS – phase noise vs. power consumption
• If IB,SS = 2IB,DS  ASS = ADS  same phase noise
• In this case, VDD,SS = ½ VDD,DS  same power consumption
• Thus, same maximum achievable “figure-of-merit” (phase

noise for a given power consumption)
69
Asymmetry between nMOS and pMOS in DS
• If Cpar >> C
– ΓN1, ΓN2 unchanged
– ΓP1, ΓP2  larger
• Cpar large  pMOS noise

Cpar dominates
70
Asymmetry between nMOS and pMOS in DS – II
• A part of the charge stored

in Cpar discharges through
pMOS  Q deterioration
 further increase in phase
noise
Cpar • If Cpar = 50% of total C 
4.4dB simulated phase
noise deterioration (also
depending on pMOS size)
• SS oscillator insensitive to
Cpar  great advantage
Andreani and Fard, JSSC Dec. ‘06; Murphy, Rael, Abidi, TCAS-I June ‘10
71
Impact of parasitic tail capacitance in SS/DS
• Ctail,par + cross-coupled MOS

entering linear region 
phase noise deterioration
• Distortion of oscillation
waveform, MOS ISF
increases, even by a large
amount
Ctail,par • Ctail,par good for filtering

noise from bias MOS
72 72
Possible solution – noise filter
• Noise filter: Ctail,par resonates with

Ltail at 2 ω 0  tail at high impedance
• CBIG filters bias noise
• CBIG includes CDB of MOS bias 
long and large MOS, low 1/f noise
• Drawback: narrow-band, extra Ltail
needed
Ltail Ctail,par
CBIG
Hegazi, Sjöland, Abidi, JSSC Dec. ‘01

73 73
More on tail filter
CBIG
• Many variations on the
same theme
• In voltage-limited designs,
effective in diminishing the
losses introduced by the
MOS pair
• Popular technique
Ltail Ctail,par
Hegazi, Sjöland, Abidi, JSSC Dec. ’01; Murphy, Rael, Abidi, TCAS-I June ‘10
74 74
Class-C LC oscillator
V+ V- Ctail turns class-B operations

into class-C  optimal
convergence of two topologies:
1) classical diff-pair LC oscillator
N2 N1
2) differential Colpitts oscillator
Ctail However, there are drawbacks

IB as well
Mazzanti and Andreani, JSSC Dec. ’08

75
Advantage of class-C
• Same effective noise as in diff-pair LC oscillator
• However, class-C operation  higher oscillation
amplitude
• Ideally, 3.9 dB phase noise improvement
Idrain Ibias
Iω0≈ I bias
I N1 I N2
class-C
2
Iω0≈ ⋅ I bias
“diff-pair” π
76
More on class-C oscillator
• Diff-pair must not enter the linear

region
V+ V-
• Shift of MOS DC gate voltage
necessary
• RC bias should not load tank
• Transformer feedback also an option
VB • Ctail  from foe to friend (class-C +
bias noise filtering)
Ctail
• Ctail includes CDB of MOS bias 
long and large MOS, low 1/f noise
77
Drawbacks of class-C
• An extra (low-noise) bias voltage VB is needed

• MOS transistors must not enter the linear region 
maximum oscillation amplitude Amax is
VDD − VB + Vth
Amax =
2
 lower than with standard LC oscillator, where Amax = VDD

• If MOS enters linear region  severe phase noise
penalty
• If Ctail larger than a limit value  instability of the
oscillation amplitude (“squegging”)
78
Example of class-C VCO
• 4.90 GHz < fc< 5.65GHz
3
• VDD= 1V, IB=1.4 mA
fosc= 5.52 GHz
-130 dBc/Hz
fosc = 4.90 GHz
Mazzanti and Andreani, JSSC Dec. ’08

79
On the upconversion of 1/f noise
No upconversion from cross-coupled transistors if:

1) PSD of 1/f noise current of cross-coupled transistors is
2
proportional to g m
– E.g., square-law MOS with 1/f noise proportional to drain
current
2) And, common source of cross-coupled transistors sees
a very high impedance at low frequencies
• A few 2nd-order effects cause 1/f noise upconversion,
especially from tail current source and power supply:
– Change in bias point and AM-to-PM conversion in non-linear
varactors and parasitic capacitors
– Possibly, Groszkowski’s effect (frequency shift induced by a
change in the current harmonics flowing into the tank)
Mazzanti and Andreani, TCAS-I Oct. ’09; Andreani et al., unpublished; Levantino et al., JSSC Aug. ‘02;
Hegazi and Abidi, JSSC June ‘03; Rael and Abidi, CICC ’00; Bevilacqua and Andreani, ISCAS ‘11
80 80
Pushing from power supply
VDD
• Non-linear capacitances
• Groszkowski’s effect
Andreani et al, ESSCIRC ’10

81 81
Voltage regulator

VCO-regulator co-design
• Pushing + regulator noise  phase noise

• Regulator must be co-designed with VCO  target is
negligible phase noise deterioration
• Usually achievable with moderate power consumption
(compared to VCO)

LO distribution
3.4 mm
• Large chip  long

distance between PLL
2nd RXFE Main RXFE and mixers / dividers
RX • Long routings would
PLL load the VCO tank
• Possibly, several blocks
driven by PLL (maybe
not at the same time)
• Buffers needed!
• It is a good idea to
isolate the VCO anyway
M. Nilsson et al, “A 9-Band WCDMA/EDGE Transceiver Supporting HSPA Evolution”, ISSCC ’11, paper 21.2

Possible buffer configurations
Very long routings or

many routings in parallel
 convenient to add
one more buffer stage

Inverters as buffers
C
• Pseudo-differential
• Low noise
Vout Noise
window
Large C and narrow
noise window 
large inverter 
high power consumption
t
Δt

Phase noise floor
L Noise floor from buffers

1/f noise
Thermal noise
f
TX-to-RX leakage
in WCDMA Large offset and low
phase noise  buffer
noise floor dominates
TX RX

Summary
• Popular LC VCOs
– Colpitts, cross-coupled pair (single-pair and double-pair),
noise filter, class-C
• Passive components
– MOS varactor, switched linear capacitor
– Inductors: hollow, differential, with ground shield, 8-shaped
• Phase noise
– Impact in radio transceivers
– Hajimiri and Lee’s theory – the Impulse Sensitivity Function
– Phase noise equations for all treated oscillators
• Interface circuits
– Voltage regulator, pushing from power supply
– Buffers: inverters, cascaded inverters, noise floor
88

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Integrated LC oscillators

ISSCC 2011 Tutorial, S. Francisco, February 20th, 2011

© 2011 IEEE IEEE International Solid-State Circuits Conference © 2011 IEEE

• Popular LC (voltage-controlled) oscillators

• LC VCO a truly fundamental analog block in radio

Reference frequency from crystal

All losses compacted into a

Classical embodiment with only one active device

Barkhausen’s criterion: oscillation

T. H. Lee, “The Design of CMOS Radio-Frequency Integrated Circuits”, 2003

“Tail” current source

• Low impedance source

Ismail and Abidi, ISSCC ‘03

In standard nm CMOS, take advantage of the (relatively) thick top

Craninckx and Steyaert, JSSC May ‘97

Ground strips Slots between strips

No closed loops in the ground shield

Yue and Wong, JSSC May ‘98

PGS = Patterned ground shield

8-shaped  rejects common-

• Only one frequency is not enough  a more or less

Tuning voltage (V)

Berny et al, CICC ‘03

Vctr,off Vctr,on Vctr,min Vctr,max

Sjöland, TCAS-II, May ‘02

Floating nodes must be avoided;

Sjöland, TCAS-II, May ’02; Andreani et al, ESSCIRC ‘10

. • 5-bit coarse tuning,

Andreani et al, ESSCIRC ‘10

Example: for 2kHz resolution at 3.6GHz with

Chen et al, A-SSCC ‘07

Staszewski et al, JSSC Nov. ‘05

• A large Cs between the sources is

For 2ω0CS >> gm 

Fanori, Liscidini, Castello, JSSC Dec. ’10

Phase noise in transceiver is important for at least three

Phase noise, in dBc/Hz

• The oscillation is modulated by unavoidable noise sources 

Hegazi and Abidi, JSSC May ‘03

Desired signal + Blocker

Noise floor raised by mixing of LO phase noise

−23dBm Noise floor due to

−23 −138 = −161 dBm Hz

This should be compared to the RX thermal noise floor:

−174 + NF ≈ −171 dBm Hz

880 915 925 960 f (MHz)

Margin for 0.5dB

−13 + PN < −174 + NF − 9 PN < −167 dBc/Hz

Up-converted 1/f noise (30dB/dec, 1/f3 region)

Thermal noise (20 dB/dec, 1/f2 region)

Notch  artifact of the

1/f3 noise corner

The conversion of noise

Hajimiri and Lee, JSSC Feb. ‘98

• Current noise source in (φ ) is weighed by associated Γin (φ )

• We define in2,eff ,rms as

• If in (φ ) is a cyclo-stationary 1/f current noise source, its

LC oscillator Ring oscillator