Phase Noise and Jitter in CMOS Ring Oscillators
Phase Noise and Jitter in CMOS Ring Oscillators
Phase Noise and Jitter in CMOS Ring Oscillators
AbstractA simple, physically based analysis illustrate the noise is tuned in frequency by a current, its tuning range can span or-
processes in CMOS inverter-based and differential ring oscillators. ders of magnitude. Only the relaxation oscillator, which is also
A time-domain jitter calculation method is used to analyze the ef- tuned by a current, offers a similar tuning range.
fects of white noise, while random VCO modulation most straight-
forwardly accounts for flicker (1 ) noise. Analysis shows that In spite of its widespread use in communication circuits and
in differential ring oscillators, white noise in the differential pairs on microprocessors, the ring oscillator is designed empirically.
dominates the jitter and phase noise, whereas the phase noise due Based on delay data given by the foundry, the right number of
to flicker noise arises mainly from the tail current control circuit. stages is chosen to oscillate at the desired frequency. This is re-
This is validated by simulation and measurement. Straightforward fined by simulation. Today the time jitter or phase noise in the
expressions for period jitter and phase noise enable manual design
of a ring oscillator to specifications, and guide the choice between oscillation can also be simulated. Before the advent of phase
ring and LC oscillator. noise simulation, there was little recourse but to build the cir-
cuit and find out. This has not escaped researchers. There has
been a stream of publications since the early 1980s on analyt-
I. INTRODUCTION
ical estimation of delay in chains of CMOS inverters, and since
the mid1990s on estimation of jitter in ring oscillators. How-
HE ring oscillator is the most widely manufactured inte-
T grated circuit of all. Foundries use ring oscillators on every
semiconductor wafer to monitor the gate delay and speed-power
ever, the analysis for gate delay becomes increasingly nonintu-
itive as it gets more accurate, and the latest editions of textbooks
on VLSI design [4], [5] hold that it is better to use the simplest
product of fabricated MOS inverters. Automated measurements possible analysis for a first-order estimate of gate delay and then
of oscillation frequency determine which wafers are acceptable, refine it with simulation. Similarly, the available analyses for
and which fall outside an acceptable window and must be dis- jitter offer upper limits or estimates within orders of magni-
carded. Ring oscillators have occupied this role since the earliest tude, but no crisp, simple expression that is validated by mea-
days of MOS IC technology because they are easy to build, al- surements and that gives enough design insight to enable a ring
ways oscillate, and are readily measured. The ring oscillator is oscillator to be designed first time right without guesswork and
a closed loop comprising an odd number of identical inverters, lengthy simulations.
which forms an unstable negative feedback circuit. Its period of Section II briefly reviews the prior literature on this subject.
oscillation is twice the sum of the gate delays in the ring.
Because these oscillators are so well-known to digital and
analog circuit designers alike, they have found use beyond the II. SUMMARY OF LITERATURE
monitoring of the semiconductor process in communications
circuits and clock generation. A voltage-controlled ring CMOS A. CMOS Gate Delay
inverter-based oscillator was first used for clock recovery in An accurate estimate of the delay through a CMOS inverter
an Ethernet controller [1]. Since then, the ring oscillator has loaded by the capacitance of a similar inverter is important not
become a widely used component in the communications IC only for our purposes here, but is at the very center of the enter-
toolbox. On todays mixed-signal ICs, almost all ring oscilla- prise of VLSI design. The delay through a gate with fanout of
tors use differential delay stages [2], [3] because of their greater one sets the absolute upper limit on clock frequency for a logic
immunity to supply disturbances. In this role, the ring oscillator block. Propagation delay ( ) is defined as the time between
is still the most widely fabricated of all oscillators. when the input crosses the switching threshold [4] or toggle
Why is this? First, compared to alternatives such as the LC point ( ) of the inverter to when its output crosses the toggle
resonator-based oscillator, the ring oscillator is exceptionally point of the next inverter in a chain (Fig. 1). The first publica-
compact. A large number of ring oscillators take up the same tions on the subject estimated delay by the time for the output
chip area as a small spiral inductor. Second, it can oscillate at voltage of an nMOS or CMOS inverter driving the capacitance
very high frequencies, that is, at very short periods limited only of the next stage to cross the trip point in response to an input
by the sum of a few gate delays. The maximum oscillation fre- step [Fig. 2(a)]. However, the input waveforms in a practical
quency is always much higher than relaxation or RC phase shift logic chain are not ideal steps but have a finite slope, which in
oscillatorsalthough not as fast as LC oscillators that can tune the case of a chain of identical stages is the same at every other
a transistor to oscillate at its . Third, as the ring oscillator stage [6], and in the case of balanced CMOS inverters with equal
pullup and pulldown is the same at the input and output of each
inverter with opposite sign. This led to a refinement of the cal-
Manuscript received December 21, 2005; revised April 24, 2006. culation based on step response delay to one which takes into
The author is with the Electrical Engineering Department, University of Cal-
ifornia, Los Angeles, CA 90095-1594 USA (e-mail: [email protected]). account the finite slope of the input ramp [7] [Fig. 2(b)]. In gen-
Digital Object Identifier 10.1109/JSSC.2006.876206 eral, for large fanouts this calculates a longer propagation delay
0018-9200/$20.00 2006 IEEE
1804 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
(1)
(2)
(3)
(4)
Fig. 3. White noise of unit standard deviation, and its integration over an in-
Its frequency response in magnitude is creasingly wide window with multiple trials.
and (11)
The search for a link between jitter and phase noise is mo-
tivated by the problem that baseband communication systems (13)
specify clock purity in the time domain, either as the jitter in a
single period of the clock, that is, period jitter, or by accumu- This is the spectrum of the quantity sampled at , and is
lated jitter over cycles of the clock [16][20], but oscillators therefore defined only over the frequency range (0, ). In
are specified by phase noise. The two are fundamentally dif- practice, more important than the spectral density of jitter is its
ferent, and the relationship is not obvious. mean-square value , as would be measured on a time-domain
Phase noise is a continuous stochastic process indicating instrument such as a digital oscilloscope [12], [20]. Once again,
random accelerations and decelerations in phase as an we use the WienerKhinchine theorem to calculate this from the
oscillator orbits at a nominally constant frequency in spectral density:
steady-state (Fig. 5). Jitter arises from sampling the orbit at
certain points. For example, for a noisy oscillatory waveform
that is nominally free of DC the period may be defined as (14)
the interval between successive zero crossings of the waveform
with, say, positive slope. In the presence of phase noise, This then is the general form of the link between jitter and
is a set of discrete random variables. Period jitter is defined as phase noise, two directly measurable quantities.
the standard deviation of this discrete sequence around its Let us see how the link simplifies under the special case when
mean value [15]. By contrast, the underlying phase noise is a all phase noise arises from white noise sources. Ref. [23]and
continuous random variable that is specified by its PSD . the earlier, but to our readers the less accessible, [24]shows
So what is the link between the two? that in an oscillator with white noise sources alone, the SSB
ABIDI: PHASE NOISE AND JITTER IN CMOS RING OSCILLATORS 1807
(15)
(20)
(16)
The capacitor integrates noise into voltage over the window
. This voltage wavers randomly at a rate that is inversely pro-
Thus portional to , advancing or delaying the instant of threshold
(17) crossing. It is unlikely that on a macroscopic time scale this
noisy ramp will cross the threshold more than once (Fig. 7)
(whereas [14] discusses multiple crossings). The dynamics of
Using heuristic reasoning, others [10], [25], [26] also have
the threshold crossing are described by
found this relationship for white noise.
We will now apply these analytical tools to commonly used
ring oscillators. As these circuits are most naturally analyzed in
the time domain, we will first analyze the jitter, and then deduce (21)
the phase noise. The predictions of phase noise will be validated
against measurements.
where is a random variable that arises from noise current.
The statistics of follow:
IV. INVERTER-BASED RING OSCILLATOR
(18)
and this current will fall gradually in the triode region. For sim- (25)
plicity we assume that even if the NFET enters triode during
, its drain current will not change appreciably. Thus, the
output voltage crosses the toggle point with a slope Using (20) this simplifies to
(19) (26)
This current is accompanied by noise from the NFET (Fig. 6).
The spectral density of the noise is [27] This is a compact expression for uncertainty in propagation
delay caused by current noise integrating on the capacitor .
The expression could be refined to take into account integrator
leak caused by nonzero when the pulldown FET enters
1808 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
(32)
Using (17), the SSB phase noise due to white noise is now
found from the jitter
(30)
In the expression for ring oscillator frequency (30) depends and due to the uncorrelated contributions of the NFETs and
on , and this dependence can be made explicit assuming PFETs in the oscillator it is
that is only due to the gate capacitance:
(35)
(41)
so that
To gain design insight from this expression, we must specify
the spectral density of flicker noise in terms of FET geometry
(36) and bias. For many years, we have used a measurement-based
model of flicker noise [29] in amplifiers, mixers, and oscillators
Clearly, aside from using FETs with as long a channel length that has proved itself to be a reliable predictor. According to this
as is possible, not much else will desensitize the inverter-based model the flicker noise PSD in nMOS referred to the FET gate
voltage-controlled oscillator (VCO) against supply noise. At as a voltage is given by the expression
high frequencies, FET capacitances will further raise the supply
sensitivity. This is the CMOS inverters main weakness: that
although with enough noise margin [5] it is a reliable logic ele- (42)
ment on mixed-signal ICs, it cannot usually be a precise delay.
D. Ring Oscillator Phase Noise Due to Flicker Noise where the empirical coefficient is essentially in-
dependent of bias, fabricator and technology. The same expres-
Flicker noise is qualitatively different, and invokes dif- sion holds for PMOS, but here is lower and depends on
ferent mechanisms of jitter and phase noise, so it should be ana- bias. One can estimate an upper limit on the effects of flicker
lyzed from first principles. Pullup and pulldown currents contain noise by setting . To find the noise in the drain
flicker noise which may not fluctuate over a single transition, but current we use (18)
varies slowly over many transitions. The noise arising in every
FET is, of course, uncorrelated.
Suppose and are the pulldown and pullup currents (43)
supplied, respectively, by the NFET and PFET in the th stage
of an -stage ring oscillator. Then the period of oscillation The final expression for SSB phase noise induced by flicker
and frequency are noise is
(37) (44)
(45)
(38)
This last expression gives design insight. To lower flicker noise
upconversion into phase noise, choose large to burn as
In a symmetrically designed inverter where the pullup and pull-
much current in the oscillator as the budget allows, and use FETs
down currents are equal to , the expression for frequency is
with the longest practical channel . As the ring oscillators
identical to (30).
average bias current does not depend on the number of stages
The sensitivity of to, say, the pulldown current in the th
, use the largest number of stages. It is satisfying to see that
inverter is
these guidelines will also lower phase noise due to white noise
(see end of Section IV-B).
(46)
(50)
As the loads are RC circuits, the propagation delay and fre-
quency of oscillation are determined by decaying exponentials:
Let us start by analyzing noise due to the load resistors. This
noise is continuously coupled into the load capacitors, and at all
(47) times its differential mean square fluctuation is
(48)
(49)
Using the results from Section III-A-2, the mean-square voltage If it is believed that because of short-channel effects the FETs
after period is do not obey the square law, the phase noise expression should
be recast in terms of the FET transconductance by substituting
(54)
We can check this result by noting that as , this assumes and using simulated values of these s. The FET noise factor
the steady-state value of (52). The mean-square value of the may also be larger for short channels.
differential noise voltage is independent of : Whereas the inverter-based delay cell operates in Class B, that
is, there is no static standing current, the differential delay cell
operates in Class A and consumes a steady current per cell.
(55) Therefore, the oscillator as a whole consumes .
This development largely parallels an earlier analysis for BJT
This is because the differential noise arises from the periodic differential ring oscillators [12], we hope in simpler terms.
commutation of a noise current into a differential RC load. Com-
C. Phase Noise Due to Flicker Noise
mutation of bandlimited white noise does not change its mean-
square value in steady state. Once again, flicker noise should be thought of differently than
During the transition time, noise from the differential pair white noise, because it fluctuates at a rate much lower than the
FETs (Fig. 8) modulates the fraction of tail current being steered oscillation frequency. First we show that flicker noise in the dif-
to the left and right branches. This describes the effect of the dif- ferential pairs does not cause phase noise. Next we show that
ferential pairs current noise , which flows as a differential flicker noise in the tail currents modulates the VCO with random
current on to the two load capacitors. To simplify analysis, we FM.
assume that this noise integrates over , although strictly it is Let us associate flicker noise with only one differential pair
over some fraction of , and also that over this duration the in the ring oscillator, and assume all other FETs are noiseless
noise PSD remains the same as in the balanced condition. The (Fig. 9). The noise can be modeled as an input offset voltage
magnitude of the differential current is that varies slowly. In response to a transition in the differential
input, the offset either advances or retards the rising edge, and
vice-versa the falling edge. When the input offset is constant
(56) over one period, it changes the duty cycle or mark-space ratio
of the output without affecting the period. Duty cycle variations
where at balance is defined as create second harmonic. Therefore, we conclude that flicker
noise in the differential pairs upconverts to , but does not
appear around .
(57) Flicker noise in the tail current modulates the delay directly.
While fluctuations originating in each tail current are uncorre-
The differential noise current integrates on a differential load of lated, the delay variations in all cells will add in phase due to
in parallel with . Using the result for leaky integration noise on the common gate voltage driving the tail FETs (Fig. 10)
(10), (57), the mean-square differential voltage after time is and cause a large phase deviation and phase noise. The mean
square jitter due to correlated noise is proportional to , in-
stead of as, for instance, in (41). This noise originates, for ex-
ample, from noise in the diode-connected FET that mirrors into
the tail currents. Mirrored white noise from this FET also raises
(58) the white noise in each tail current, but because of the rapid fluc-
tuations its effect is uncorrelated between the switching of one
Next we sum the uncorrelated noise voltages in (58), (55), delay stage and the next. Flicker noise, on the other hand, slows
and (51) and use (50) to calculate the period jitter: down or speeds up every delay stage in a concerted manner over
many cycles of oscillation, accumulating into a large variance in
phase.
We analyze this by deriving an effective VCO gain. In gen-
eral, the width of the diode-connected FET is of the width
(59) of the tail FETs in the delay stages. Further we assume that the
control current is noiseless. Using the expression (48) for oscil-
From (17) an expression follows for SSB phase noise due to lation frequency, we find the sensitivity to tail current. Phase
white noise in the differential oscillator: noise follows from (34).
(60) (61)
1812 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 8, AUGUST 2006
Fig. 9. Differential pair flicker noise modeled as a slowly changing input-referred voltage in a single delay stage of a ring oscillator, and the resulting effect on
the oscillation waveform.
Fig. 12. Differential ring oscillator, in which white noise cannot be measured
up to 1 MHz offset. Simulated phase noise, with flicker noise turned off, is com-
pared with predictions based on noise in delay stages.
Fig. 11. Differential delay cell with decoupled tail current control FET. Mea-
sured phase noise of ring oscillator is compared with prediction due to noise in
delay stages only, and simulation of complete circuit.
Fig. 14. Differential ring oscillator whose measured phase noise was, due to external noise sources, well above simulation. Composite prediction of flicker and
white noise-induced phase noise corresponds exactly with simulation.
the analysis shows that the slight change of slope measured at 2) flicker noise in the controlling branch of the tail currents
1 MHz offset is due to the onset of white noise. dominates the total close-in phase noise.
We have designed a three-stage, 1-GHz ring oscillator in
0.35- m CMOS as part of a disk drive read channel [35]
(Fig. 14). It uses NFET-based delay stages and an antisymmet- VII. RING OSCILLATOR OR LC OSCILLATOR?
rical load. Although its measured jitter was low enough for the Faced with the need for a high-frequency oscillator on a com-
application, the phase noise was several dBs larger than simu- munications IC, the circuit designer must decide between a ring
lation. We believe that we failed to take into account random oscillator and an LC oscillator. The tradeoffs are broadly un-
FM caused by noise on the frequency control (bias) current in derstood: for a given power budget, ring oscillators are compact
the transconductor driven by the PLL filter. Therefore, we use but noisy, whereas LC oscillators consume considerably more
SPECTRE-RF simulation to estimate the true inherent phase chip area but are low noise. We are now in a position to explore
noise of this circuit due to both flicker and white noise, except this tradeoff quantitatively. Assume that the oscillator is inside
in the bias which is assumed noiseless. This is a worthwhile a PLL which suppresses flicker noise, so white noise is the basis
exercise because we know the circuit details fully. In this circuit for comparison.
, but tail current modulation by the large input-referred The mechanisms of phase noise in the commonly used differ-
flicker noise voltage of the operational transconductance ampli- ential LC oscillator (Fig. 15) are well understood [36]. The total
fier (OTA) multiplied by causes phase noise. phase noise due to white noise is given by
Only this source of noise is used for predictions.
The fit between our expressions for composite phase noise
and simulation is striking. The phase noise simulation includes
all auxiliary circuits that tune frequency and control amplitude. (65)
The inset shows the parameter values used. This serves as fur-
ther validation of both white and flicker noise. where is the unloaded quality factor of the resonator at fre-
We may conclude that: quency , and the circuit-specific noise factor is given by
1) the simple expression (64) predicts phase noise due
to flicker noise accurately enough for the purposes of
(66)
first-time right design;
ABIDI: PHASE NOISE AND JITTER IN CMOS RING OSCILLATORS 1815
ACKNOWLEDGMENT
Fig. 15. Differential LC oscillator. S. Samadian checked the analysis and applied it to the
oscillators used for validation. He also simulated them on
SPECTRE-RF. He acknowledges help from, and useful dis-
Let us assume that this oscillator is designed optimally: that is, cussions with, L. Dai, D. Badillo, P. Kalkhoran, R. Harjani, S.
its output swing is the largest possible, ; and a filter Kiaei, J. Wong, and M. Mansuri. A. Mirzaie carefully read the
[37] suppresses its tail current noise, the third and largest term manuscript, pointed out errors and suggested improvements,
in (66). Then the phase noise reduces to derived (9) and (10), and plotted Fig. 4.
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IEEE Trans. Circuits Syst. I, Fundam. Theory Applicat., vol. 47, no. 5, Asad A. Abidi (S75M80SM95F96) received
pp. 655674, May 2000. the B.Sc. (with honors) degree from the Imperial Col-
[24] M. Lax, Classical noise. V. Noise in self-sustained oscillators, Phys. lege, London, U.K., in 1976, and the M.S. and Ph.D.
Rev., vol. 160, no. 2, pp. 291307, 1967. degrees in electrical engineering from the University
[25] C. Samori, A. Lacaita, A. Zanchi, and F. Pizzolato, Experimental ver- of California, Berkeley, CA, in 1978 and 1981, re-
ification of the link between timing jitter and phase noise, Electron. spectively.
Lett., vol. 34, no. 21, pp. 20242025, 1998. From 1981 to 1984, he was with Bell Laboratories,
[26] F. Herzel and B. Razavi, A study of oscillator jitter due to supply and Murray Hill, NJ, as a Member of Technical Staff at
substrate noise, IEEE Trans. Circuits Syst. II, Analog Digit. Signal the Advanced LSI Development Laboratory. Since
Process., vol. 46, no. 1, pp. 5662, Jan. 1999. 1985, he has been with the Electrical Engineering
[27] P. R. Gray, P. J. Hurst, S. H. Lewis, and R. G. Meyer, Analysis and Department, University of California, Los Angeles
Design of Analog Integrated Circuits, 3rd ed. New York: Wiley, 2001. (UCLA), where he is a Professor. He was a Visiting Faculty Researcher at
[28] E. Hegazi and A. Abidi, Varactor characteristics, oscillator tuning Hewlett Packard Laboratories in 1989. His research interests are in CMOS RF
curves, and AM-FM conversion, IEEE J. Solid-State Circuits, vol. 38, design, data high-speed analog integrated circuit design, conversion, and other
no. 6, pp. 10331039, Jun. 2003. techniques of analog signal processing.
[29] J. Chang, A. A. Abidi, and C. R. Viswanathan, Flicker noise in CMOS Dr. Abidi was the Program Secretary for the IEEE International Solid-State
transistors from subthreshold to strong inversion at various tempera- Circuits Conference (ISSCC) from 1984 to 1990, and the General Chairman of
tures, IEEE Trans. Electron Devices, vol. 41, no. 11, pp. 19651971, the Symposium on VLSI Circuits in 1992. He was the Secretary of the IEEE
Nov. 1994. Solid-State Circuits Council from 1990 to 1991. From 1992 to 1995, he was the
[30] C. Liu and J. McNeill, Jitter in oscillators with 1/f noise sources, Editor of the IEEE JOURNAL OF SOLID-STATE CIRCUITS. He received an IEEE
in Proc. IEEE Int. Symp. Circuits and Systems (ISCAS), 2004, pp. Millennium Medal, the 1988 TRW Award for Innovative Teaching, and the 1997
773776. IEEE Donald G. Fink Award, and is co-recipient of the Best Paper Award at the
[31] R. Navid, T. Lee, and R. Dutton, Minimum achievable phase noise 1995 European Solid-State Circuits Conference, the Jack Kilby Best Student
of RC oscillators, IEEE J. Solid-State Circuits, vol. 40, no. 3, pp. Paper Award at the 1996 ISSCC, the Jack Raper Award for Outstanding Tech-
630637, Mar. 2005. nology Directions Paper at the 1997 ISSCC, the Design Contest Award at the
[32] M. Grzing and M. Berroth, Derivation of single-ended CMOS in- 1998 Design Automation Conference, an Honorable Mention at the 2000 De-
verter ring oscillator close-in phase noise from basic circuit and de- sign Automation Conference, and the 2001 ISLPED Low Power Design Contest
vice properties, in IEEE Radio Frequency Integrated Circuits (RFIC) Award. He is a Fellow of the IEEE, and he was named one of the top ten con-
Symp. Dig. Papers, Ft. Worth, TX, 2004, pp. 277280. tributors to the ISSCC.