AMC1200

AMC1200B
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Fully-Differential Isolation Amplifier

Check for Samples: AMC1200, AMC1200B

1FEATURES DESCRIPTION
2• ±250-mV Input Voltage Range Optimized for The AMC1200 and AMC1200B are precision isolation
Shunt Resistors amplifiers with an output separated from the input
circuitry by a silicon dioxide (SiO2) barrier that is
• Very Low Nonlinearity: 0.075% max at 5 V highly resistant to magnetic interference. This barrier
• Low Offset Error: 1.5 mV max has been certified to provide galvanic isolation of up
• Low Noise: 3.1 mVRMS typ to 4250 VPEAK (AMC1200B) or 4000 VPEAK
(AMC1200) according to UL1577 and IEC60747-5-2.
• Low High-Side Supply Current: Used in conjunction with isolated power supplies,
8 mA max at 5 V these devices prevent noise currents on a high
• Input Bandwidth: 60 kHz min common-mode voltage line from entering the local
• Fixed Gain: 8 (0.5% accuracy) ground and interfering with or damaging sensitive
circuitry.
• High Common-Mode Rejection Ratio: 108 dB
• 3.3-V Operation on Low-Side The input of the AMC1200 or AMC1200B is optimized
for direct connection to shunt resistors or other low
• Certified Galvanic Isolation: voltage level signal sources. The excellent
– UL1577 and IEC60747-5-2 Approved performance of the device supports accurate current
– Isolation Voltage: 4250 VPEAK (AMC1200B) control resulting in system-level power saving and,
especially in motor-control applications, lower torque
– Working Voltage: 1200 VPEAK ripple. The common-mode voltage of the output
– Transient Immunity: 10 kV/µs min signal is automatically adjusted to either the 3-V or
• Typical 10-Year Lifespan at Rated Working 5-V low-side supply.
Voltage (see Application Report SLLA197) The AMC1200 and AMC1200B are fully specified
• Fully Specified Over the Extended Industrial over the extended industrial temperature range of
Temperature Range –40°C to +105°C and are available in a wide-body
SOIC-8 package (DWV) and a gullwing-8 package
APPLICATIONS (DUB).

• Shunt Resistor Based Current Sensing in:

– Motor Control
– Green Energy
– Frequency Inverters
– Uninterruptible Power Supplies
VDD1 VDD2

5V

2.55 V 2V
VINP VOUTP

0V 250 mV

3.3 V
VINN VOUTN
1.29 V 2V

GND1 GND2

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
AMC1200
AMC1200B
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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

PACKAGE/ORDERING INFORMATION
For the most current package and ordering information see the Package Option Addendum at the end of this
document, or visit the device product folder on www.ti.com.

ABSOLUTE MAXIMUM RATINGS (1)

Over the operating ambient temperature range, unless otherwise noted.
AMC1200, AMC1200B UNIT
Supply voltage, VDD1 to GND1 or VDD2 to GND2 –0.5 to 6 V
Analog input voltage at VINP, VINN GND1 – 0.5 to VDD1 + 0.5 V
Input current to any pin except supply pins ±10 mA
Maximum junction temperature, TJ Max +150 °C
Human body model (HBM)
JEDEC standard 22, test method ±2500 V
Electrostatic discharge (ESD) ratings, A114-C.01
all pins Charged device model (CDM)
JEDEC standard 22, test method ±1000 V
C101

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute
maximum rated conditions for extended periods may affect device reliability.

THERMAL INFORMATION
AMC1200, AMC1200B
(1)
THERMAL METRIC DUB (SOP) DWV (SOIC) UNITS
8 PINS 8 PINS
θJA Junction-to-ambient thermal resistance 75.1 102.8
θJCtop Junction-to-case (top) thermal resistance 61.6 49.8
θJB Junction-to-board thermal resistance 39.8 56.6
°C/W
ψJT Junction-to-top characterization parameter 27.2 16.0
ψJB Junction-to-board characterization parameter 39.4 55.2
θJCbot Junction-to-case (bottom) thermal resistance N/A N/A

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

REGULATORY INFORMATION
VDE/IEC UL
Certified according to IEC 60747-5-2 Recognized under 1577 component recognition program
File number: 40016131 File number: E181974

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IEC 60747-5-2 INSULATION CHARACTERISTICS

Over operating free-air temperature range (unless otherwise noted).
PARAMETER TEST CONDITIONS VALUE UNIT
VIORM Maximum working insulation voltage 1200 VPEAK
Qualification test: after Input/Output Safety Test Subgroup
1140 VPEAK
2/3 VPR = VIORM x 1.2, t = 10 s, partial discharge < 5 pC
Qualification test: method a, after environmental tests
VPR Input to output test voltage subgroup 1, VPR = VIORM x 1.6, t = 10 s, partial discharge 1920 VPEAK
< 5 pC
100% production test: method b1, VPR = VIORM x 1.875,
2250 VPEAK
t = 1 s, partial discharge < 5 pC
AMC1200 4000 VPEAK
VIOTM Transient overvoltage Qualification test: t = 60 s
AMC1200B 4250 VPEAK
AMC1200 4000 VPEAK
Qualification test: VTEST = VISO, t = 60 s
AMC1200B 4250 VPEAK
VISO Insulation voltage per UL
100% production test: VTEST = 1.2 x VISO, AMC1200 4800 VPEAK
t=1s AMC1200B 5100 VPEAK
9
RS Insulation resistance VIO = 500 V at TS > 10 Ω
PD Pollution degree 2 °

IEC SAFETY LIMITING VALUES

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output (I/O) circuitry. A
failure of the I/O circuitry can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient
power to overheat the die and damage the isolation barrier, potentially leading to secondary system failures.
The safety-limiting constraint is the operating virtual junction temperature range specified in the Absolute Maximum Ratings
table. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware
determine the junction temperature. The assumed junction-to-air thermal resistance in the Thermal Information table is that of
a device installed in the JESD51-3, Low Effective Thermal Conductivity Test Board for Leaded Surface Mount Packages and
is conservative. The power is the recommended maximum input voltage times the current. The junction temperature is then
the ambient temperature plus the power times the junction-to-air thermal resistance.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IS Safety input, output, or supply current θJA = 246°C/W, VIN = 5.5 V, TJ = +150°C, TA = +25°C 10 mA
TC Maximum case temperature +150 °C

IEC 61000-4-5 RATINGS

PARAMETER TEST CONDITIONS VALUE UNIT
VIOSM Surge immunity 1.2-μs/50-μs voltage surge and 8-μs/20-μs current surge ±6000 V

IEC 60664-1 RATINGS

PARAMETER TEST CONDITIONS SPECIFICATION
Basic isolation group Material group II
Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-IV
Installation classification
Rated mains voltage ≤ 400 VRMS I-III
Rated mains voltage < 600 VRMS I-III

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PACKAGE CHARACTERISTICS (1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Shortest terminal to terminal DWV package 8 mm
L(I01) Minimum air gap (clearance)
distance through air DUB package 7 mm
Shortest terminal to terminal DWV package 8 mm
Minimum external tracking
L(I02) distance across the package
(creepage) DUB package 7 mm
surface
Tracking resistance
CTI DIN IEC 60112/VDE 0303 part 1 ≥ 400 V
(comparative tracking index)
Minimum internal gap
Distance through the insulation 0.014 mm
(internal clearance)
Input to output, VIO = 500 V, all pins on each side of
the barrier tied together to create a two-terminal > 1012 Ω
RIO Isolation resistance device, TA < +85°C
Input to output, VIO = 500 V,
> 1011 Ω
+85°C ≤ TA < TA max
Barrier capacitance input to
CIO VI = 0.5 VPP at 1 MHz 1.2 pF
output
CI Input capacitance to ground VI = 0.5 VPP at 1 MHz 3 pF

(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of a specific
application. Care should be taken to maintain the creepage and clearance distance of the board design to ensure that the mounting
pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal
according to the measurement techniques shown in the Isolation Glossary section. Techniques such as inserting grooves and/or ribs on
the PCB are used to help increase these specifications.

ELECTRICAL CHARACTERISTICS
All minimum/maximum specifications at TA = –40°C to +105°C and within the specified voltage range, unless otherwise noted.
Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
AMC1200, AMC1200B
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT
Maximum input voltage before
VINP – VINN ±320 mV
clipping
Differential input voltage VINP – VINN –250 +250 mV
VCM Common-mode operating range -0.16 VDD1 V
VOS Input offset voltage –1.5 ±0.2 +1.5 mV
TCVOS Input offset thermal drift –10 ±1.5 +10 µV/K
VIN from 0 V to 5 V at 0 Hz 108 dB
CMRR Common-mode rejection ratio
VIN from 0 V to 5 V at 50 kHz 95 dB
CIN Input capacitance to GND1 VINP or VINN 3 pF
CIND Differential input capacitance 3.6 pF
RIN Differential input resistance 28 kΩ
Small-signal bandwidth 60 100 kHz
OUTPUT
Nominal gain 8
Initial, at TA = +25°C –0.5 ±0.05 +0.5 %
GERR Gain error
–1 ±0.05 +1 %
TCGERR Gain error thermal drift ±56 ppm/K
4.5 V ≤ VDD2 ≤ 5.5 V –0.075 ±0.015 +0.075 %
Nonlinearity
2.7 V ≤ VDD2 ≤ 3.6 V –0.1 ±0.023 +0.1 %
Nonlinearity thermal drift 2.4 ppm/K
Output noise VINP = VINN = 0 V 3.1 mVRMS
vs VDD1, 10-kHz ripple 80 dB
PSRR Power-supply rejection ratio
vs VDD2, 10-kHz ripple 61 dB

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ELECTRICAL CHARACTERISTICS (continued)

All minimum/maximum specifications at TA = –40°C to +105°C and within the specified voltage range, unless otherwise noted.
Typical values are at TA = +25°C, VDD1 = 5 V, and VDD2 = 3.3 V.
AMC1200, AMC1200B
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Rise/fall time 0.5-V step, 10% to 90% 3.66 6.6 µs
0.5-V step, 50% to 10%, unfiltered output 1.6 3.3 µs
VIN to VOUT signal delay 0.5-V step, 50% to 50%, unfiltered output 3.15 5.6 µs
0.5-V step, 50% to 90%, unfiltered output 5.26 9.9 µs
Common-mode transient
CMTI VCM = 1 kV 10 15 kV/µs
immunity
2.7 V ≤ VDD2 ≤ 3.6 V 1.15 1.29 1.45 V
Output common-mode voltage
4.5 V ≤ VDD2 ≤ 5.5 V 2.4 2.55 2.7 V
Short-circuit current 20 mA
ROUT Output resistance 2.5 Ω
POWER SUPPLY
VDD1 High-side supply voltage 4.5 5.0 5.5 V
VDD2 Low-side supply voltage 2.7 5.0 5.5 V
IDD1 High-side supply current 5.4 8 mA
2.7 V < VDD2 < 3.6 V 3.8 6 mA
IDD2 Low-side supply current
4.5 V < VDD2 < 5.5 V 4.4 7 mA
PDD1 High-side power dissipation 27.0 44.0 mW
2.7 V < VDD2 < 3.6 V 11.4 21.6 mW
PDD2 Low-side power dissipation
4.5 V < VDD2 < 5.5 V 22.0 38.5 mW

PIN CONFIGURATIONS

DUB PACKAGE
SOP-8 DWV PACKAGE
(TOP VIEW) SOIC-8
(TOP VIEW)

VDD1 1 8 VDD2
VDD1 1 8 VDD2
VINP 2 7 VOUTP
VINP 2 7 VOUTP
VINN 3 6 VOUTN
VINN 3 6 VOUTN
GND1 4 5 GND2
GND1 4 5 GND2

PIN DESCRIPTIONS
PIN # PIN NAME FUNCTION DESCRIPTION
1 VDD1 Power High-side power supply
2 VINP Analog input Noninverting analog input
3 VINN Analog input Inverting analog input
4 GND1 Power High-side analog ground
5 GND2 Power Low-side analog ground
6 VOUTN Analog output Inverting analog output
7 VOUTP Analog output Noninverting analog output
8 VDD2 Power Low-side power supply

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TYPICAL CHARACTERISTICS
At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
INPUT OFFSET INPUT OFFSET
vs HIGH-SIDE SUPPLY VOLTAGE vs LOW-SIDE SUPPLY VOLTAGE
2 2
VDD2 = 2.7 V to 3.6 V
1.5 1.5

1 1
Input Offset (mV)

Input Offset (mV)

0.5 0.5

0 0

−0.5 −0.5

−1 −1

−1.5 −1.5

−2 −2
4.5 4.75 5 5.25 5.5 2.7 3 3.3 3.6
VDD1 (V) VDD2 (V)
Figure 1. Figure 2.

INPUT OFFSET INPUT OFFSET

vs LOW-SIDE SUPPLY VOLTAGE vs TEMPERATURE
2 2
VDD2 = 4.5 V to 5.5 V
1.5 1.5

1 1
Input Offset (mV)

Input Offset (mV)

0.5 0.5

0 0

−0.5 −0.5

−1 −1

−1.5 −1.5

−2 −2
4.5 4.75 5 5.25 5.5 −40 −25 −10 5 20 35 50 65 80 95 110 125
VDD2 (V) Temperature (°C)
Figure 3. Figure 4.

COMMON-MODE REJECTION RATIO INPUT CURRENT

vs INPUT FREQUENCY vs INPUT VOLTAGE
130 40

120 30

110 20
Input Current (µA)

100 10
CMRR (dB)

90 0

80 −10

70 −20

60 −30

50 −40
0.1 1 10 100 −400 −300 −200 −100 0 100 200 300 400
Input Frequency (kHz) Input Voltage (mV)
Figure 5. Figure 6.

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TYPICAL CHARACTERISTICS (continued)

At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
INPUT BANDWIDTH GAIN ERROR
vs TEMPERATURE vs HIGH-SIDE SUPPLY VOLTAGE
120 1
0.8
110
0.6
Input Bandwidth (kHz)

0.4
100

Gain Error (%)

0.2
90 0
−0.2
80
−0.4
−0.6
70
−0.8
60 −1
−40 −25 −10 5 20 35 50 65 80 95 110 125 4.5 4.75 5 5.25 5.5
Temperature (°C) VDD1 (V)
Figure 7. Figure 8.

GAIN ERROR GAIN ERROR

vs LOW-SIDE SUPPLY VOLTAGE vs LOW-SIDE SUPPLY VOLTAGE
1 1
VDD2 = 2.7 V to 3.6 V VDD2 = 4.5 V to 5.5 V
0.8 0.8
0.6 0.6
0.4 0.4
Gain Error (%)

Gain Error (%)

0.2 0.2
0 0
−0.2 −0.2
−0.4 −0.4
−0.6 −0.6
−0.8 −0.8
−1 −1
2.7 3 3.3 3.6 4.5 4.75 5 5.25 5.5
VDD2 (V) VDD2 (V)
Figure 9. Figure 10.

GAIN ERROR NORMALIZED GAIN

vs TEMPERATURE vs INPUT FREQUENCY
1 10
0.8 0
0.6 −10
Normalized Gain (dB)

0.4
−20
Gain Error (%)

0.2
−30
0
−40
−0.2
−50
−0.4
−0.6 −60

−0.8 −70

−1 −80
−40 −25 −10 5 20 35 50 65 80 95 110 125 1 10 100 500
Temperature (°C) Input Frequency (kHz)
Figure 11. Figure 12.

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TYPICAL CHARACTERISTICS (continued)

At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
OUTPUT PHASE OUTPUT VOLTAGE
vs INPUT FREQUENCY vs INPUT VOLTAGE
0 5
−30 VOUTP
4.5 VOUTN
−60
4
−90
3.5

Output Voltage (V)

Output Phase (°)

−120
−150 3
−180 2.5
−210 2
−240
1.5
−270
1
−300
−330 0.5
−360 0
1 10 100 1000 −400 −300 −200 −100 0 100 200 300 400
Input Frequency (kHz) Input Voltage (mV)
Figure 13. Figure 14.

OUTPUT VOLTAGE NONLINEARITY

vs INPUT VOLTAGE vs HIGH-SIDE SUPPLY VOLTAGE
3.6 0.1
3.3 VDD2 = 2.7 V to 3.6 V VOUTP
VOUTN 0.08
3
0.06
2.7
0.04
Output Voltage (V)

2.4
Nonlinearity (%)

2.1 0.02
1.8 0
1.5 −0.02
1.2
−0.04
0.9
−0.06
0.6
0.3 −0.08
0 −0.1
−400 −300 −200 −100 0 100 200 300 400 4.5 4.75 5 5.25 5.5
Input Voltage (mV) VDD1 (V)
Figure 15. Figure 16.

NONLINEARITY NONLINEARITY
vs LOW-SIDE SUPPLY VOLTAGE vs LOW-SIDE SUPPLY VOLTAGE
0.1 0.1
VDD2 = 2.7 V to 3.6 V VDD2 = 4.5 V to 5.5 V
0.08 0.08
0.06 0.06
0.04 0.04
Nonlinearity (%)

Nonlinearity (%)

0.02 0.02
0 0
−0.02 −0.02
−0.04 −0.04
−0.06 −0.06
−0.08 −0.08
−0.1 −0.1
2.7 3 3.3 3.6 4.5 4.75 5 5.25 5.5
VDD2 (V) VDD2 (V)
Figure 17. Figure 18.

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TYPICAL CHARACTERISTICS (continued)

At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
NONLINEARITY NONLINEARITY
vs INPUT VOLTAGE vs TEMPERATURE
0.1 0.1
VDD2 = 3 V
0.08 VDD2 = 5 V 0.08
0.06 0.06
0.04 0.04
Nonlinearity (%)

Nonlinearity (%)
0.02 0.02
0 0
−0.02 −0.02
−0.04 −0.04
−0.06 −0.06
−0.08 −0.08
−0.1 −0.1
−250 −200 −150 −100 −50 0 50 100 150 200 250 −40 −25 −10 5 20 35 50 65 80 95 110 125
Input Voltage (mV) Temperature (°C)
Figure 19. Figure 20.

OUTPUT NOISE DENSITY POWER-SUPPLY REJECTION RATIO

vs FREQUENCY vs RIPPLE FREQUENCY
2600 100
VDD1
2400 90 VDD2
2200 80
Noise (nV/sqrt(Hz))

2000 70
PSRR (dB)

1800 60
1600 50
1400 40
1200 30
1000 20
800 10
600 0
0.1 1 10 100 1 10 100
Frequency (kHz) Ripple Frequency (kHz)
Figure 21. Figure 22.

OUTPUT RISE/FALL TIME FULL-SCALE

vs TEMPERATURE STEP RESPONSE
10
9
8
Output Rise/Fall Time (µs)

7 500 mV/div
6
5
4
3 200 mV/div

2
1 500 mV/div
0
−40 −25 −10 5 20 35 50 65 80 95 110 125 Time (2 ms/div)
Temperature (°C)
Figure 23. Figure 24.

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TYPICAL CHARACTERISTICS (continued)

At VDD1 = VDD2 = 5 V, VINP = –250 mV to +250 mV, and VINN = 0 V, unless otherwise noted.
OUTPUT SIGNAL DELAY TIME OUTPUT COMMON-MODE VOLTAGE
vs TEMPERATURE vs LOW-SIDE SUPPLY VOLTAGE
10 5
50% to 10% VDD2 rising
9

Output Common−Mode Voltage (V)

50% to 50% VDD2 falling
8 50% to 90% 4
7
Signal Delay (µs)

6 3
5
4 2
3
2 1
1
0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 3.5 3.6 3.7 3.8 3.9 4 4.1 4.2 4.3 4.4 4.5
Temperature (°C) VDD2 (V)
Figure 25. Figure 26.

OUTPUT COMMON-MODE VOLTAGE SUPPLY CURRENT

vs TEMPERATURE vs SUPPLY VOLTAGE
5 8
VDD2 = 2.7 V to 3.6 V IDD1
Output Common−Mode Voltage (V)

VDD2 = 4.5 V to 5.5 V 7 IDD2

4
6
Supply Current (mA)

3 5

4
2 3

2
1
1

0 0
−40 −25 −10 5 20 35 50 65 80 95 110 125 4.5 4.75 5 5.25 5.5
Temperature (°C) Supply Voltage (V)
Figure 27. Figure 28.

LOW-SIDE SUPPLY CURRENT SUPPLY CURRENT

vs LOW-SIDE SUPPLY VOLTAGE vs TEMPERATURE
8 8
VDD2 = 2.7 V to 3.6 V
7 7

6 6
Supply Current (mA)

5 5
IDD2 (mA)

4 4

3 3

2 2

1 1 IDD1
IDD2
0 0
2.7 3 3.3 3.6 −40 −25 −10 5 20 35 50 65 80 95 110 125
VDD2 (V) Temperature (°C)
Figure 29. Figure 30.

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THEORY OF OPERATION

INTRODUCTION
The differential analog input of the AMC1200 and AMC1200B is a switched-capacitor circuit based on a second-
order modulator stage that digitizes the input signal into a 1-bit output stream. These devices compare the
differential input signal (VIN = VINP – VINN) against the internal reference of 2.5 V using internal capacitors that
are continuously charged and discharged with a typical frequency of 10 MHz. With the S1 switches closed, CIND
charges to the voltage difference across VINP and VINN. For the discharge phase, both S1 switches open first
and then both S2 switches close. CIND discharges to approximately AGND + 0.8V during this phase. Figure 31
shows the simplified equivalent input circuitry.
VDD1 GND1
GND1

CINP = 3pF
3pF
400W
Equivalent
VINP AGND + 0.8V VINP
S1 S2 Circuit
CIND = 3.6pF RIN = 28kW
S1 400W S2
VINN AGND + 0.8V VINN

3pF
CINN = 3pF

1 GND1
RIN =
GND1 GND1 fCLK · CDIFF
(fCLK = 10MHz)

Figure 31. Equivalent Input Circuit

The analog input range is tailored to directly accommodate a voltage drop across a shunt resistor used for
current sensing. However, there are two restrictions on the analog input signals, VINP and VINN. If the input
voltage exceeds the range AGND – 0.5 V to AVDD + 0.5 V, the input current must be limited to 10 mA to prevent
the implemented input protection diodes from damage. In addition, the linearity and the noise performance of the
device are ensured only when the differential analog input voltage remains within ±250 mV.
The isolated digital bit stream is processed by a third-order analog filter on the low-side and presented as a
differential output of the device.
The SiO2-based capacitive isolation barrier supports a high level of magnetic field immunity, as described in
application report SLLA181, ISO72x Digital Isolator Magnetic-Field Immunity (available for download at
www.ti.com).

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APPLICATION INFORMATION

MOTOR CONTROL
A typical operation of the AMC1200 and AMC1200B in a motor-control application is shown in Figure 32.
Measurement of the motor phase current is done through the shunt resistor, RSHUNT (in this case, a two-terminal
shunt). For better performance, the differential signal is filtered using RC filters (components R2, R3, and C2).
Optionally, C3 and C4 can be used to reduce charge dumping from the inputs. In this case, care should be taken
when choosing the quality of these capacitors; mismatch in values of these capacitors leads to a common-mode
error at the input of the modulator.
Floating Isolation
HV+ Power Supply
Barrier

Gated TMC320
Drive R1 AMC1200 C/F28xxx
Circuit AMC1200B

VDD1 VDD2
D1 R2 C1(1) C5(1)
5.1V 12W 0.1mF 0.1mF
VINP VOUTP
R3 C2(1)
ADC
RSHUNT 12W 330pF
To Load VINN VOUTN
C3 C4
Power 10pF 10pF
Supply (optional) (optional)
GND1 GND2

Gated
Drive
Circuit

HV-

(1) Place these capacitors as close as possible to the AMC device.

Figure 32. Typical Application Diagram

The high-side power supply (VDD1) for the AMC1200 and AMC1200B are derived from the power supply of the
upper gate driver. For lowest cost, a Zener diode can be used to limit the voltage to 5 V ±10%. A decoupling
capacitor of 0.1 µF is recommended for filtering this power-supply path. This capacitor (C1 in Figure 32) should
be placed as close as possible to the VDD1 pin for best performance. If better filtering is required, an additional
1-µF to 10-µF capacitor can be used. The floating ground reference (GND1) is derived from the end of the shunt
resistor, which is connected to the negative input (VINN) of the AMC device. If a four-terminal shunt is used, the
inputs of AMC device are connected to the inner leads, while GND1 is connected to one of the outer leads of the
shunt.
The high transient immunity of the AMC1200 and AMC1200B ensures reliable and accurate operation even in
high-noise environments such as the power stages of the motor drives.
The differential output of the AMC1200 and AMC1200B can either directly drive an analog-to-digital converter
(ADC) input or can be further filtered before being processed by the ADC.
As shown in Figure 33, it is recommended to place the bypass and filter capacitors as close as possible to the
AMC device to ensure best performance.

12 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: AMC1200 AMC1200B

 AMC1200
AMC1200B
www.ti.com SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013

Top View

VDD1 VDD2

12 W VINP VOUTP 0.1mF

SMD 0603
330 pF 0.1 mF 0.1 mF
To Shunt SMD SMD AMC1200 SMD To Filter or ADC
12 W 0603 1206
AMC1200B SMD
1206
SMD 0603 VINN VOUTN 1206

GND1 GND2

LEGEND
Clearance area.
Top layer; copper pour and traces Keep free of any
conductive materials.
High-side area

Controller-side area

Via

Figure 33. Layout Recommendation

To maintain the isolation barrier and the high CMTI of the device, the distance between the high-side ground (GND1) and the low-side ground (GND2)
should be kept at maximum; that is, the entire area underneath the device should be kept free of any conducting materials.

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 13

Product Folder Links: AMC1200 AMC1200B
AMC1200
AMC1200B
SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013 www.ti.com

VOLTAGE MEASUREMENT
The AMC1200 and AMC1200B can also be used for isolated voltage measurement applications, as shown in a
simplified way in Figure 34. In such applications, usually a resistor divider (R1 and R2 in Figure 34) is used to
match the relatively small input voltage range of the AMC device. R2 and the input resistance RIN of the
AMC1200 also create a resistance divider that results in additional gain error. With the assumption that R1 and
RIN have a considerably higher value than R2, the resulting total gain error can be estimated using Equation 1:
R
GERRTOT = GERR + 2
RIN

Where GERR = the gain error of AMC device.

(1)

L1

R1

R2 RIN

L2

Figure 34. Voltage Measurement Application

14 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: AMC1200 AMC1200B

 AMC1200
AMC1200B
www.ti.com SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013

ISOLATION GLOSSARY

Creepage Distance: The shortest path between two conductive input to output leads measured along the
surface of the insulation. The shortest distance path is found around the end of the package body.

Clearance: The shortest distance between two conductive input to output leads measured through air (line of
sight).

Input-to-Output Barrier Capacitance: The total capacitance between all input terminals connected together,
and all output terminals connected together.
Input-to-Output Barrier Resistance: The total resistance between all input terminals connected together, and
all output terminals connected together.
Primary Circuit: An internal circuit directly connected to an external supply mains or other equivalent source that
supplies the primary circuit electric power.
Secondary Circuit: A circuit with no direct connection to primary power that derives its power from a separate
isolated source.
Comparative Tracking Index (CTI): CTI is an index used for electrical insulating materials. It is defined as the
numerical value of the voltage that causes failure by tracking during standard testing. Tracking is the process that
produces a partially conducting path of localized deterioration on or through the surface of an insulating material
as a result of the action of electric discharges on or close to an insulation surface. The higher CTI value of the
insulating material, the smaller the minimum creepage distance.
Generally, insulation breakdown occurs either through the material, over its surface, or both. Surface failure may
arise from flashover or from the progressive degradation of the insulation surface by small localized sparks. Such
sparks are the result of the breaking of a surface film of conducting contaminant on the insulation. The resulting
break in the leakage current produces an overvoltage at the site of the discontinuity, and an electric spark is
generated. These sparks often cause carbonization on insulation material and lead to a carbon track between
points of different potential. This process is known as tracking.

Insulation:
Operational insulation—Insulation needed for the correct operation of the equipment.
Basic insulation—Insulation to provide basic protection against electric shock.
Supplementary insulation—Independent insulation applied in addition to basic insulation in order to ensure
protection against electric shock in the event of a failure of the basic insulation.
Double insulation—Insulation comprising both basic and supplementary insulation.
Reinforced insulation—A single insulation system that provides a degree of protection against electric shock
equivalent to double insulation.

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: AMC1200 AMC1200B
AMC1200
AMC1200B
SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013 www.ti.com

Pollution Degree:
Pollution Degree 1—No pollution, or only dry, nonconductive pollution occurs. The pollution has no influence on
device performance.
Pollution Degree 2—Normally, only nonconductive pollution occurs. However, a temporary conductivity caused
by condensation is to be expected.
Pollution Degree 3—Conductive pollution, or dry nonconductive pollution that becomes conductive because of
condensation, occurs. Condensation is to be expected.
Pollution Degree 4—Continuous conductivity occurs as a result of conductive dust, rain, or other wet conditions.

Installation Category:
Overvoltage Category—This section is directed at insulation coordination by identifying the transient overvoltages
that may occur, and by assigning four different levels as indicated in IEC 60664.
1. Signal Level: Special equipment or parts of equipment.
2. Local Level: Portable equipment, etc.
3. Distribution Level: Fixed installation.
4. Primary Supply Level: Overhead lines, cable systems.
Each category should be subject to smaller transients than the previous category.

16 Submit Documentation Feedback Copyright © 2011–2013, Texas Instruments Incorporated

Product Folder Links: AMC1200 AMC1200B

 AMC1200
AMC1200B
www.ti.com SBAS542C – APRIL 2011 – REVISED SEPTEMBER 2013

REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision B (August 2012) to Revision C Page

• Added DWV (SOIC-9) package to document ....................................................................................................................... 1

• Deleted device graphic ......................................................................................................................................................... 1
• Changed last paragraph of Description section .................................................................................................................... 1
• Added DWV column to Thermal Information table ............................................................................................................... 2
• Added row for DWV package to L(I01) and L(I02) parameters in Package Characteristics table ....................................... 4
• Added DWV pin out drawing ................................................................................................................................................. 5

Changes from Revision A (August 2011) to Revision B Page

• Added AMC1200B device to data sheet ............................................................................................................................... 1

• Changed Isolation Voltage feature bullet .............................................................................................................................. 1
• Changed CTI parameter minimum value in Electrical Characteristics from ≥ 175 to ≥ 400 ................................................. 4
• Changed title for Figure 25 ................................................................................................................................................. 10

Changes from Original (April 2011) to Revision A Page

• Changed sign for maximum junction temperature from minus to plus (typo) ....................................................................... 2
• Changed surge immunity parameter from ±4000 to ±6000 .................................................................................................. 3
• Added "0.5-V step" to test condition for Rise/fall time parameter ......................................................................................... 5
• Changed Figure 12 ............................................................................................................................................................... 7
• Changed Figure 13 ............................................................................................................................................................... 7

Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback 17

Product Folder Links: AMC1200 AMC1200B
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jul-2014

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

AMC1200BDUB ACTIVE SOP DUB 8 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 1200B
& no Sb/Br)
AMC1200BDUBR ACTIVE SOP DUB 8 350 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 1200B
& no Sb/Br)
AMC1200BDWV ACTIVE SOIC DWV 8 64 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 105 AMC1200B
& no Sb/Br)
AMC1200BDWVR ACTIVE SOIC DWV 8 1000 Green (RoHS CU SN Level-2-260C-1 YEAR -40 to 105 AMC1200B
& no Sb/Br)
AMC1200SDUB ACTIVE SOP DUB 8 50 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 AMC1200
& no Sb/Br)
AMC1200SDUBR ACTIVE SOP DUB 8 350 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 105 AMC1200
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 25-Jul-2014

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF AMC1200 :

• Automotive: AMC1200-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Nov-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
AMC1200BDUBR SOP DUB 8 350 330.0 24.4 10.9 10.01 5.85 16.0 24.0 Q1
AMC1200BDWVR SOIC DWV 8 1000 330.0 16.4 12.05 6.15 3.3 16.0 16.0 Q1
AMC1200SDUBR SOP DUB 8 350 330.0 24.4 10.9 10.01 5.85 16.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 8-Nov-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
AMC1200BDUBR SOP DUB 8 350 358.0 335.0 35.0
AMC1200BDWVR SOIC DWV 8 1000 367.0 367.0 38.0
AMC1200SDUBR SOP DUB 8 350 406.0 348.0 63.0

Pack Materials-Page 2
 PACKAGE OUTLINE

DWV0008A SCALE 2.000

SOIC - 2.8 mm max height
SOIC

SEATING PLANE
11.5 0.25
PIN 1 ID TYP 0.1 C
AREA
6X 1.27
8
1

5.95 2X
5.75 3.81
NOTE 3

4
5
0.51
8X
0.31
7.6 0.25 C A B
A B 2.8 MAX
7.4
NOTE 4

0.33
TYP
0.13

SEE DETAIL A

(2.286)
0.25
GAGE PLANE

0.46
0.36
0 -8
1.0
0.5 DETAIL A
(2) TYPICAL

4218796/A 09/2013

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

www.ti.com
 EXAMPLE BOARD LAYOUT

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SEE DETAILS

SYMM

8X (0.6) SYMM

6X (1.27)
(10.9)

LAND PATTERN EXAMPLE

9.1 mm NOMINAL CLEARANCE/CREEPAGE
SCALE:6X

SOLDER MASK SOLDER MASK METAL

METAL
OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4218796/A 09/2013

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN

DWV0008A SOIC - 2.8 mm max height

SOIC

8X (1.8) SYMM

8X (0.6)
SYMM

6X (1.27)

(10.9)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4218796/A 09/2013

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

www.ti.com
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