TLC 5971
TLC 5971
TLC 5971
1FEATURES APPLICATIONS
•
23 12 Constant-Current Sink Output Channels • RGB LED Cluster Lamp Displays
• Current Capability: 60 mA per channel
• Grayscale (GS) Control with Enhanced DESCRIPTION
Spectrum PWM: The TLC5971 is a 12-channel, constant-current sink
16-bit (65536 steps) driver. Each output channel has individually
adjustable currents with 65536 PWM grayscale (GS)
• Global Brightness Control (BC): steps. Also, each color group can be controlled by
7-bit (128 steps) for each color group 128 constant-current sink steps with the global
• Power-Supply Voltage Range: brightness control (BC) function. GS control and BC
Internal linear regulator: 6 V to 17 V are accessible via a two-wire signal interface. The
Direct power supply: 3 V to 5.5 V maximum current value for each channel is set by a
single external resistor. All constant-current outputs
• LED Supply Voltage: Up to 17 V are turned off when the IC is in an over-temperature
• Constant-Current Accuracy: condition.
– Channel-to-Channel = ±1% (typ)
– Device-to-Device = ±1% (typ)
• Data Transfer Rate: 20 MHz
• Linear Voltage Regulator: 3.3 V
• Auto Display Repeat Function
• Display Timing Reset Function
• Internal/External Selectable GS Clock
• Thermal Shutdown (TSD) with Auto Restart
• Unlimited Device Cascading
• Operating Temperature Range: –40°C to +85°C
VCC
Power
Supply
(6 V to 17 V) GND
OUTG3 OUTG3
OUTB3 OUTB3
GND
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments Incoporated.
3 All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
TLC5971
DESCRIPTION (CONTINUED)
VCC
Power
Supply
(3 V to 5.5 V) GND
¼
OUTG3 OUTG3
GND
VLED
Power
Supply
(15 V) GND
VCC
Power
Supply
(3 V to 5.5 V) GND
¼
OUTG3 OUTG3
GND
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or visit the
device product folder at www.ti.com.
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to network ground terminal.
THERMAL INFORMATION
TLC5971 TLC5971
THERMAL METRIC (1) PWP RGE UNITS
20 PINS 24 PINS
θJA Junction-to-ambient thermal resistance 68.6 38
θJCtop Junction-to-case (top) thermal resistance 44.2 40.5
θJB Junction-to-board thermal resistance 19.3 10.2
°C/W
ψJT Junction-to-top characterization parameter 2.7 0.3
ψJB Junction-to-board characterization parameter 15.7 10
θJCbot Junction-to-case (bottom) thermal resistance 1.8 2.9
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
DISSIPATION RATINGS
DERATING FACTOR POWER RATING POWER RATING POWER RATING
PACKAGE
ABOVE TA = +25°C TA < +25°C TA = +70°C TA = +85°C
HTSSOP 20-pin with PowerPAD soldered (1) 25.7 mW/°C 3121 mW 1998 mW 1623 mW
QFN 24-pin exposed thermal pad
24.8 mW/°C 3106 mW 1988 mW 1615 mW
soldered (2)
(1) With PowerPAD soldered onto copper area on TI recommended printed circuit board (PCB); 2-oz. copper. For more information, see
application report SLMA002, PowerPAD Thermally-Enhanced Package (available for download at www.ti.com).
(2) The package thermal impedance is calculated in accordance with JESD51-5.
ELECTRICAL CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, VLED = 5 V, and CVREG = 1 µF, unless otherwise
noted. Typical values are at TA = +25°C and VCC = 12 V.
TLC5971
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VOH High-level output voltage, SDTO/SCKO IOH = –2 mA VREG – 0.4 VREG V
VOL Low-level output voltage, SDTO/SCKO IOL = 2 mA 0 0.4 V
II Input current, SDTI/SCKI VI = VREG or GND –1 1 µA
SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,
ICC 2 4 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 24 kΩ (IOLCMax = 2 mA)
SDTI/SCKI = low, BLANK = 1, GSn = FFFFh,
ICC1 6 9 mA
BCX = 7Fh, VOUTXn = 1 V, RIREF = 1.6 kΩ (IOLCMax = 30 mA)
(1) The deviation of each output in the same color group (OUTR0-OUTR3 or OUTG0-OUTG3 or OUTB0-OUTB3) from the average current
from the same color group. Deviation is calculated by the formula:
IOLCXn
D (%) = -1 ´ 100
(IOLCX0 + IOLCX1 + IOLCX2 + IOLCX3)
4
Where: X = R/G/B, and n = 0-3
(2) The deviation of each color group constant-current average from the ideal constant-current value.
Deviation is calculated by the following formula:
(IOLCX0 + IOLCX1 + IOLCX2 + IOLCX3)
- (Ideal Output Current)
4
D (%) = ´ 100
Ideal Output Current
Where: X = R/G/B.
Ideal current is calculated by the following formula for the OUTRn and OUTGn groups:
1.21
IOLCXn(IDEAL) (mA) = 41 ´
RIREF (W)
Where: X = R/G/B.
(3) Line regulation is calculated by this equation:
(IOLCXn at VCC = 5.5 V) - (IOLCXn at VCC = 3 V) 100
D (%/V) = ´
(IOLCXn at VCC = 3 V) 5.5 V - 3 V
SWITCHING CHARACTERISTICS
At TA = –40°C to +85°C, VCC = 6 V to 17 V or VCC = VREG = 3 V to 5.5 V, CVREG = 1 µF, CL = 15 pF, RL = 68 Ω, and VLED =
5 V, unless otherwise noted. Typical values are at TA = +25°C and VCC = 12 V.
TLC5971
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tR0 Rise time, SDTO/SCKO 3 10 ns
tR1 Rise time, OUTXn BCX = 7Fh 5 15 ns
tF0 Fall time, SDTO/SCKO 3 10 ns
tF1 Fall time, OUTXn BCX = 7Fh 15 25 ns
tD0 SCKI↑ to SDTO↑↓ 10 25 60 ns
tD1 SCKI↑ to SCKO↑ 5 15 40 ns
tD2 (1) SCKO↑ to SDTO↑↓ 5 10 20 ns
SCKI↑ to OUTRn↑↓, BLANK = 0, BCXn = 7Fh,
OUTTMG = 1
tD3 10 25 60 ns
Or SCKI↓ to OUTRn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 0
SCKI↑ to OUTGn↑↓, BLANK = 0, BCXn = 7Fh,
Propagation delay
OUTTMG = 1
tD4 25 50 90 ns
Or SCKI↓ to OUTGn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 0
SCKI↑ to OUTBn↑↓, BLANK = 0, BCXn = 7Fh,
OUTTMG = 1
tD5 40 75 120 ns
Or SCKI↓ to OUTBn↑↓, BLANK = 0, BCXn =
7Fh, OUTTMG = 0
16384/fO
tD6 (2) Last SCKI↑ to internal latch pulse genaration 8/fOSC sec
SC
Shift clock output one pulse
tW(SCKO) SCKO↑ to SCKO↓ 12 25 35 ns
width
fOSC Internal oscillator frequency 6 10 12 MHz
VCC
3.3 V VREG
REG
LSB MSB UVLO reset
SDTI
224-Bit Shift Register SDTO
Clock 0 223
SCKI Timing SCKO
Adjust 6
Write
218
Command
Decode
wrtena
LSB MSB
intlat
Data 218-Bit Data Latch
Latch reset
Control
0 217
26
EXTCLK
1 intlat 2 BLANK
TMGRST 192 3
Clock GS Clock Thermal
Select Counter BLANK Detection
DSPRPT
16 GSX
OUTTMG
Internal
16-Bit ES-PWM Timing Control
Oscillator
12
21
BCX
12
Reference
12-Channel Constant Sink Current Driver
IREF Current
with 7-Bit, 3-Grouped BC
Control
GND
PIN CONFIGURATIONS
PWP PACKAGE
HTSSOP-20 PowerPAD RGE PACKAGE
(TOP VIEW) QFN-24
(TOP VIEW)
OUTG1
OUTG0
OUTR0
OUTR1
OUTB0
OUTB1
IREF 1 20 VREG
GND 2 19 VCC
21
23
22
20
24
19
OUTR0 3 18 OUTB3
OUTG0 4 17 OUTG3
SDTI 1 18 GND
OUTB0 5 PowerPAD 16 OUTR3
SCKI 2 17 NC
(Bottom Side)
OUTR1 6 15 OUTB2 (1)
NC 3 Thermal Pad 16 IREF
OUTG1 7 14 OUTG2 (Bottom Side)
NC 4 15 VREG
OUTB1 8 13 OUTR2
SCKO 5 14 NC
SDTI 9 12 SDTO
SDTO 6 13 VCC
SCKI 10 11 SCKO
11
12
10
9
8
7
OUTR2
OUTR3
OUTB2
OUTG3
OUTB3
OUTG2
(1) NC = not connected
TERMINAL FUNCTIONS
TERMINAL
NAME PWP RGE I/O DESCRIPTION
SDTI 9 1 I Serial data input for the 224-bit shift register
Serial data shift clock input.
Data present on SDTI are shifted to the LSB of the 224-bit shift register with the SCKI rising edge
SCKI 10 2 I
Data in the shift register are shifted toward the MSB at each SCKI rising edge.
The MSB data of the shift register appear on SDTO.
Serial data output of the 224-bit shift register.
SDTO 12 6 O SDTO is connected to the MSB of the 224-bit shift register.
Data are clocked out at the SCKI rising edge.
Serial data shift clock output.
SCKO 11 5 O The input shift clock signal from SCKI is adjusted to the timing of the serial data output for SDTO
and the signal is then output at SCKO.
Internal linear voltage regulator output.
A decoupling capacitor of 1 µF must be connected. This output can be used for external devices
VREG 20 15 I/O as a 3.3-V power supply. This terminal can be connected with the VREG terminal of other
devices to increase the supply current. Also, this pin can be supplied with 3 V to 5.5 V from an
external power supply by connecting it to VCC.
Maximum current programming terminal.
A resistor connected between IREF and GND sets the maximum current for every constant-
IREF 1 16 I/O
current output. When this terminal is directly connected to GND, all outputs are forced off. The
external resistor should be placed close to the device.
OUTR0 3 19 O
OUTR1 6 22 O RED constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTR2 13 7 O Different voltages can be applied to each output.
OUTR3 16 10 O
OUTG0 4 20 O
OUTG1 7 23 O GREEN constant-current outputs.
Multiple outputs can be configured in parallel to increase the constant-current capability.
OUTG2 14 8 O Different voltages can be applied to each output.
OUTG3 17 11 O
INPUT
OUTPUT
GND
GND
Figure 1. SDTI/SCKI
Figure 2. SDTO/SCKO
(1)
OUTXn
GND
(1) X = R/G/B, n = 0-3.
TEST CIRCUITS
VCC
RL
VREG VCC
(1)
OUTXn VLED
VCC
IREF
CVREG CL
(2) VREG SDTO/SCKO
GND VCC
RIREF
(1)
CVREG CL
GND
VCC
OUTR0
¼ ¼
VREG
(1)
OUTXn
VCC
IREF
CVREG OUTB3 VOUTXn
RIREF GND
VOUTfix
TIMING DIAGRAMS
TWH, TWL:
VREG
(1)
SCKI 50%
GND
TWH TWL
TSU, TH:
VREG
(1)
SCKI 50%
GND
TSU TH
VREG
(1)
SDTI 50%
GND
(1) Input pulse rise and fall time is 1ns to 3ns.
tR0, tR1, tF0, tF1, tD0, tD1, tD2, tD3, tD4, tD5:
VREG
(1) 50%
INPUT
GND
tD
VOH or VOUTXnH
90%
OUTPUT 50%
10%
VOL or VOUTXnL
tR or tF
DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTI 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C 215C
tH
tSU tWH
SCKI
1 2 6 222 223 224 1 2 3 4 5 6 7 8 9
tWL
224-Bit Shift Register DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA
LSB (Internal) 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C
224-Bit Shift Register DATA DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA
CMD0
LSB + 1 (Internal) 1A 0A CMD5 CMD1 3B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C
¼
¼
224-Bit Shift Register WRT WRT WRT DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA DATA
MSB - 1 (Internal) CMD4 CMD3 CMD2 216A 215A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B 214B
224-Bit Shift Register WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
MSB (Internal) CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B
(2)
tD6
Latch Signal
(Internal)
Latch Data
Previous Data Latest Data (All GS Data are 0001h)
(Internal)
1
BLANK Bit in Data Latch
(Internal) 0
1
EXTGCK Bit in Data Latch
(Internal) 0
1
OUTTMG Bit in Data Latch
(Internal) 0
tD0
WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTO CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B
tR0/tF0
tD1 tW(SCKO)
SCKO
tF1
(VOUTXnH)
OFF (1)
OUTR0-R3 (VOUTXnL)
ON
tR1
(VOUTXnH) tD3
OFF (1)
OUTG0-G3 (VOUTXnL)
ON
tD4
(VOUTXnH)
OFF (1)
OUTB0-B3 (VOUTXnL)
ON
tD5
(1) OUTXn on-off timing depends on previous GS data in the 218-bit data latch.
(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal latch signal
generation.
DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTI 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C 215C
tH
tSU tWH
SCKI
1 2 6 222 223 224 1 2 3 4 5 6 7 8 9
tWL
224-Bit Shift Register DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA
LSB (Internal) 0A CMD5 CMD4 CMD0 217B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C 216C
224-Bit Shift Register DATA DATA WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA
CMD0
LSB + 1 (Internal) 1A 0A CMD5 CMD1 3B 2B 1B 0B CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217C
¼
¼
224-Bit Shift Register WRT WRT WRT DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA DATA
MSB - 1 (Internal) CMD4 CMD3 CMD2 216A 215A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B 214B
224-Bit Shift Register WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
MSB (Internal) CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B
(2)
tD6
Latch Signal
(Internal)
Latch Data
Previous Data Latest Data (All GS Data are 0001h)
(Internal)
1
BLANK Bit in Data Latch
(Internal) 0
1
EXTGCK Bit in Data Latch
(Internal) 0
1
OUTTMG Bit in Data Latch
(Internal) 0
tD0
WRT WRT WRT DATA DATA DATA DATA WRT WRT WRT WRT WRT WRT DATA DATA DATA
SDTO CMD5 CMD4 CMD3 217A 216A 1A 0A CMD5 CMD4 CMD3 CMD2 CMD1 CMD0 217B 216B 215B
tR0/tF0
tD1 tW(SCKO)
SCKO
tF1
(VOUTXnH)
OFF (1)
OUTR0-R3 (VOUTXnL)
ON
tR1
(VOUTXnH) tD3
OFF (1)
OUTG0-G3 (VOUTXnL)
ON
tD4
(VOUTXnH)
OFF (1)
OUTB0-B3 (VOUTXnL)
ON
tD5
(1) OUTXn on-off timing depends on previous GS data in the 218-bit data latch.
(2) The propagation delay time shows the period from the rising edge of the last SCKI, not the 224th SCKI to the internal latch signal
generation.
TYPICAL CHARACTERISTICS
At TA = +25°C and VCC = 24 V, unless otherwise noted.
50 61
IOLCMax = 40 mA
40 60
IOLCMax = 30 mA 59
30
58
IOLCMax = 20 mA
20 57
TA = -40°C
IOLCMax = 2 mA IOLCMax = 5 mA
IOLCMax = 10 mA 56
10 TA = +25°C
55 TA = +85°C
0 54
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3
Output Voltage (V) Output Voltage (V)
CONSTANT-CURRENT ERROR vs
CONSTANT-CURRENT ERROR vs OUTPUT CURRENT AMBIENT TEMPERATURE
(Channel-to-Channel in Color Group) (Channel-to-Channel in Color Group)
3 3
TA = +25°C IOLCMax = 60 mA
VCC = 12 V VCC = 12 V
2 2
BCx = 7Fh BCx = 7Fh
1 1
DIOLC (%)
DIOLC (%)
0 0
-1 -1
-2 -2
-3 -3
0 10 20 30 40 50 60 -40 -20 0 20 40 60 80 100
Output Current (mA) Ambient Temperature (°C)
Figure 15. Figure 16.
50
20
ICC (mA)
40
IOLCMax = 2 mA IOLCMax = 30 mA 15
30
10
20
IOLCMax = 10 mA
10 5
0 0
0 16 32 48 64 80 96 112 128 0 10 20 30 40 50 60
Brightness Control Data (dec) Output Current (mA)
Figure 17. Figure 18.
15 3.3
3.25
10
IOLCMax = 60 mA, VCC = 12 V TA = +25°C, IOLCMax = 60 mA,
3.2
5 BCx = 7Fh, GSx = FFFFh VCC = 12 V
EXTGCK = 1, DSPRPT = 1 3.15 BCx = 7Fh, GSx = FFFFh
SDTI = 10 MHz, SCKI = 20 MHz EXTGCK = 0, DSPRPT = 1
0 3.1
-40 -20 0 20 40 60 80 100 0 5 10 15 20 25
Ambient Temperature (°C) Linear Regulator Output Current, IREG (mA)
APPLICATION INFORMATION
Where:
VIREF = the internal reference voltage on the IREF pin (1.21 V, typically, when the the global brightness
control data are at maximum),
IOLCMax = 2 mA to 60 mA. (1)
IOLCMax is the maximum current for each output. Each output sinks the IOLCMax current when it is turned on and
global brightness control data (BC) are set to the maximum value of 7Fh (127d).
RIREF must be between 0.82 kΩ and 24.8 kΩ to hold IOLCMax between 60 mA (typical) and 2 mA (typical).
Otherwise, the output may be unstable. Output currents lower than 2 mA can be achieved by setting IOLCMax to 2
mA or higher and then using global brightness control to lower the output current. The constant-current sink
values for specific external resistor values are shown in Figure 11 and Table 1.
Where:
IOLCMax = the maximum channel current for each channel determined by RIREF
BC = the global brightness control value in the data latch for the specific color group
(BCX = 0d to 127d, X = R/G/B) (2)
Table 2 summarizes the BC data value versus the output current ratio and set current value.
Where:
tGSCLK = one period of the selected GS reference clock
(internal clock = 100ns typical, external clock = the period of SCKI)
GSXn = the programmed GS value for OUTXn (0d to 65535d) (3)
Table 3 summarizes the GS data values versus the output total on-time and duty cycle. When the IC is powered
up, BLANK (bit 213) is set to '1' to force all outputs off; however, the 224-bit shift register and the 218-bit data
latch are not set to default values. Therefore, the GS data must be written to the data latch when BLANK (bit
213) is set to '0'.
T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0001h) ON
¼
¼
T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0041h) ON
T = GS Clock ´ 1d T = GS Clock ´ 1d
¼
T = GS Clock ´ 1d
¼
T = GS Clock ´ 1d
T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0080h) ON
T = GS Clock ´ 1d T = GS Clock ´ 1d T = GS Clock ´ 1d
T = GS Clock ´ 2d T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0081h) ON
T = GS Clock ´ 1d T = GS Clock ´ 2d T = GS Clock ´ 1d
T = GS Clock ´ 2d T = GS Clock ´ 1d T = GS Clock ´ 1d
OUTXn OFF
(GS Data = 0082h) ON
¼
T=
¼
GS Clock ´ 511d
T = GS Clock ´ 511d in 2nd to 128th Periods
OUTXn OFF
(GS Data = FF80h) ON
T = GSCLK ´ 512d
T = GS Clock ´ 511d in 2nd to 128th Periods
OUTXn OFF
(GS Data = FF81h) ON
¼
T= T=
¼
GS Clock ´ 512d T = GS Clock ´ 512d in 2nd to 63rd and 65th to 127th Periods, GS Clock ´ 511d
T = GS Clock ´ 511d in 64th Period
OUTXn OFF
(GS Data = FFFEh) ON
T= T=
GS Clock ´ 512d GS Clock ´ 511d
T = GS Clock ´ 512d in 2nd to 127th Periods
OUTXn OFF
(GS Data = FFFFh) ON
MSB LSB
Write Write Write Write Write Write Write Write Write Write SDTI
SDTO Command ¼ Command Data Data Data Data ¼ Data Data Data Data
Bit 5 Bit 0 Bit 217 Bit 216 Bit 215 Bit 214 Bit 3 Bit 2 Bit 1 Bit 0 SCKI
223 218 217 216 215 214 3 2 1 0
218
6 218-Bit Data Latch
MSB LSB
Internal
6-Bit Write OUT EXT TMG DSP OUTR0 OUTR0 OUTR0 OUTR0 Latch Pulse
Command TMG GCK RST RPT
¼ Bit 3 Bit 2 Bit 1 Bit 0
Decoder
217 216 215 214 3 2 1 0
Figure 24. Common Shift Register and Control Data Latch Configuration
MSB LSB
217 216 215 214 213 212-206 205-199 198-192 191 176 31 16 15 0
Function Control Data (5 Bits) BC Data for OUTRn/Gn/Bn GS Data for OUTB3 GS Data for OUTG0 GS Data for OUTR0
(7 Bits ´ 3 = 21 Bits) (16 Bits) (16 Bits) (16 Bits)
5 21 192
To function control (FC) circuit. To global brightness control (BC) circuit. To grayscale timing control (GS) circuit.
SCKI
218-Bit
218-bit data are copied from shift register
Data Latch when the internal latch is generated.
(Internal)
DSPRPT = 1
(Auto Repeat On)
DSPRPT Bit DSPRPT = 0
in Data Latch (Auto Repeat Off)
(Internal)
1st
1st Display Period 2nd Display Period 3rd Display Period Display Period
1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
EXTCLK Bit
in Data Latch
(Internal)
1 = OUTXn on-off state is changed at the rising edge of the clock selected by the EXTCLK bit.
OUTTMG Bit
in Data Latch
(Internal)
SCKI
N-4 N-3 N-2 N-1 N 8x or greater internal 1 2 3 ¼
8x Period A clock period
Internal Latch Pulse Period A (1.34 ms, min).
(Internal)
1
BLANK Bit
in Data Latch 0
(Internal)
SCKI
OFF
OUTR0-R3
ON
tD3 OUTXn on-off state changes at the rising tD3
OFF edge of the clock selected by the EXTCLK bit.
OUTG0-G3
ON
tD4 tD4
OFF
OUTB0-B3
ON
tD5 tD5
Figure 29. Output On-Off Timing with Four-Channel Grouped Delay (OUTTMG = 1)
1
BLANK Bit
in Data Latch 0
(Internal)
OUTTMG Bit
in Data Latch
(Internal)
0 = OUTXn on-off state changes at the falling edge of the clock selected by the EXTCLK bit.
SCKI
OFF
OUTR0-R3
ON
tD3 OUTXn on-off state changes at the falling tD3
edge of the clock selected by the EXTCLK bit.
OFF
OUTG0-G3
ON
tD4 tD4
OFF
OUTB0-B3
ON
tD5 tD5
Figure 30. Output On-Off Timing with Four-Channel Grouped Delay (OUTTMG = 0)
THERMAL SHUTDOWN
The thermal shutdown (TSD) function turns off all IC constant-current outputs when the junction temperature (TJ)
exceeds the threshold (TTSD = +165°C, typ). When the junction temperature drops below (TTSD – THYS), the
output control starts at the first GS clock in the next display period.
NOISE REDUCTION
Large surge currents may flow through the IC and the board if all 12 outputs turn on simultaneously at the start of
each GS cycle. These large current surges could induce detrimental noise and EMI into other circuits. The
TLC5971 turns on the outputs for each color group independently with a 25 ns (typ) rise time. The output current
sinks are grouped into three groups. The first group that is turned on/off are OUTR0-3; the second group that is
turned on/off are OUTG0-3; and the third group is OUTB0-3. However, the state of each output is controlled by
the selected GS clock; see the Output Timing Select Function section.
Write Function BC for BC for BC for GS for GS for GS for GS for GS for GS for
16 Bits
Command Control BLUE GREEN RED OUTB3 OUTG3 OUTR3 OUTB0 OUTG0 OUTR0
´6
(6 bits, 25h) (5 bits) (7 bits) (7 bits) (7 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits) (16 Bits)
VLED
¼ ¼ ¼ ¼
3.3 V
Data Write and PWM Control with Internal Grayscale Clock Mode
When the EXTCLK bit is '0', the internal oscillator clock is used for PWM control of OUTXn (X = R/G/B and n = 0-
3) as the GS reference clock. This mode is ideal for illumination applications that change the display image at
low frequencies. The data and clock timing is shown in Figure 9 and Figure 33. A writing procedure for the
function setting and display control follows:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet (with MSB bit first) for the Nth TLC5971 using the SDTI and SCKI signals. The
first six bits of the 224-bit data packet are used as the write command. The write command must be 25h
Copyright © 2010–2012, Texas Instruments Incorporated Submit Documentation Feedback 27
Product Folder Links: TLC5971
TLC5971
(100101b); otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch.
The EXTCLK bit must be set to '0' for the internal oscillator mode. Also, the DSPRPT bit should be set to '1'
to repeat the PWM timing control and BLANK set to '0' to start the PWM control.
3. Write the 224-bit data packet for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is now 224 ×
N. After all device data are written, stop the SCKI at a high or low level for 8× the period between the last
SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices and the PWM control is started or updated at the same time.
VLED Power The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
MSB LSB MSB LSB MSB LSB
Shift Data From 224-Bit Packet 224-Bit Packet for for 224-Bit Packet 224-Bit Packet Next
Controller (SDTI) for Nth TLC5971 for N-1st TLC5971 N-2’th 3’rd for 2nd TLC5971 for 1st TLC5971 Data
MSB LSB MSB LSB MSB
Latch Pulse
(Internal)
The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.
Figure 33. Data Packet and Display Start/Update Timing 1 (Internal Oscillator Mode)
Data Write and PWM Control with External Grayscale Clock Mode
When the EXTCLK bit is '1', the data shift clock (SCKI) is used for PWM control of OUTXn (X = R/G/B and n = 0-
3) as the GS reference clock. This mode is ideal for video image applications that change the display image with
high frequencies or for certain display applications that must synchronize all TLC5971s. The data and clock
timing are shown in Figure 9 and Figure 34. A writing procedure for the display data and display timing control
follows:
1. Power- up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet MSB-first for the Nth TLC5971 using the SDTI and SCKI signals. The first six
bits of the 224-bit data packet are used as the write command. The write command must be 25h (100101b);
otherwise, the 218-bit data in the 224-bit shift register are not copied to the 218-bit data latch. The EXTCLK
bit must be set to '1' for the external oscillator mode. Also, the DSPRPT bit should be set to '0' so that the
PWM control is not repeated, the TMGRST bit should be set to '1' to reset the PWM control timing at the
internal latch pulse generation, and BLANK must be set to '0' to start the PWM control.
3. Write the 224-bit data for the (N – 1) TLC5971 without delay after step 2.
4. Repeat the data write sequence until all TLC5971s have data. The total shift clock count (SCKI) is 224 × N.
After all device data are written, stop the SCKI at a high or low level for 8× the period between the last SCKI
rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift resister are
copied to the 218-bit data latch in all devices.
5. To start the PWM control, send one pulse of the SCKI clock with SDTI low after 1.34µs or more from step 4.
The OUTXn are turned on when the output GS data are not 0000h.
6. Send the remaining 65535 SCKI clocks with SDTI low. Then the PWM control for OUTXn is synchronized
with the SCKI clock and one display period is finished with a total of 65536 SCKI clock periods.
7. Repeat step 2 to step 6 for the next display period.
VLED Power
The next shift clock should start after 1.34 ms
or more from the internal latch pulse generation timing.
MSB LSB MSB LSB MSB
Shift Data From 224-Bit Packet for for 224-Bit Packet 224-Bit Packet
Controller (SDTI) for Nth TLC5971 N-1st 2nd for 1st TLC5971 Low for Nth TLC5971
MSB LSB
Latch Pulse
(Internal)
The time that generates the internal latch pulse is 8x the period between the last
SCLK rising edge and the second to last SCLK rising edge. The time changes
depending on the period of the shift clock within the range of 2.74 ms to 666 ns.
Figure 34. Data Packet and Display Start/Update Timing 2 (External Clock Mode)
There is another control procedure that is recommended for a long chain of cascaded devices. The data and
clock timings are shown in Figure 9 and Figure 35. When 256 TLC5971 units are cascaded, use the following
procedure:
1. Power up VCC (VLED); all OUTXn are off because BLANK is set to '1'.
2. Write the 224-bit data packet MSB-first for the 256th TLC5971 using the SDTI and SCKI signals. The
EXTCLK bit must be set to '1' for the external oscillator mode. Also, the DSPRPT bit should be set to '0' so
that the PWM control does not repeat, the TMGRST bit should be set to '1' to reset the PWM control timing
with the internal latch pulse, and BLANK must be set to '0' to start the PWM control.
3. Repeat the data write sequence for all TLC5971s. The total shift clock count (SCKI) is 57344 (224 × 256).
After all device data are written, stop the SCKI signal at a high or low level for eight or more periods between
the last SCKI rising edge and the second to last SCKI rising edge. Then the 218 LSBs in the 224-bit shift
resister are copied to the 218-bit data latch in all devices.
4. To control the PWM, send 8192 SCKI clock periods with SDTI low after 1.34µs or more from step 3 (or step
7). These 8192 clock periods are used for the OUTXn PWM control.
5. Write the new 224-bit data packets to the 256th to first TLC5971s for the next display with 256 × 224 SCKI
clock for a total of 57344 clocks. The PWM control for OUTXn remains synchronized with the SCKI clock and
one display period is finished with a total of 65536 SCKI clocks. The SCKI clock signal is therefore used for
PWM control and, at the same time, to write data into the shift registers of all cascaded parts.
6. Stop the SCKI signal at a high or low level for eight or more periods between the last SCKI rising edge and
the second to last SCKI rising edge. Then the 218-bit LSBs in the 224-bit shift resister are copied to the 218-
bit data latch in all devices.
7. Repeat step 4 to step 6 for the next display periods.
VLED Power The next shift clock should start after 1.34 ms or more from the internal latch pulse generation timing.
Timing clock for 1st display and
MSB LSB MSB LSB Timing clock for 1st display. 2nd display data write.
Shift Data From 224-Bit Packet for for for 224-Bit Packet 256 ´ 224-Bit Packet for
Low Low
Controller (SDTI) 256th TLC5971 255th 2nd for 1st TLC5971 256th TLC5971
MSB LSB
Latch Pulse
(Internal)
The time is 8 periods between the last SCLK rising edge and the second to last SCLK rising edge.
The wait time changes between 2.74 ms and 666 ns, depending on the period of the shift clock.
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from the page numbers in the current version.
• Changed typical application circuit (internal linear regulator), added footnote 1 .................................................................. 1
• Changed typical application circuit (direct power), added footnote 1 ................................................................................... 2
• Added typical application circuit example (direct power supplying VCC = 3 V to 5.5 V, VLED = 15 V), added footnote 1 ..... 2
www.ti.com 11-Apr-2013
PACKAGING INFORMATION
Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing Qty (2) (3) (4)
TLC5971PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971
& no Sb/Br)
TLC5971PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC5971
& no Sb/Br)
TLC5971RGER ACTIVE VQFN RGE 24 3000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
& no Sb/Br) 5971
TLC5971RGET ACTIVE VQFN RGE 24 250 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TLC
& no Sb/Br) 5971
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com 11-Apr-2013
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com 26-Jan-2013
Pack Materials-Page 2
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