Rail-to-Rail, Fast, Low Power 2.5 V to 5.

5 V,
Single-Supply TTL/CMOS Comparator
Data Sheet ADCMP608
FEATURES FUNCTIONAL BLOCK DIAGRAM
Fully specified rail to rail at VCC = 2.5 V to 5.5 V
NONINVERTING
Input common-mode voltage from −0.2 V to VCC + 0.2 V INPUT
+

Low glitch CMOS-/TTL-compatible output stage ADCMP608 Q OUTPUT

40 ns propagation delay
INVERTING –
Low power: 1 mW at 2.5 V INPUT

Shutdown pin
Power supply rejection > 60 dB

06769-001
SDN
−40°C to +125°C operation
Figure 1.
APPLICATIONS
High speed instrumentation
Clock and data signal restoration
Logic level shifting or translation
High speed line receivers
Threshold detection
Peak and zero-crossing detectors
High speed trigger circuitry
Pulse-width modulators
Current-/voltage-controlled oscillators

GENERAL DESCRIPTION
The ADCMP608 is a fast comparator fabricated on XFCB2, an The TTL-/CMOS-compatible output stage is designed to drive
Analog Devices, Inc. proprietary process. This comparator is up to 15 pF with full rated timing specifications and to degrade
exceptionally versatile and easy to use. Features include an input in a graceful and linear fashion as additional capacitance is
range from VEE − 0.2 V to VCC + 0.2 V, low noise, TTL-/CMOS- added. The input stage of the comparator offers robust protection
compatible output drivers, and shutdown inputs. The device against large input overdrive, and the outputs do not phase
offers 40 ns propagation delays driving a 15 pF load with 10 mV reverse when the valid input signal range is exceeded.
overdrive on 500 µA typical supply current. The ADCMP608 is available in a tiny 6-lead SC70 package with
A flexible power supply scheme allows the device to operate a single-ended output and a shutdown pin.
with a single +2.5 V positive supply and a −0.2 V to + 2.7 V
input signal range up to a +5.5 V positive supply with a −0.2 V
to +5.7 V input signal range.

Rev. B Document Feedback

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Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
ADCMP608 Data Sheet

TABLE OF CONTENTS
Features .............................................................................................. 1 Applications Information .................................................................7
Applications ....................................................................................... 1 Power/Ground Layout and Bypassing ........................................7
Functional Block Diagram .............................................................. 1 TTL-/CMOS-Compatible Output Stage ....................................7
General Description ......................................................................... 1 Optimizing Performance..............................................................7
Revision History ............................................................................... 2 Comparator Propagation Delay Dispersion ..................................7
Specifications..................................................................................... 3 Crossover Bias Point .....................................................................8
Electrical Characteristics ............................................................. 3 Minimum Input Slew Rate Requirement ...................................8
Absolute Maximum Ratings............................................................ 4 Typical Application Circuits ............................................................9
Thermal Resistance ...................................................................... 4 Outline Dimensions ....................................................................... 10
ESD Caution .................................................................................. 4 Ordering Guide .......................................................................... 10
Pin Configuration and Function Descriptions ............................. 5
Typical Performance Characteristics ............................................. 6

REVISION HISTORY
11/14—Rev. A to Rev. B
Changes to Figure 7 and Figure 8 ................................................... 6

6/14—Rev. 0 to Rev. A
Changes to Temperature Parameter, Table 2................................. 4
Changes to Ordering Guide .......................................................... 10

4/07—Revision 0: Initial Version

Rev. B | Page 2 of 10
Data Sheet ADCMP608

SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
VCC = 2.5 V, TA = −40°C to +125°C. Typical values are TA = 25°C, unless otherwise noted.

Table 1.
Parameter Symbol Conditions Min Typ Max Unit
DC INPUT CHARACTERISTICS
Voltage Range VP, VN VCC = 2.5 V to 5.5 V −0.2 VCC V
Common-Mode Range VCC = 2.5 V to 5.5 V −0.2 VCC V
Differential Voltage VCC = 2.5 V to 5.5 V VCC V
Offset Voltage VOS −5.0 ±3 +5.0 mV
Bias Current IP, IN −0.4 +0.4 µA
Offset Current −1.0 +1.0 µA
Capacitance CP, CN 1 pF
Resistance, Differential Mode −0.5 V to VCC + 0.5 V 200 7000 kΩ
Resistance, Common Mode −0.5 V to VCC + 0.5 V 100 4000 kΩ
Active Gain AV 80 dB
Common-Mode Rejection CMRR VCC = 2.5 V, VCM = −0.2 V to 2.7 V 45 dB
VCC = 5.5 V 45 dB
SHUTDOWN PIN CHARACTERISTICS1
VIH Comparator is operating 2.0 VCC V
VIL Shutdown guaranteed −0.2 +0.4 +0.4 V
IIH VIH = VCC −6 +6 µA
Sleep Time tSD lCC < 100 µA 300 ns
Wake-Up Time tH VPP = 10 mV, output valid 150 ns
DC OUTPUT CHARACTERISTICS VCC = 2.5 V to 5.5 V
Output Voltage High Level VOH IOH = 0.8 mA, VCC = 2.5 V VCC − 0.4 V
Output Voltage Low Level VOL IOL = 0.8 mA, VCC = 2.5 V 0.4 V
AC PERFORMANCE2 VCC = 2.5 V to 5.5 V
Rise Time/Fall Time tR, tF 10% to 90%, VCC = 2.5 V 25 to 50 ns
10% to 90%, VCC = 5.5 V 45 to 75 ns
Propagation Delay tPD VOD = 10 mV, VCC = 2.5 V 30 to 50 ns
VOD = 50 mV, VCC = 5.5 V 35 to 60 ns
Propagation Delay Skew—Rising to Falling Transition VCC = 2.5 V 4.5 ns
VCC = 5.5 V 8 ns
Overdrive Dispersion 10 mV < VOD < 125 mV 12 ns
Common-Mode Dispersion −0.2 V < VCM < VCC + 0.2 V 1.5 ns
POWER SUPPLY
Supply Voltage Range VCC 2.5 5.5 V
Positive Supply Current IVCC VCC = 2.5 V 550 800 µA
VCC = 5.5 V 800 1300 µA
Power Dissipation PD VCC = 2.5 V 1.375 2.0 mW
VCC = 5.5 V 4.95 7.15 mW
Power Supply Rejection Ratio PSRR VCC = 2.5 V to 5.5 V −50 dB
Shutdown Current ISD VCC = 2.5 V to 5.5 V 250 350 µA
1
The output will be in a high impedance mode when the device is in shutdown mode. Note that this feature should be used with care since the enable/disable time is
much longer than with a true tristate output.
2
VIN = 100 mV square input at 1 MHz, VCM = 0 V, CL = 15 pF, VCCI = 2.5 V, unless otherwise noted.

Rev. B | Page 3 of 10
ADCMP608 Data Sheet

ABSOLUTE MAXIMUM RATINGS

Table 2. THERMAL RESISTANCE
Parameter Rating θJA is specified for the worst-case conditions, that is, a device
Supply Voltages soldered in a circuit board for surface-mount packages.
Supply Voltage (VCC to GND) −0.5 V to +6.0 V
Table 3. Thermal Resistance
Supply Differential −6.0 V to +6.0 V
Package Type θJA1 Unit
Input Voltages
ADCMP608 6-Lead SC70 426 °C/W
Input Voltage −0.5 V to VCC+ 0.5 V 1
Measurement in still air.
Differential Input Voltage ±(VCC + 0.5 V)
Maximum Input/Output Current ±50 mA
Shutdown Control Pin ESD CAUTION
Applied Voltage (SDN to GND) −0.5 V to VCC + 0.5 V
Maximum Input/Output Current ±50 mA
Output Current ±50 mA
Temperature
Operating Temperature, Ambient −40°C to +125°C
Operating Temperature, Junction 150°C
Storage Temperature Range −65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.

Rev. B | Page 4 of 10
Data Sheet ADCMP608

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Q 1 6 VCC
ADCMP608
VEE 2 TOP VIEW 5 SDN
(Not to Scale)

06769-002
VP 3 4 VN

Figure 2. Pin Configuration

Table 4. ADCMP608 Pin Function Descriptions

Pin No. Mnemonic Description
1 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input, VP, is greater than the
analog voltage at the inverting input, VN.
2 VEE Negative Supply Voltage.
3 VP Noninverting Analog Input.
4 VN Inverting Analog Input.
5 SDN Shutdown. Drive this pin low to shut down the device.
6 VCC VCC Supply.

Rev. B | Page 5 of 10
ADCMP608 Data Sheet

TYPICAL PERFORMANCE CHARACTERISTICS

VCC =2.5 V, TA = 25°C, unless otherwise noted.
5 38.0

4 37.8

3 37.6 PROPAGATION DELAY FALL

PROPAGATION DELAY (ns)

2 37.4

1 37.2
IB (µA)

0 37.0
PROPAGATION DELAY RISE
–1 36.8

–2 36.6
+125°C
–3 36.4
+25°C

06769-006
06769-003
–4 36.2
–40°C
–5 36.0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 0.5 1.0 1.5 2.0 2.5 3.0
VCM AT VCC (2.5V) VCM AT VCC (2.5V)

Figure 3. Input Bias Current vs. Input Common-Mode Voltage Figure 6. Propagation Delay vs. Input Common-Mode Voltage

60

55

50 Q

45
TPD (ns)

VCC = 5.5V
40 RISE DELAY

35 VCC = 5.5V
FALL DELAY
30 VCC = 2.5V
FALL DELAY
25
06769-004

VCC = 2.5V

06769-007
RISE DELAY
0.5V/DIV 100ns/DIV
20
0 50 100 150
OD (mV)

Figure 4. Propagation Delay vs. Input Overdrive at VCC = 2.5 V and 5.5 V Figure 7. 1 MHz Output Voltage Waveform VCC = 2.5 V

1.5

SOURCE

1.0 Q
SINK
LOAD CURRENT (mA)

0.5

–0.5
06769-008
06769-005

1V/DIV 100ns/DIV
–1.0
–1.0 –0.5 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
VOUT (V)

Figure 5. Load Current (mA) vs. VOH/VOL Figure 8. 1 MHz Output Voltage Waveform VCC = 5.5 V

Rev. B | Page 6 of 10
Data Sheet ADCMP608

APPLICATIONS INFORMATION
POWER/GROUND LAYOUT AND BYPASSING VLOGIC

The ADCMP608 comparator is a high speed device. Despite the

low noise output stage, it is essential to use proper high speed A1 Q1

design techniques to achieve the specified performance. Because

comparators are uncompensated amplifiers, feedback in any phase
relationship is likely to cause oscillations or undesired hysteresis. Of +IN OUTPUT
critical importance is the use of low impedance supply planes, AV
–IN
particularly the output supply plane (VCC) and the ground plane
(GND). Individual supply planes are recommended as part of a
multilayer board. Providing the lowest inductance return path for
A2 Q2
switching currents ensures the best possible performance in the
target application.

06769-009
GAIN STAGE OUTPUT STAGE
It is also important to adequately bypass the input and output
Figure 9. Simplified Schematic Diagram of
supplies. A 0.1 μF bypass capacitor should be placed as close as TTL-/CMOS-Compatible Output Stage
possible to the VCC supply pin. The capacitor should be connected
to the GND plane with redundant vias placed to provide a OPTIMIZING PERFORMANCE
physically short return path for output currents flowing back As with any high speed comparator, proper design and layout
from ground to the VCC pin. High frequency bypass capacitors techniques are essential for obtaining the specified performance.
should be carefully selected for minimum inductance and ESR. Stray capacitance, inductance, common power and ground
Parasitic layout inductance should also be strictly controlled to impedances, or other layout issues can severely limit performance
maximize the effectiveness of the bypass at high frequencies. and can often cause oscillation. The source impedance should be
TTL-/CMOS-COMPATIBLE OUTPUT STAGE minimized as much as is practicable. High source impedance, in
combination with the parasitic input capacitance of the comparator,
Specified propagation delay performance can be achieved only
causes an undesirable degradation in bandwidth at the input, thus
by keeping the capacitive load at or below the specified minimums.
degrading the overall response. Higher impedances encourage
The output of the ADCMP608 is designed to directly drive one
undesired coupling.
Schottky TTL, or three low power Schottky TTL loads, or the
equivalent. For large fan outs, buses, or transmission lines, use COMPARATOR PROPAGATION DELAY DISPERSION
an appropriate buffer to maintain the excellent speed and The ADCMP608 comparator is designed to reduce propagation
stability of the comparator. delay dispersion over a wide input overdrive range of 10 mV to
With the rated 15 pF load capacitance applied, more than half VCC – 1 V. Propagation delay dispersion is the variation in
of the total device propagation delay is output stage slew time. propagation delay that results from a change in the degree of
Because of this, the total propagation delay decreases as VCC overdrive or slew rate (how far or how fast the input signal
decreases, and instability in the power supply may appear as exceeds the switching threshold).
excess delay dispersion. Propagation delay dispersion is a specification that becomes
Delay is measured to the 50% point for whatever supply is in important in high speed, time-critical applications, such as data
use; thus, the fastest times are observed with the VCC supply at communication, automatic test and measurement, and instru-
2.5 V, and larger values are observed when driving loads that mentation. It is also important in event-driven applications, such
switch at other levels. as pulse spectroscopy, nuclear instrumentation, and medical
imaging. Dispersion is defined as the variation in propagation
Overdrive and input slew rate dispersions are not significantly
delay as the input overdrive conditions are changed (see Figure 10
affected by output loading and VCC variations.
and Figure 11).
The TTL-/CMOS-compatible output stage is shown in the
ADCMP608 dispersion is typically < 12 ns as the overdrive
simplified schematic diagram (see Figure 9). Because of its
varies from 10 mV to 125 mV. This specification applies to both
inherent symmetry and generally good behavior, this output
positive and negative signals because the device has very closely
stage is readily adaptable for driving various filters and other
matched delays for both positive-going and negative-going
unusual loads.
inputs, and very low output skews. Remember to add the actual
device offset to the overdrive for repeatable dispersion
measurements.

Rev. B | Page 7 of 10
ADCMP608 Data Sheet
500mV OVERDRIVE
CROSSOVER BIAS POINT
Rail-to-rail inputs of this type, in both op amps and comparators,
INPUT VOLTAGE
have a dual front-end design. Certain devices are active near the
10mV OVERDRIVE VCC rail and others are active near the VEE rail. At some
VN ± VOS predetermined point in the common-mode range, a crossover
occurs. At this point, normally VCC/2, the direction of the bias
current reverses and there are changes in measured offset
DISPERSION voltages and currents.

06769-010
Q OUTPUT The ADCMP608 slightly elaborates on this scheme. Crossover
Figure 10. Propagation Delay—Overdrive Dispersion points can be found at approximately 0.8 V and 1.6 V.
MINIMUM INPUT SLEW RATE REQUIREMENT
INPUT VOLTAGE
1V/ns
With the rated load capacitance and normal good PC board
design practice, as discussed in the Optimizing Performance
VN ± VOS section, these comparators should be stable at any input slew
10V/ns
rate with no hysteresis. Broadband noise from the input stage is
observed in place of the violent chattering seen with most other
high speed comparators. With additional capacitive loading or
poor bypassing, oscillation may be encountered. These oscillations
DISPERSION
06769-011

are due to the high gain bandwidth of the comparator in

Q OUTPUT
combination with feedback through parasitics in the package
Figure 11. Propagation Delay—Slew Rate Dispersion and PC board. In many applications, chattering is not harmful.

Rev. B | Page 8 of 10
Data Sheet ADCMP608

TYPICAL APPLICATION CIRCUITS

2.5V TO 5V CMOS
VCC
0.1µF 2.5V TO 5V

INPUT
2kΩ
2kΩ ADCMP608 OUTPUT LVDS 100Ω ADCMP608 OUTPUT

06769-013
06769-012
0.1µF

Figure 12. Self-Biased, 50% Slicer Figure 13. LVDS-to-CMOS Receiver

Rev. B | Page 9 of 10
ADCMP608 Data Sheet

OUTLINE DIMENSIONS
2.20
2.00
1.80

1.35 6 5 4 2.40
1.25 2.10
1.15 1 2 3 1.80

0.65 BSC
1.30 BSC

1.00 0.40
1.10
0.90 0.10
0.80
0.70

0.46
SEATING 0.22
0.10 MAX 0.30 0.36
PLANE 0.08
COPLANARITY 0.15 0.26
0.10

072809-A
COMPLIANT TO JEDEC STANDARDS MO-203-AB

Figure 14. 6-Lead Thin Shrink Small Outline Transistor Package [SC70]
(KS-6)
Dimensions shown in millimeters

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Option Branding
ADCMP608BKSZ-R2 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U
ADCMP608BKSZ-RL −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U
ADCMP608BKSZ-REEL7 −40°C to +125°C 6-Lead Thin Shrink Small Outline Transistor Package [SC70] KS-6 G0U
EVAL-ADCMP608BKSZ Evaluation Board
1
Z = RoHS Compliant Part.

©2007–2014 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D06769-0-11/14(B)

Rev. B | Page 10 of 10