A

Major Project Report On

Design and implementation of parallel CRC algorithm for fibre channel on FPGA
Dissertation Submitted in the Partial Fulfillment of Academic Requirements for the

Award of the Degree of master of Technology In

Electronics and Communication Engineering(vlsi system design)

By

R.raju (19B61D5706)

Under the guidance of MR.P.Surendranath

Assistant Professor

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERIN

NALLA MALLA REDDY ENGINEERING COLLEGE

(NBA Accredited, Approved by AICTE, Affiliated to JNTUH) Divya Nagar,

Kachivani Singaram post, Narapally, Ghatkesar(M), Medchal(Dist)

Pincode-500088

2021
 Nalla Malla Reddy Engineering College
(NAAC ‘A’ & NBA Accredited, Approved by AICTE, Affiliated
to JNTU H) Divya Nagar, Ghatkesar(M), Medchal-Malkajgiri District-
500088

CERTIFICATE

This is to certify that the major project report titled “Design and implementation of parallel CRC algorithm
for fibre channel on FPGA” is being submitted by R.raju (19B61D5706) in partial fulfillment of the
academic requirements for the degree of Bachelor of technology in Electronics and Communication
Engineering,Nalla Malla Reddy Engineering College, JNTUH during the academic year 2020-21 is a record
of BONAFIDE work carried out under any guidance and supervision.

MR.P.surendranath Mrs. T.RAJANI

(Internal guide) (Head of the Department)

EXTERNAL EXAMINER
 CANDIDATE’S DECLARATION

We hereby declare that the project work entitled “Design and implementation of parallel CRC

algorithm for fibre channel on FPGA” is the bonafide work done and submitted by us under the

guidance of MR.P.Surendranath in partial fulfillment of the requirements for the award of the degree of Master

of Technology in Electronics and Communication Engineering to the department of Electronics &

Communication Engineering, Nalla Malla Reddy Engineering College, Divya Nagar, R.R Dist.Further we

declare that the report has not been Submitted by us to any other institute or university for award of any other

degree.

Place:Hyderabad

Date: R.raju[19B61D5706]
 ACKNOWLEDGEMENT

The completion of the major project gives us an opportunity to convey

our gratitude to all those who helped us.

We express our sincere thanks to Principal Dr. M. N. V. Ramesh

Nalla Malla Reddy Engineering College, Divyanagar, for providing all
necessary facilities in completing our project.

We express our sincere gratitude to Mrs. T. Rajani, Head of the

Department, Electronics and Communication Engineering, for providing
necessary facilities in order to complete our project successfully.

We are also thankful to our project coordinator MR.P.surendranath,

Associate Professor, Nalla Malla Reddy Engineering College for his valuable
guidance, encouragement and co-operation throughout the project. It was his
able guidance and support, which resulted in the successful completion.

We also acknowledge Dr.B.Khaleelu Rehman, Associate Professor,

Electronics and Communication Engineering, our guide for his help at each
and every instant and efforts taken by him in helping us complete the project
successfully within the specified time and his unflinching help and
encouragement was a constant source of inspiration to us.

Finally, we would like to thank our parents and friends for

their continuous encouragement and valuable support.
 LIST OF CONTENTS

Certificates

Candidate Declaration

Acknowledgement

.Abstract……………………………………………………..8

1.INTRODUCTION………………………………………..9

2.PRINCIPLE OF CRC ALGORITHM…………………..15

3.LITERATURE REVIEW………………………………..24

4.VERILOG CODE………………………………………..28

5.ABOUT FIBRE CHANNEL…………………………….30

6.ABOUT FPGA……………………………………………37

7.FLOWCHART…………………………………………….38

8.CRC-32 APPROACHES………………………………….41

9.RESULTS…….……………………………………………43

10.CONCLUSION………………………………………… 46

11.REFERENCES……………………………………………48

5
 LIST OF FIGURES

1.FC frame format………………………………………..10

2.Pipelined architecture of parallel crc algorithm…………16

3.General LFSR architecture………………………………16

4.LFSR architecture for CRC-5…………………………….17

5.Mapping CRC scope into fcsinput………………………..43

6.Mapping fcs Coefficients into crc field……………………43

7.Result of simulation………………………………………..45

6
 LIST OF TABLES

1.Comparision of utilization…………………………………….19

2.Comparision of utilization……………………………………..45

7
 ABSTRACT

Fiber channel (FC) Used in modern communication technology. it’s having features like
high-speed and low-latency between the transmission data system. It mostly used in various
applications in data science ,aerospace and those systems having most electronic equipment ex
ample radar, satellite data communications.. Excellent in error detection and easy to be
implemented in hardware, cyclic redundancy check (CRC) is an important error detection
method widely used in network data transmission. This study implements a design and
development of parallel CRC algorithm for the hardware implementation on FPGA to meet
the features for FC. The algorithm can perform128-bit parallel data in a block by divided into
four 32-bit data and calculate CRC bits, respectively, based on the linear feedback shift
register, modify easily the calculation process and reducing resource utilization. CRC is
various degree of versatilities in CRC-8, CRC-12, CRC-16, CRC-CCITT and CRC-32. For
the FC features I perform CRC-32 to improve the accuracy of data transmission and I continue
my introduction on CRC-32

8
 1.Introduction
Now Present and Future of technology .rapid tremendous changes in computer science .for
the rapid improvements of Computer Science. its generators of large volume of data like Tera
Bytes of data ,Giga bytes of data, meta data (data about data).for that data transmission system
needs higher transfer rates of data transmission .modern communication use the Fiber channel
or Fiber channel it’s called short as FC .Major advantage of FC it transmit the data over long
data transmission .For long data transmission system requires high data transfer rates .that meet
the Specifications of FC
 It technology developed by the American National Standards Institute (ANSI), FC is
used in longer data transmission .its high-Speed data transmission between
transmission Ends. Less Delay between transmission heads. High- data rate or
Bandwidth, low-latency, long-distance transmission, its available various
topologys.in that Flexible -topology support for multiple upper-layer protocols
features of FC make it advantage for high-speed communication.
 FC have various protocols and various environments in space domain in that avionics
environment is important .FC-Committee introduces FC-AE network. After several
years of research and development, FC has new Generation of fighter in avionics
environment. upcoming aerospace fighter aircrafts applied in various machines such
as F-35 and B-1B ,It is applied in various defence fighter aircrafts
 Apart from avionic field it is used in the airborne field, large ship related
machines .in ship related fighters. those fighter have the radar communication .for
radar mostly used for long Distance communication. FC Used in high speed and long
distance communication that advantage it helps in above applications.
 FC mainly fiber communication in that transmission system transmit the light instead
of electric signals. it main advantage to avoid of electromagnetic interference. but
light transmission other interfaces included in the channel .that interfaces mainly
internal reflection or internal refraction and interferences act like noise in the FC
communication it differs sender and receiver data
 Most of the Situations these interfaces and internal refractions will block the
communication and results error bits .Receiver data it is not correct at output by the

9
 above situations.in this CRC is come into the Picture. CRC is powerful error
detection and verification method .it easily implemented in hardware.by this
advantage I go to CRC algorithm
 The CRC algorithm was introduced by Peterson and Brown in 1961.the CRC
mathematics is used in widely subjects of Acadamics . This concept is put forward in
the future in many application storage and mainframes domain. Many applications
used pipelined CRC algorithm based on the lookup tables
 In All the CRC algorithms pipelined CRC algorithm is the best kind of
generalization it is don’t have Negative degree terms in application usage.
 Bajarangbali and Anand was designed concept of FC format. it’s contains two formats those
are Frame content and FC –Frame format. Frame content contains extended _header ,frame
header ,data, CRC in addition to Frame format add the start and end address combination is
called as FC-Frame Format.

Fig. 1  FC frame format

 High-speed CRC algorithm it is many ways mostly parallel CRC algorithm used
in Ethernet to reducing the lookup table consumption to achieve the speed of
40gbps.this speed meet the FC specifications.
 Although the Parallel CRC algorithm has a certain degree of versatility, it is in
CRC-8, CRC-12, CRC-16, CRC-CCITT and CRC-32. Essential to figure out the
design and implementation of FC due to meet the specification of FC protocols
simplified.
 In the radar technology also CRC plays a crucial role. the increasing the number
of targets detection in radar systems and feasible movement of targets and
flexible of targets data volume is increased rapidly .the higher volume of data
generation CRC is used in detection and long distance transmission obtain the
Speed by reducing the look up tables

10
  In FPGA resources are massive data limited. parallel CRC algorithm reduces the
resources .by the results most of data volume transmits.it is higher-speed to
design to meet features of FC protocols. Here the simply Introduces resource-
intensive FPGA to meet the specifications on FC
 a type of design and implementation parallel CRC algorithm for FC by Verilog
language in coarse and fine dimension.it resource intensive FPGA to meet the
specification of FC.by reducing the lookup table consumption.
 In my document tells the principle of CRC and CRC method to generate CRC
bits.and FC Specification calculation to CRC bits .i briefly discuss the parallel
CRC method to generate CRC bits to implement the resource-intense FPGA.how
it is used in the FC communication
A cyclic redundancy check (CRC) is one of the most commonly used error detecting or
powerful verification codes in communications like radar, ship airfacts,aerospace,satellite,fighter
aircrafts and storage devices like mainframes and Before a message is transferred, a transmitter
calculates the CRC using the agreed upon polynomial called a generator, and attaches the
resulting residue(remainder) to the message. When the message is received, a receiver calculates
the CRC using the same polynomial and verifies the message. If the two CRC values are
different ,It means an error has occurred during the data transfer.

Cyclic reduancy check(CRC)

Sender Receiver
1.Data
2.CRC generator
3.CRC bits
4.Division….XOR
Crc generator…..n bits(4)
Crc bits……….(n-1)bits(3)

Sender Receiver

11
CRC bits = Data+(n-1)0’s
(Remainder) CRC generator
Data+000
CRC generator
 Data+CRC……………………………………. Data+CRC
CRC generator
Gives 000 as remainder Other than
000 at receiver Know some data bits are corrupted but don’t know which data bits are corrupted
This is for error detection not for Correction
Example :

SENDER RECEIVER
Data………….101101 Data=101101010
CRC Generator……..1101 CRC generator =1101
CRC Bits…………..(4-1)=3 XOR 1101 and Data(101101010) gives
000 as remainder this is for error detection
CRC Bits=101101000/1101(CRC Generator)
101101000
1101
01100
1101
0001100
1101
00010
CRC =010
SENDER WILL SEND DATA
Data + CRC
101101010……………………………………………………………….
 

A CRC is easily implemented in hardware and in software. it is Software based parallelized CRC
algorithm reduce the resources on FPGA take an account of lookup tables. Normal CRC lookup

12
table Calculation differs from ARM Cortex-A 15 CRC calculation it takes 2.5 times faster than
Conventional CRC calculation
The rapid development in avionics environment FC Committee introduces FC-AE environment
based on transmission speed and bandwidth . For high transmission rate required for long data
transmission .it achievable by FC-AE Bandwidth.

In the development of Fiber Aerospace channel Devices and building FC-AE System in my
reaserch I heared developed a portable FC-AE fault Simulation instrument.. by the device can
simulate the failure in the bus channel path between two FC-AE instruments at three rates.
which can be used to detect the fault tolerance and error correction program of the system. My
document shows the simulation related topics (project) and development process of the fault
simulation instrument .firstly my discussion introduces the design process of logic firmware
based on FPGA in widely , especially the logic design or process of frame/word trigger and fault
simulation under ternary sets of trigger conditions. Finally, in order to detect whether the
function of the instrument is normal or abnormal , in my reaserch heared to built a test platform
with various communication rates, and conducted fault simulation test cases
The test Cases show that the FC-AE fault simulation instrument can achievable of the proposed
technical performance or technical Results, and can rebuilt the fault in the process of system
maintenance, which shows the great credibility to test the stability and reliability of an FC-AE
environment
Fusion image technology domant over domain reaserch for last years. the Concepts of fusion
have widely used in realtime and designed in the use of military and remote Sensing
applications ,military fighter aircratfs, remote sensing systems such as barcode and tag,image
sensing apps .the fusion image is very efficient in creation or design of digital image. Single
image obtained from Composition of two or more information which results multi fusion image
which generates more data rate ,data width is also increased in that Sconorios. FPGA is the best
hardware implementation.it used widely most of the technologies for high data rate.FPGA works
with modern versions for different critical specifications same huge number of elements logic in
order to perform composed algorithm evaluated.In my document , filters are designed and
Evaluated in FPGA utilized for disease pointed verification from images Computed
tomography/Magnetic resonance imaging scanned where the samples are taken for human's brain

13
with different medical images and the performing of fusion employed by using method of
Stationary Wavelet Transform and Principal Component Analysis (SWT-PCA). Accuracy image
outcome enhances when Evaluated .this process and that was done by sampling down terminates
where effects blurring and doesnot influence the airtifacts. SWT-PCA algorithm tells the
parameters quality measurements like NCC,MSE, Peak signal to noise ratio(PSNR), coefficents
and Eigen values.
The benfits of significant of this system that provide practical, rapidly to market and
portability beside the parametric changes continuing in the Discrete wavelet transform(DWT).
The system designed and simulation has been done by using Matrix laboratory (MATLAB)
simulink and blocks generator system, Xilinx synthesized with synthesis tool (XST) and
Evaluated in Xilinx Spartan 6-SP605 device

14
 2. PRINCIPLE OF CRC ALGORITHM

CRC is Contains Several bits of binary digits its adds data is called as sender data or
transmission Data to be check and used to verify or correct the integrity of Data. the FC frame
format Contains start address of frame content(SOF),Extended header, frame header,data
field, CRC,end address of frame content(EOF). the CRC field appended behind the Data field
The frame content checks or verifys the integrity of the frame content Composition of
Frame_Headers, if any the Frame_Header, and the Data_field.

For ease of Summarization, the original data to be verified in the frame content are treated
as the coefficients of a polynomial U(x) and CRC can be generalized as the following steps:

1.
Adding m zeros after the original data to get xmU(x), here g(x) is CRC generator
polynomial .where m is the degree of a CRC Generator polynomial .by calculate the CRC
polynomial in binary digits .i consider the missing coffients as zero

Example: g(x) = x32 + x26 + x22 + x16 + x12 + x11 + x10+ x8 + x7 + x5 + x4 + x2 + x + 1

It can take missing coefficients as zero in binary digits in the degree of co-effients
3,6,9,13,14,15,17,18,19,20,21,23,24,25,27,28,29,30,31
g(x) generally I written as=100000100010000010001110110110111
2.
Modulo 2 or exclusive OR dividing the data with m zeros appended by the generate
polynomial g(x) to get the remainder r(x) .Here data is equal to data with m zeros where m
is degree of CRC generator polynomial.
Example: Data=1011101010 ,m=32 degree of CRC generator I add the 32 zeros to data
appending
3.
After Modulo 2 with data to get remainder r(x) .Adding zeros before the data
corresponding to r(x) to extend it to m bits. Where m is degree of the CRC generator

Data got in step 3 r(x) with extended m bits. it is appended in after the original data U(x) and I

get the data to be transmitted, Taken as xmU(x) + r(x).

15
 Fig. 2  Pipelined architecture of parallel CRC algorithm

As shown in Fig. 2, I can implement the CRC block based on pipelined architecture as the
following steps:
1. Depart the 128 bits of data divide into four 32-bits data.
2. XOR the CRC generated by the previous 128 bits of data with the first 32-bits block of
data of the 128-bits data.
3. Calculate the CRC of each 32-bits data, respectively.
4. XOR the CRC calculated in step 3 so that I get the CRC of the data.at time pipelined
architecture of parallel CRC algorithm can process 256 bits of data it’s combination two

Fig. 3  General LFSR architecture

128-bits of data.it process large volume of data CRC calculation in parallel. 256 bits,512

16
 bits,1024 bits (1mb). it better verification method for large volumes of data it is fit for modern
communication

The parallel CRC algorithm processed in coarse-gained and fine-gained dimension .the
coarse-gained method OR algorithm to calculate the 128- bits data. I depart the 128-bits data
into four sections .128-bits of data into four -32 bits of data and calculate their CRC,
respectively.

However, how to calculate the CRC of 32 bits of data still needs to be proceed furthur. In my
reaserch CRC Calculation through fine-gained method derived from the linear feedback shift
register (LFSR) shown in above figure 3.

From Figure 3 LFSR architecture showns, which is built from the coefficients of the generator
polynomial it is also called as Parallel CRC generator Polynomial

g(x) = x32 + x26 + x22 + x16 + x12 + x11 + x10+ x8 + x7 + x5 + x4 + x2 + x + 1

Taken missing coefficients as 0 then I can written as G(X) IN binary digital format as
G(x)=100000100010000010001110110110111
The LFSR architecture is consist with the principle of the CRC algorithm. The LFSR can be
done modulo2 operation by flip- flop with shifting .flip-flop cantains (or)holds the data in the
storage .modulo-2 divided by g(x) calculate the results taken remainder as r(x) .Append 32 zeros
behind the original k-bit message U(x), I could get its CRC after k + 32 clock cycles.

Fig. 4  LFSR architecture for CRC-5

CRC get after 32 shifts .in this case I use the right shift and modulo-2 dividing with CRC
generator .every shift taken as clock cycle. original data is k bytes of data.after 32 clock cycles
generate CRC at output these CRC bits taken oxs or hexa decimal format it is appended to data
it will transmit through channel

Serial CRC-LFSR architecture differs from parallel CRC-algorithm while generate the CRC-

17
bits.Serial CRC-LFSR architecture takes more time to generate the CRC code .Parallel CRC
quickly generate the CRC-bits. it’s not consistant with the data holding of Flipflop.

Linear feedback shift register Bases ,I can directly correlated between the data and it’s CRC
I take CRC-5 with 4-bit data U(x) as an example. The generate polynomial of CRC-5 OR CRC

generator polynomial is x5 + x2 + 1, it can written in binary digit form 100101 .so the CRC-5
architecture using linear feedback shift registers discuss on the above digram from that I can
conclude the states in equations
The ⊕ operation is the same with modulo-2 operation, demonstrating XOR addition
operation.
I can write the equations as Described below:
S4[i+1]=S3[i]
S3[i+1]=S2[i]
S2[i+1]=S4[i] xor S1[i]
S[i+1]=S[i]
Taken as 1 0
S0[i+1]=S4[i] xor D[8-i] .I taken the CRC-5 generator polynomial then CRC bits (n-1) where n
is the degree of CRC generator .here CRC-5 then 5 zeros are appeneded to the original data those
are D[4],D[3],D[2],D[1],D[0] all zeros are added to original data to generate CRC according to
CRC Method

S4[i] 01000
S3[i] 00100
S2[i] 10010
S1[i] 00001
S0[i] 10000

18
S[i+1] = A S[i] XOR D[8-i]
S[i+2]= A S[i+1] XOR D[7-i] here substitute the S[i+1] in this equation to generate the data in
matrix from that take CRC .this Same principle applied for CRC-32 architecture to generate the
CRC

TABLE1. Comparison of utilization of resources

Implementation SliceLUTs Slice registers Slice LUT flip-flop

pairs

lookup 393 288 14 500

tables
parallel 390 128 11 393
algorithm

By comparision of conventional to parallel algorithm .this consumes less resources in point of

source parameters those are slice LUTs, Slice registers, slice-pairs, LUT Flipflop in the case of
parallel algorithm takes in my reaserch less 3 slice LUTs, 100 registers,3 slice pairs,107 flip
flops than conventional CRC Calculation

CRC algorithm reduces the delay from receiving data to generating its CRC bits or CRC
Calculation it generates higher speed ,high bitrate .it is most useful transfer laong distance
transmission .it is meet the specification of FC .this process built direct correlation between the
input data and its CRC .from following telling process parallel CRC algorithm takes less
resource consumption than conventional for the same FPGA Chip design .so finally I can
conclude this algorithm is efficient.

19
 Cyclic redundancy check (CRC) is a largly used technique for Correcting errors in
modern digital communication. It is ability to correct the errors with burst number in
transmission.In the CRC method, m number of bits added to message being transmitting here m
is the degree of certain polynomial that polynomial called as CRC generator polynomial . that
data modulo-2 divide with CRC-polynomial to get remainder CRC bits those are append to the
data and finally send the data at transmission .and receiver check data with divide modulo2
CRC generator get remainder as zero receiver data is correct . Other than zero some error
occurred in transmission.
Some number of bits are added to the message being transmitted. The receiver can determine
whether these appended bits agree with the data to check with a certain degree of probability if
an error obtained in communication. .this method is used in Storage like mainframe ,large
volumes of data storage (metadata,giga data,tera data in data Science applications),radar and
satellite communications and also used in computer storage example disk drive .for read and
write operations of disk drive this technique does not know address how to correct the data
while errors are verification.when the error is occurred . the receiver usually feedback "negative
acknowledgement (NAK) " to the transmitter, and transmitter resends the message.
CRC has been employed in many various communication protocols including Ethernet,
asynchronous transfer mode (A TM), and fiber distributed data interface (FDDI). CRC
calculations can be evaluated in either hardware or software.It is powerful verification method
and it’s easily implemented in hardware .it can built by linear feedback shift register(LFSR)
consists of flip-flops and XOR gates here flip flop for data storage and XOR gate for the
modulo2 operation. In most of situations LFSR based CRC calculation hardware deals with only
one data bit per clock cycle in implemented conventional serial input but not suitable modern
communication or high band width,high bit rate ,long dat transmission from the following
reasons .it leads the different parallelization schemes in hardware .in that I can go for the parallel
CRC algorithm inthat CRC-32 bits improve the accuracy of data transmission..
CRC generator polynomial given for the LFSR transition in parallel CRC algorithm given by
pei and Zukowski. Parallel CRC based on LFSR cascaded approach given by Sprachmann .In
software calculations, straight forward polynomial evaluations are not optimal, and CRCs are commonly
evaluated using table lookups . Buller and kounavis showns parallel method for CRC calculation with out
using Lookup table .this frame work used in various computer architectures.

20
 In my reaserch . I introduced ARM coartex-A 15 processor based new software parallelization
method for Speed CRC calculation .it method is based on 32 bit word –wise CRC calculation in
contrast to byte -wise table lookups.by this method achieved 2.6 times faster than conventional
CRC Calculation.
BASIC CRC CALCULATION
The CRC calculation is an arithmetic polynomial. The represented Message divides a CRC
Generator polynomial GF(2) (Galois field of two elements) resulting in a remainder. A
polynomial in GF(2) is a polynomial in a single variable x whose coefficients are either 1 or 0
missing co-efficients are taken as 0 in g(x) polynomial it taken binary digita format Modulo2
operation represents exclusive OR operation. Addition and subtraction are all done in modulo 2.
In other way, those are the same as the "exclusive OR". The multiplication between two
polynomials are represented by the "logical AND" for the multiplication and "exclusive OR" for
the summation of the partial product. Division of polynomials is done in mst of the similar way.
PROPOSED SOFTWARE BASED PARALLELIZED CRC CALCULATION
Direct CRC calculation requires various operations combination of exclusive ORs and shift
operations. CRC evaluation with lookup tables also ineffient in resource –intensive embedded systems..In
My reaserch, I propose a software implementation of a parallelized CRC calculation which is even more
efficient than conventional CRC based table lookup methods. The parallelized CRC calculation method
calculates the CRC 32 bits at a movement compared to a traditional or conventional bit-wise iteration or
byte-wise table lookup iteration.bit -wise means serial CRC calculation
For this Eample, it takes 4 clock time speed to calculate 4 bit CRC .and accumulator updates
one bit at atime this method perform well in systems where data is handled flowly. The serial
shift register algorithm can also be evaaluated in software:
void CRC(int &acc, int data, int len, int poly)
{
for(int i=O; i<len; i++)
{
if ((data&l) ==1)
acc = (acc» l) A poly;
else
ace = acc» l;
data = data» l;

21
}
Here uses for loop .it used as iteration .This algorithm iterates its inner loop once for each bit of
the input data stream.
Table-driven CRC calculation
Iteration based CRC algorithms are also important most of the applications in that A table driven
algorithm which iterates once per byte( 8 bits of data is called one byte) of input data is
commonly used when CRCs must be evaluated in software. It iterates once per byte of input.
This algorithm is suitable for any accumulator and polynomial width or polynomial length, and
can be Evaluated as follows for each data byte or each data bits
Error correction codes provides a mean to correct and verify errors introduced by the
transmission channel. Two main types of codes exist: 1.block code 2.convolution codes .these
are reduce the message data to adding parity.block codes are also called as linear block codes
Linear block codes………….cyclic codes……….Cyclic redundancy check(CRC) codes
Cyclic codes are subset of linear block codes and Cyclic redundancy check(CRC) codes are
subset of Cyclic codes.it is hugely used to correct errors in data transmission and storage
applications ,storage devices example disk drive here read/write the disk drive operations.CRC is
very powerful hardware detection method to obtain the data reliably and easily implemented in
hardware
The CRC technique is used to correct the integrity of blocks or bytes of data called Frames. In
this method transmitter appends an extra n check bit added to frame then it is called as frame
check sequence (FCS) .FCS contains residue bits or CRC bits about the Frame that helps the
receiver correct errors in the frame. When the transmission is received at the receiver check the
transmission data then receiver CRC bits is generated and compare against the appended CRC
bits .
Fast data transmission, the serial CRC algorithm can not meet specifications .but
Parallel processing is avery efficient way to increase the speed or throughput rate to meet
specifications.Although parallel algorithm increases the number of message or data bits that can
be performed in one clock cycle, it can also lead to a long transmission path(TP) OR critical path
(CP).
Thus ,the parallel processing or parallel algorithm is used to the increase of high speed rate or
high band width or throughput accumulation will be reducing by the reduces the circuit speed

22
 Parallel processing or parallel algorithm increases the hardware cost or hardware
implementation. it is be controlled.The parallel CRC algorithm in perform an m-bit message
data in (m+k)/L clock cycles, where k is the order of the CRC- generator polynomial and L is the
level of parallelism. However, in [ m message bits can be processed in m/L clock cycles. Fast-
speed architectures for parallel long encoders are based on the multiplication and division
calculation on generator polynomial are efficient in terms of fast up the parallel linear feedback
shift register (LFSR) structures.
Example: message data=1010101010
K is order of data I use the CRC-32 here k=32 bit polynomial
128 bit data divided in to 4 CRC-32 bit data divide into 4 parallel blocks L=4=level of
parallelism Here m=10
K=32
Parallel algorithm process (m+k/L) clock cycles
(10+32)/4 it takes 10 clock cycles
For fast speed algorithms m/L=10/4 . fast algorithms it can process m/L clock cycles it takes
around 2 to 3 clock cycles.
Parallel CRC circuit design to achieve shorter distance path perform high processing speed
than commonly used.the design through LFSR .Which is generally usedfor conventional or serial
CRC An unfolding algorithm is used to design parallel processing. However, direct application
of unfolding may lead to a parallel CRC circuit with long iteration bound, which is the lowest
achievable Critical Path(CP). original serial LFSR CRC structures to reduce the iteratin bound
developed by look -head pipeline methods; then, the parallel CRC algorithm with minimum
iteration bound it is used in unfolding algorithm. The retiming algorithm or timing based
algorithm is then applied to obtain the achievable lowest Critical Path or transmission path

3.literature review

23
 • Chuxiong, W. and Haifeng, S., 2019. Design and implementation of parallel CRC

algorithm for fibre channel on FPGA. The Journal of Engineering, 2019(21), pp.7827-

7830 ………………from this reaserch paper is helpful in my project based on this I take

my intial idea .that thought go on reaserch in this particular concern. I observed from

this journal .it tells the how to implement parallel CRC algorithm to meet the

specifications For fibre channel .and it is easily implemented in hardware .it is powerful

error detection or verification method.by this parallel CRC algorithm use less resource

consumption on FPGA .it is resource intensive method

• Perterson, W.W., Brown, D.T.: ‘Cyclic codes for error detection------------from this paper

I observe the codes for error detection .these are two types block code and convolution

code.block code is also called linear block code.cyclic code are subset of block

code .cyclic redundancy check(CRC) is subset of cyclic code.the concept of cyclic

redundancy check(CRC) is came into picture .this is the CRC concept life cycle

observed from this paper

• Sun, Y., Kim, M.S.: ‘A table-based algorithm for pipelined CRC calculation Conf. on

Communications (ICC), Cape Town, South Africa------------from these paper I observed

pipelined CRC Calculation it is done by a table –based algorithm.table-based algorithm

study so much helped in my reaserch

 Sun, Y., Kim, M.S.: ‘A pipelined CRC calculation using lookup tables’. 7th IEEE

Consumer Communications and Networking Conf., Las Vegas, NV,USA……….from

these paper A pipelined CRC calculation using LU T .Look up tables based CRC

calculation is mostly used in my research project.

24
  J. Buller, "High Speed Software CRC Generation, " EON, vol. 36, no. 25, pp 210. [8]
M. E. Kounavis and F. L. Berry, "Novel TableLookup-Based Algorithms for High-
Performance
 CRC Generation, " IEEE Trans. Computers, vol.57, no. 11, pp. 1550-1560, 2008

 tallings, William, "Data and computer communicat ions", Upper Saddle River,

N.J.:Pearson/Prentice Hall, 8th Edition, 2007.

 [2] Palani Subbaiah, "Bit- Error Rate for High Speed Serial Data Communication", Data-

communications Division, Cypress Semiconductor, November 2008.

 [3] Peterson, W. & E. Weldon, "Error-Correcting Codes", Second Edition, MIT Press,

1972.

 [4] Ulf Nordqvist, Thesis: "Protocol Processing in Network Terminals", Depart ment of

Electrical Engineering,Linkopings University, SE-581 83 Linkoping, Sweden 2004.

 [5] U. Nordqvist, T. Henriksson, D. Liu, "CRC Generation for Protocol Processing",

Norchip 2000, Turku,Finland, pp. 288-293.

 [6] Ming-Der Shieh, Ming-Hwa Sheu, Chung-Ho Chen,Hsin-Fu Lo, "A Systematic

Approach for Parallel CRC Computations", Journal of Informat ion Science and

Engineering, Vol. 17, 2001 pp. 445-461.

 [7] Giuseppe Campobello, Giuseppe Patane, Marco Russo, "Parallel CRC Realization",

IEEE Transactions On Computers, Vol. 52, No. 10, 2003, pp. 245-256.

 [8] A. H. Saleh, K. M. Saleh and S. Al-Azawi, "Design and simulation of CRC encoder

and decoder using VHDL",1st International Scientific Conference of Engineering

Sciences - 3rd Scientific Conference of Engineering Science (ISCES), IEEE 2018, pp.

221-225.

25
  [9] A. K. Panda, S. Sarik and A. Awasthi, "FPGA Implementation of Encoder for (15, k)

Binary BCH Code Using VHDL and Performance Comparison for Multiple Error

Correct ion Control", International Conference on Communication Systems and Network

Technologies, Rajkot, 2012, pp. 780-784.

 [10] Bajarangbali P., Aparna Anand, “Des ign of High Speed CRC Algorithm for

Ethernet on FPGA using reduced lookup table algor ithm” , I EEE Annual

IndiaConference (INDICON) 2016.

 [11] Zavodnik, T; Kekely, L.; and Pus, V., "CRC based hashing in FPGA using DSP

blocks," in Design and Diagnostics of Electronic Circuits & Systems, 17th International

Symposium on , vol., no., pp.179-182, 2325 April 2014.

 [12] Kounavis, M.E. and Berry, F.L. "Novel Table Lookup Based Algorithms for High-

Performance CRC Generation," in Computers, IEEE Transactions. pp. vol.57, no.11,

pp.1550-1560, Nov. 2008.

 [13] M.D. Shieh, M. H. Sheu, C. H. Chen, and H.F. Lo, “A Sys tematic Approach for

Pa ralle l CRC Co mputations ,”J. Informat ion Science and Eng., vol. 17, pp. 445-461,

2001. 978-1-7281-1261-9/19/$31.00 ©2019 IEEE 2011

 [1] Anish, N.K., Kowshick, B. and Moorthi, S., 2013, September.Ethernet based industry

automation using FPGA. In2013 Africon IEEE.

 [2] Sung, G.M., Wang, H.K. and Li, Z.Y., 2018, May. Hardware design on FPGA for

Ethernet/SONET bridge in smart sensor system. In2018 7th International Symposium on

Next Generation Electronics (ISNE)(pp. 1-4). IEEE.

26
  [3] Wang, H. K., Yu, C. P., Sung, G. M., & Li, M. W. (2018, October). Intelligent Packet

Transformation and Transmission Between Ethernet and Optical Fiber Systems Based on

a Field-Programmable

 5 Gate Array Board. In 2018 IEEE International Conference on Systems, Man, and

Cybernetics (SMC) (pp. 4071-4076). IEEE [4] Chakrabarti, P., 2015. Optical Fiber

Communication. McGraw-Hill Education. [5] Borrelli, C., 2001. IEEE 802.3 Cyclic

Redundancy Check, XAPP209(v1.0).

 [6] Kadric, E., Manjikian, N. and Zilic, Z., 2012, September. An FPGA implementation

for a high-speed optical link with a PCIe interface. In 2012 IEEE International SOC

Conference(pp. 83-87). IEEE.

 [7] Jabbar, M.A., Albaker, B.M. and Iqbal, S.Z., 2017. Using DifferentTechniques in

Data Transferring by Optisystem Program.American Journal of Optics and Photonics

 , [8] Alvarado, A., Agrell, E., Lavery, D., Maher, R. and Bayvel, P., 2015. Replacing the

soft-decision FEC limit paradigm in the design of optical communication systems.

Journal of Lightwave Technology

27
 4.Verilog code:

 Width = 16 bits
 Truncated polynomial = 0x1021
 Initial value = 0xFFFF
 Input data is NOT reflected
 Output CRC is NOT reflected
 No XOR is performed on the output CRC

1 //--------------------------------------------------
---
2 // Design Name : parallel_crc_ccitt
3 // File Name : parallel_crc.v
4 // Function : CCITT Parallel CRC
5 // Coder : Deepak Kumar Tala
6 //--------------------------------------------------
---
7 module parallel_crc_ccitt (
8 clk ,
9 reset ,
10 enable ,
11 init ,
12 data_in ,
13 crc_out
14 );
15 //-----------Input Ports---------------
16 input clk ;
17 input reset ;
18 input enable ;
19 input init ;
20 input [7:0] data_in ;
21 //-----------Output Ports---------------
22 output [15:0] crc_out;
23 //------------Internal Variables--------
24 reg [15:0] crc_reg;
25 wire [15:0] next_crc;
26 //-------------Code Start-----------------
27 assign crc_out = crc_reg;
28 // CRC Control logic
29 always @ (posedge clk)
30 if (reset) begin
31 crc_reg <= 16'hFFFF;
32 end else if (enable) begin
33 if (init) begin

28
 34 crc_reg <= 16'hFFFF;
35 end else begin
36 crc_reg <= next_crc;
37 end
38 end
39 // Parallel CRC calculation
40 assign next_crc[0] = data_in[7] ^
data_in[0] ^ crc_reg[4] ^ crc_reg[11];
41 assign next_crc[1] = data_in[1] ^
crc_reg[5];
42 assign next_crc[2] = data_in[2] ^
crc_reg[6];
43 assign next_crc[3] = data_in[3] ^
crc_reg[7];
44 assign next_crc[4] = data_in[4] ^
crc_reg[8];
45 assign next_crc[5] = data_in[7] ^
data_in[5] ^ data_in[0] ^ crc_reg[4] ^
crc_reg[9] ^ crc_reg[11];
46 assign next_crc[6] = data_in[6] ^
data_in[1] ^ crc_reg[5] ^ crc_reg[10];
47 assign next_crc[7] = data_in[7] ^
data_in[2] ^ crc_reg[6] ^ crc_reg[11];
48 assign next_crc[8] = data_in[3] ^
crc_reg[0] ^ crc_reg[7];
49 assign next_crc[9] = data_in[4] ^
crc_reg[1] ^ crc_reg[8];
50 assign next_crc[10] = data_in[5] ^
crc_reg[2] ^ crc_reg[9];
51 assign next_crc[11] = data_in[6] ^
crc_reg[3] ^ crc_reg[10];
52
53 endmodule

29
 5.ABOUT FIBRE CHANNEL

Fiber channel is most advanced usage in communication it is better than other

communications. it’s modern connecting technology with high speeds. Fiber channel used in
various types of audio and video data transmission and it’s performed various types of audio . FC
used in aero space environment it most suitable in huge volume data transmission between ends
have the features high bandwidth and interference .For most usage applications in
commericial,aircrafts,military ,aerospace rapid data generated it is transmit over long distances
requires high data rates because data may be audio and video data transmission for these demand
Avionics environment (AE) ,American national introduced Fiber Channel committee(FC)
Decides the concept of protocol FC-AE in the avionics environment it requires high speed
interconnecting medium for transferring high volume of data transmission between ends
Fiber Channel committee introduced avionics environment FC-AE ,it supports different
protocols and it is used in various applications .it used different kinds of upper level protocols,
those are Fibre Channel Anonymous Synchronous Messaging (FCAE-ASM) and Avionics
Digital Video Bus (ADVB) , Fibre channel remote direct memory access in avionics
environment (FC-AE-RDMA) and Switching system based on FC-AE-1553. My study
introduces design and implementation of the framework for Fiber channel based message
protocol.
II. FIBER CHANNEL
Fiber channel used in the very high speed data between ends. it is operated in different
technologies those are.

1. Point_To_Point
2.Arbitrated loop
3. Switched fabric

Point-to-point topology is the basic fibre channel technology .it is like one to one nodes
directly connected
Arbitrated loop topology upper technology on point To Point it is performed to connect
multiple devices in circulaly

30
 In the case of avionics environment used Switched fabric topology. It is switch based fibre
channel technology FC-AE-1553 devices are connected through switch fiber channel protocol
used in different levels . The fiber channel communication model protocols those are

1.Ultra-short Light pulse(ULP)s ULP means unit of last pulse .it used mainly defence
applications those signal or pulse transmission example military applications for meet the high
speed data rate it requires for long path transmission.

FIbre channel is a modern communication usage .it is used in high speed data transmission
protocol for long distance transmission ends .it is under lossless medium .delivery of raw block
data.it is used primarly data storages,big data applications example computer data storage for
servers it used as storage area networks in data networks it as different types of protocols

FC_4 it is four layer FC Protocol used mainly in protocol mapping example LUN mapping
FC_3
It is third layer of FC it is denoted as layer3 mainly used for common services
FC_2
It is second layer of FC it is called as layer2 mainly used in the network
FC_1
It is first layer of FC it is called as layer1 mainly used in data links or data interfacing
FC_0
It is called layer 0 .it is called physical protocol
FCVI it means fluorescence correction Vegetation index .A physically based reflectance index
to divide the physiological and non –physiological data
FCP_2
Fibre channel protocol is short called as FCP it used as interfacing protocol for fibre channel
connection
Hunt Groups Common Services
It is pass communication protocols .two servers direct connection through pass communication
under this Groups common services CISCO protocols under this hunt Groups
Link

31
It is used in the computer networking .also called as link layer it is lowest layer in the internet
protocol main purpose is used to link the group of methods and communication protocols to host
Signaling protocol
It is known as FC-2 protocol.transport protocol of fibre channel,its have some signaling rules of
the data to be transmit between the transmission ends
Transmission protocol
Fiber channel protocol(FCP) is also called as transmission protocol .it also known as interface
protocol example SCSI interface used to fibre channel connection .high speed data transmission
system used to connect storage devices,mainframe computers
Transmitter and Receiver
In the fibre channel wherever data transmission end is called transmitter and data or information
collection end is called reciever
Media
it is the data transmission medium .it is also called as channel in communication systems
different channels available in the modern communication systems those are fiber optic,electro
magnetic interference
SBCC
It is sequence or speed controlled protocol it is mostly used in fibre channel communication
S
It is major protocol used in fibre channel
Apart above protocol Others are
IP
It is an internet protocol frequently used in FC related to the internet information
SCSI
SCSI means small computer system interface .it is interface protocol .it is set of
protocols,commands,electrical,optical and logical interfaces
VIA
It is mainly used in HTP(hypertext transfer protocol) .seperate authentication scopes under one
internet protocol
IP over

32
Fibre channel over ip (FCIP or FC/IP, also known as fibre channel tunneling or storage
tunneling) is an internet protocol
FCSB-2
Fibre channel security protocol is mainly used in fibre channel in that switch based security is
one of the major that is known as FCSB protocol
Others protocol are discription below
FC_0 layer tells the physical connections those are link speeds,length and the channel type .the
channel type is optical fiber and connection type is lightmedium .the optical fiber can be two
catagories those are
1.single mode channel type
2. multi-mode channel type.
FC_1 is a transmission protocol or layer 1 protocol .encoding and decoding methods and
special symbols used for protocol usage .it tells the information about the frame delimiters and
primitive data information.
FC_2 is the signaling protocol, it is called as layer-2 protocol .frame structure of the protocol it
is combination of frame header,frame data field and CRC
FC_3 layer it also known as layer-3 protocol .tells the common services provided by link
services .those extended link services combination session management,login services and world
wide service.
FC_4 layer is also known as layer-4 protocol .it tells the information of interface mapping.it
gives the mapping of upper level protocols over fiber channel.
Rapid development in avionics environment in the aero-space applications. those are
aircrafts,radar,fighter aircrafts, satellite communications .it generates high volumes of data.to
meet the high data rate avionics environment fibre channel committee (FC) introduces FC_AE
protocol it is used in above applications
FC-AE protocol used in various classes of services . those services differs in communication
between two communication ports. Difference in communication defined as class .these classes
of services are
Class 1,Class 2,Class 3 and Class 6.
Class1 service is secured connection between the two transmission ends .it is an
acknowledgement protocol.

33
Class 2 is not a Secure connection service. It is the service with fabric multiplexing at the frame
content or frame header .
Class 3 is a connection less service .in this service donot have connection between transmission
ends and unacknowledged service.
Class 6 is a secured connection service, featured with multiport connection. Single source port
will form secured connection with multiple destination ports. Fibre channel avionics
environment contain frame with maximum size length of 2148 bytes .frame will consists of
combination of SOF,frame header, data field ,CRC bits,End of frame(EOF).
 Start Of the Frame (SOF),
 Frame header,
 Data field,
 CRC BITS,
 End of the Frame (EOF).
In order to maintain the data linkage ,primitive signals should be sent between the frames fibre
channel avionics environment frame is below parts
SOF
Extended Header(s)
FRAME HEADER
PAYLOAD CRC
EOF
FC-AE Environment use the FC-AE protocol .its Structure all parts are connected in sequences
those sizes are start of frame whose size is 4 Bytes.and Extended header or Optional header
whose size of 24 bytes. Frame header size between 0 to 2112 Bytes .and payload CRC bits
whose length is 4 bytes and end of frame (EOF) whose length is 4 Bytes or 0 or more
FC-AE STRUCTURE EVALUATION:
A. Start of Frame (SOF)
Start Of Frame delimiter is denoted by SOF .it is used for sequence control .where X
represents the specific class for which the delimiter is used

34
B. Extended Header(s)
Extended Headers are Frame optional headers .it is frequently or immediately followed by the
SOF delimiter.it is used for adding the extra functionality in the frame content.The extended
header extension or sequence is Frame Header.
C. Frame Header
Frame Header is used for controlling the connection operations,.transfer data protocols , detect
missing frames.extended headers are optional . it is not available.frame structure immediately
follows the SOF delimiter.
D. Payload
Data,which send the data from one end to other is packed in this payload field .maximum length
of playload per frame content is 2112 bytes.
E. CRC
CRC bits used for error correction in the data transmission.it is Cyclic redundancy check for
the frame content.SOF and EOF are excluded for CRC calculation .CRC is a 4 byte word. which
is calculated for Extended Header (if present), Frame header and payload.CRC is used for the
error handling of the frame.
F. End of Frame (EOF)
EOF delimiter length of 4 byte word which is an ordered set and immediately follows the CRC
field of frame Content . There are multiple EOF delimiters which are used for sequence control.
IV. FRAMES USED IN THE PROTOCOL IMPLEMENTATION
FC-AE environment differs in communication between the transmission ends those services
divided as types of class services . Class 3 service is connection less service.implementation of
this protocol .based on unacknowledged service .destination can discard the multiple frames sent
by source without any acknowledgement. class of service donot have the flow control frames.
Data frames for the communication these data Frames are two types
1.initializing frame
2.data frame
Initializing frame which estabilishing the connection between two transmission nodes
Data frame which carriers the information from source end to destination end

35
SOF delimiter of Initializing frame is SOF initiate (Sofi). This frame establishes the connection
between twoends. Header contains the information of source and destination. Frame header
contains frame count and frame name is the connection initialization of Frame. data frame
contains data . CRC is calculated for the complete frame excluding SOF and EOF delimiter and
value is filled in the CRC field. EOF field contains the value of EOF which denotes the normal
end of the frame. EOF used in this frame does not shows the termination of communication.
G. Data frame
Data frame immediately follow the frame header in the frame structure. Frame structure for
normal frame used in the protocol.

36
 6.FLOW CHART

37
 7.ABOUT FPGA

Fibre Channel (FC) mainly used for long distance transmission .its need high data rate .FC
Protocols are helpful in the interconnecting transmission.its having multiple advantages like
large bandwidth, low latency, high anti-interference, flexible architecture or heirachy. In the
case of avionics environment or aerospace applications like radar, fighter aircrafts, satellites
and storage area applications like mainframe ,data science, data networks,large ship borne
applications, military, defence applications .its advantages are helpful in data communication
for long transmission those are the high-speed,high-reliability and low latency, large flexibility.
The aerospace applications data transmission in the form of video and audio ,signals means
graphs,images. this information or data most important to aircraft pilot by this data only is
handle the safely flight or aircraft .this verified data sequence is prevent hazardous misleading
information.in my study conclude receiver module of aerospace system is a Field
Programmable Gate Array (FPGA) based large bandwidth Fiber Channel Analyser (FCA). The
study or reaserch design is to be implemented using Xilinx Spartan-6 FPGA SP605 evaluation
board. The receiver module study requires data with high resolution in the case of aerospace
pilot handle the flight by video/audio inframation, signals/graph information.for high video
resolution use the (VGA) and data link speed not meet specifications of ethernet interface.for
that developed a high bandwidth FCA .it useful for speed improvement,high resolution of data
in the form video and audio transmission much helpful in aerospace applications.the resulted
from above scenario used for multiple aerospace systems.

The Field Programmable Gate Array (FPGA) design with compound asynchronous circuits
such as Time Mode (TM) design structure almost unfeasible. generally Field programmable
Gate Array(FPGA) is combination of Programmable logic (PL) devices. the operation of logic is
synchronous with clock pluse. However, for avionics environment like aerospace applications
data transmission in the audio and video format .in the case high resolution of data need high
performance specifications to failure the above criteria and follow an asynchronous
implementative solution.The reaserch community and industrial R & D study use the PL devices
instead of Application Specific Integrated Circuits (ASIC).Prorammable devices are main drive
force for an asynchronous design,

38
For Avionic environment aerospace applications need video resolution .for high resolution in
my study TDC (Time to Digital converter) .it’s clock pulse at some hundreds of MHz
implemented in FPGA need TDC with high resolution .Clock pulse means frequency time period
is inversely Propotional to frequency
F=1/T, T=1/F,
F= MHz
T= 1/MHz
= ns
TDC with resolution at ns .FPGA used as receiver in avionics environment.in the avionics
applications need high video resolution for the pilot in the aircraft system to handle or control
safely by display high video resolution needed .for these FPGA Implementing a TDC with
resolution at ns. For high performance need higher resolution required ,above TDC ns resolution
not enough .signal frequency cannot be increased MHz further and quantize the time intervals by
Propagation delay of the logic this concept is Called as Tapped Delay Line(TDL).in the avionics
environment best utilization of all available resources implemented of TDL based TDC in FPGA
It is best receiver module in FC-AE environment.how signals propogate inside these resources.

In my study, Xilinx FPGA Size length are in nms .Short length Xilinx nm FPGA term high
performance extended dynamic range perform high resolution. My reaserch 28_nm7_Series
Xilinx FPGA board is used for TDL Based TDC best utilization of resources in FPGA, Xilinx
FPGA Sizes varies from 65_nm to 20_nm. In this context, the term high_performance means
extended dynamic_range (up to 10.3 s), high_resolution and single_shot precision (up to 366 fs
and 12 ps r.m.s respectively), low differential and integral non_linearity (up to 250 fs and 2.5 ps
respectively), and multi_channel capability (up to 16).
Any Communication network information Security is much important.for security encrypting
algorithms is used in modern communication. commonly it is called Advanced Encryption
Standard(AES).The AES algorithm major disadvantage is more time consumption to encrypt the
operation.more time requires encrypt the data ,information security is less .easily hackers have to
break the system. My reaserch presents encrypted algorithms are effectively by different
methods those are parallel and pipelined .by these algorithms effective processing time is
reduced to encrypt the data by these information security is stronger by the encrypt algorithm

39
these algorithms data size bigger.. These algorithms system able to encrypt many various
states(the data will be encrypted) in the synchronous time with no necessity to wait for the before
encrypted operation to be finished.in My reaserch or study introduces encrypted algorithms are
three : traditional,pipelined and parallel algorithms and finally a differ between them.

40
 8. CRC-32 APPROACHES

1.Coarse-gained algorithm for CRC-32

Let U(x) be first 128 bits of the message data and r(x) be the CRC of U(x). Let g(x) be the
binary polynomial of the generator or CRC generator polynomial ; then for some polynomial
w(x), the definitions can be written as the input of 128 bits of data .first 32-bit data can be
written as below in equation 1.r(x) is remainder or CRC of U(x) it is also called residue of
U(x)

x32U(x) = r(x) + g(x)w(x) (1)

g(x) = x32 + x26 + x22 + x16 + x12 + x11 + x10+ x8 + x7 + x5 + x4 + x2 + x + 1

(2
)
g(x)=100000100010000010001110110110111

U(x) is the first 128 bits of the message, and it follows with other 128-bit data to be processed.
Let U′(x) be the next 128-bit of the message, which is closely after the first one. The two 128-
bits data forms 256 bits of the message, denoted as N(x). So, N(x) equals to 256 bits of
data.here r’(x) be the CRC of next 128 bit data can be represented in equation 4

N(x) = x128U(x) + U′(x)

x32N(x) = r′(x) + g(x)w′(x) (4)

x32(x128U(x) + U′(x)) = r′(x) + g(x)w′(x) (5)

x128x32U(x) + x32U′(x) = r′(x) + g(x)w′(x) (6)

41
 2.Fine-gained algorithm for CRC-32

Now I have got the coarse-gained method to calculate the 128- bits data. I depart the 128-bits
data into four sections and calculate their CRC, respectively. However, how to calculate the
CRC of 32 bits of data still needs to be discussed. We are going to achieve it in a fine-gained
method derived from the linear feedback shift register (LFSR).

g(x) = x32 + x26 + x22 + x16 + x12 + x11 + x10+ x8 + x7 + x5 + x4 + x2 + x + 1

The figure of LFSR architecture is consistent with the principle of the CRC algorithm. The
LFSR can be seen as a module 2 divider used to calculate the results of U(x) divided by g(x).
Append 32 zeros behind the original k-bit message U(x), we could get its CRC after k + 32
clock cycles. The serial CRC-LFSR architecture takes a long time to generate the CRC code,
inconsistent with the data processing requirement of FC.

Based on LFSR, we can directly establish the relationship between the data and its CRC.
Without loss of generality, we take CRC-5 with 4-bit data U(x) as an example. The generate

polynomial of CRC-5 is x5 + x2 + 1

I can conclude the states in these equations

S4[i + 1] = S3[i]

S3[i + 1] = S2[i]

42
 9. RESULTS

The FC protocol requires the data and the CRC reverse in a certain rule, so we should reverse
the data and CRC polynomial coefficients before and after the calculation, respectively.
The SOF and EOF delimiters shall not be included in the CRC scope, so we should detect
and exclude EOF and SOF delimiters from the CRC scope. Referring to [8], the algorithm
flowchart can be drawn in Fig. 7.
Mapping CRC scope to FCS input

fig:6
f5:Mapping crc scopeinto fcs input Mapping fcs coefficients to crc field

43
Calculation of crc procedure

According to the flowchart and the theory of CRC, we program the CRC encoding module
for FC in Verilog, designed and simulated with Vivado design suite.
Fig. 8 shows the simulation results. As the paper mainly discusses the design and
implementation of CRC for frame content, the figure shows the results of CRC of the data and
skips the steps to detect SOF and EOF delimiters. From the figure, we can see that for a 128-
bit data ‘0 × 313233343536373839383736353433’,
reverse it and we will get its reversed CRC ‘0 × 9bd00176’. In addition, for a data
stream of 512 bits ‘0 × 313233343536373839383736353433_31323334353637383938373
6353434_313233343536373839383736353435_313233343536373
839383736353436’, its revered CRC is ‘0 × 4e6dd731’. It can be seen that the results generated
by our algorithm are consistent with [9], showing the algorithm is feasible. Append the
reversed CRC after the reserved data, we will get the frame content to transfer (Table 1).
The CRC can be generated immediately when the input data is received by the posedge of
the clock.

44
 Figure7:results of simulation

Table 2 Comparison of utilisation

Implementation Slice LUTs Slice registers Slice LUT flip-flop

pairs

lookup tables 393 288 14 500

8
parallel 390 128 11 393
algorithm 1

The implementation of CRC algorithm reduces the latency from receiving data to generating
its CRC, better meeting the transfer rate requirement of FC. The algorithm simplifies the
process of the calculation to construct the direct relationship between the input data and its
CRC. From Above table, compared with a common CRC algorithm based on lookup tables,
the resources consumption of our algorithm reduces about 20% in LUT flip-flop pairs of the
same FPGA chip, denoting the algorithm is efficient.

45
 10. CONCLUSION

CRC, as a kind of widely-used algorithm in data communication, can verify data integrity
effectively. Aimed at the design and implementation of CRC for high-speed FC protocol, the
paper gives a method to calculate CRC of 128-bit parallel data. The method is parallel in both
coarse dimension and fine dimension. The coarse dimension demonstrates how to depart the
128-bit data into four 32-bit parts and the relationship of CRC of each 128-bit data. The fine
dimension gives a method that uses matrices to previously generate the direct connection of
original data and it's CRC based on LFSR. According to the method and following the
specifications of FC, the paper designed a resource-intensive method to generate CRC for FC.

In my reaserch showns that multiple data bytes can be exclusive OR ed to a CRC

accumulator before recirculation, resulting in a slight optimization of many existing CRC
algorithms. It is also shown that a symbolic solution of the CRC equation can be automated,
producing a tabular result which can be usedto produce parallelized algorithms which in some
casesare significantly faster than previously known methods.The symbolic evaluation software
will be further developed to fully automate the production of an optimized algorithm. The fast
software CRCs produced by this methodology can enable high reliability end-to-end data
protection in heterogeneous Systems
In my Reasrch implements pipelining method for high-speed parallel CRC circuits. Pipelining
has decreased the iteration bound of the architecture effectively. Applying unfolding technique to
pipelined architecture increased the throughput of the circuit and thereby applying retiming to
the architecture reduced the critical path delay. So applying pipelining, unfolding and retiming to
the CRC has increased the throughput to achieve high speed design. This brief has proposed two
pipelining methods for high speed parallel CRC hardware implementation. Proposed look ahead
pipelining has a simpler structure, parallel CRC design can efficiently reduce the critical path.
Although the proposed design is not efficiently applicable for the LFSR architecture of any
generator polynomial, it is very efficient for the generator polynomials with many zero
coefficients between the second and third highest order nonzero coefficients, as showns in the
commonly used generator polynomials. The serial implementation of CRC-9 uses 9 clock cycles,
iteration bound is 2T and critical path is 2T Whereas the parallel implementation of CRC-9
using pipelining, retiming and unfolding

46
 Uses only 5 clock cycles, its iteration bound is TXORXOR and critical path is T
. Thus increasing the speed of the architecture. This can be extended to achieve the high speed
CRC circuit without increasing the hardware resources such that area occupied by the design is
minimized. Parallel CRC architecture implemented here is having high speed compared to
previous algorithms and also hardware cost is controlled.

47
 11 .REFERENCES

[1] Perterson, W.W., Brown, D.T.: ‘Cyclic codes for error detection’, Proc. IRE, 1961, 49,
(1), pp. 228–235
[2] Sun, Y., Kim, M.S.: ‘A table-based algorithm for pipelined CRC calculation’. 2010 IEEE
Int. Conf. on Communications (ICC), Cape Town, South Africa, 2010, pp. 1–5
[3] Sun, Y., Kim, M.S.: ‘A pipelined CRC calculation using lookup tables’. 7th IEEE
Consumer Communications and Networking Conf., Las Vegas, NV,
USA, 2010, pp. 1–2

[4] Kennedy, C.E., Mozaffari-Kermani, M.: ‘Generalized parallel CRC computation on

FPGA’. 2015 IEEE 28th Canadian Conf. on Electrical and Computer Engineering
(CCECE), Halifax, Canada, 2015, pp. 107–113
[5] Kennedy, C., Reyhani-Masoleh, A.: ‘High-speed parallel CRC circuits’. Proc. of the
42nd Annual Asilomar Conf. on Signals, Systems and Computers (ACSSC2008), Pacific
Grove, CA, USA, 2008, pp. 1823–1829
[6] Bajarangbali, D., Anand, P.A.: ‘Design of high speed CRC algorithm for Ethernet on
FPGA using reduced lookup table algorithm’. IEEE Annual Indian Conf. (INDICON),
Bangalore, India, 2016, pp. 1–7
[7] ‘ANSI INCITS, fibre channel framing and signaling-4(FC-FS-4)’, 2013
[8] Narapureddy, P., Ananda, C.M., Pradeep Kumar, B., et al.: ‘Design and implementation
of fiber channel based high speed serial transmitter for data protocol on FPGA’. IEEE Int.
Conf. on Recent Trends in Electronics Information Communication Technology,
Bangalore, India, 2015, pp. 926– 931
[9] ‘Online CRC calculation’, Available at http://www.ip33.com/crc.html, accessed 2 April
2018

48
49