Scribd Logo
Upload

Welcome to Scribd!

  • 17 views

    Lecture2 - Embedded

    Uploaded by

    Black Hunter
    The document discusses two main CPU architectures: 1) The Von Neumann architecture, which uses a single memory for both instructions and data and a single bus. It is simpler but slower. 2) The Harvard architecture, which separates instruction and data memory and uses separate buses. It allows parallel execution and is faster but more complex and expensive. The document recommends the Von Neumann architecture for general processors due to lower cost and space needs, and the Harvard architecture for microcontrollers due to the ability to take advantage of parallelism to compensate for lower speeds.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    Lecture2 - Embedded

    Uploaded by

    Black Hunter
    17 views20 pages
    The document discusses two main CPU architectures: 1) The Von Neumann architecture, which uses a single memory for both instructions and data and a single bus. It is simpler but slower. 2) The Harvard architecture, which separates instruction and data memory and uses separate buses. It allows parallel execution and is faster but more complex and expensive. The document recommends the Von Neumann architecture for general processors due to lower cost and space needs, and the Harvard architecture for microcontrollers due to the ability to take advantage of parallelism to compensate for lower speeds.

    Original Title

    Lecture2- Embedded

    Copyright

    © © All Rights Reserved

    Available Formats

    PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    The document discusses two main CPU architectures: 1) The Von Neumann architecture, which uses a single memory for both instructions and data and a single bus. It is simpler but slower. 2) The Harvard architecture, which separates instruction and data memory and uses separate buses. It allows parallel execution and is faster but more complex and expensive. The document recommends the Von Neumann architecture for general processors due to lower cost and space needs, and the Harvard architecture for microcontrollers due to the ability to take advantage of parallelism to compensate for lower speeds.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    17 views20 pages

    Lecture2 - Embedded

    Uploaded by

    Black Hunter
    The document discusses two main CPU architectures: 1) The Von Neumann architecture, which uses a single memory for both instructions and data and a single bus. It is simpler but slower. 2) The Harvard architecture, which separates instruction and data memory and uses separate buses. It allows parallel execution and is faster but more complex and expensive. The document recommends the Von Neumann architecture for general processors due to lower cost and space needs, and the Harvard architecture for microcontrollers due to the ability to take advantage of parallelism to compensate for lower speeds.

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 20

    Introduction to Embedded System

    Lecture 2
    CPU Architecture
    CPU Architectures

    1) Princeton Architecture (Von Neumann Architecture) :


    Between 1945 & 1951 John von Neumann set down the structure, layout,
    interaction, cooperation, realization , implementation, functionality and
    activity for the whole computer as a system. The Von Neumann
    Architecture is characterized by: -
     A memory, arithmetical-logical unit (ALU), control unit, input and output
    device…. etc.
     All parts of a computer are connected together by Bus.
     Memory and Devices are controlled by CPU .
     Data can pass through bus in half duplex mode to and from CPU.
     Memory is split to small cells with the same size. Their ordinal numbers are
    called address numbers.
     Each time CPU fetches a program instruction it may have to perform one or
    more read/write operation “instruction” from/to data memory space. It must
    wait until these subsequent “instruction“ are complete before it can fetch and
    decode the next program instruction.
    CPU Architectures

    Princeton Architecture (Von Neumann Architecture) :


    CPU Architectures

    Princeton Architecture (Von Neumann Architecture) :


    CPU Architectures

    Princeton Architecture (Von Neumann Architecture) :


    CPU Architectures

    2) Harvard Architecture:
    The Harvard Mark II was finished at Harvard University in 1947 . It
    wasn’t so modern as the computer from von Neumann team. But it
    introduced a slightly different architecture. Memory for data was
    separated from the memory for instruction. This concept is known as the
    Harvard Architecture :
     There is no need to make the two memories share characteristics. In particular,
    the word width, timing, implementation technology, and memory
    address structure can differ.
     The CPU can read an instruction and perform a data memory access at the
    same time..
     This speeds up execution time but increases the cost of more hardware
    complexity.
     If, for instance, every instruction run in the CPU requires an access to memory,
    the computer gains nothing for increased CPU speed—a problem referred to as
    being "memory bound".
    CPU Architectures

    Harvard Architecture:
    Harvard Von Neumann

    Used in DSPs and other processors Used in conventional processo


    found in latest embedded systems rs found in PCs and Servers,
    and Mobile communication systems, and embedded systems with
    audio, speech, image processing only control functions.
    systems
    Control unit for two buses is more One bus is simpler for the
    complicated and more expensive control unit design
    The code is executed in parallel The code is executed serially
    and takes more clock cycles

    Avg computation speed is high Avg computation speed is low


    CPU Architectures
    Which is the best ?
    For Processors :
    Von Neumann is used in Processors because, unlike MCUs, processors don’t have
    internal memory or peripherals and the connection to memory is through external
    bus and Von Neumann is suitable because:
     Cost: less buses means less cost.
     Space: we don’t need to waste large space of motherboard.
     Processors mainly deal with only one memory, RAM which holds the
    data and instructions, so only one bus will be suitable and the slow
    access will be substituted by the high speed of the processor and
    using the cash memory.
    For Microcontroller :
    Harvard architecture is used in MCU because:
     Microcontroller contains everything on the chip. RAM, flash, and
    peripherals and due to the small size using multiple buses is not an
    issue.
     Microcontroller speed is not high so multiple buses will help with
    the limited speed of MCU.
    CPU Structure
    The basic elements of the CPU are:
    • ALU
     Arithmetic & Logic Unit
     Responsible for performing logic and arithmetic
    calculations.
    • Floating-Point Unit (FPU)
     performs arithmetic operations on floating
    point numbers.
    • Registers
     Registers are used to store data beside the ALU
     Registers are used to transfer data to/from
    memory
     Registers carry the inputs of ALU, as well
    as, receiving the output of the ALU.
    • Internal CPU Bus
     It is a special bus.
     It is responsible for transferring data between
    registers, ALU, and system memory
    • Control Unit
     It is responsible for organizing the actions of the
    CPU
     It can be thought of as the heart of the CPU
    CPU Structure

    Arithmetic logic unit :


    • ALU is a digital circuit that performs :
     Arithmetic operations :
    o Add, Sub,….etc.
     Logical operations :
    o And, Or, Not,…etc.

    • Operates and stores results in general


    registers
    • Stores operation status in flag/status
    registers
     Carry occurrence, overflow occurrence
    CPU Structure

    FPU ( Floating-Point Unit):


    • The FPU performs arithmetic operations on floating point numbers.
    • An FPU is complicated to design, although the IEEE 754 standard
    helps to answer some of the specific questions about implementation
    • 8086 : First computer to implement IEEE FP
    • Three types of the Floating-Point Data :
     The half-precision floating-point format (16-bit data)
     The single-precision floating-point format (32-bit data)
     The double-precision floating-point format (64-bit data)
    CPU Structure
    IEEE Floating Point Standard 754 (FPS)
    1. Half precision :
     16-bits 15 14 10 9 0
    – 10-bit mantissa
    – 5-bit exponent S Exponent Mantissa (bits 0-22)
    – 1-bit sign

    2. Single precision :
     32-bits
    – 23-bit mantissa 31 30 23 22 0
    – 8-bit exponent S Exponent Mantissa (bits 0-22)
    – 1-bit sign
    3. Double precision :
     64-bits
    – 52-bit mantissa 63 62 52 51 0
    – 11-bit exponent S Exponent Mantissa (bits 0-51)
    – 1-bit sign
    Pipeline :
    • Continuous and parallel streaming of instruction to the CPU.
    • A method of achieving higher execution speed at same clock
    speed.
    Pipeline :
    Pipeline :
    Superscalar vs.
    Super pipeline
    • Simple pipeline system
    performs only one
    pipeline stage per clock
    cycle

    • Super pipelined system is


    capable of performing
    two pipeline stages per
    clock cycle

    • Superscalar performs only


    one pipeline stage per
    clock cycle in each
    parallel pipeline
    MIPS:

    • The number of machine code instructions a computer can process while


    executing a "standard" program is measured in MIPS (Million
    Instructions Per Second). Specifically

    • MIPS is a method of measuring the raw speed of a computer's


    processor and is defined as the number of machine instructions (in
    millions) that a processor can execute in one second.

    𝑃𝑟𝑜𝑐𝑒𝑠𝑠𝑜𝑟 𝐶𝑙𝑜𝑐𝑘 𝐹𝑟𝑒𝑞𝑢𝑒𝑛𝑐𝑦 (𝑀𝐶𝐿𝐾)


    • 𝑀𝐼𝑃𝑆 =
    𝐴𝑣𝑒𝑟𝑎𝑔𝑒 𝐶𝑦𝑐𝑙𝑒𝑠 𝑝𝑒𝑟 𝐼𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 (𝐶𝑃𝐼) ∗ 1,000,000

    = 𝑐𝑦𝑐𝑙𝑒𝑠 / 𝑠𝑒𝑐𝑜𝑛𝑑
    = 𝑚𝑖𝑙𝑙𝑖𝑜𝑛 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛𝑠
    𝑐𝑦𝑐𝑙𝑒𝑠 / 𝑖𝑛𝑠𝑡𝑟𝑢𝑐𝑡𝑖𝑜𝑛 𝑠𝑒𝑐𝑜𝑛𝑑
    MIPS:
    Processor MIPS Clock
    Intel 8086 .33 5 MHz
    Analog Devices ADSP 12.5 12.5 MHz
    -2100
    Microchip PIC16F 5 20 MHz
    Intel Pentium III 2.054 600 MHz
    AMD Athlon 3,561 1.2 GHz
    NEC Earth Simulator 28,293,540 500 MHz
    ( 5120 cores)
    ARM Cortex-M3 125 100 MHz
    Qualcomm Scorpion 2,100 1 GHz
    (Cortex A8)
    Raspberry Pi 2 4,744 1.2 GHz
    Intel Core i7 5960X 238,310 3 GHz
    Pentium 4 Extreme 9,726 3.2 GHz
    Edition
    MIPS:

    You might also like