1J.

21798
6809
MICROCOMPUTER
PROGRAMMING
&
INTERFACING
WITH EXPERIMENTS
BY ANDREW C. STAUGAARD JR.
L
 The Blacksburg Continuing Education™ Series
The Blacksburg Continuing Education Series™ of books provide a Laboratory-or experiment-
oriented approach to electronic topics. Present and forthcoming titles in this series include:

• Basic Business Software

• Circuit Design Programs for the TRS-80
• DBUG: An 8080 Interpretive Debugger
• Design of Active Filters, With Experiments
• Design of Op-Amp Circuits, With Experiments
• Design of Phase-Locked Loop Circuits, With Experiments
• Design of Transistor Circuits, With Experiments
• Design of VMOS Circuits, With Experiments
• 8080/8085 Software Design (2 Volumes)
• 8085A Cookbook
• 555 Timer Applications Sourcebook, With Experiments
• Guide to CMOS Basics, Circuits, & Experiments
• How to Program and Interface the 6800
• Microcomputer-Analog Converter Software and Hardware Interfacing
• Microcomputer Interfacing With the 8255 PPI Chip
• NCR Basic Electronics Course, With Experiments
• NCR Data Communications Concepts
• NCR Data Processing Concepts Course
• NCR EDP Concepts Course
• PET Interfacing
• Programming and Interfacing the 6502, With Experiments
• 6502 Software Design
• 6801, 68701, and 6803 Microcomputer Programming and Interfacing
• 6809 Microcomputer Programming & Interfacing, With Experiments
• TEA: An 8080/8085 Co-Resident Editor/Assembler
• TRS-80 Interfacing (2 Volumes)

In most cases, these books provide both text material and experiments, which permit one to
demonstrate and explore the concepts that are covered in the book. These books remain among
the very few that provide step-by-step instructions concerning how to learn basic electronic con-
cepts, wire actual circuits, test microcomputer interfaces, and program computers based on popu-
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who desires to join the "electronics revolution," with minimum time and effort.

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Bug symbol trademark Nanotran, Inc., Blacksburg, VA 24060

6809 Microcomputer
Programming &
Interfacing, With
Experiments

by
Andrew C. Staugaard, Jr.

Howard W. Sams & Co., Inc.

4300 WEST 62ND ST. INDIANAPOLIS, INDIANA 46268 USA
Copyright © 1981 by Andrew C. Staugaard, Jr.

FIRST EDITION
FIRST PRINTING-1981

All rights reserved. No part of this book shall be

reproduced, stored in a retrieval system, or
transmitted by any means, electronic, mechanical,
photocopying, recording, or otherwise, without
written permission from the publisher. No patent
liability is assumed with respect to the use of the
information contained herein. While every precaution
has been taken in the preparation of this book, the
publisher assumes no responsibility for errors or
omissions. Neither is any liability assumed for
damages resulting from the use of the
information contained herein.

International Standard Book Number: 0-672-21798-6

Library of Congress Catalog Card Number: 81-50567

Printed in the United States of America.

 Preface

Welcome to the world of advanced microprocessors! In the early

seventies we witnessed the dawn of a second industrial revolution
with the introduction of first-generation programmable logic devices.
These "smart" devices on a single piece of sand (silicon chip) were
appropriately called microprocessors. They revolutionized the engi-
neering of many everyday products, from toys and appliances to the
automobile and large computer systems.
In the past few years the microprocessor chip industry has ex-
ploded into a multibillion dollar business. As stated in the June 30,
1980, issue of Newsweek magazine, "The explosion is just beginning.
In 1979, the world market for microelectronics topped $11 billion.
Over the next five years, chip sales are expected to grow by at least
20 percent annually, and the market for microprocessors 'computers
on a chip' will expand by 50 percent each year-even though the
chips themselves and the computing power they represent are diving
in price."
Two large microprocessor application markets have emerged-the
dedicated market and the systems market. The resources of the first-
and second-generation devices, such as the 6800, 8080, and Z-80,
were made to satisfy both market applications. Each market, how-
ever, requires separate microprocessor features for efficient utiliza-
tion of the device. For example, the dedicated market requires a
device which incorporates many functions such as CPU, R/W mem-
ory, ROM/EPROM, timer, serial i/o, etc., onto one chip to minimize
the chip count for such applications as the automobile, appliances,
machine tool control, toys, etc. The systems market, on the other
hand, requires a very powerful software device such that high-level
language programming can be efficiently implemented. Most micro-
processor chip manufacturers have taken these two directions in
their newer-generation chip designs. In the Motorola family the 6801
and 6805 satisfy the dedicated market applications, with the 6809
and 68000 having been designed particularly for the systems market.
The 6809 is a high-performance 8-bit microprocessor. It has many
very powerful software features which are particularly useful for
high-level language (Pascal, FORTRAN, BASIC, COBOL, etc.)
implementation. In fact, as you are about to discover, the 6809 ap-
proaches the performance of many 16-bit devices, such as the 8086,
Z-8000, and 68000, without the inherent overhead costs required to
engineer such a 16-bit system. Flexible 8-bit devices, like the 6809,
will be around for many years to come despite the onslaught of the
16-bitters, since many applications do not require such high per-
formance. In addition, when 16-bit systems do become common, they
This book is meant to be a tutorial type of text for a first exposure
will rely on 8-bit devices to perform many dedicated tasks such as
peripheral control, data acquisition, etc.
to the 6809 or to high-performance microprocessors in general. I am
confident that you will also find it extremely valuable as a "cook-
book" type aid when you are working with the 6809. Since the 6809
is a "souped up" 6800, a basic understanding of the 6800 will be
assumed throughout the text. If a review is needed, you may wish
to consult my How to Program and Interface the 6800, published by
Howard W. Sams & Co., Inc.
A set of objectives is provided in the first part of each chapter,
with review questions and answers provided at the end of each
chapter. There are also numerous examples that illustrate the text.
I encourage you to study the examples in detail, since many of the
important software concepts are demonstrated within the example
programs. I also encourage you to pay particular attention to Chap-
ter 2, "6809 Addressing Modes." You will find that the secret to
understanding the 6809 software concepts is understanding its 19
addressing modes.
Finally, I would like to express my appreciation to Motorola Semi-
conductor Products at Austin, Texas, and Phoenix, Arizona, for their
technical assistance and permission to use their 6809 documentation
in this text.

ANDREW C. STAUGAARD, In.

To my mother and father, who provided me the good home life and
education required to be successful in today's world. And to one of
my best friends, my father in law, Zane Benefiel, whose encourage-
ment in my early professional days led to the completion of this
and two previous manuscripts.
 Contents

CHAPTER 1
FUNDAMENTAL 6809 CONCEPTS AND CHIP STRUCTURE 7
Introduction-Objectives-6809' Evolution and Design Philosophy-
6809 Improvements - 6809 Chip Structure - Review Questions-
Answers

CHAPTER 2
6809 ADDRESSING MODES . 23
Introduction-Objectives-Inherent, Immediate, and Extended Ad-
dressing-Direct Addressing and the Direct Page Register Relative
Addressing-Indexed Addressing-Post Byte-Indirect Addressing-
Register Addressing-Review Questions-Answers

CHAPTER 3
6809 REGISTERS AND DATA MOVEMENT INSTRUCTIONS 51
Introduction - Objectives - 6809 Internal Register Format - Data
Movement Instructions-Review Questions-Answers

CHAPTER 4
ARITHMETIC, LOGIC, AND TEST INSTRUCTIONS 73
Introduction-Objectives-Arithmetic Instructions-Logic Instructions
-Test Instructions-Review Questions-Answers

CHAPTER 5
BRANCH AND MISCELLANEOUS INSTRUCTIONS 93
Introduction - Objectives - Branch Instructions - Miscellaneous In-
structions-Review Questions-Answers
 CHAPTER 6
6809/6809E INPUT AND OUTPUT SIGNALS 115
Introduction-Objectives-6809 Pin-Outs-6809E Pin-Outs-Review
Questions-Answers

CHAPTER 7
6809/6809E INTERFACING AND ApPLICATIONS 140
Introduction-Objectives-A Minimum 6809 System-An Expanded
6809 System-Multiprocessor Systems-Remote Data Acquisition-
The MEK6809D4 Microcomputer Evaluation System

APPENDIX A
6809/6809E INSTRUCTION SET . 163
Operation Notation-Register Notation-Definitions of Executable
Instructions

APPENDIX B
THE 6820/6821 PERIPHERAL INTERFACE ADAPTER (PIA) 192
6821 Functional Description-6820/6821 Pin Assignments-PIA In-
terfacing and Addressing-PIA Initialization and Servicing-Review
Questions-Answers

APPENDIX C
SPECIFICATION SHEETS. 211
MC6809/MC68A09/MC68B09-MC6809E/MC68A09E/MC68B09E
-MC6829 - MC6839 - MC6842 - MEK6809AC - MEK6809D4/
MEK68KPD

APPENDIX D
MC6809 INSTRUCTION SET SUMMARY. . 256

INDEX . 268
 CHAPTER 1

Fundamental 6 809
Concepts and iC'hip Structure

INTRODUCTION
As you will discover in this and subsequent chapters, the 6809 is
one of the most powerful 8-bit processors to come on the market to
date. In conceiving the 6809 the Motorola design engineers wanted
to maintain compatibility with the popular 6800 at some level, yet
"soup up" the 6800 architecture and instruction set to approach the
performance of a 16-bit processor, such as the 68000 or Z-8000. From
user surveys Motorola concluded that many customers desired such
performance from an 8-bit, 40-pin device. It was found that many
users did not want to pay the price for conversion to a 16-bit device
with up to 64 pins if a high-performance 8-bit device were available.
Therefore, the 6809 was designed to approach 16-bit performance at
minimum cost to the user.
In this chapter we begin by discussing the 6809 evolution and
design philosophy. You will see that the 6809 has been designed
primarily for the systems market, where high-level language imple-
mentation is common. Throughout the discussion, comparisons will
be made between the 6809, 6800, and other competitive processors.
In addition, as an introduction to subsequent chapters, this chapter
will summarize the 6809's architecture, software, and hardware. It
is important that you understand what improvements have been
made in the 6809 over the 6800 since this will enable you to better
understand the material to follow.

OBJECTIVES
At the end of this chapter you will be able to do the following:

7
 • Explain the evolution of the 6800 family.
• Understand the design philosophy that created the 6809.
• State the differences between the 6809, 68A09, 68B09, and
6809E.
• List the additional registers present in the 6809 that do not exist
in the 6800.
• Describe the two additional condition code Rags available in the
6809.
• Define indirect addressing.
• Compare 6809 branching to 6800 branching.
• Explain what is meant by "memory paging" and how this is
accomplished with the 6809.
• Describe the fundamental hardware differences between the
6809 and 6800.
• Explain the difference between a standard interrupt request and
a fast interrupt request.

6809 EVOLUTION AND DESIGN PHILOSOPHY

As stated in the introduction to this chapter the 6809 was designed
to upgrade or "soup up" the 6800 to be superior to any 8-bit micro-
processor. Also, :Motorola wanted to capitalize on their customers'
familiarity with the 6800 so that exposure to the 6809 would not
create severe learning problems for those 6800 users. Therefore this
design philosophy dictates that the fundamental 6800 architecture
be used as a basis for the 6809 architecture and that software com-
patibility be available at some level. As you will discover in Chapter
3 this compatibility exists at the source code (mnemonic) level and
not the object code (op-code) level. You will also discover that the
6809 does not contain dozens of new instructions. However, it uses
over three times as many addressing modes as the 6800 to provide
more efficient utilization of the existing instructions. The power of
a processor is not a function of the number of unique instructions
available in its instruction set. The real power of a processor lies in
how many different ways a given instruction can operate on the same
data and also how the given instruction set can operate on different
data in the same manner. This flexible instruction power is provided
by the different addressing modes available to the fundamental in-
struction set. The 6809 uses its 19 addressing modes in conjunction
with 59 fundamental instructions to provide a total of 1464 unique
operations. Motorola believes that the 6809 contains the most power-
ful addressing modes available in any microprocessor to date.
Since the 6809 is primarily designed for the systems market, pro-
gram position independence, program re-entrancy, and easy imple-
mentation of block-structured high-level languages (such as Pascal)

8
were also prime design considerations. These terms have the follow-
ing meanings:
• program position independence-that quality of a program to
execute properly when placed anywhere within the memory
address map. Thus the program is independent of its position
within the memory map.
• program re-entrancy-that quality of a program which allows a
subroutine to be shared by several tasks concurrently, without
destroying the return addresses by nesting routines.
\Vith position independence, programs can be loaded from a mass
storage disc and located anywhere within R/vV memory without
requiring the use of a relocating loader routine. In addition, position
independence will allow ROM programs to be written for general
distribution. The user can assign any arbitrary set of addresses to
the RO~1 since the program execution is "independent" of its posi-
tion within the memory map. This wiII eliminate the necessity for
full ROJ'.1 address decoding and will also allow the user to locate
the ROM such that it will not interfere with other software. As you
will see shortly, the advanced 6809 architecture also facilitates the
use of modular programming. Such programming will allow the sys-
tem software designer to divide a project up into modular programs
which can be designed and tested independently before being in-
corporated into the final system design. This same architecture al-
lows programs to be structured and interrupted in any part of the
address map and still execute properly on return, thus satisfying the
program re-entrancy design goaL In addition, high-level block-
structured languages, such as Pascal, BASIC, FORTRAN, and
COBOL, can be compiled into more efficient and faster-running
machine code than was possible \vith earlier processors.
The 6800 family evolution scheme is shown in Fig. 1-1. Note the
position of the 6809. As far as central processing unit (CPU) per-
formance is concerned the 6809 is the most advanced processor in
the :Motorola 8-bit family. However, the 6809, by itself, is a micro-
processor and not a microcomputer. It requires external Rl'iV mem-
ory and ROM to function as a microcomputer. Therefore a minimum
6809 system would consist of three chips. Recall from our discussion
in the Preface that microprocessor/microcomputer applications take
two directions: small, dedicated applications and systems applica-
tions. In the 8-bit Motorola family the 6809 satisfies the needs of the
latter, while the 6801, 6802, 6803, and 6805 were designed for the
dedicated applications. These four devices all contain various
amounts of R/W memory, ROM, and parallel/serial i/o capabilities.
They are therefore more advanced as far as chip integration is con-
cerned since some or all of these capabilities are integrated into the

9
 1-CHIP MIN SYS -

A CONSISTENT, COMPATIBLE FAMILY

en
w
U
z 2-CHIP
« MIN SYS-
>
c
«
z
o
i=
«
a:
C)
w
I-
Z
5-CHIP t
MUCH MORE
MIN SYS-
CAPABLE
1.0-J.l.s
STANDARD t t t INST
PERFORMANCE 2.0-J.l.s 1.3-J.l.s 1.0-J.l.s
INST INST INST
PERFORMANCE ADVANCES

Fig. 1-1. M6800 family evolution.

same chip, along with the CPU. For example, the 6801 contains an
enhanced 6800 CPU, R/W memory, ROM, timer, parallel interfacing
ports, and a serial port, all on one 40-pin chip. Hence, we say that
the 6801 is a "single-chip" microcomputer. o The 6809, however, is a
far more advanced processor, approaching 16-bit performance.
As you will see in Chapter 6, the standard 6809 does contain an
on-chip clock/ oscillator and therefore only requires an external crys-
tal to provide the clock signal. The standard 6809 operates at 1 MHz.
However, it is also available in 1.5-MHz and 2.0-MHz versions: the
68A09 and 68B09, respectively. In addition, there is an off-chip clock
version of the 6809 available, the 6809E.
Now let's compare the performance of the 6809 to the 6800 and
some other well-known processors. Compared to the 6800, the 6809
boasts the following performance:
• 72 percent decrease in the number of instructions required for a
program compared to similar 6800 programs.
• 58 percent decrease in the required program memory compared
to 6800 programs.
• 167 percent increase in 6809 processor throughput compared to
6800 throughput.

o For a detailed discussion of the 6801/68701 and 6803 consult Staugaard,

A.C. 6801/68701 and 6803 Microcomputer Programming and Interfacing, pub-
lished by Howard W. Sams & Co., Inc., Indianapolis.

10
Motorola claims that these statistics allow the user to achieve 2.5 to
5 times the performance from a 6809 system compared with a similar
6800-based system. Of course, the exact amount of increased per-
formance depends on how efficiently the increased capabilities of the
6809 are utilized and on the specific application.
Comparisons of the 6809 to the 6800 and other processors are
summarized in Fig. 1-2 and in Tables 1-1 through 1-3. Note, espe-
cially from Fig. 1-2, that the 6809 approaches 16-bit performance.
The comparison values in these tables and Fig. 1-2 were supplied
by Motorola and thus tend to illustrate the better aspects of the 6809
over the other processors.

6809 IMPROVEMENTS
The increased performance of the 6809 over other 8-bit processors
is made possible by specific improvements in architecture, software,
and hardware. Each of the following improvements over the 6800
is discussed in detail in subsequent chapters; however, we will sum-
marize them here.

Architectural Improvements
Compared with the 6800 architecture the 6809 adds an 8-bit regis-
ter and three 16-bit registers as shown in Fig. 1-3. The additional
8-bit register is the direct page register, which will allow you to use
the direct addressing mode anywhere within the 6809 memory map.
(Recall that direct addressing is limited to the first 256 bytes of
memory with the 6800.) The three additional 16-bit registers include
a 16-bit accumulator, index register, and stack pointer. The addi-
tional accumulator is referred to as accumulator D and is simply the
concatenation of the two 8-bit accumulators, A and B. The additional
index register is called the Y index register (Y) and the additional
stack pointer is referred to as the user stack pointer (U). The two
index registers, X and Y, will also function as pointers and the two
stack pointers (S and U) can be used for indexing.
In addition, you will note from Fig. 1-3 that all 8 bits of the con-
dition code register (CC) are being used in the 6809. Recall that
only the first 6 bits are utilized in the 6800. The functions of the first
6 CC bits (C, V, Z, N, I, H) in the 6809 are identical with those of
the 6800. The two additional bits (F and E) are used in conjunction
with the 6809's interrupts. The use of these two additional bits will
be discussed in detail in subsequent chapters.
These architectural improvements along with the 6809's powerful
addressing modes speed processor throughput, since less data move-
ment is required between the internal registers and memory, and

11
..
N

Table 1·1. Relative Processor Execution·Time Comparisons for Eight Software Operations
Double Vector Vector
Shift Addition Addition Average
I/O Character Computed Right 16·Blt 8·Blt 16 x 16·Blt Move Block Execution
Handler Search GoTo 5 Bits Elements Elements Multiplication (64 Bytes) Time
6809 2.0 MHz 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0
1.5 MHz 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3 1.3
1.0 MHz 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0 2.0
Z-80 4.0 MHz 1.4 0.8 2.1 2.7 1.6 1.8 3.3 1.0 1.8
2.5 MHz 2.2 1.2 3.4 4.4 2.6 2.9 5.2 1.6 2.9
9900 3.0 MHz 2.6 2.3 2.8 1.5 1.7 3.0 0.5 1.6 2.0
6800 2.0 MHz 0.9 1.4 1.9 1.3 3.1 2.8 5.0 3.3 2.4
1.5 MHz 1.2 1.9 2.5 1.7 4.1 3.7 6.7 4.3 3.3
1.0 MHz 1.8 2.8 3.7 2.5 6.1 5.5 10 6.5 4.9
8080 3.0 MHz 1.9 1.8 2.8 6.1 2.3 2.7 9.6 2.4 3.7
8085 2.0 MHz 2.8 2.6 4.2 9.1 3.4 4.1 14.3 3.7 5.5
 Table 1-2. Actual Processor Execution-Time Comparisons for Eight Software Operations
Double Vector Vector
Shift Addition Addition
I/O Character Computed Right 16-Bit 8·Bit 16 x 16-Blt Move Block
Handler Search Go To 5 Bits Elements Elements Multiplication (64 Bytes)
6809 2.0 MHz 28 287.5 34.5 15 325 180 82 344.5
1.5 MHz 37.3 383 46 20 433 240 109.3 459.3
1.0 MHz 56 575 69 30 650 360 164 689
Z·80 4.0 MHz 38.3 220.5 73.3 41 518 323 267 342
2.5 MHz 61.3 352.8 117.2 65.6 828.8 516.8 427.2 547.6
9900 3.0 MHz 72 661 98 22 537 537 42 537
6800 2.0 MHz 24.5 404 64.5 19 993.5 498.5 409.5 1123.5
1.5 MHz 32.7 539 86 25.3 1325 665 546 1498
1.0 MHz 49 808 129 38 1987 997 819 2247
8080 3.0 MHz 52.7 506.7 96.7 91.3 732 492 784 841
8085 2.0 MHz 79 760 145 137 1098 738 1176 1262

...w
 Table 1·3. Summarized Processor Performance Comparisons
Performance Criteria MC6809 Z·80A MC6800 8085
Number of Instructions 1.0* 1.56 1.72 2.30
Number of Bytes 1.0 1.31 1.58 1.80
Number of Microseconds 1.0 1.80 2.40 2.20
(2 MHz) (4 MHz) (2 MHz) (5 MHz)
'Normalized to 1.00 for the MC6809 - poorer performance has higher numbers.

they also aid software development since many of the internal regis-
ters can be made to perform different functions at different times.
Software Improvements
Improvements in the 6809's architecture have allowed the Moto-
rola designers to make many significant software improvements over

15 MC68000 (16 BITS)

10 Z·8000 (16 BITS)

8086 (16 BITS)
9900 (1 2L) MIL VERSION (16 BITS)

5 MC6809 (2 MHz; 8 BITS)

Fig. 1-2. Relative processor
execution-time
comparisons.
4

3
2.7 Z·80A (4 MHz; 8 BITS)
2.45 9900 (3 MHz; 16 BITS) 8085 (5 MHz; 8 BITS)

2 MC68BOO (2 MHz; 8 BITS)

Z·80 (2.5 MHz; 8 BITS)

MC6800 (1 MHz; 8 BITS)

14
 B O a - B I T ACCUMULATOR A AND 8-BIT
~ _ _-':"':'-_ _--L______ ACCUMULATOR B OR 16-BIT
'-.,;..... 0 DOUBLE ACCUMULATOR D

L...- 0....J Y INDEX POINTER REGISTER

L...- ° ....J U INDEx/STACK POINTER REGISTER

L...- ° ....J S INDEx/STACK POINTER REGISTER

DP ° DIRECT PAGE REGISTER

cc ° CONDITION CODE REGISTER

FHINZVC

ENTIRE STATE SAVE ~ CARRY (FROM BIT 7)

FAST INTERRUPT MASK _ - OVERFLOW
HALF CARRY (FROM BIT 3) ZERO
INTERRUPT MASK NEGATIVE

Fig. 1·3. 6809 internal registers.

the 6800. In fact, the 6809 has been termed «the programmer's dream
machine." Prior to firm definition of the 6809 instruction set Motorola
conducted a survey of 6800 users to determine: (1) if a 16-bit archi-
tecture was more desirable than an 8-bit architecture and (2) should
6809 compatibility with the 6800 occur at the object code level or
source code level? The survey results indicated that most of the
6800 users felt that an 8-bit architecture was adequate for their future
applications. They did not want to pay the price for a new 16-bit
device if an 8-bit device could be designed to perform common 16-
bit operations, such as load, store, add, subtract, compare, and multi-
ply. As you will discover in Chapter 3, the inclusion of the 16-bit
accumulator and associated instructions will allow such 16-bit opera-
tions to be performed internally. In answer to the second survey
question, almost all of the responses indicated that source code com-
patibility would be adequate, mainly because they did not foresee
using 6800 ROMs in future 6809 systems. Source code compatibility
meant that users could take full advantage of their familiarity with
the 6800 mnemonic code for assembly language programming and
it also allowed the 6809 designers to completely remap or reassign
the 6800 op codes to produce more efficient and faster running 6809
programs. Also, source code compatibility would allow any 6800
programs to be processed through a 6809 assembler to produce 6809
code. Therefore, you will see a familiar mnemonic code in Chapters
3,4, and 5; however, most of the corresponding op codes are differ-
ent from those of the 6800.

15
 As mentioned earlier, the 6809 adds many new and powerful ad-
dressing modes. For example, the indexed mode of addressing can
use the four 16-bit indexible registers (X, Y, U, and S) to point to
the address of an operand or to the address of the address of an
operand. The latter is referred to as iruIirect addressing. These regis-
ters can also be incremented and decremented automatically or
under program control. The 6809 can even use the program counter
to access operands or operand addresses. Furthermore, with the use
of the direct page register, you can access any part of the 6809 mem-
ory map using direct addressing. You can also branch to any part of
the program using relative addressing. Recall that with the 6800, you
were limited to a plus 127 10 and minus 128 10 branch range within the
program, since the relative address offset is only 1 byte. However,
the 6809 allows for a 2-byte relative address offset and thus permits
branching anywhere within the 64K memory map (long branch).
This allows position-independent programs to be written for the
6809. We will discuss the idea of position independence in more
detail when discussing relative addressing.
Other software features of the 6809 include:

• An 8 X 8 unsigned multiply instruction which generates a 16-bit

result.
• 2-byte instructions which will push or pull any or all registers
onto or from either stack (U or S).
• 16-bit add, subtract, load, store, and compare instructions which
utilize the 16-bit accumulator (D).
• Instructions which permit you to add any of the accumulators
(A, B, or D) to any of the index registers and stack pointers
(X, Y, S, or U).
• Instructions which permit you to perform exchanges and trans-
fers between any two like-size CPU registers.

Hardware Improvements
Besides the architectural and software improvements of the 6809
over the 6800, many hardware improvements were also made. Most
of these improvements involve the 6809's interrupts, control signals,
and associated control lines. We will summarize these new hardware
features here; however, a complete discussion of the 6809 pin-outs
and associated chip operation is provided in Chapter 6.
Like the 6800, the 6809 is a 40-pin device available in both a plas-
tic (P-suffix) and ceramic (L-suffix) package. A bus and control
signal diagram for the 6809 is shown in Fig. 1-4. The most obvious
change to the chip hardware is the inclusion of an on-chip clock/
oscillator for the standard 6809 package. (Recall that the 6809E is
an off-chip clock version of the 6809.) The 6809 on-chip clock re-

16
 +5V GND

BUS AVAILABLE
DATA BUS

BUS STATUS

FIRO
16 ADDRESS BUS
NON-MASKABLE INT
MC6809
RESET

DMA REO

MEMORY READY

XTAL out

EXTAL E
°out 1
CONTROL
BUS

IRO READ/WRITE

Fig. 1-4. 6809 bus and control signals.

quires only the addition of an external crystal (EXTAL and XTAL) to

establish the internal clock frequency. The crystal frequency must
be four times (4x) the desired internal clock frequency. Therefore,
to achieve a I-MHz operation, a 4-MHz crystal must be used. This
has been done to create a more cost-effective system since an inex-
pensive 3.58-MHz tv color-burst crystal can be used, resulting in a
0.895-MHz clock frequency, without seriously affecting the chip
performance.
The ~ontrol features of the 6809 include a fast interrupt re-
quest (FIRQ), bus status CBS), quadrature clock (Q), memory
ready (MRDY), and direct memory access request (DMA REQ)
control signals. You will use the fast interrupt request (FIRQ) line
when it is known that the interrupt routine will use existing register
data. Thus, with the fast interrupt, all the registers are not stored
unnecessarily requiring extra time; only the program counter and
condition code register are saved. However, as you will discover in
Chapter 6, you can also use FIRQ to initiate a standard interrupt
request where the contents of all the internal registers are saved.

17
The new bus status (BS) line is used in conjunction with the bus
available (BA) line to indicate bus status and provide an interrupt
acknowledge. The quadrature clock (Q) is a clock signal which
leads the enable clock signal (E) by one-quarter cycle (90°). En-
able (E) is the same as the 6800's ep2 clock signal. Valid addresses
are available from the 6809 on the leading edge of Q, with data
being latched on the trailing edge of E. These two external clock
signals provide four effective system timing edges for interfacing
purposes. The memory ready line (MRDY) is for interfacing with
slow memories. This input control signal. effectively stretches the E
pulse to extend data-access time. Finally, the direct memory access
request line (DMA REQ) is an input control line which provides a
method for suspending processor execution and freeing the external
buses for other purposes, such as direct memory access by a periphe-
ral device or dynamic memory refresh.
A bus and control signal diagram for the 6809E is shown in Fig.
1-5. Since the 6809E does not require an external crystal connection,
two additional control signals are added. They are: Busy, and Last
Instruction Cycle (LIC). Since these two control signals are avail-

DMA/BREO
Rm
HALT
BA
BS

XTAL
EXTAL
MRDY
E
Q

Fig. 1-6. 6809 chip structure.

18
 +5V GND

BUS AVAILABLE
DATA BUS
HALT

BUS STATUS

16 ADDRESS BUS
NON-MASKABLE INT
MC6809E

TSC VMA

L1C
CONTROL
BUS
BUSY

READ/WRITE

Fig. 1-5. 6809E bus and control signals.

able, the 6809E is ideally suited for multiprocessor applications.

Busy is an output control line which indicates that the 6809E is ac-
cessing memory and the last instruction cycle (LIe) signal alerts
external devices to the fact that the 6809E is executing the last cycle
of an instruction.
If you are familiar with the 6800, note that the standard 6809 does
not include two control lines that are available on the 6800. They are
the valid memory address (VMA) and three-state control (TSe)
signals. Recall that VMA was required in external device interfacing
to provide proper device selection. Therefore, the elimination of this
signal eliminates the gating required to use it for external device
selection. Instead of using VMA to indicate a valid address exists
on the address bus, the 6809 places FFFF on the address bus during
any clock cycle when it is not using the bus structure. The three-state
control line (TSe) is simply replaced by the DMA REQ line on the
6809. The 6809E, however, uses both VMA and TSe (Fig. 1-5).
Finally, there is one other subtle hardware difference between the
6800 and 6809. Both the 6809 and 6809E contain a Schmitt trigger
input on the RESET interrupt such that a simple RC circuit is all
that is required to reset the processor during "power up." This is not
included in the 6800.

19
 6809 CHIP STRUCTURE
The 6809 chip structure is shown in Fig. 1-6 in summary to the
discussion just completed. You should now have a basic understand-
ing of each functional region and the associated control features of
the 6809 and 6809E. In addition, you should now be aware of the
architectural, software, and hardware improvements of the 6809 and
6809E over the 6800. In the chapters that follow we will discuss each
of these new features in detail, beginning with the 6809's addressing
modes and its instruction set.

REVIEW QUESTIONS
1. Compatibility between the 6800 and 6809 instruction set exists at what
level?

2. How many basic instructions are contained in the 6809 instruction set?

3. How many different addressing modes does the 6809 utilize?

4. The 6809 was designed primarily for the '--_~__ market.

5. Two prime design considerations for the 6809 are: ~_~_ and _

6. The most advanced processor in the Motorola 8-bit family is the _

7. The most advanced microcomputer in the Motorola 8-bit family is the

8. What is the fundamental difference between the 6809 and 6809E?

9. List the additional registers present in the 6809 architecture which do not
exist in the 6800.

10. The two new condition code Hags and their bit positions in the CC

register are: ~_~ __ and _

n. Which of the internal 6809 registers are indexible and can therefore be
used with the index mode of addressing?
12. When an instruction points to an address of the address of an operand,

20
 this is called ____ addressing.
13. What is the branching range of the 6809 and how does this compare to
the 6800?
14. What is the difference in the direct addressing mode for the 6809 versus
the 6800?

15. A 3.2-MHz crystal would produce a _~_-·-MHz 6809 clock frequency.

16. With the 6809's fast interrupt request (FIRQ) only the ,_ _~~_ and

_~__ registers are stacked.

17. The quadrature clock signal (Q) is the same frequency as the enable
clock signal (E); however, Q leads E by what amount?
18. When a valid memory address is not present from the 6809, what is the
status of the address bus?

19. The 6809 replaces the 6800 three-state control line (TSC) with >-- _

20. The two extra control lines available on the 6809E which are not available

on the 6809 are: _ and ~_

ANSWERS
1. Source code (mnemonic)
2.59
3. 19
4. Systems
5. Position-independent code and 6800 compatibility
6. 6809
7. 6801
8. The 6809E is an off-chip clock version of the 6809.
9. Accumulator D (D)
Direct page register (DP)
Y index register (Y)
User stack pointer (U)
10. F (bit 6)
E (bit 7)
11. All the index registers and stack pointers (X, Y, 5, and U)
12. Indirect
13. The 6809 can branch anywhere within the 64K memory map using long
relative addressing where the 6800 is limited to a plus 12710 and minus 12&0
byte branching range.

21
14. With the direct addressing mode the 6809 can access any part of the 64K
memory map using the direct page register ( DP), where the 6800 is
limited to the first 256 bytes of memory (page 0).
15. 0.8 MHz
16. Program counter (PC) and condition code (CC)
17. One-quarter cycle (90 0
)

18. The 6809 address is FFFF 16 during any clock signal when it is not using
the bus structure.
19. Direct memory access request (DMA REQ)
20. Busy and last instruction cycle (LIC)

22
 CHAPTER 2

6809 Addressing Modes

INTRODUCTION
You are about to see what makes the 6809 a super microprocessor.
As was mentioned earlier, it is not the mere number of instructions
in an instruction set that makes one processor more powerful than
another but a more important consideration: how many different
ways the processor can utilize the fundamental instructions available
to it. Instructions can access and operate on data in different ways
by using different addressing modes. The 6809 has 59 instructions
which utilize ten fundamental addressing modes, bringing the total
number of unique operations to 1464. The ten fundamental address-
ing modes available to the 6809 are: inherent (implied), immediate,
direct, extended, branch relative, indexed, extended indirect, pro-
gram counter relative, indexed indirect, and register.
In addition, variations of these ten fundamental modes actually
bring the total number of unique addressing modes to 19. For exam-
ple, one of the most powerful addressing modes, indexed addressing,
has five options: zero offset, constant offset (5-,8-, or 16-bit), accu-
mulator offset (A, B, or D) and auto-increment or auto-decrement
(by 1 or 2). All of these options can access data indirectly using in-
dexed indirect addressing. Indirect addressing means to address a
memory location that contains the address of the operand rather than
the operand itself. Thus, the instruction accesses the address of the
operand, which in turn accesses the operand. Indirect operations are
also available with the extended and program counter relative ad-
dressing modes.
As with the 6800, relative addressing is used with branch opera-
tions. With the 6809, however, relative addressing can also be used

23
to access and operate on memory data. It is also available in two
versions: short relative (8-bit oHset) and long relative (16-bit oH-
set). Thus 6809 programs can be written with complete position
independence.
Finally, register addressing will allow you to transfer to, or ex-
change, data between any two like-size registers within the 6809's
architecture.
You might be wondering how an 8-bit machine can perform so
many unique operations and, given an instruction, how do you
specify which addressing mode is to be used? The answer is found
in a post byte. A post byte is used with indexed, indexed indirect,
extended indirect, program counter relative, and register addressing.
The post byte follows the instruction op code in the instruction state-
ment. It is used to specify the addressing mode and which internal
register is to be used in the operation. With register addressing it is
used to specify which two like-size registers are to be used in the
transfer or exchange of data.
It is very important that you understand how to use the post byte
and, for that matter, all the concepts presented in this chapter such
that you can take full advantage of all of the 6809's capabilities.
Once a full understanding of the addressing modes is achieved, you
will be ready to apply these modes to the 6809 instruction set pre-
sented in Chapters 3, 4, and 5.

OBJECTIVES
At the end of this chapter you will be able to do the following:

• State the diHerence between direct addressing for the 6809

versus direct addressing for the 6800.
• Explain the role of the direct page register in direct addressing
for the 6809.
• List the ten fundamental 6809 addressing modes.
• Explain how to use program counter relative addressing.
• Describe the four basic forms of indexed addressing.
• Understand how to use a post byte for indexed, program counter
relative, extended, and register addressing.
• Interpret the meaning of a given post byte.
• Determine the required post byte for a given addressing situa-
tion.
• Define indirect addressing.
• Determine the eHective operand address for instructions using
indirect addressing.
• Understand assembly language symbols used for the various
6809 addressing modes.

24
 INHERENT, IMMEDIATE, AND EXTENDED ADDRESSING
Inherent Addressing
I nherent addressing, also referred to as implied addressing, is the
simplest type of addressing since it only involves I-byte instructions.
Instructions involving the accumulators, such as increment, decre-
ment, clear, shift (left or right), complement, etc., fall into this cate-
gory. This type of addressing is also sometimes referred to as accu-
mulator addressing when the instruction involves an operation on
one of the accumulators. The format for inherent addressing is the
same as that for the 6800 and most of the same instructions are in-
volved.

Immediate Addressing (#)

As with the 6800 the 6809 uses immediate addressing when the
operand immediately follows the instruction op code. Therefore this
type of addressing includes the data operand within the instruction
statement. Operations involving the accumulators and index regis-
ters, such as load, add, subtract, AND, OR, compare, etc., can all utilize
immediate addressing. When the immediate operation involves ac-
cumulator A or B, the instruction will be 2 bytes: a I-byte instruc-
tion op code followed by the I-byte operand. When the operation
involves a I6-bit register, accumulator D or one of the index registers
(X, Y, 5, or U), the instruction will be 3 or 4 bytes: a 1- or 2- byte
instruction op code (depending upon the particular instruction, refer
to Chapter 3) followed by a 2-byte operand. With the 6800, op codes
were never more than 1 byte in length; however, with the 6809
you will frequently see 2-byte instruction op codes, especially where
the I6-bit registers are involved. This is necessitated since, with the
6809, there are more than 256 unique executable instructions. Also,
a 2-byte operand is required when a 16-bit register is involved. The
immediate addressing format is shown in Fig. 2-IA.
Extended Addressing ($$)
Extended addressing is used to access memory. Here, the memory
address of the data operand follows the instruction op code. Ex-
tended addressing is used to access the full 64K memory address

INSTRUCTION OP CODE INSTRUCTION OP CODE

-------------------------- --------------------------
(1 OR 2 BYTES) (1 OR 2 BYTES)
DATA OPERAND HI ADDRESS BYTE
--------------------------
(1 OR 2 BYTES) LO ADDRESS BYTE

(A) Immediate addressing. (B) Extended addressing.

Fig. 2-1. Immediate and extended addressing formats.

25
map, and therefore the address is 2 bytes in length: a HI address
byte followed by a LO address byte. The instruction op code will be
1 or 2 bytes, depending on the particular instruction involved. There-
fore 6809 instructions using extended addressing will be a total of
3 or 4 bytes in length. The instruction format for extended address-
ing is shown in Fig. 2-1B. Another form of extended addressing, ex-
tended indirect, will be discussed later in this chapter.

DIRECT ADDRESSING AND THE

DIRECT PAGE REGISTER ($)
In the 6800, direct addressing was used to access operands that
were stored in the first 256 bytes of memory (addresses OOOO-OOFF).
Recall that when accessing this area of memory it was advantageous
to use direct addressing over extended addressing, since fewer in-
struction bytes are used. For example, consider the following in-
struction codes:

1. LOA $ 2. LOA $$
C7 00
C7

These instructions accomplish the same function, i.e., load accumula-

tor A with the contents of memory address C7. However, instruction
No.1 uses direct addressing while instruction No.2 uses extended
addressing. The obvious advantage is that direct addressing requires
only 2 instruction bytes while extended addressing requires 3. In
addition, more MPU cycles would be required to execute the instruc-
tion using extended addressing. Therefore, direct addressing is used
whenever operands are located in low memory. The drawback to
the use of direct addressing in the 6800 is that you are limited to
addressing the first 256 bytes of memory (OO-FF) in this way. An
operand residing in higher memory would require the use of ex-
tended addressing. However, the 6809 design engineers have elimi-
nated this problem by including a direct page register (DPR) as
part of the 6809's architecture. The direct page register essentially
forms the most significant byte of the effective address. The least
significant address byte is part of the instruction. When in the direct
addressing mode the 6809 simply looks to the DPR for the most sig-
nificant address byte and relies on the instruction to supply the least
significant address byte. Therefore, to access the data located at
address OOC7, as in the previous example, the direct page register
would contain 00 (all zeros) and the 2-byte instruction

LOA $
C7

26
would be used. If, however, the DPR contained 01, the same instruc-
tion would access address 01C7. This eliminates the need to use ex-
tended addressing when you are accessing addresses above OOFF.
Some terminology is useful here. When the DPR contains 00, we
say it is accessing page zero; when the DPR contains 01, it is access-
ing page 1, and so on, up to page 255 (FF). Note that the DPR can
be used to access 256 pages (including page zero). Each page con-
tains 256 address bytes. In other words, the DPR can be used to
"page" through the entire 6809 address map, since 256 pages with
256 address bytes per page equals 64K address bytes, or the total
6809 map. A common application of the DPR is in high-level lan-
guages where global variables are accessed frequently. A global
variable is a variable whose value is accessible throughout an entire
program, in contrast to a local variable, whose value is accessible
only in the program block (or subroutine) in which it is defined. In
a subroutine the DPR can be used to "point" to a page containing
the global variables, with the stack containing local variables. No
problems arise as long as the language compiler keeps track of the
DPR value. The DPR can also be used for multitasking operations.
Multitasking is when several separate but interrelated tasks operate
within a single program. In this application each task will be allo-
cated a different page by the main program and accessed via the
DPR. When writing programs you must be very careful in using the
DPR since it is very easy to lose track of its value. But, when the
DPR is used properly, you can generate very efficient, byte-saving
programs.
After the 6809 is reset, the DPR contains all zeros (page zero) and
the 6809 direct addressing mode will perform just as it would in the
6800. As you will see in Chapter 3 the DPR contents can then be
easily modified to point to any page within the 6809's memory map.

RELATIVE ADDRESSING
There are two types of relative addressing available to the 6809.
They are branch relative and program counter relative. By using
these relative addressing modes you will be able to write complete
position-independent programs for the 6809. A discussion of branch
relative addressing will be provided first since it is very similar to
the branching operation used in the 6800. Then a complete discus-
sion of program counter relative addressing will be provided.

Branch Relative Addressing

Recall that the 6800 uses relative addressing for its branch instruc-
tions. The branch instruction op code is followed by a I-byte twos
complement (signed) relative address offset. Upon execution of the

27
branch the offset is added to the program counter's contents to form
the branch destination address.
Example 2-1: Determining Forward Branch Destinations
Given a branch instruction located at address 002B with a relative
address offset of 6F, determine the branch destination.
Since the branch instruction is 2 bytes (op code followed by the
relative address offset), the program counter contains 002B+2 =
002D. The destination equals the program counter contents plus the
offset, or 002D+006F = 009C.

Example 2-2: Determining Backward Branch Destinations

Consider a branch instruction located at address 002B as in the pre-
vious example. The relative address offset, however, is now F7.
Determine the branch destination.
The program counter contents are 002D (refer to Example 2-1).
Since the most signi£cant bit of the twos complement offset is a logic
1, it is negative and the 6809 will branch backward. To obtain the
destination the twos-complement offset is added to the program
counter's contents. Therefore the destination address is 002D+FFF7
= 0024. Here the two most signi£cant hex digits (FF) of the offset
are implied since the offset is negative.
Refer to Table 2-1 for determining the 8-bit relative address offset
required to branch to a given destination.
A serious limitation arises with this type of branching: since the
signed offset is only 1 byte, with the most signi£cant bit of that byte
used to determine branching direction (forward or backward), you
are limited to a range of -128 10 to +127 10 branching addresses, with
respect to the branch operation. This is called short branching. To
branch beyond this range with the 6800 would require branching to
a branch or the use of a jump instruction. But, by using a jump,
position independence is lost, which is a serious consequence, espe-
cially for high-level language programming, since an absolute ad-
dress location is speci£ed. However, if the relative address offset
were 2 bytes, branches within a -32,768 10 to 32,76710 range could be
accomplished, thus allowing branching anywhere within the entire
memory map while maintaining position independence throughout
the program. This has been done with the 6809 while maintaining
the short-branch instructions for byte efficiency when only short
branches are required.
The 6809 adds a series of long-branch instructions which use a
2-byte signed relative address offset. The 6809 long-branch instruc-
tions contain a 2-byte op code followed by a 2-byte signed offset.
Therefore, long-branch instructions are 4 bytes in length as com-
pared with the 2-byte short-branch instructions.

28
 Table 2-1.6809 Short-Branch Calculator Table

MSH·B F E 0 C B A 9 8
LSH·B LSH·F
16 32 48 64 80 96 112 0
F 1 17 33 49 65 81 97 113 1
E 2 18 34 50 66 82 98 114 2
0 3 19 35 51 67 83 99 115 3
C 4 20 36 52 68 84 100 116 4
B 5 21 37 53 69 85 101 117 5
A 6 22 38 54 70 86 102 118 6
9 7 23 39 55 71 87 103 119 7
8 8 24 40 56 72 88 104 120 8
7 9 25 41 57 73 89 105 121 9
6 10 26 42 58 74 90 106 122 A
5 11 27 43 59 75 91 107 123 B
4 12 28 44 60 76 92 108 124 C
3 13 29 45 61 77 93 109 125 0
2 14 30 46 62 78 94 110 126 E
1 15 31 47 63 79 95 111 127 F
0 16 32 48 64 80 96 112
0 1 2 3 4 5 6 7 MSH·F
1. Count the number of bytes (in decimal) from the instruction following the branch to the branch target instruction.
2. Find this number inside the table.
3. Read this hexadecimal equivalent.
a. Top and left for branching backward.
b. Bottom and right for branching forward.
Examples: Back 15 10 bytes F116' Forward 77 10 bytes =4016' BacK 107 10 bytes =9516'
4. Key:
MSH·B = Most significant hex-backward
LSH-B = Least significant hex-backward
MSH-F = Most significant hex-forward
LSH·F = Least significant hex-forward

Courtesy Mr. Ray Boaz, 1516 Jarvis PI., San Jose, Calif. 95118

Both the 6809 long- and short-branch instruction formats are

shown in Fig. 2-2. The short-branch instruction format shown in Fig.
2-2A is the same as that required for the 6800. The long-branch in-
struction format shown in Fig. 2-2B requires a 2-byte op code fol-
lowed by the 2-byte signed offset. The high offset byte is first, fol-
lowed by the low offset byte.

BRANCH INSTRUCTION OP CODE

(1ST BYTE)

BRANCH INSTRUCTION OP CODE

(2ND BYTE)

BRANCH INSTRUCTION OP CODE RELATIVE ADDRESS OFFSET

(1 BYTE) (HI BYTE)

RELATIVE ADDRESS OFFSET RELATIVE ADDRESS OFFSET

(1 BYTE) (LO BYTE)

(A) Short-branch instruction format. (B) Long-branch instruction format

(except for long branch always
and subroutine).
Fig. 2-2. 6809 branch instruction formats.

29
 Example 2-3: Determining Long-Branch Destinations
Given a branch instruction located at address 5000 with a relative
address offset of 02FO, determine the branch destination.
Since the long branch instruction is 4 bytes (a 2-byte op code
followed by a 2-byte signed offset), the program counter contains
5000+4 = 5004. The destination equals the program counter's con-
tents plus the offset, or 5004+02FO = 52F4.
Now, suppose the offset were F2FO. Then, since the most signifi-
cant bit of the offset is a logic 1, the 6809 will branch backward. As
with short branches, to obtain the destination, add the twos comple-
ment offset to the program counter's contents. Therefore the destina-
tion address is 5004+F2FO = 42F4.
Program Counter Relative (PC Relative) Addressing
To allow complete position-independent programs to be written
without a lot of software overhead, the 6809 includes program
counter relative addressing. With this type of addressing the address
of an operand located in memory can be determined relative to the
program counter's contents. With PC relative addressing an 8- or
16-bit signed offset is added to the program counter's contents to
create the effective address of the operand, or the effective address
of the address of the operand. (The latter case is referred to as indi-
rect addressing, and will be discussed later.) Therefore data can be
accessed anywhere within the 6809's memory map, relative to the
program counter contents, thus allowing for complete position-inde-
pendent programs.
The instruction format required for program counter relative ad-
dressing is shown in Fig. 2-3. Note that the instruction can be 3 or 4
bytes in length, depending on the offset desired. Both 8- and 16-bit
offsets are allowed. In either case a post byte follows the instruction
op code. The offset byte( s) then follows the post byte. When this
type of addressing is used, the program counter is used as a pointer
register with an 8- or 16-bit offset; thus program counter relative

INSTRUCTION OP CODE
--------------------------
(1 OR 2 BYTES)
INSTRUCTION OP CODE
-------------------------- POST BYTE
(1 OR 2 BYTES)
± OFFSET
POST BYTE (HI BYTE)

OFFSET
± OFFSET
(LO BYTE)

(A) 8-bit signed offset. (B) 16-bit signed offset.

Fig. 2-3. Program counter relative addressing.

30
addressing can be thought of as a type of indexed addressing. As you
will see in Chapter 3 any instructions which use indexed addressing
can also use program counter relative addressing. Since program
counter addressing is considered a type of indexed addressing, a
post byte is required to designate that the program counter register
is being used as the pointer register rather than one of the indexible
registers (X,Y,S,U). The use of the post byte will be discussed in
more detail in the next section, on indexed addressing.
The following examples illustrate program counter relative ad-
dressing.
Example 2-4: Using Program Counter Relative Addressing
With an 8-Bit Signed Offset
Consider the following instruction mnemonic sequence:

OOFF
0100 LOA (instruction op code)
0101 post byte
0102 10 (8-bit offset)
0103

The instruction is to load accumulator A with the contents of the

memory address determined by adding the signed offset to the pro-
gram counter's contents. The signed offset is 1016 (0001 00002 ) and
the post byte specifies that the program counter is to be the pointer
register. Recall that the 'program counter always points to the next
instruction to be executed. Therefore, the program counter's contents
are 0103 at this point in the program. Thus the operand to be loaded
into accumulator A is located at address 0103+0010 = 0113. In this
example the offset was positive since its most significant bit is O.
However, if the most significant bit ef the offset is 1, the twos com-
plement offset is negative. For example, if the offset were FO (1111
00002 ), the effective operand address would be 0103+FFFO = 00F3.

Example 2-5: Using Program Counter Relative Addressing

With a 16-Bit Signed Offset
Consider the following instruction mnemonic sequence:

OOFF
0100 LOB (instruction op code)
0101 post byte
0102 01 (offset HI byte)

31
 0103 FF (offset LO byte)
0104

This instruction will load accumulator B with the contents of the

memory location formed by adding the 16-bit offset (OIFF) to the
program counter's contents. The program counter contains 0104 at
this point in the program. Therefore the effective operand address is
0104+01FF = 0303.

INDEXED ADDRESSING
You can probably recall that indexed addressing is the most
powerful form of addressing available to the 6800. It became ex-
tremely valuable when operating on data located in consecutive
memory locations. In the 6800 the indexed addressing instruction is
a 2-byte instruction consisting of the instruction command followed
by a signed indexed offset. To form the effective operand address the
6800 adds the offset to the contents of the 16-bit index register. Sev-
eral 6800 instructions are associated with the index register. Recall
also that you can increment, decrement, load, store and transfer the
index register contents to and from the stack pointer. A substantial
amount of programming power was gained by including the index
register within the 68oo's architecture.
Now, with the 6809, the indexed addressing mode has been en-
hanced by the inclusion of four 16-bit registers which may be used
as pointer registers in the indexed mode of addressing. As mentioned
in Chapter 1 these registers are the X, Y, S, and U registers (refer to
Fig. 1-3). With the 6809 there are four basic forms of indexed ad-
dressing that can be used with these registers. They are: zero-offset
indexed, constant-offset indexed, accumulator-offset indexed, and
auto-increment/ decrement indexed.
The instruction format for indexed addressing is shown in Fig. 2-4.
You see that the instruction op code is always followed by a post
byte, which in turn mayor may not be followed by an offset. The
post byte of an indexed instruction specifies the basic form of in-

INSTRUCTION OP CODE
~--------------------------
(1 OR 2 BYTES)

POST BYTE

I OFFSET I
r-------(10R-2BYTES)-------j
L J

Fig. 2-4. General indexed addressing instruction format.

32
dexed addressing to be used as well as the specific pointer register
that will be used in determining the effective operand address. In-
dexed addressing can be used with 31 of the 59 instructions of the
6809.
Now let us discuss each basic type of indexed addressing; then,
we will learn how to use the post byte. Examples of each indexed
mode are provided at the end of this chapter.
Zero-Offset Indexed Addressing
This type of indexed addressing allows the pointer register to
point directly to the effective operand address, since the offset is
zero. In other words, the specified pointer register contains the ad-
dress of the operand to be used in the operation. These instructions
will be 2 or 3 bytes: the instruction op-code byte ( s ) ~ followed by
the post byte. The post byte will specify the zero-offset mode and the
pointer register to be used. This mode of indexed addressing is the
fastest since a minimum number of bytes is required and no offset
calculation is required.
Constant-Offset Indexed Addressing
This form of indexed addressing is very similar to the 6800's in-
dexed addressing. However, any of the pointer registers (X, Y, U,
or S) can be used and the signed offset can be 5, 8, or 16 bits. The
post byte will follow the instruction op code and will specify the
pointer register and the offset size. When a 5-bit signed offset is used,
the offset is included as part of the post byte and therefore the 5-bit
offset is most efficient in the use of bytes and MPU cycles as com-
pared with the other constant-offset versions. Also, the offset is a
twos complement (signed) value with the most significant bit
(msb) of the offset used to determine its sign. If the most significant
bit is a logic 0, the offset will be positive, and if the most significant
bit is a logic 1, the offset will be negative. Therefore, the 5-bit offset
reduces to a ±4-bit offset with a corresponding offset range of from
-16 10 to + 15] o.
If an 8-bit offset is desired, the instruction will be 3 or 4 bytes in
length. Here the instruction op-code byte ( s ) ~ is followed by the post
byte, which in turn is followed by the 8-bit offset byte. The post byte
will specify constant-offset indexed addressing and the pointer reg-
ister to be used. The offset byte is then added to the pointer register
contents to determine the effective address. Again, the offset is a
twos complement (signed) value with the msb used to determine
the sign. Therefore the 8-bit offset reduces to a ±7-bit offset with a
corresponding range of from -128 10 to +127]0'

~ With the 6809 some instructions require 2 op-code bytes.

33
 If a 16-bit offset is desired, the post byte will be followed· by 2
offset bytes. The most significant offset byte will be first, then the
least significant byte. To determine the effective address, the 16-bit
signed offset will be added to the pointer register specified by the
post byte. Since the offset is signed, it reduces to ±15 bits with a
corresponding range of from -32,76810 to +32,767 10 ,

Accumulator-Offset Indexed Addressing

This type of indexed addressing is similar to the constant-offset
mode, except that the contents of one of the accumulators (ACCA,
ACCB, or ACCD) are added to the specified index register (X, Y,
S, or U) to obtain the effective address. The obvious advantage here
is that the offset can be calculated just prior to the indexed opera-
tion. The instruction will be 2 or 3 bytes in length: the instruction
op-code byte( s) followed by the post byte. The post byte will spec-
ify the accumulator-offset mode, pointer register, and which accumu-
lator is to be used. The 6809 uses the twos complement (signed)
value of the specified accumulator to determine the effective address.
Neither the specified accumulator or index register contents are
affected by the offset calculation.
Auto-Increment/Decrement Indexed Addressing
This mode of indexed addressing is a blessing, since it eliminates
the need to increment/ decrement the index register with a separate
instruction when stepping through memory tables and moving blocks
of data within memory. In the auto-increment mode the specified
pointer register contains the address of the first operand. Then, after
the first operand is used in the operation specified by the op code,
the pointer register is automatically incremented to point to the next
consecutive operand address and so on, as many times as the instruc-
tion is executed. Therefore, memory data are fetched consecutively
from a low to a higher memory address. In the auto-decrement
mode, memory data are fetched from a high to a lower memory ad-
dress since the specified pointer register is automatically decre-
mented just prior to the operand's being fetched. The auto-increment
is therefore a post-increment operation and the auto-decrement a
pre-decrement operation. Thus, if you are using the auto-decrement
option, the starting address must be n+ 1 to fetch information from
address n. The increment/ decrement can be either by 1 or 2 to
allow for 8- or 16-bit data.
The auto-increment/ decrement instruction will be 2 or 3 bytes in
length: the instruction op-code byte ( s) followed by the post byte.
The post byte will specify auto incrementing or decrementing, the
pointer register to be incremented or decremented, and· the amount
of increment or decrement (lor 2).

34
 POST BYTE
From the previous discussion it is obvious that the post byte plays
an important role in the indexed addressing mode. In addition, you
saw that a post byte was also required when using program counter
relative (PC relative) addressing. In summary, you should have dis-
covered from previous discussions that:
1. The post byte is used to specify one of the following modes of
addressing:
program counter relative
zero-offset indexed
constant-offset indexed
accumulator-offset indexed
auto-increment/ decrement indexed
2. The post byte specifies either the program counter, X, Y, S, or U
register to be used as the pointer register.
3. The post byte specifies the offset size to be used in program
counter relative and constant-offset indexed addressing.
4. The post byte specifies the accumulator (A, B, or D) to be used
during accumulator-offset indexed addressing.
5. When using a 5-bit signed constant-offset, the offset value is in-
cluded as part of the post byte.
How is all of this accomplished with 1 byte of information? The an-
swer is found in the post-byte format shown in Fig. 2-5. You see that
the post byte is divided into the following bit fields:
addressing mode field (bits 0-3)
indirect field (bit 4)
pointer register field (bits 5 and 6 )
5-bit offset field (bit 7)
Each of the above post-byte fields will now be discussed.
Addressing Mode Field (Bits 0-3)
This 4-bit field is used to select the type of addressing mode that
is to be used. The addressing modes and their respective bit pattern

POINTER ADDRESSING
REGISTER MODE SELECT
SELECT
5-81T INDIRECT
OFFSET SELECT
SELECT
Fig. 2-5. Indexed addressing post-byte format.

35

....
 Table 2-2. Bit Pattern Definitions of Addressing Mode Fields
Post-Byte
Addressing Mode Field
Bit 3 Bit 2 Bit 1 Bit 0 Addressing Mode Symbol
0 0 0 0 Auto Increment (+1) R+
0 0 0 1 Auto Increment (+2) R++
0 0 1 0 Auto Decrement (-1) -R
0 0 1 1 Auto Decrement (-2) --R
0 1 0 0 Zero Offset R ±O
0 1 0 1 ACCB Offset R ±ACCB
0 1 1 0 ACCA Offset R ±ACCA
1 0 0 0 a·Bit Signed Offset R ±7 Bit
1 0 0 1 16-Bit Signed Offset R ±15 Bit
1 0 1 1 ACCD Offset R ±ACCD
1 1 0 0 PC Relative - a·Bit Signed PC ±7 Bit
1 1 0 1 PC Relative -16-Bit Signed PC ±15 Bit
1 1 1 1 Extended Indirect [n]

definitions are shown in Table 2-2, where R denotes the specified

pointer register (X, Y, S, or U). Note that all of the previously dis-
cussed modes of indexed addressing and program counter relative
addressing can be defined with the first 4 post-byte bits. Also, an
additional mode of addressing, extended indirect, can also be speci-
fied. This mode will be discussed shortly.
Indirect Field (Bit 4)
Bit 4 of the post byte selects indirect addressing. A logic 0 in this
bit position indicates that direct addressing is to be used. Thus the
operand is actually located at the address specified in the operation.
A logic 1 indicates that indirect addressing is to be used. Here the
address points to a location that contains the actual address of the
operand. More will be said about indirect addressing shortly.
Pointer Register Field (Bits 5 and 6)
This field selects the pointer register that is to be used in the ad-
dress determination. The pointer registers and their respective bit
pattern definitions are shown in Table 2-3. Note that anyone of the
four indexible registers (X, Y, S, or U) may be specified as the
pointer register.
Five-Bit Offset Field (Bit 7)
You will always set this bit to a logic 1 state except when you
desire a 5-bit signed offset. In this case, bit 7 will be cleared and the
5-bit, twos complement offset is placed in bits 0 through 4 of the

36
 Table 2·3. Bit Pattern Definitions of Pointer Register Fields
Post·Byte
Pointer Register Field
Bit 6 Bit 5 Pointer Register
o 0 R =X
o 1 R=Y
1 0 R= U
1 1 R= S

post byte. Bit 4 becomes the sign bit, with bits 0 through 3 repre-
senting the offset weight.
All of the post-byte register bit assignments are summarized in
Table 2-4. Now, let us look at some examples of instructions which
use the post byte. Before you can write mnemonic code for these in-
structions, however, you need a code which can be used to represent
the various post-byte designations. Such a code is shown in Table
2-5. In this table, n denotes offset value, R the specified pointer reg-
ister, and PC the program counter. You will follow the instruction
mnemonic with the respective post-byte designation shown in Table
2-5. For example, LDA 23,X means to load accumulator A with the
contents of the memory location specified by adding the constant
offset 23 16 to pointer register X; LDX D, Y means to load index
register X with the contents of the memory location specified by
adding the contents of accumulator D to pointer register Y.

Example 2-6: Assembler Code and Post-Byte

Determination
Suppose you wish to store the contents of accumulator D in memory
at the address specified by the S pointer register using a constant
offset of -5. What would be the assembler code to represent this
operation?
From Table 2-5, the proper assembler code would be: STD -5, S.
What post byte is required to perform this operation? The post byte
would be:
7B16 = 0 1 1 1 1 0 1 b
Let's analyze the above post byte. Since the constant offset is -5, a
5-bit signed offset can be used. Therefore the offset can be included
as part of the post byte. Bit 7 of the post byte is cleared to indicate
a 5-bit constant offset. Bits 5 and 6 are set to specify the S register
as the pointer register. The constant offset is then represented by bits
o through 4: bit 4 is set to indicate a negative offset, while the twos
complement offset value (1011) is specified in bits 0 through 3.

37
 Table 2·4. Indexed Addressing Post·Byte Bit Assignments
Post-Byte Register Bit Indexed
Addressing
7 6 5 4 3 2 1 0 Mode
0 R R X X X X X EA = ,R ± 4 bit offset
1 R R 0 0 0 0 0 ,R+
1 R R I 0 0 0 1 ,R++
1 R R 0 0 0 1 0 ,-R
1 R R I 0 0 1 1 ,--R
1 R R I 0 1 0 0 EA = ,R ±O offset
1 R R I 0 1 0 1 EA = ,R ± ACCB offset
1 R R I 0 1 1 0 EA = ,R ± ACCA offset
1 R R I 1 0 0 0 EA = ,R ± 7·bit offset
1 R R I 1 0 0 1 EA = ,R ± 15-bit offset
1 R R I 1 0 1 1 EA = ,R ± D offset
1 X X I 1 1 0 0 EA = ,PC ± 7·bit offset
1 X X I 1 1 0 1 EA = ,PC ± 15·bit offset
1 R R 1 1 1 1 1 EA = ,Address

L
I
"
T r Addressing Mode Field
Indirect Field (I)
Sign Bit When B7 = 0

Register Field
OO:R = X
01:R = Y
10:R = U
11:R = S
X = Don't Care

Example 2-7: Post-Byte Interpretation

Given the post byte AO, interpret its meaning and determine the as-
sembler code that would be used with an instruction which used this
post byte.
Refer to Table 2-4:
post byte = A016 = 101000002
Bit 7 is set, meaning that a 5-bit constant offset is not specified. The
specified pointer register is the Y register since the pointer register
field (bits 5 and 6) is 01. The address mode field (bits 0 through 4)
is all zeros, indicating that auto increment by one is the specified
addressing mode. The required assembler code for this post byte
would be: ,Y+ (refer to Table 2-5). The effective address for an
operation using this post byte would be the contents of the Y index

38

J
 Table 2·5. Post·Byte Assembler Code
Addressing Mode Assembler
Symbol Code
R ±O ,R
R ±4 Bit n,R
R ±7 Bit n,R
R ±15 Bit n,R
R ±ACCA A,R
R ±ACCB B,R
R ±ACCD D,R
PC ±7 Bit n,PCR
PC ±15 Bit n,PCR
R+ ,R+
R++ ,R++
-R ,-R
--R ,--R

register. After the operation has been executed, the Y index register
contents would be automatically incremented by 1.

Example 2-8: Post-Byte Interpretation

Repeat the steps of Example 2-7 for a post byte of ED.
Here the post byte ED 16 = 1110110b. Again, refer to Table 2-4 to
follow the following interpretation. The addressing mode field con-
tains 1101 which, from Table 2-4, specifies program counter relative
addressing with a 16-bit signed offset. The indirect field is cleared,
meaning that indirect addressing is not specified. The pointer regis-
ter field bits are set; however, since PC relative addressing is speci-
fied, we "don't care" what the contents of this field are since the pro-
gram counter is the pointer register. Finally, the 5-bit constant offset
field is also set meaning that a 5-bit offset is not specified. Note that
if this field were cleared the post byte would take on a whole new
meaning.
The proper assembler code would be: n, PCR where n would
equal the 16-bit signed offset value. The effective address for an
operation using this post byte would be obtained by adding the con-
stant offset n to the present program counter contents.

Example 2-9: Assembler Code and Post-Byte

Determination
Suppose you wish to load the X index register with the contents of
the memory location specified by the X pointer register using the
accumulator D contents as a constant offset. What would be the

39
proper assembler code to represent this operation and what post
byte would be required?
From Table 2-5, the proper assembler code would be: LDX D, X.
Since accumulator D offset is required, the addressing mode field of
the post byte must be 1011 (refer to Table 2-4). Also, since the X
register must be the specified pointer register, the pointer register
field must be 00. The indirect addressing field (bit 5) must be
cleared and the 5-bit constant offset field (bit 7) must be set. There-
fore the required post byte would be 10001011 2 or 8B 1G •

INDIRECT ADDRESSING
As mentioned in previous discussions the 6809 is capable of a very
powerful mode of addressing known as indirect addressing. With
indirect addressing the operand's address (effective address) is con-
tained at the location specified by the operation. Therefore you ob-
tain the operand "indirectly" via an intermediate address. For exam-
ple, suppose that an indirect addressing operation is to locate an
operand at address 02FO. The operation would first point to an inter-
mediate address, say 01FO, which would contain the actual address
of the operand, 02FO. Actually, address 01FO would contain 02 and
address OlFl would contain FO. This operation is summarized in
Fig. 2-6.

Address Obtained From Operation -01 FO 02} Actual Operand Address

(Absolute Address) 01 F1 FO (Effective Address)

I
C::::::02FO Operand

Fig. 2-6. Indirect addressing

Indirect addressing is a very valuable asset of the 6809 since it can

be used with any of the indexed modes of addressing, except for
auto-increment/ decrement by 1. In addition, indirect addressing can
be used with program counter relative addressing and extended
addressing. To specify indirect addressing for any of the above ad-
dressing modes, you will simply set the indirect field, bit 4, of the
post byte. The assembler codes to indicate indirect addressing will
be the same as those listed in Table 2-5, except that the code is
bracketed: [ ]. For example, LDA [10, X] would mean to load ac-
cumulator A with the contents of the address located at the memory
location specified by the X pointer register plus the offset 1016.

40
 Example 2-10: Indirect Addressing (Indexed)
The following program segment is given:

OOFF
0100 LOA [10,X]
0101 post byte
0102 10

020E FO
020F 95
0210 05
0211 00
0212 87

04FE C6
04FF E9
0500 AA
0501 F5

If, prior to executing the LDA instruction, the X index register con-
tains 0200, what will be loaded into accumulator A? The operand's
address will be found at the memory location formed by adding the
constant offset 0010 to the contents of the index register. Therefore
the memory location which contains the address of the operand is
0010 + 0200, or 0210. From the program listing you find 05 at this
address, which is the high byte of the operand's address. The low
byte is found in the next conseclitive memory location. Therefore the
operand's address is 0500. Thus the operand is located at address
0500. At this address you find the value AA, which will be loaded
into accumulator A.
\Vhat post byte would be required for this operation? Since an
8-bit signed offset is required, the addressing mode field of the post
byte must be 1000 (refer to Table 2-4). Since the pointer register is
the X index register, the pointer register field must be 00. The indi-
rect addressing field (bit 5) must be set to indicate indirect address-
ing and the 5-bit offset field (bit 7) must be set. Therefore the
proper post byte would be 100110002 or 98 16 • This value must appear
at address 0101 in the above program listing. The constant offset,
10](), follows the post byte at address 0102.
Example 2-11: Indirect Addressing (PC Relative)
Consider the following program segment:

OOFF STO [OE, PCR]

41
 0100 post byte
0101 OE
0102 next instruction

010F 70
0110 F1
0111 50
0112 AS

Where will the contents of accumulator D be stored? The instruction

specifies program counter relative, indirect addressing with an 8-bit
signed offset of OE. The program counter always points to the next
instruction; therefore the program counter contains 0102. The high
byte of the address where the accumulator D contents are to be
stored is found at the memory location formed by adding the con-
stant offset, OE, to the program counter contents of 0102, or OE+
0102 = 0110. Note from the program listing that F1 is at this address.
The next consecutive address contains 50. Therefore, the address
where the contents of accumulator D will be stored is F150. Since
accumulator D is a 16-bit accumulator, the high byte will be stored
at address F150, with the low byte stored at address F15!.
What post byte would be required for this operation? Since pro-
gram counter relative addressing with an 8-bit signed offset is re-
quired, the addressing mode field of the post byte must be 1100
(refer to Table 2-4). The pointer register is the program counter;
therefore, it doesn't matter what the pointer register field contains
( don't care-refer to Table 2-4). The indirect addressing field (bit 5)
must be set to indicate indirect addressing and the 5-bit offset field
(bit 7) must be set. Therefore the proper post byte would be
1XX111002 or 9C l6 if the don't cares were zeros. This value must
appear at address 0100 in the above program. The constant offset,
OE 16 , follows the post byte at address 0101.

Example 2-12: Indirect Addressing (Extended)

Consider the following program segment:

0500 STX [F150]

0501 post byte
0502 F1
0503 50

F14F AF
F150 C5

42
 F151 50
F152 9C

Where will the contents of the X index register be stored? The as-
sembly language code for extended indirect addressing is [nl, where
n is the address of the address of the operand (or where the operand
is to be stored). Therefore the above instruction specifies extended
indirect addressing. Note that this instruction consists of 4 bytes: the
instruction op code followed by the post byte, which is in turn fol-
lowed by the address at which the effective address will be found.
Thus the high byte of the effective address is located at F150 and
the low byte is located at F1.51. Address F150 contains C5 and F151
contains 50. Therefore, the address where the X index register con-
tents will be stored is C550. Since the X index register is a 16-bit
register, the high byte will be stored at address C550 and the low
byte at address C551.
What post byte would be required for this operation? Since ex-
tended indirect addressing is required, the addressing mode field of
the post byte must be 1111. Neither of the pointer registers is used
to determine the effective address and the pointer register field must
be cleared (refer to Table 2-6). The indirect addressing field (bit 5)
must be set to indicate indirect addressing and the 5-bit offset field
(bit 7) must be set. Therefore, the proper post byte would be
1001111!:! or 9F 16. This value must appear at address 0501 in the
above program.
Obviously, many more possibilities exist than those provided in
these few examples. The reader is encouraged to work the problems
given in the review questions at the end of this chapter, and then to
make up examples such that a full understanding of the various ad-
dressing modes is obtained. Finally, Table 2-6 summarizes the vari-
ous indexed addressing modes, along with their respective assembly
language codes and post-byte formats.

REGISTER ADDRESSING
There is one more major mode of addressing available to the 6809
that should be discussed. Within the 6809, any user register may be
transferred to, or exchanged with, any other register of like size. In-
herent instructions are used to accomplish this task; however, a post
byte is required to define the registers involved. Therefore any in-
structions which involve the transfer or exchange of data between
internal registers will be referred to as register addressing instruc-
tions. As you will see in Chapter 3, these instructions will be 2 bytes
in length: the instruction op code followed by a post byte. The in-

43
t
Table 2-6. Indexed Addressing Modes Summary
Nonindirect Indirect
Assembler Post· Byte x + Assembler Post·Byte + +
Type Forms Form Op Code rv # Form Op Code rv #
Constant Offset From R No offset ,R 1RR00100 0 0 [,R] 1RR10100 3 0
(Signed Offsets) 5·Bit offset n, R ORRnnnnn 1 0 Defau Its to a·bit
a·Bit offset n, R 1RR01000 1 1 [n, R] 1RR11000 4 1
16·Bit offset n, R 1RR01001 4 2 [n, R] 1RR11001 7 2
Accumulator Offset From R A - Register offset A, R 1RR00110 1 0 [A, R] 1RR10110 4 0
(Signed Offsets) B - Register offset B, R 1RR00101 1 0 [B, R] 1RR10101 4 0
0- Register offset 0, R 1RR01011 4 0 [0, R] 1RR11011 7 0
Auto·1 ncrementlDecrement R Increment by 1 ,R+ 1RROOOOO 2 0 Not allowed
Increment by 2 jR++ 1RROOO01 3 0 [,R++] 1RR10001 6 0
Decrement by 1 ,-R 1RROO010 2 0 Not allowed
Decrement by 2 ,--R 1RROO011 3 0 [,--R] 1RR10011 6 0
Constant Offset From PC a·bit offset n, PCR 1XX01100 1 1 [n, PCR] 1XX11100 4 1
16·bit offset n, PCR 1XX01101 5 2 [n, PCR] 1XX11101 a 2
Extended Indirect 16·bit address - - - - [n] 10011111 5 2
R =x, Y, U orS x=oo Y=01
X = Don't care U = 10 s= 11
+ and + Indicate the number of additional cycles and bytes for the particular variation.
rv #
 TRANSFER OR EXCHANGE
INSTRUCTION OP CODE
(A) Instruction format.
POST BYTE

Source Register Select Destination Register Select

(13) Post-byte format.

INTERNAL
4·BIT FIELD REGISTER

0000 ACCD
0001 X
0010 Y
0011 U
(C) Bit field designations. 0100 S
0101 PC
1000 ACCA
1001 ACCB
1010 CCR
1011 DP

Fig. 2-7. Register addressing.

struction and post-byte formats are shown in Fig. 2-7. The post byte
is divided into two fields: the source register field and destination
register field. With the instructions provided in Chapter 3, data can
be moved from the source register to the destination register or ex-
changed between the source and destination registers. The bit-pat-
tern definitions for each internal register are also given in Fig. 2-7.
The only requirement is that both registers defined by the post byte
must be of like size; that is, 8-bit to 8-bit, or 16-bit to 16-bit.

REVIEW QUESTIONS

1. Inherent addressing is also referred to as O--~ addressing.

2. Instructions which involve transfers or exchanges of data between internal

registers use ~_ addressing.

3. State the diHerence between direct addressing with the 6809 vs. direct
addressing with the 6800.

45
 4. The DPR forms the ~_______ byte of the direct address and the

_ _ _~_ _ byte is supplied as part of the instruction.

5. Two types of relative addressing that are available to the 6809 are

~ and · 0

6. Two types of branches available to the 6809 are and 0

7. Describe the 6809 long branch instruction format.

8. Given a branch instruction located at address 2000 with a relative address

offset of F150, determine the branch destination.

9. State the two types of PC relative addressing.

10. List the registers available for use with indexed addressing.

11. The four basic forms of indexed addressing are: _~~_

______, and ,

12. With indexed addressing the instruction op code is always followed by

13. The three constant offsets available with constant-offset indexed addressing

are: -) :, and _

14. Why is the 5-bit signed offset mode the most efficient constant-offset in-
dexed addressing mode?

15. The range of the 16-bit signed offset is from to _

46

-J
16. State an advantage of accumulator-oHset over constant-oHset indexed
addressing.

17. Another name for auto-increment/decrement could be _ _~~_

18. Using auto-increment/decrement, the specified pointer register can be

automatically incremented or decremented by ~ or ~ _

19. List the bit fields, and their corresponding bit positions, that make up the
indexed addressing post byte.

20. When a 5-bit signed oHset is not included in the post byte, the 5-bit offset

field (bit 7) must be _

21. You want to load accumulator A with the contents of a memory location
specified by the Y index register using a constant offset of 1016. What
would be the assembler code used to represent this operation?

22. What post byte would be required to perform the operation in Question 21?

23. Given an indexed addressing post byte of 83I6, interpret its meaning and
determine the proper assembler code.

24. Define indirect addressing.

25. Which of the 6809 addressing modes can use indirect addressing?

47
26. The assembly language symbol used to represent indirect addressing is:

27. Given the following program segment,

04FB LDA#
04FC 10
04FD LDU#
04FE FC
04FF 50
0500 LDX [A, U]
0501 post byte

06FE C7
06FF F5
0700 IB
0701 AA

FC5E D5
FC5F C7
FC60 06
FC61 FF
FC62 00

what will be loaded into the X index register?

28. What post byte would be required for this operation?

29. How many bytes are required for an instmction using extended indirect
addressing?

30. As you will discover in Chapter 3, the EXG instmction exchanges the
contents of two like-size registers. Which two registers would be exchanged
using the following instmction?

EXG
8B

48
 ANSWERS
1. Implied or accumulator if the operation involves one of the accumulators
2. Register
3. With the 6800, direct addressing is limited to the first 256 bytes of memory.
With the 6809, direct addressing can be used with the entire 64K memory
map by using the direct page register (DPR).
4. Most significant
Least significant
5. Branch relative and program counter relative
6. Short and long branches
7. A 2-byte instruction op code followed by a 2-byte relative address offset
(except for LBRA and LBSR, where the op code is only 1 byte; see Chap. 5)
8. Since the offset is 2 bytes (F150), a long branch instruction is required.
Long branches use 4 bytes; therefore the program counter contains 2000 +
4 = 2004. Now, the most significant bit of the offset is a logic 1; therefore
the 6809 will branch backward. To obtain the destination, you add the
twos complement offset to the program counter contents. Thus the destina-
tion address is 2004 + F150 =1154.
9. Program counter relative with an 8-bit signed offset and program counter
relative with a 16-bit signed offset
10. X, Y, S, and U
11. Zero-offset, constant-offset, accumulator-offset, and auto-increment/decre-
ment indexed
12. A post byte
13. 5-, 8-, and 16-bit signed offsets
14. Since the 5-bit signed offset is included as part of the post byte
15. -32,768 to +32,767 (±15 bits)
16. With accumulator-offset, the offset can be calculated just prior to the
indexed operation.
17. Post-increment/pre-decrement
18. 1 or 2
19. Addressing mode field (bits 0-3)
Indirect field (bit 4 )
Pointer register field (bits 5 and 6)
5-Bit offset field (bit 7)
20. Set (logic 1)
21. LDA 10, Y (reference, Table 2-5)
22. 101010002 = A816 (reference, Table 2-6)
23. This post byte specifies auto decrement by two on the X index register.

49
 The X index register will be decremented by two after each execution of an
instruction using this post byte. The assembler code will be: ,--X.
24. With indirect addressing the addressed memory location contains the
address of the operand rather than the operand itself.
25. Extended addressing, program counter relative addressing, and all of the
indexed addressing modes except auto-increment/decrement by 1
26. The bracket, [ ]
27. Prior to the LDX instruction, accumulator A is loaded with 10 and the
U pointer register is loaded with FCSO. The LDX instruction is using
indirect accumulator A offset addressing on the U pointer register. There-
fore the memory location which contains the address of the operand is
+
0010 FC50 = FC60. From the program listing you find 06 at this
address, which is the high byte of the operand's address. The low byte is
found at address FC6!. Thus the operand is located at address 06FF. At
this address you find the value F5. But, the X index register is a 16-bit
register. Therefore F5 forms the high byte to be loaded and the contents
of the next consecutive memory location will form the low byte to be
loaded. Thus the value F51B will be loaded into the index register.
28. 1l0l01lCh = D616 (reference, Table 2-6)
29. 4 or 5: the instruction op-code byte ( s ), followed by a post byte, followed
by a 2-byte address
30. Accumulator A and the direct page register (reference Fig. 2-7)

50
 CHAPTER 3

6809 Registers and Data

Movement Instructions

INTRODUCTION
As stated previously, the main design goal for the 6809 was to
make it a super 8-bit processor, approaching 16-bit performance,
without sacrificing compatibility with the 6800. Therefore, the
6800's architecture was expanded and the instruction set "cleaned
up" to provide more efficient processing. The 72 fundamental 6800
instructions have been reduced to 59 for the 6809. Combined with
the various addressing modes discussed in the previous chapter,
these 59 fundamental instructions, however, allow for 1464 unique
operations within the 6809, as compared with 197 for the 6800.
Prior to defining the 6809's instruction set, Motorola conducted a
survey of 6800 users to determine which 6800 instructions were used
most frequently and which were not so well used. The most fre-
quently used instructions were the loads and stores, followed by
subroutine calls, branches, compares, increments/ decrements, clears,
and adds/ subtracts, in that order. Therefore, the major 6809 instruc-
tion set improvements have been made in the data movement in-
struction category: loads, stores, transfers, exchanges, etc. For ex-
ample, data transfers and exchanges may be made between any two
like-size registers (R1, R2) using the TFR R1, R2 and EXG R1, R2
instructions. There are 42 valid combinations of the TFR instruc-
tion and 21 valid combinations of the EXG instruction. You there-
fore have just learned 63 6809 instructions with two mnemonics
rather than 63 unique mnemonics of the form: transfer A to B
(TAB), transfer A to CCR ( TAP), transfer X to S (TXS), etc.,

51
as was the case with the 6800. This frees a number of op codes for
more efficient use elsewhere. To maintain compatibility with the
6800 the 6809 source code (mnemonic code) has not changed, ex-
cept for the new instructions. Changes have been made, however,
at the object code (op code) level to allow for more efficient instruc-
tion coding.
You have already been familiarized with the 6809's internal reg-
ister format (architecture). We will begin this chapter by discuss-
ing each internal register in detail. Then a discussion of the 6809
instruction set will begin and continue through the next two chap-
ters. For convenience, we have broken the 59 fundamental 6809
instructions down into six functional categories. They are: data
movement, arithmetic, logic, test, branch, and miscellaneous in-
structions. The data movement instructions will be discussed in this
chapter, with the remaining instructions being covered in Chap-
ters 4 and 5.
If you are familiar with the 6800, you will find many of the 6809
instructions are familiar. The difference is in how they are used
with the various addressing modes which were presented in Chap-
ter 2. Therefore, a basic understanding of the 6800's instruction set
will be assumed in this and subsequent chapters. If you are not
familiar with the 6800 instruction set or need some "brushing up,"
consult a textbook on the 6800, such as How to Program and I nter-
face the 6800, published by Howard W. Sams & Co., Inc.

OBJECTIVES
At the end of this chapter you will be able to do the following:

• List and describe the function of each 6809 internal register.

• Describe the function of each condition code register Hag.
• Understand the relationship between the E and F condition
code register Hags.
• Explain the use of the load effective address (LEA) instruc-
tions.
• Explain how constant offsets or any accumulator contents may
be added to any of the indexible registers ( X, Y, S, U) using
the LEA instructions.
• Describe how to transfer or exchange data between any two
like-size registers.
• Write a program to load and store the direct page register
(DPR).
• Understand how the X and Y registers may be used as stack
pointers with the auto-increment/ decrement mode of indexed
addressing.

52

J
 • Explain how to push/pull any or all of the internal 6809 reg-
isters on the S or U stacks.
• List the order of stacking with the PSHS and PSHU instruc-
tions.
• Define a "stack processor."

6809 INTERNAL REGISTER FORMAT

Before we begin a discussion of the 6809 instruction set, let's
briefly review the function of each internal register available to the
programmer. The programming register format is shown in Fig. 3-1.
As stated earlier, this format adds one 8-bit and three 16-bit regis-

B a-BIT ACCUMULATOR A AND a-BIT

ACCUMULATOR B OR 16-BIT
o DOUBLE ACCUMULATOR D

X INDEX POINTER REGISTER

Y INDEX POINTER REGISTER

U INDEX/STACK POINTER REGISTER

DP 0 DIRECT PAGE REGISTER

PROGRAM COUNTER

CC CONDITION CODE REGISTER

ENTIRE STATE SAVE ~

FAST INTERRUPT MASK
HALF CARRY (FROM BIT 3)
INTERRUPT MASK - - - - - - - '

Fig. 3-1. 6809 programming register format.

ters to the 6800 architecture. The new 8-bit register is the direct
page register (DPR) whose function was discussed in Chapter 2.
The three new 16-bit registers are accumulator D, the Y index reg-
ister, and the U stack pointer. The remaining registers are identical
with those in the 6800 and they perform similar functions. The fol-
lowing is a brief review of each register, as shown in Fig. 3-1.
Accumulators A, B, and 0 (A, B, D)
Accumulators A and Bare 8-bit storage registers that are used to
hold operands before they are used in an operation, and also to hold
the results of various operations. As with the 6800, data may be

53
loaded into, stored from, transferred to and from, exchanged with,
added to, subtracted from, shifted, ANDed with, oRed with, xORed
with, and compared to, the contents of either accumulator. Accum-
ulator D is a 16-bit register which combines accumulators A and B.
Accumulator A forms the high byte, with accumulator B forming
the low byte, of accumulator D. Accumulator D is used in the same
way as accumulators A and B, but it is used for 16-bit arithmetic
operations. As you will see presently, there are several instructions
associated with this accumulator. These instructions allow 16 bits
of data to be loaded into, stored from, transferred to and from, ex-
changed with, added to, subtracted from, and compared with the
contents of accumulator D.
X Register
The X register is a 16-bit register that can be used as a pointer
register to store data or 16-bit addresses in conjunction with the in-
dexed mode of memory addressing, as discussed in Chapter 2. As you
discovered in Chapter 2, this register can be automatically incre-
mented or decremented by either one or two counts. The 6809's
instruction set will allow the X register to be loaded from and
copied into memory. In addition, you can add to, subtract from,
and compare its contents, as well as push and pull its contents
from a memory stack. As you will soon see, this register may also
be used as a software controlled stack pointer using auto-increment/
decrement.
Y Register
The Y register functions are identical to those of the X register.
Instructions are provided to manipulate this register in the same
ways as the X register.
U Register
This 16-bit register has the same capabilities and can function
in the same way as the X and Y registers, or it can be used to de-
fine a user or software memory stack, which is not used automati-
cally by the 6809's interrupts as in the case of the hardware stack.
As you will see, the same instructions which operate on the X and
Y registers are also available to the U register. Moreover, push and
pull instructions are provided such that you may stack any or all
of the internal 6809 registers' contents in an R/W memory stack de-
fined by the U register. We will refer to such a stack as the U stack.

.s Register
The S register corresponds to the 68oo's stack pointer. It is a
hardware stack pointer and thus provides for automatic stacking

54
of the internal 6809 register information during subroutine calls
and interrupts. However, it may also be used as a pointer register
for any of the indexed modes of addressing, and it has associated
instructions which allow it to be loaded, stored, added to, sub-
tracted from, and compared. In addition, it can be used to define
a software stack since push and pull instructions are provided so
that you can stack any or all of the 6809 internal register contents
in the S stack.
Direct Page Register (DP)
This is an 8-bit register which is used to define the high-memory
address byte (page) for the direct mode of memory addressing (see
Chapter 2).
Program Counter {PC}
The program counter is a 16-bit binary counter that provides in-
struction sequencing. In addition, it is used in the calculation of
branch destinations for branch relative addressing and effective ad-
dresses for the program counter relative mode of memory address-
ing (see Chapter 2).

Condition Code Register (CCR)

As with the 6800 the 6809 CCR is an 8-bit status flag register.
The functions of the first 6 bits (0 through 5) are identical with
those of the 6800. These first 6 CCR bits are the carry (C), twos
complement overflow (V), zero (Z), negative (N), interrupt (I)
and half-carry (H) flags, respectively. Let us briefly review the
function of each of these flags:
Carry Flag (C-Bit O)-The carry flag is set (=1) whenever there
is a "last" carry (or borrow) generated by the eighth bit column
in an arithmetic operation, or, as you will see later, whenever data
are "moved" or rotated within the accumulators. The carry bit can
sometimes be thought of as a "ninth bit" on the most significant end
of the accumulator.
Twos Complement Overflow Flag (V-Bit 1 )-The V flag is set
whenever a twos complement overflow occurs. This condition is a
result of twos complement arithmetic. If you add two positive num-
bers, you expect to obtain a positive result. If you add two nega-
tive numbers, you expect to obtain a negative result. Bit 7 in twos
complement arithmetic indicates the sign of the number. When-
ever two twos complement numbers are added, or subtracted, a
carry or borrow generated in the D6 column would overflow into
the sign bit, bit D7. If this happens, the sign of the result would
be incorrectly changed. Thus, the V flag will set to indicate this
error condition. Note N exclusive-OR V (N V V) will always give the

55
correct sign, even if the result sign is wrong. Loads, stores, and
logical operations will clear V.
Zero Flag (Z-Bit 2)-The Z flag is set (=1) whenever the result
of an operation or data transfer is identically equal to zero. It can
also be used to reflect the equal or unequal condition between 2
data bytes that are being compared. If the bytes are identical, the
Z flag will set.
Negative Flag (N-Bit 3)-The N flag is the twos complement
sign bit and can be thought of as being connected directly to the
msb (bit 7) of the result. A 1 indicates a negative result, with a
o indicating a positive result. If a twos complement overflow oc-
curs, the sign of the result (N flag) will be incorrect. Therefore
signed branches will always test the condition N "if V to obtain a
valid sign result.
Interrupt Flag (I-Bit 4)-This flag is used in conjunction with
external if 0 device interfacing and it will be discussed in detail
later. Briefly, when this flag is set, it will not allow the 6809 to be
interrupted by the interrupt request (IRQ) line. As you will dis-
cover later, the 6809 interrupts are: NMI, FIRQ, IRQ, RESET,
SWIl, SWI2, and SWI3. All of the above, except SWI2 and SWI3,
will automatically set the I flag during their respective interrupt
sequences.
Half-Carry Flag (H-Bit 5)-The half-carry flag is used to indi-
cate a carry from bit 3 to bit 4 in the arithmetic logic unit (alu).
It will be set if a carry from bit 3's column to bit 4's column took
place during an addition operation only (ADD or ADC). The 6809
uses this flag to implement the decimal-adjust instruction that al-
lows it to operate on binary-coded decimal, or bcd, values.
Fast Interrupt Mask (F-Bit 6) and Entire State Saved (E-
Bit 7) Flags-The two new 6809 flags which were mentioned in
Chapter 1 are the fast interrupt mask (F) and entire state saved
( E) flags, bits 6 and 7 of the CCR, respectively. Recall that these
2 bits are not used and are permanently set (logic 1) in the 6800.
Associated with these flags is a hardware interrupt line called the
fast interrupt request (FIRQ) line. Like the 6800, the 6809 auto-
matically. stacks all the internal register data when an interrupt re-
quest (IRQ) is acknowledged. There is, however, no need for the
computer to waste its time stacking all of the internal register data
if it is known ahead of time that the interrupt service routine will
either use the existing internal register contents or it is not necessary
to save these contents. For this reason the 6809 includes a fast inter-
rupt request (FIRQ) in addition to the standard interrupt request
(IRQ). When an FIRQ is acknowledged, the 6809 will finish exe-
cuting its current instruction and then it automatically "stacks" only
the contents of the program counter and the condition code register.

56
Program control is then passed to the FIRQ interrupt service rou-
tine via the FIRQ interrupt vector. (Interrupt vectors are discussed
in Chapters 5 and 6.) The F flag of the condition code register is
a mask bit for all FIRQ interrupts. When it is cleared (logic 0),
fast interrupts are allowed; however, when it is set (logic 1), fast
interrupts are masked out or disallowed. The E flag of the condition
code register is used in conjunction with the fast interrupt request
(FIRQ) and all other 6809 interrupts. When an FIRQ is acknowl-
edged, the E flag is automatically cleared (logic 0), indicating that
only the program counter and condition code register have been
stacked. However, the E flag is set (logic 1) when an IRQ, NMI,
or SWI is acknowledged, indicating that all the internal working
registers have been stacked. The E flag of the stacked condition
code register is then used by the 6809 during a return from inter-
rupt (RTI) to determine the extent of "unstacking" that is required.
All the 6809 interrupts, except FIRQ will cause the E flag to set.
We will discuss the 6809's interrupt structure in detail later. At this
time it is only necessary that you understand the basic functions
of the E and F flags.
Now that you are familiar with the 6809 addressing modes and
internal register structure, you are ready to study the 59 fundamen-
tal instructions that make up the 6809 instruction set.

DATA MOVEMENT INSTRUCTIONS

The data movement instructions will perform the following op-
erations:
• Load and store registers, A, B, D, X, Y, U, and S.
• Transfer and exchange between any two like-size internal reg-
isters.
• Load an effective address into the X, Y, U, and S registers.
• Push and pull to or from the S or U stacks, any or all of the
internal registers.
• Add 8-bit data to X, Y, U, and S.
• Add 16-bit data to X, Y, U, and S.
• Add A, B, and D to X, Y, U, and S.
• Increment and decrement X, Y, U, and S by one or two counts.
The instruction mnemonics which will accomplish the above op-
erations are listed in Table 3-1 with their respective operation
symbols. First, note from the information in Table 3-1 that you can
load or store any of the accumulators (A, B, or D) or any of the
indexible registers (X, Y, S, or U). As you will see at the end of
this chapter, the load operation may be performed using immediate,
direct, extended, program counter relative, or indexed addressing.

57
 Table 3·1. Data Movement Instructions
Mnemonic Operation Operation Symbol
LD LDA Load A immediate, or from memory M-A
LDB Load B immediate, or from memory M-B
LDD Load D immediate, or from memory M:M + 1-D
LDS Load S immediate, or from memory M:M + 1-S
LDU Load U immediate, or from memory M:M + 1-U
LDX Load X immediate, or from memory M:M + 1-X
LDY Load Y immediate, or from memory M:M + 1-Y
ST STA Store A to memory A-M
STB Store B to memory B-M
STD Store D to memory D-M:M + 1
STS Store S to memory S-M:M + 1
STU Store U to memory U-M:M + 1
STX Store X to memory X-M:M + 1
STY Store Y to memory Y-M:M + 1
TFR R1, R2 Transfer R1 to R2 R1-R2
EXG R1, R2 Exchange R1 with R2 R1-R2
LEA LEAS Load effective address into S EA-S
LEAU Load effective address into U EA-U
LEAX Load effective address into X EA-X
LEAY Load effective address into Y EA-Y
PSH PSHS Push onto hardware stack (S) None
PSHU Push onto user stack (U) None
PUL PULS Pull from hardware stack (S) None
PULU Pull from user stack (U) None

The store operation can be performed using direct, extended, pro-

gram counter relative, or indexed addressing. The op codes for these
instructions will be given shortly. However, for now, let's concen-
trate on the meaning of the instructions.
From the load and store operation symbols, you can see that
whenever a 16-bit register is involved, 2 bytes of memory or im-
mediate data must be provided. These 2 bytes are symbolized by
M:M+ 1. The instruction will determine the effective address M,
with M+ 1 being the next consecutive memory location's address.
Memory address M is associated with the high byte of the register
being operated upon, and M+ 1 is associated with the low register
byte. In the case of the immediate addressing mode, M and M+ 1
are the actual high and low data bytes, respectively. For example,
the 3-byte instruction

LDX $$
F1
C5

58
means to load the X register with the contents of memory locations
FIC5 and FIC6. Here, M equals FIC5, whose contents will be
loaded into the high byte of the X register. The value to be loaded
into the low X register byte is found at memory location M + 1, or
FIC6 in this example. In contrast, the instruction

LOX #
F1
C5

would mean to actually load the X register with FIC5.

We should briefly consider the load and store operations on ac-
cumulator D. Since accumulator D is actually the concatenation of
accumulators A and B, any operations on D obviously operate on
A and B. For example, a load accumulator D operation (LDD)
actually loads accumulator A with the high data byte and accumu-
lator B with the low data byte. On the other hand, a store accumu-
lator D operation (STD) actually stores accumulator A at memory
address M and accumulator B at memory address M + 1.
The transfer (TFR) and exchange (EXG) instructions are 2-
byte instructions which utilize register addressing. The TFR or
EXG instruction op code is followed by a post byte to define the
registers (Rl and R2) involved in the data transfer or exchange.
The definition of this post byte was discussed in the previous chap-
ter under register addressing. Because of the various register com-
binations, there are actually 42 different transfers and exchanges
which can be executed using these two instructions. The only re-
quirement is that the two registers involved must be of like size.
The inclusion of the load effective address (LEA) instructions
in the 6809's instruction set provides a unique capability that is not
intuitively obvious on the surface. These instructions are used to
load the indicated pointer register (S, U, X, or Y) with the value
which results from the indexed mode of addressing's effective ad-
dress (EA) calculation. Therefore the effective address value is
loaded in the pointer register rather than the data at the effective
address, as would be the case with a standard load instruction. All
the indexed modes of addressing, including program counter rela-
tive, are available to the LEA instructions.
Using these instructions, the address of a data byte can be cal-
culated by the main program using the indexed mode of addressing
then passed on to a subroutine, since the pointer register contents
are not destroyed when a subroutine is called. In addition, these
instructions will allow you to add or subtract from any of the pointer
registers. You can add or subtract a constant offset or any of the
accumulator contents. For example, LEAX -5, X will subtract 5
from the X register; LEAS A, S will add the contents of accumu-

59
lator A to the S register; and LEAY 10, U will add 10 to the U reg-
ister and transfer the sum to the Y register. To increment the X
register, you could use LEAX 1, X; while LEAY -1, Y would dec-
rement the Y register. Obviously there are many more possibilities
than the examples presented here. The LEA instructions used in
conjunction with the various modes of indexed addressing will find
many applications in your assembly-language programs.
The 6809 PSH and PUL instructions will allow you to push or
pull one or any number of internal registers to and from the user
(U) or hardware (S) memory stack. Before we discuss these in-
structions, let's notice something about the 6809 stacking. First, the
user stack pointer (U) defines the beginning of a software stack
which is not affected by the use of subroutine calls or interrupts.
Therefore the U stack is controlled completely by the programmer.
In contrast, the hardware stack pointer (S) defines the beginning
of a hardware stack that is used automatically by the 6809 to stack
internal register data during subroutine calls and interrupt servic-
ing. During a subroutine call the program counter is automatically
saved on the S stack, and during an interrupt all the internal reg-
isters are automatically saved on the S stack. The fast interrupt re-
quest (FIRQ) is an exception, since only the condition code reg-
ister and program counter are "stacked." More will be said later
about the use of the S stack with subroutines and interrupts. Recall
that both the U and S stack pointers can be used as index registers
in the indexed mode of addressing, but in addition they support the
push and pull instructions. This dual function allows the 6809 to be
used as a stack processor, and thus it can readily support such high-
level languages as Pascal, FORTRAN, and so on.
• stack processor-a processor which allows unlimited memory
stacking for easy processing of multiple-level interrupts and
subroutine nesting.
In the 6800 the stack pointer "points" to the next available loca-
tion on an R/W memory stack. However, with the 6809 the stack
pointer actually points to the last value pushed onto the stack, some-
times referred to as the top of the stack. This change was made to
allow the 6809's X and Y registers to function also as software stack
pointers in the auto-increment/ decrement mode of indexed address-
ing. For example, an STA, -Xis equivalent to a pull-accumulator-A-
from-the-stack instruction, using a stack defined by the address in
the X register. The instruction LDA, X+ would pull the top byte of
a stack defined by the X register into accumulator A. Before-and-
after illustrations of the operation of these instructions are shown in
Figs.3-2 and 3-3. .
The same types of instructions can be used to push and pull ac-

60
 ACCA ACCA
89 89

MEMORY MEMORY
r--- ---
·
OOFE
··
XX OOFE
·
XX
ooFF XX OOFF XX
0100 XX 0100 89
0101 XX 0101 XX
0102 XX 0102 XX

-·
·
(A) 6809 chip and X stack before
··-
(8) 6809 chip and X stack after
STA, -X. STA, -X.
Fig. 3-2. Before and after STA, - X.

ACCA X REGISTER ACCA

XX ~ 0101 I 89

MEMORY MEMORY

--- --·
OOFE
··
XX OOFE
·
XX
OOFF XX OOFF XX
0100 89 0100 89
0101 XX 0101 XX
0102 XX 0102 XX

··- ·
- ·-
(A) 6809 chip and X stack before (8) 6809 chip and X stack after
LOA, X+. LOA, X+.
Fig. 3-3. Before and after LOA, X +.

cumulator data to and from stacks defined by other pointer regis-

ters by replacing the pointer register designations in the above in-
structions with Y, S, or U, for example, STA, -Y; LDA, Y+; etc.
In addition, accumulators B or D and registers X, Y, S, or U may
be pushed or pulled using the remaining store (ST) and load (LD)
instructions given in Table 3-1 (STB, STD, LDY, LDD, etc.).
However, when you push or pull to or from the 16-bit register, you
must use an instruction that causes an auto-increment/ decrement

61
 :
ACCD Y REGISTER ACCD

__ ~_:::_ ~ ~_:::o_l _
FC50

MEMORY

--·-
L
MEMORY
--
OOFE
·
XX OOFE XX
··
OOFF XX OOFF FC
0100 XX 0100 50
0101 XX 0101 XX
0102 XX 0102 XX

..... -··- .... -

··
-
(A) 6809 chip and Y stack before (B) 6809 chip and Y stack after
STD, --V. STD, --V.
Fig. 3-4. Before and after STO, - - Y.

ACCD ACCD
I xxxx I FC50

MEMORY MEMORY

- ·--- --
· ··
OOFE XX OOFE XX
OOFF FC OOFF FC
0100 50 0100 50
0101 XX 0101 XX
0102 XX 0102 XX

- ·-
....
·
- ·-
·
(A) 6809 chip and Y stack before (B) 6809 chip and Y stack after
LDD, Y++. LDD, Y++.
Fig. 3-5. Before and after LOO, Y + +.

by 2 since the data will require 2 bytes in the stack. For example,
STD, - - Y would push the contents of accumulator D onto a stack
defined by the Y register, while LDD, Y++ would pull the top 2
bytes of a stack defined by the Y register into accumulator D. Before
and after illustrations of these instructions are shown in Figs. 3-4
and 3-5.
So, you might be wondering why we need the PSH and PUL
instructions listed in Table 3-1. The advantage is that, with these

62
 IBIT 7\ BIT 6\ BIT 51 BIT 41 BIT 31 BIT 2\ BIT 1 I I
BIT 0 PU LL ORDER

I •
I C CR

:}O INCREASING
OPR MEMORY
X
~
Y
S/U
PC

•
PUSH ORDER
Fig. 3-6. Push/pull post-byte format.

instructions, you can push or pull any or all of the internal 6809
registers onto a stack denned by the S or U registers with one 2-byte
instruction. The PSH and PUL instructions require 2 bytes: the in-
struction op code followed by a post byte. The post byte dennes
which registers are to be pushed or pulled. The push/pull post-byte
format is shown in Fig. 3-6. A logic 1 in a bit position will cause that
respective register to be pushed/pulled. The order in which the
registers are pushed or pulled is also shown in Fig. 3-6. For exam-
ple, if you wanted to push accumulators A, B, and the program
counter (PC) onto the U stack, the proper assembly code would
be: PSHU A, B, PC. The required post byte would then be 1000
01102 or 86 16 -
When using PSHU or PULU, bit 6 of the post byte will corre-
spond to the S register being pushed or pulled. When using PSHS
or PULS, bit 6 corresponds to the U register. Not all the registers
need to be stacked, but the order given in Fig. 3-6 is the same even
if only a subset is stacked. You will see shortly that this order of
stacking is the same when the 6809 services interrupts. When a 16-
bit register is pushed, the low byte is pushed nrst, followed by the
high byte. And when a 16-bit register is pulled from the stack, the
high byte is pulled nrst, then the low byte. Note from Fig. 3-6 that
stacking all of the internal 6809 registers would require 12 bytes
of stack memory. Also, accumulator D is not specincally stacked
since it is simply the concatenation of accumulators A and B.
The data handling instruction op codes are listed alphabetically
in Table 3-2. Note that, besides providing the instruction op codes,
this table also provides the number of bytes and MPU cycles re-
quired for a given instruction. In addition, the effect that an instruc-
tion has on the condition code register flags is also provided. The
notes and legend provided with this table will also apply to all sub-
sequent op-code tables.

63
 M OD Cod

.
en Instructlonl
Forms
I
I
I OP
Inherent
'V # OP
Direct
'V #
6809 Addressing Modes
Extended
OP 'V #
Immediate
OP 'V # OP
Indexed'
'V # OP
Relative
'V 5
I
I
#1 Description
5
H
3
N
2
Z
1
V
0
C
EXG R1,R2 1E 7 2
A6
R1-R2'
M....A ·· · · · ··
t t
··
LO LOA 4 2 B6 5 86 2 2 0
··
96 3 4+ 2+
LOB 06 4 2 F6 5 3 C6 2 2 E6 4+ 2+ M.... B t t 0
EC M:M+1 ....0 t t
·
LOO DC 2 FC 6 CC 3 3 2+ 0
·
5 3 5+
LOS 10 6 3 10 7 4 10 4 4 10 6+ 3+ M:M+1 ....S t t 0

··
DE FE CE EE
LOU DE 5 2 FE 6 3 CE 3 3 EE 5+ 2+ M:M+1 ....U
M:M+1 ....X
t
t
t
t
0
··
·
9E 2 BE 8E 3 3 AE 0
·
LOX 5 6 3 5+ 2+
LOY 10 6 3 10 7 4 10 4 4 10 6+ 3+ M:M+1 ....Y t t 0
AE
·· ·· ·· ·· ··
9E BE 8E
LEA LEAS 32 4+ 2+ EA'....S
EA'....U
·· ·· ·· ··
LEAU 33 4+ 2+
LEAX 30 4+ 2+ EA'....X t
EA'....Y t
·····
LEAY 31 4+ 2+
PSH PSHS 34 5+< 2 Push registers
on S stack
PSHU 36 5+< 2 Push registers
·····
·····
on U stack
PUL PULS 35 5+< 2 Pull registers
from S stack
PULU 37 5+< 2
~~~I~e8i:::~~ ·····
ST STA 97 4 2 B7 5 A7 A....M t
· t
·
···
3 4+ 2+ 0

···
STB 07 4 2 F7 5 3 E7 4+ 2+ B....M t t 0
STD DO 5 2 FO 6 3 ED 5+ 2+ 0....M:M+1 t t 0
STS 10 6 3 10 7 4 10 6+ 3+ S....M:M+1 t t 0

···
OF FF EF
STU OF 5 2 FF 6 3 EF 5+ 2+ U....M:M+1 t
t
t
t
0
··
· · · · ··
STX 9F 5 2 BF 6 3 AF 5+ 2+ X....M:M+1 0
STY 10 6 3 10 7 4 10 Y....M:M+1 t t 0
9F BF AF 6+ 3+
TFR R1,R2 1F 7 2 R1 ....R2'
..
Notes.
1. Given in the table are the base cycles and byte counts. To determine the total 4. The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte
cycles and byte counts add the values from the 6809 indexing modes table. pushed or pulled.
2. R1 and R2 may be any pair of 8-bit or any pair of 16-bit registers. 5. 5(6) means: 5 cycles if branch not taken, 6 cycles if taken.
6. SW1 sets I&F bits. SW12 and SW13 do not affect I&F.
The 8-bit registers are: A, B, CC, OP 7. Conditions codes set as a direct result of the instruction.
The 16-bit registers are: X, Y, U, S, 0, PC 8. Value of half-carry flag is undefined.
3. EA is the effective address. 9. Special Case-carry set if b7 is SET.
Legend
OP Operation code (hexadecimal); Z Zero lbyte)
'V Number of MPU cycles; V Overf ow, twos complement
#
+
Number of program bytes;
Arithmetic plus;
Arithmetic minus;
Multiply
.
C
t
CC
Carry from bit 7
Test and set if true, cleared otherwise
Not affected
Condition code register
M Complement of M; Concatenation
.... Transfer Into; V Logical OR
I H ~~~:~~r:y,!f~!!1 ...~l~ 3; II ~og!ca~ ANI?
 This completes the discussion of the data handling instructions.
The following examples illustrate the use of these instructions.
Study the examples carefully. Then, if you have a Motorola MEK-
6809D4 trainer, or an equivalent 6809-based system available to
you, implement the following examples to verify their proper exe-
cution. (A discussion of the Motorola ~1EK6809D4 evaluation sys-
tem is provided in Chapter 7.)
Example 3-1: Loading and Storing the Direct
Page Register
Write an instruction sequence to load the direct page register with
a new value and to store the old value.
Even though there is no LDDP or STDP, the exchange instruc-
tion (EXG) makes this a rather simple process. Suppose the new
value to be loaded into the direct page register (DP) is E5, and
the old DP contents are to be stored in memory location E510.
Then, the following instructions should accomplish this task:
LDA #
E5
EXG A, DP
STA $
10
The above instruction sequence loads accumulator A with immedi-
ate data byte E5. The contents of accumulator A and the direct page
register are then exchanged. Thus the new value (E5) is now in the
DP register and the DP contents are in accumulator A. Since it is
desired to store the old DP contents in memory location E510 and
the DP register now contains E5, you can use direct addressing for
the store operation. The store accumulator A direct operation will
cause the contents of accumulator A (old DP register contents) to
be stored at memory location E510 since the DP register contains
E5 and forms the high memory location byte and the instruction
contains 10, which forms the low memory location byte.
What post byte would be required for the EXG instruction in the
above program?
To exchange accumulator A and the DP register, the required
post byte would be 1000 lOll:! or 8B 16 (see Fig. 2-7).
Determine the number of bytes and MPU cycles required to exe-
cute this program.
Adding the number of bytes and MPU cycles required for each
instruction from Table 3-2, you should find that this program re-
quires 6 bytes of memory and 13 MPU cycles for execution.
Example 3-2: Adding to a Pointer Register
Write an instruction sequence to add the contents of accumulator
A to the Y register, then transfer that result to the S register.

65
 There are no 6809 ADD instructions which allow you to add to
any of the pointer registers. However, the load effective address
(LEA) instruction can be used for this purpose. The following sin-
gle instruction will accomplish the above task:
LEAS A, Y

The effective address (EA) is formed by adding the contents of ac-

cumulator A to the Y register contents. The LEAS instruction then
transfers this effective address to the S register.
Determine the post byte required for the above instruction.
The proper post byte would be 101001102 or A6 16 (see Table 2-6).
The following instruction sequence would accomplish the same
task. However, two instructions are required.

LEAY A, Y
TFR Y, S

How many bytes and MPU cycles are required for each of the
above programs?
From Table 3-2 the LEAS A, Y instruction requires 2+ bytes and
4+ MPU cycles. This means that to determine the exact number of
bytes and MPU cycles, you must add the values from the 6809 in-
dexed addressing modes table (Table 2-6) for the given operation.
Referring to Table 2-6, you find that this operation requires no addi-
tional bytes and one additional MPU cycle. Therefore the LEAS A,
Y instruction requires 2 bytes and 5 MPU cycles for execution. In
the same way you find from Tables 3-2 and 2-6 that the second pro-
gram requires 4 memory bytes and 12 MPU cycles for execution.
Note the difference in the number of bytes and MPU cycles for the
two different programs, both of which accomplish the same task.
Example 3-3: Stack Operations
Write an instruction sequence that will stack accumulator A, the
DP register and the U stack pointer on a stack defined by the Y
register.
To use the Y register as a stack pointer, you must use auto-incre-
ment/ decrement by 1, or 2, depending upon the size of the register
to be stacked or unstacked. The following instructions will accom-
plish the given task:

TFR OP, B
STO , - - Y
STU , - - Y

The transfer instruction transfers the DP register contents into ac-

cumulator B, since we cannot store the DP register directly. Now,

66
since you must store both accumulators A and B, you can use an
STD instruction, since accumulator D is simply the combination of
A and B. The STD, - - Y instruction will push accumulator B onto
the Y stack first, followed by accumulator A. The STU, - - Y instruc-
tion will then push the U register onto the Y stack. The low U reg-
ister byte (U L) will be pushed first, followed by the high U register
byte (UII)' After the instructions have been executed, the Y register
will point to the top of the stack or the memory location which con-
tains Un. Accumulator B will be at the bottom of the stack.
Determine the proper post byte for each of the above instruc-
tions.
The transfer (TFR) instruction post byte will be 1011 100b or
B9 16 since the source register is the direct page register and the
destination register is accumulator B '( see Fig. 2-7). The proper
post byte for the STD, - - Y instruction is 1010 00lb or A3 16 • The
post byte for the STU, - - Y instruction will be the same since both
instructions use the same mode of indexed addressing and operate
on the same pointer register (see Table 2-6).
Write an instruction sequence to unstack the above registers.
The correct instruction sequence would be:
LOU, Y++
LOO, Y++
TFR B, OP

Note that you will unstack the register data in the reversed order
to that in which they were originally stacked, since the last-in, first-
out (LIFO) principle applies. The proper post bytes for the above
instructions would be: A1 16 , A1 16 , and 9B 16, respectively (see Ta-
ble 2-6 and Fig. 2-7).
Example 3-4: Stack Operations
Write an instruction sequence that will stack accumulator A, the
CCR, DPR, PC, and X register on the user stack.
This task only requires one 2-byte instruction:
PSHU A, CC, OP, PC, X

The first byte of the above instruction will be the instruction op

code, which you will find to be 3616 , from Table 3-2. The second
byte is the post byte. From Fig. 3-6 you can determine that the post
byte required to stack the given register data is 1001 101b or 9B 16 •
In what order would the above registers be stacked?
As shown in Fig. 3-6 the stacking order would be: PC, X, DPR,
A, CCR. The CCR would be at the top of the stack (lowest memory
address) and the PC at the bottom of the stack (highest memory
address) .

67
 Chart 3-1. Performing Additional Data Transfer Operations
With 6809 Instructions

Exchange A and X PSHS A,B

(XH-A) TFR X,D
(A:XL-X) PULS A
TFR D,X
PULS B

Exchange B and A PSHS A

(XL-B) PSHS B
(XH:B-X) TFR X,D
PULS B
TFR D,X
PULS A

Transfer A to X PSHS X
(A:XL-X) STA O,S
PULS X

Transfer B to X PSHS X
(XH:B-X) STB 1,S
PULS X

Finally, Chart 3-1 shows you how to perform some additional

data transfer operations using the instructions discussed in this
chapter.

REVIEW QUESTIONS
1. List the 8·bit registers of the 6809.

2. List the 16·bit registers of the 6809.

3. Which of the 16·bit registers can be used as index registers?

68
4. Which register is used automatically by the 6809 for stacking data during
subroutines and interrupts?

5. What is the difference between the X and Y registers?

6. When is the Z Hag set?

7. Which CCR Hag indicates a sign error in the result of an operation?

8. For the 6809 to acknowledge a fast interrupt request, the F Hag must be

9. Which registers are automatically stacked during an FIRQ?

10. What is the function of the E Hag?

11. Which of the internal 6809 registers can be loaded and stored?

12. Explain the difference between:

LOX # and LOX $$
FC FC
50 50

69
13. EA~ Y is the operation symbol for the instruction.

14. Write an instruction that will subtract 7 from the contents of the S
register.

15. Write an instruction that will add the contents of accumulator B to the
Y register.

16. Write an instruction that will add the contents of accumulator A to the
U register, then transfer the result to the X register.

17. Which of the 6809's registers may be used as stack pointers?

18. With the 6809 a stack pointer always points (where?).

19. How are the X and Y registers used as stack pointers?

20. Write an instruction sequence which will stack the Y register, accumulator
A, and the condition code register, in that order on the X stack.

21. Why wouldn't the following be a correct answer to the preceding question?
STY, --X
TFR ee, B
STD, --X

70
22. Write an instruction sequence that will unstack the stack created in
Question 20.

23. What is the order of stacking when using the PSH instructions?

24. Write an instruction which will stack both accumulators (A and B), the
X register, and the program counter on the U stack.

25. Write the correct op-code listing for the preceding instruction.

ANSWERS
1. Accumulator A (A)
Accumulator B (B)
Direct page register (DPR)
Condition code register (CCR)
2. Accumulator D (D)
Program counter (PC)
X register (X)
Y register (Y)
U register (U)
S register (S)
3. The X, Y, S, or U register
4. The S register
5. None. They can be used in exactly the same manner and are operated on
by the same set of instructions.
6. When the result of an operation is zero
7. The V flag
8. Cleared (logic 0)
9. Only the program counter and condition code register
10. The E flag is used in conjunction with the F flag. The E flag is automatically
cleared when a fast interrupt request is acknowledged and set for all other

71
 interrupts. This flag is used by the 6809 for unstacking purposes to de-
termine the amount of unstacking required.
11. Accumulators A, B, and D and the X, Y, S, and U registers.
12. LDX # loads the X register immediately with FC50, while LDX $$ loads
the high X register byte (X H ) with the contents of FC50 and the low
register byte (XL) with the contents of FC5l.
13. Load effective address into Y (LEAY)
14. LEAS -7, S
15. LEAY B, Y
16. LEAX A, U
17. The X, Y, S, and U registers
18. To the "top" of the stack or last value pushed onto the stack
19. By using auto-increment/decrement indexed addressing on the X and Y
registers in conjunction with the various load and store instructions
20. STY, --X
STA, -X
TFR CC, B
STB, -X
21. This instruction sequence will stack the Y register, the CCR, then accumu-
lator A which is not the specified order of stacking in Question 20.
22. LDB, X+
TFR B, CC
LDA, X+
LDY, X++
Note that the data must be unstacked in the reverse order of stacking.
23. CC
A Increasing
B memory
DP
X
Y
U/S
PC
24. PSHU A, B, X, PC
25. From Table 3-2 and Fig. 3-6 the correct op-code listing would be:
PSHU op code: 3616
Post byte: 96t6

72
 CHAPTER 4

Arithmetic, Logic, and

Test Instructions

INTRODUCTION
Most of the arithmetic, logic, and test instructions of the 6809 are
very similar to those of the 6800, except in the way they can be used
with the various addressing modes. There are, however, a few sur-
prises. You will see arithmetic and test instructions which allow you
to operate on accumulator D. One of the most significant of these is
the multiply (MUL) instruction that allows you to multiply the con-
tents of accumulators A and B, with a 16-bit product being gener-
ated in accumulator D. In addition, you will find an instruction that
will allow you to extend the sign bit of accumulator B into accumu-
lator D such that 8-bit signed (twos complement) values can be ex-
tended into 16-bit signed (twos complement) values.
The logic instructions of the 6809 allow you to perform the stan-
dard logic operations of AND, OR, XOR or EOR, complement, shift, etc.,
on the contents of accumulators A, B, and memory. However, rather
than have separate, inherent instructions to set and clear the condi-
tion code register flags, the 6809 uses two logic instructions, ANDCC
and ORCC. These two 6809 instructions replace six 6800 instructions
and therefore release valuable op codes for more efficient use else-
where.
The discussions and examples in this chapter will concentrate on
how to apply the arithmetic, logic, and test instructions using the
addressing modes presented in Chapter 2. Only the new instructions
will be defined and discussed separately. Again, a basic understand-
ing of the 6800 instruction set is assumed.

73
 OBJECTIVES
At the end of this chapter you will be able to do the following:

• Write a program to multiply two values and store the result in-
directly.
• Understand why the 6809 multiply (MUL) instruction is an
unsigned multiply.
• Write an instruction sequence to compute the U stack pointer.
• Determine the correct op-code listing, given an assembly-lan-
guage program listing.
• Determine the MPU cycles required to execute a given instruc-
tion sequence.
• Explain how to set and clear the condition code register flags.
• Describe the three main categories of test instructions.
• Understand which CCR flags are affected by the various test
instructions.
• Determine CCR flag status after execution of a given test in-
struction.

ARITHMETIC INSTRUCTIONS
The 6809 arithmetic instructions can be used to perform the fol-
lowing operations:
• Add and subtract memory into A, Band D.
• Add and subtract memory with carry into A and B.
• Increment and decrement A, B, D, and memory.
• Clear A, B, and memory.
• Negate A, B, and memory.
• Operate on bcd numbers.
• Multiply A times B.
• Sign extend B into D.
The 6809 arithmetic instructions are listed in Table 4-1. If you are
familiar with the 6800, you will recognize many of the instruction
mnemonics. The difference between these and the similar 6800 in-
structions is simply in how they can be applied using the numerous
6809 addressing modes. Therefore a detailed description of each in-
struction will not be given here, but examples will be given pres-
ently, showing various ways in which many of these instructions may
be used. However, three new instructions do justify explanation.
They are: ABX (add B to X), MUL (multiply), and SEX (sign ex-
tend B into A).
The ABX instruction adds the unsigned (8-bit straight binary)
contents of accumulator B to the X register contents, with the result

74
 Table 4-1. 6809 Arithmetic Instructions
Mnemonic Operation Operation Symbol
ABX Add B to X (unsigned) B+X-X
ADC ADCA Add memory to A with carry A + M +C-A
ADCB Add memory to B with carry B + M + C-B
ADD ADDA Add memory to A A+M-A
ADDB Add memory to B B+M-B
ADDD Add memory to 0 0+ M:M + 1-0
CLR CLRA Clear A O-A
CLRB Clear B O-B
CLR Clear memory O-M
DAA Decimal adjust A None
DEC DECA Decrement A A -1-A
DECB Decrement B B -1-B
DEC Decrement memory M -1-M
INC INCA Increment A A+1-A
INCB Increment B B + 1-B
INC Increment memory M +1-M
MUL Multiply A times B (unsigned) AxB-D
NEG NEGA Negate A (twos complement) A+1-A
NEGB Negate B (twos complement) B +1-B
NEG Negate memory (twos complement) t1 + 1-M
SBC SBCA Subtract memory from A with borrow A - M -C-A
SBCB Subtract memory from B with borrow B - M - C-B
SEX Sign extend B into A None
SUB SUBA Subtract memory from A A-M-A
SUBB Subtract memory from B B-M-B
SUBD Subtract memory from 0 0- M:M + 1-0

being placed in the X register. ABX is a I-byte inherent instruction.

This instruction is very similar to LEAX B, X. However, ABX treats
accumulator B as an unsigned positive offset between 0 and 255, and
LEAX B, X treats accumulator B as a twos complement signed offset
between -128 and +127. In addition, the LEAX B, X instruction
requires 2 bytes compared to 1 for ABX. Therefore it will be advan-
tageous to use ABX when it is known that a relatively large positive
offset is to be placed, or generated, in accumulator B.
In high-level languages it is often necessary to perform calcula-
tions on various arrays of information. These calculations frequently
require multiplication operations, and therefore a multiply instruc-
tion (MUL) has been added to the 6809 instruction set. The MUL
instruction permits you to multiply directly in the 6809 without any
special algorithms. The unsigned (8-bit binary) contents of accu-

75
 "MUL"

8 ALU 8

8 8
16
ACCA ACCB

RESULT

ACCD
Fig. 4·1. Execution of the multiply (MUL) instruction.

mulators A and B are multiplied together. An unsigned 16-bit result

is generated and placed in accumulator D. The internal execution of
this instruction is shown in Fig. 4-1. Note from the figure that the
contents of accumulators A and B are multiplied in the arithmetic
logic unit (alu), with the result being placed in accumulator D.
Since accumulators A and B combine to form accumulator D, the
most significant byte of the result is actually placed in accumulator
A and the least significant result byte is placed in accumulator B.
Therefore the previous contents (multiplier and multiplicand) of
these accumulators are lost. The MUL instruction is a I-byte inher-
ent instruction. It has been made an unsigned multiply to facilitate
multiple-precision (multibyte) multiplications. A signed multiply
would not lend itself easily to such a task.
Finally, the 6809 does have SEX appeal, by way of the sign extend
instruction. Thi~ instruction will allow you to convert a signed (twos
complement) 8-bit value in accumulator B to a 16-bit twos comple-
ment value in accumulator D. The SEX instruction actually extends
the most significant bit (sign bit) of accumulator B into the most
significant bit of accumulator A. This will allow 8-bit signed numbers
to be easily converted to 16-bit numbers for subsequent internal 16-
bit operations. For example, data communications with the outside
world use 8-bit words, but internally the 6809 can perform 16-bit
operations; therefore, such a conversion might be desirable. SEX is
also a I-byte inherent instruction.
Now, let's look at some example programs which utilize these new
instructions and the other arithmetic instructions. If you have a
Motorola MEK6809D4 or equivalent trainer available to you, you
may wish to implement the example programs on your trainer to
verify their proper execution. The arithmetic instruction op codes
are provided in Table 4-2.

76
 Table 4-2. Arithmetic Instruction Op Codes
6809 Addressing Modes

Instructlonl Inherent Direct Extended Immediate Indexed Relative 5 3 2 1 0

·...·
Forms OP '" # OP '" # OP '" # OP '" # OP '" # OP '" # Description H N Z V C
ABX 3A 3 1 B+X-X
(Unsigned)
ADC ADCA 99 4 2 B9 5 3 89 2 2 A9 4+ 2+ A+ M +C-A t t t t t
ADCB 09 4 2 F9 5 3 C9 2 2 E9 4+ 2+ B + M +C-B t t t t t
ADD ADDA 9B 4 2 BB 5 3 8B 2 2 AB 4+ 2+ A+M-A t t t t t
ADDB DB 4 2 FB 5 3 CB 2 2 EB 4+ 2+ B+M-B t t t t t
ADDD D3 6 2 F3 7 3 C3 4 3 E3 6+ 2+ D + M:M + 1-0 t t t t t
CLR CLRA
CLRB
4F
5F
2
2
1
1
O-A
O-B ··
0
0
1
1
0
0
0
0
CLR OF 6 2 7F 7 3 6F 6+ 2+ O-M 0
· 1 0 0

···
DAA 19 2 1 Decimal adjust A t t 0 t
DEC DECA
DECB
4A
5A
2
2
1
1
A -1-A
B -1-B
t
t
t
t
t
t··
··· ···
DEC OA 6 2 7A 7 3 6A 6+ 2+ M -1-M t t t
INC INCA 4C 2 1 A +1-A t t t
INCB 5C 2 1 B + 1-B t t t
MUL
INC
3D 11 1
OC 6 2 7C 7 3 6C 6+ 2+ M +1-M
AxB-D
.;unsigned)
t
·· . . ·
t
t
t
9

NEG NEGA 40 2 1 +1-A 8 t t t t

NEGB 50 2 1 8+1-B 8 t t t t
NEG 00 6 2 70 7 3 60 6+ 2+ M+1-M 8 t t t t
SEX

SBC SBCA
1D 2 1

92 4 2 B2 5 3 82 2 2 A2 4+ 2+
Sign extend B
into A
A - M -C-A
·
8
t
t
t
t
0

t
·
t
SBCB D2 4 2 F2 5 3 C2 2 2 E2 4+ 2+ B -M -C-B 8 t t t t
SUB SUBA 90 4 2 BO 5 3 80 2 2 AO 4+ 2+ A-M-A 8 t t t t
SUBB DO 4 2 FO 5 3 CO 2 2 EO 4+ 2+ B-M-B 8 t t t t
SUBD 93 6 2 B3 7 3 83 4 3 A3 6+ 2+ 0- M:M + 1-D
· t t t t

::I
 Example 4-1: Using the Multiply (MUL) Instruction
Describe the task of the following instruction sequence:
LOA #
20
LOB #
OA
MUL
STO [, Xl
The instruction sequence first loads accumulator A with 20, then
loads accumulator B with OA. The MUL instruction then multiplies
these values and places the 16-bit result, 0140, in accumulator D.
Note, since accumulator D is the combined contents of accumulators
A and B, accumulator A should now contain 01 and accumulator B
will contain 40. The previous accumulator contents are lost. Finally,
the result is stored by the STD instruction using indirect addressing,
with the X pointer register (no offset). Therefore, the contents of
the X register specify the address where you will find the high ad-
dress byte of the high result byte storage location. The low address
byte of the high result byte storage location will be found at the ad-
dress specified by the index register contents plus 1, or X+ 1. For
example, suppose the index register contains 0100. Then, X=OI00
and X+1=0101. Also, suppose that memory location 0100 contains
FC and memory location 0101 contains 50. Then the high result byte
is stored in memory location FC50 and the low result byte is stored
in memory location FC51.
Write the correct op-code listing for the above instruction mne-
monic sequence.
From Tables 2-6,3-2, and 4-2 the proper op-code listing would be:
LOA # 86
20 20
LOB # C6
OA OA
MUL 30
STO [, Xl EO
94

Verify that the above listing is correct.

By observation, you see that the above instruction sequence re-
quires 7 bytes. How many MPU cycles would be required to execute
this instruction sequence?
From the same set of tables (Tables 2-6, 3-2, 4-2) you can deter-
mine that 9 MPU cycles would be required.
Example 4-2: Computed Stack Pointer
Write an instruction sequence that will compute an X register offset
by adding the contents of two consecutive memory locations which

78

..
are specified by the Y register. Once the offset is computed, add it to
the X register to create an X stack pointer. Then, save the Sand U
registers on the X stack.
The following instruction sequence will perform the above task:
LOB ,Y
ADDB 1, Y
ABX
STS ,--X
STU ,--X

The LDB instruction will load accumulator B with the contents of

the memory location specified by the Y register, since a zero offset is
being used. The ADDB instruction will then add the contents of the
next consecutive memory location (specified by Y+1, since a con-
stant offset of 1 is used) to accumulator B and place the result in
accumulator B. Now that the offset is computed, the ABX will add
the computed offset in accumulator B to the X register and place the
result in the X register, thus providing the computer X stack pointer.
The STS and STU instructions are then used with auto-decrement
by 2 and the X register to save the Sand U registers on the X stack.
Write the correct op-code listing for this instruction sequence.
From Tables 2-6, 3-2, and 4-2 the proper op-code listing would be:

LOB, Y E6
A4
ADDB 1, Y EB
21
ABX 3A
STS ,--X 10
EF
83
STU ,--X EF
83

You should verify the proper instruction op codes and post bytes
such that a complete understanding of the 6809 instruction set is
achieved. A few comments are in order:
1. The constant offset of 1 in the ADDB instruction is included as
part of the post byte (see Chapter 2).
2. The STS instruction requires a 2-byte op code (see Table 3-2).

How many MPU cycles would be required to execute the above

program?
From the same set of tables you can determine that 29 MPU
cycles would be required.
You will see more applications of the arithmetic instructions as we
develop other examples throughout the text.

79
 LOGIC INSTRUCTIONS
The logic instructions of the 6809 can be used to perform the fol-
lowing operations:
• AND, OR, and EOR memory into A or B.
• Shift and rotate memory, A, or B.
• Complement memory, A, or B.
• AND or OR immediate data into the CCR.
The 6809 logic instructions are listed in Table 4-3. As with the
6800, the standard logic operations of AND, OR, and EOR are provided
along with the various arithmetic and logic shift functions. The
reader is encouraged to consult a 6800 text if a more detailed discus-

Table 4·3. 6809 Logic Instructions

Mnemonic Operation Operation Symbol
AND ANDA AND memory with A (1\) A 1\ M-A
ANDB AND memory with B BI\M-B
ANDCC AND condition code register CC IMM CC
ASL ASLA Arithmetic shift left A
ASLB Arithmetic shift left B ~ } 0-1 I 1 I I I I I 1-0
bo
ASL Arithmetic shift left memory M C b7

ASR ASRA Arithmetic shift right A

ASRB Arithmetic shift right B ~} LLIIIIIIII-O
b7 bo C
ASR Arithmetic shift right memory M

COM COMA Ones complement A (1-0; 0-1) A-A

COMB Ones complement B S-B
COM Ones complement memory 'M-M
EOR EORA Exclusive OR A ( '0' ) A '0' M-A
EORB Exclusive OR B B '0' M-B
LSL LSLA Logic shift left A
LSLB
LSL
Logic shift left B
Logic shift left memory ~} 0-1 I I I I I 1 I 1-
C b7 bo
a

LSR LSRA Logic shift right A

LSRB
LSR
Logic shift right B
Logic shift right memory ~} a I I I I 11111-0
b7 bo C

OR ORA OR memory with A ( v ) A v M-A

ORB OR memory with B B v M-B
ORCC OR condition code register CC vIMM-CC
ROL ROLA Rotate left A
ROLB Rotate left B ~ } CO-I I I I I I I I IJ
ROL Rotate left memory M C b7 - bo

ROR RORA Rotate right A

RORB Rotate right B ~ } [0-1 11I I 11I ~
ROR Rotate right memory M C b7 - bo

80

...
sion is needed on these instructions. The arithmet~c shift left (ASL)
and logic shift left (LSL) use the same operation symbol (Table
4-3). This is because they perform exactly the same operation and,
as you will see shortly, use the same op codes. Therefore there is no
functional difference between ASL and LSL. Motorola has simply
provided some duplication here since some users think of this opera-
tion as an arithmetic shift left, while others think of it as a logic shift
left operation.
Two surprises are provided in this instruction listing. They are the
ANDCC and ORCC instructions. These two instructions do not ap-
pear in the 6800 instruction set. However, they are meant to replace
several 6800 instructions. With the 6800 there are eight instructions
that allow you to operate on the condition code register. Two of the
eight (TAP and TPA) are used to transfer data between accumula-
tor A and the CCR. These have been replaced with the two 6809
exchange (EXG) and transfer (TFR) instructions. The remaining
six 6800 condition code register instructions are used to set and clear
the C, I, and V flags. They are: SEC, CLC, SEI, CLI, SEV, and
CLV. These six instructions have been replaced in the 6809 with two
instructions: ANDCC and ORCC. Both instructions use immediate
addressing to AND or OR a data byte immediately with the contents
of the condition code register for the purposes of setting or clearing
any CCR flag. To set any CCR flag, you simply OR a logic 1 immedi-
ately with that flag's bit position. To clear a flag, you AND a logic 0
with the respective flag bit position. Note, if you OR a logic 0 or AND
with a logic 1, the flag status will not change. This can be used to
preserve the state of various bits, while changing others. Some ex-
amples may help at this point.
Example 4-3: Clearing Condition Code Register Flags
Suppose that you wish to clear the C and I flags in the condition code
register. Determine the required instruction and immediate data
byte to be used.
To clear a flag you must AND a logic 0 with that flag's bit position.
Therefore, since the C and I flags are in bit positions 0 and 4, respec-
tively, the data byte must contain a logic 0 in these bit positions. All
other bit positions will contain a logic 1 so that the other flags are not
affected by the ANDing operation. Therefore the correct data byte
would be 1110 11102 or EE 16 • The complete instruction would then
be:
ANDCC #
EE
Example 4-4: Setting Condition Code Register Flags
Suppose that you wish to set the Nand F flags. Determine the re-
quired instruction and immediate data byte to be used.

81
 To set a flag you must OR a logic 1 with that flag's bit position. The
Nand F flags are in bit positions 3 and 6, respectively. Therefore the
data byte must contain a logic 1 in these bit positions. All other bit
positions will contain a logic 0 so that the other flags are not affected
by the oRing operation. Thus the correct data byte would be 0100
10002 or 4816 • The complete instruction would then be:

ORCC#
48
Example 4-5: Instruction Interpretation
Interpret the following:
1. ANDCC #
00
2. ORCC #
10
3. ANDCC #
FF

1. The first instruction clears the condition code register, sin~e a

logic 0 is ANDed with all of the CCR bits.
2. The second instruction sets the I flag, since a logic 1 is being
oRed with the I-flag bit position of the CCR. All other bits are
unchanged.
3. The third instruction will not accomplish anything, except to
waste MPU time, since logic Is are being ANDed with all the
CCR flags.
The logic instruction op codes are provided in Table 4-4.

TEST INSTRUCTIONS
The 6809 test instructions can be used to test data in the following
ways:
• Arithmetic compare memory with A, B, D, X, Y, U, and S.
• Logical compare memory with A and B.
• Test for zero, positive or minus on memory, A, and B.
There are no real big surprises in the 6809 test instructions over
those of the 6800. The 6809 test instructions are listed in Table 4-5.
The three main categories of testing are: logic bit test (BIT), arith-
metic compare test (CMP), and byte test (TST) for zero, positive,
or negative.
The bit test allows you to test for single bit status (logic 1 or 0)
in accumulator A or B using a data mask byte supplied (immedi-

82
 Table 4·4. Logic Instruction Op Codes
6809 Addressing Mode
Instructionl Inherent Direct Extended Immediate Indexed 5 3 2 1 0
Forms OP ru # OP ru # OP ru # OP ru # OP ru # Description H N Z V C
AND ANDA 94 4 2 B4 5 3 84 2 2 A4 4+ 2+ A /\ M-A • ~ ~ 0 •
ANDB D4 4 2 F4 5 3 C4 2 2 E4 4+ 2+ B/\M-B • ~ ~ 0 •
ANDCC 1C 3 2 CC/\ IMM-CC 1
ASL ASLA 48 2 1 8 ~ ~ ~ ~
ASLB 58 2 1 A] ~ 8 ~ ~ ~ ~
B O-OIIIIIJ] ~ 0
ASL 08 6 2 78 7 3 68 6+ 2+ M C b, bo 8 ~ ~ ~ ~
ASR ASRA 47 2 1 8 ~ ~ • ~
ASRB 57 2 1 ~ ] CCrr:Iio::IJ-o 8 ~ ~ • ~
M b, bo C
ASR 07 6 2 77 7 3 67 6+ 2+ 8 ~ ~ • ~
COM COMA 43 2 1 A-A • ~ ~ 0 1
COMB 53 2 1 B-B • ~ ~ 0 1
COM 03 6 2 73 7 3 63 6+ 2+ M-M • ~ ~ 0 1
EOR EORA 98 4 2 B8 5 3 88 2 2 A8 4+ 2+ AVM-A • ~ ~ 0 •
EORB D8 4 2 F8 5 3 C8 2 2 E8 4+ 2+ BvM-B • ~ ~ 0 •
LSL LSLA 48 2 1 • ~ ~ ~ ~
LSLB
LSL
58 2 1
08 6 2 78 7 3 68 6+ 2+
A
B
M
I C b,
~
D-OIITIIIJ ~
bo
0
•
•
~
~
~
~
~
~
~
~
LSR LSRA 44 2 1 A] _ • 0 ~ • ~
LSRB 54 2 1 B
M
0 -OIITIIIJ-D
b, bo C
• 0 ~ • ~
LSR 04 6 2 74 7 3 64 6+ 2+ • 0 ~ • ~
OR ORA 9A 4 2 BA 5 3 8A 2 2 AA 4+ 2+ Av M-A • ~ ~ 0 •
ORB DA 4 2 FA 5 3 CA 2 2 EA 4+ 2+ BvM-B • ~ ~ 0 •
ORCC 1A 3 2 CCv IMM-CC 7
ROL ROLA 49 2 1 • ~ ~ ~ ~
ROLB 59 2 1 • ~ ~ ~ ~
ROL 09 6 2 79 7 3 69 6+ 2+ ~ ] l{]-OIITIIIJ] • ~ ~ ~ ~
ROR RORA 46 2 1 M C b( - bo
• ~ ~ • ~

:3 RORB 56 2 1 ~lLD-~ • ~ ~ • ~
ROR 06 6 2 76 7 3 66 6+ 2+ M C b b 7 - o • ~ ~ • ~
 Table 4·5. Test Instructions
Mnemonic Operation Operation Symbol
BIT BITA Bit test A AAM
BITB Bit test B BAM
CMP CMPA Compare with A A-M
CMPB Compare with B B-M
CMPD Compare with D D - M:M + 1
CMPS Compare with S S - M:M + 1
CMPU Compare with U U - M:M + 1
CMPX Compare with X X - M:M + 1
CMPY Compare with Y Y - M:M + 1
TST TSTA Test A A -0
TSTB Test B B -0
TST Test Memory M -0

ately) as part of the instruction statement or obtained from memory

via direct, extended, or indexed addressing (any of the indexed ad-
dressing modes may be used). Note from the operation symbol in
Table 4-5 that bit test is an ANDing operation which only affects the
Nand Z flags of the CCR. As with all the test instructions, no "result"
is generated, besides setting or clearing the appropriate flag, since
the main function of any test instruction is to simply test data, affect-
ing only the CCR for conditional branch purposes.
The compare instructions will allow you to compare the contents
of accumulators A, B, D, and any of the indexible registers (X, Y,
S, U) with data supplied as part of the instruction (immediate) or
obtained from memory using direct, extended, or any of the indexed
modes of addressing. Compare operations are subtraction operations
which are used to determine whether two quantities are equal, or
whether one is larger (smaller) than the other. These comparison
operations are normally used just prior to conditional branch instruc-
tions such as branch if equal (BEQ), branch if not equal (BNE),
branch if higher (BHI), branch if lower (BLO), etc. When compar-
ing data to one of the accumulators or indexible registers, the data are
subtracted from the respective accumulator or register with the N,
Z, V, and C flags being set or cleared accordingly. Neither the accu-
mulator/ register contents or memory location contents are affected
by this operation. With the 6800 you can compare accumulator B to
accumulator A with an inherent (I-byte) instruction. There is no
such instruction for the 6809; however, I6-bit data may be compared
to any of the I6-bit registers (except the PC) in the 6809-an accept-
able tradeoff.
The byte test (TST) instructions are used to determine if the con-
tents of accumulator A, B, or any memory location are positive, neg-
ative, or zero, without affecting the contents of the respective regis-

84
ter. These instructions will normally be used just prior to conditional
branch instructions such as branch if plus (BPL), branch if minus
( BMI ), branch if equal zero (BEQ), and branch if not equal zero
(BNE). Note from the operation symbol that zero is subtracted from
the respective register. Only the Nand Z Hags are affected and no
result is generated with the byte test operation.
The following examples illustrate the effect of the test instructions
on the condition code register (CCR). You will observe their use in
conjunction with the branch instructions in the next chapter. You may
wish to execute these examples on a 6809-based computer and then
check the condition code register for the correct Hag status. The in-
struction op codes are supplied in Table 4-6.
Example 4-6: Using the Bit Test (BIT) Instruction
Suppose that you wish to check the logic status of bit 6 in accumula-
tor A. Which test instruction is required and what would be the
correct data mask byte?
To test for bit status in accumulator A you would use the BITA
instruction. The mask byte must be 010000002 or 4016 to check for
bit 6 status. Note that all other bit positions in the mask byte are
"masked out" with zeros. Therefore the proper instruction listing
would be:
BITA #
40

If bit 6 in accumulator A is set (logic 1) when the above instruction

is executed, the ANDing operation would cause the Z Hag of the CCR
to clear since the "result" of the ANDing operation is not o. If the Z
Hag is set as a result of the above operation, this would indicate that
bit 6 of accumulator A is cleared (logic 0), since the ANDing opera-
tion result is zero. Try this by loading various values into accumula-
tor A, executing the above instruction, and then examining the Z-Hag
status.
Example 4-7: Using the Compare (CMP) Instruction
Write an instruction sequence that will compare the contents of the
X register with data whose address is found in two consecutive mem-
ory locations which begin 50 decimal positions after the compare in-
struction in the program.
The only instruction required to perform the above task is the
CMPX instruction. Indirect addressing is required since the address
of the operand is being specified rather than the operand itself. In
addition, since the operand's address is to be found relative to the
position of the CMPX instruction, program counter relative address-
ing must be used. Therefore the CMPX instruction will use indirect

85
CICl
ca

Table 4·6. Test Instruction Op Codes

6809 Addressing Mode

Instructionl Inherent . Direct Extended Immediate Indexed 5 3 2 1 0

Forms OP f\J # OP f\J # OP f\J # OP f\J # OP f\J # Description H N Z V C
BIT BITA 95 4 2 B5 5 3 85 2 2 A5 4+ 2+ Bit test A (M A) • a •
BITB D5 4 2 F5 5 3 C5 2 2 E5 4+ 2+ Bit test B (M B) • * * a •
CMP CMPA 91 4 2 B1 5 3 81 2 2 A1 4+ 2+ Compare M from A 8 * * J
CMPB D1 4 2 F1 5 3 C1 2 2 E1 4+ 2+ Compare M from B 8 * * *
CMPD 10 7 3 10 8 4 10 5 4 10 7+ 3+ Compare M:M + 1 • * * * *
93 B3 83 A3 from D * * * *
CMPS 11 7 3 11 8 4 11 5 4 11 7+ 3+ Compare M:M + 1 •
9C BC 8C AC from S * * * *
CMPU 11 7 3 11 8 4 11 5 4 11 7+ 3+ Compare M:M + 1 •
93 B3 83 A3 from U * * * *
CMPX 9C 6 2 BC 7 3 8C 4 3 AC 6+ 2+ Compare M:M + 1 •
from X * * * *
CMPY 10 7 3 10 8 4 10 5 4 10 7+ 3+ Compare M:M + 1 •
9C BC 8C AC from Y * * * *
TST TSTA 4D 2 1 Test A • a •
TSTB 5D 2 1 Test B • * * a •
TST aD 6 2 7D 7 3 6D 6+ 2+ Test M • * * a •
* *
program counter relative addressing. Now, the instruction will be
3 bytes: the CMPX op code followed by the post byte, which in turn
is followed by the program counter relative offset. Since the CMPX
instruction requires 3 bytes, the memory locations which contain the
operand address will be located 47 10 (not 50](») positions from the
program counter. This is because the program counter always points
to the next instruction to be executed. Therefore the correct PC rela-
tive offset would be 47 10 or 2F 16. Thus the assembly language code
for this operation is CMPX [2F, PCR].
Determine the correct op-code listing for this instruction.
From Tables 2-6 and 4-6 the corresponding op-code listing would
be:

CMPX instruction op code: AC

post byte: 9C
relative offset: 2F

Example 4-8: Using the Compare Instruction

Suppose accumulator D contains OF50 at the time the following in-
struction is executed.
CMPD #
OF
49

Determine the CCR Hag status after execution of this instruction.

The CMPD instruction will subtract OF49 from OF50. Since the
accumulator's contents are larger than the "data" used in the com-
pare operation, the N Hag will be cleared, indicating a positive re-
sult. The Z Hag will also be cleared, indicating a nonzero result. The
C Hag will also clear since no carry or borrow is generated. The re-
maining Hags are not affected by this operation and will remain set,
or cleared, from some previous operation.

Example 4-9: Using the Test (TST) Instruction

Suppose accumulator A contains FF when TSTA is encountered.
Determine the CCR Hag status after TSTA is executed.
Since the contents of accumulator A (FF) are nonzero and nega-
tive (twos complement), the Z Hag will be cleared and the N Hag set.
The V Hag is always cleared during this operation (see Table 4-6).
The other Hags are not affected by the operation and will remain set,
or cleared, as the result of some previous operation.

Table 4-7 shows you how to perform some additional arithmetic,

logic, and test operations with previously discussed 6809 instructions.

87
 Table 4·7. Performing Additional Arithmetic, Logic, and Test
Operations With 6809 Instructions
Arithmetic
Operations Instructions
Add A to B PSHS A
(A + B-B) AOOB ,S+
Add X to 0 PSHS X
(X + 0-+0) AOOO ,S++
Add 0 to X LEAX O,X
(0 + X-X)
Add Y to X EXG O,Y
(Y + X-X) LEAX O,X
EXG O,Y
Decrement 0 EXG O,X
(0 -1-0) LEAX -1,X
EXG O,X
Increment 0 EXG O,X
(0 + 1-0) LEAX 1,X
EXG O,X
r:iegate 0 COMA
(0 + 1-0) COMB
AOOO #
01
tiegate X EXG O,X
(X + 1-X) COMA
COMB
AOOO #
01
EXG O,X
Subtract X from 0 PSHS X
(0 -X-D) SUBO ,S++
Subtract 0 from X PSHS 0
(X - O-X) COMA
COMB
AOOO #
01
LEAX O,X
PULS 0
Logic Operations Instructions
AND B to A PSHS B
(BAA-A) ANOA ,S+
AND A to B PSHS A
(AAB-B) AN DB ,S+
Arithmetic shift left 0 ASLB
ROLA
Logic shift right 0 LSRA
RORB
Test Operations Instructions
Bit test B to A PSHS B
(B/\A) BITA ,S+
Compare B to A PSHS B
(A- B) CMPA ,S+
Compare A to B PSHS A
(B-A) CMPB ,S+
Compare Y to X PSHS Y
(X -V) CMPX ,S++

88
 REVIEW QUESTIONS
1. What is the diHerence between ABX and LEAX B, X?

2. Why is the MUL operation an unsigned multiply operation?

3. Which 6809 arithmetic instruction will allow you to convert an 8-bit signed
number in accumulator B to a 16-bit signed number in accumulator D?

4. Write an instruction sequence which will compute the U stack pointer with
the product of accumulators A and B. Then, stack all the internal register
contents on the U stack defined by this pointer.

5. Write the correct op-code listing for the instruction sequence in Question 4.

6. How many MPU cycles would be required to execute the program in

Questions 4 and 5?

7. What is the diHerence between arithmetic shift left (ASL) and logic shift
left (LSL)?

8. What are the functions of the ANDCC and ORCC instructions?

89
 9. How would you clear a CCR flag bit?

10. How would you set a CCR flag bit?

Il. Interpret the following:

a. ORCC # b. ANDCC # c. ORCC #
FF AF 00

12. What are the three main categories of test instructions?

13. What is the purpose of the test instructions?

14. The BIT instruction performs a operation and only affects

the and _ _~__ CCR flags.

15. The CMP instruction performs a operation.

16. Which of the 6809 registers can be compared?

90
17. Which CCR Hags are affected by the CMP instruction?

18. What can be tested with the TST instruction and what does the test
indicate?

19. Which CCR Hags are affected by the TST instruction?

20. Determine the CCR Hag status after execution of the following instruc-
tions (assume accumulator A contains 5F):
a. BITA # b. CMPA c. TSTA
20 5F

ANSWERS
1. ABX is an inherent instruction which will add the unsigned contents of
accumulator B to the X register. LEAX B, X is a 2-byte instruction which
will add the signed contents of accumulator B to the X register.
2. To facilitate multiprecision (multibyte) multiplication operations.
3. Signed extend (SEX)
4. MUL
TFR D, U
PSHU CC, A, B, DP, X, Y, S, PC
5. From Tables 3-2 and 4-2 and Figs. 2-7 and 3-6 the correct op-code listing
would be: .
MUL 3D
TFR D, U 1F
03
PSHU 36
FF
6. From Tables 3-2 and 4-2 the above program would require 35 MPU cycles
to execute. The MUL instruction requires 11, the TFR requires 7, and the
PSHU requires 17. Note that 5 MPU cycles plus 1 cycle for each byte
pushed are required for the PSHU instruction.
7. There is no functional difference between these two instructions.
8. The ANDCC and ORCC instructions are used to set and clear the CCR
Hags.
9. To clear a CCR Hag bit you would AND a logic 0 with the respective Hag
bit position using the ANDCC instruction.
10. To set a CCR Hag bit you would OR a logic 1 with the respective Hag bit
position using the ORCC instruction.

91
11. a. This instruction will set all the CCR flags since a logic 1 is being oRed
with all CCR bit positions.
b. This instruction will clear the F and I flags since logic Os are being
ANDed with CCR bit positions 4 and 6.
c. This instruction will not accomplish anything since logic Os are being
oRed with all the CCR flags.
12. Logic bit test (BIT), arithmetic compare test (CMP), and byte test (TST)
for zero, positive, or negative
13. To test data, affecting only the condition code register for conditional
branch purposes. No result is generated.
14. ANDing, N, Z
15. Subtract
16. Accumulators A, B, and D and any of the indexible registers (X, Y, S, U)
17. The N, Z, V, and C flags
18. The TST instruction can be used to test the contents of accumulators
A and B or any memory location for a positive, negative, or zero quantity.
19. Only the N and Z flags
20. a. The N flag will be cleared. The Z flag will be set indicating a zero result
from the ANDing operation. All other flags are not affected and might be
set or cleared as the result of some previous operation.
b. The Z flag will be set, indicating a zero result from the subtract operation.
The C flag will also set since a last carry (borrow) is generated as a
result of the twos complement operation. The N and V flags will be
cleared, and all other flags are not affected by the operation and might
be set or cleared as the result of some previous operation.
c. The N flag is cleared, indicating a positive value in accumulator A.
The Z flag is also cleared, indicating a nonzero value in accumulator A.
The V flag will always clear with the TST operation. All other flags
are not affected by the operation and might be set or cleared as the
result of some previous operation.

92

..
 CHAPTER 5

Branch and Miscellaneous

Instructions

INTRODUCTION
The last two instruction categories that we need to discuss are the
branch and miscellaneous instructions.
The instructions that give the 6809 decision-making capability or
intelligence are branch instructions. These instructions are normally
used after arithmetic, logic, or test instructions which set or clear the
condition code register (CCR) flags according to the result of the
operation. The branch instruction will make a decision based on the
results, as indicated by the CCR flags status. When a branch is ini-
tiated, a new address is loaded into the program counter and this
causes the program to alter its flow so that program execution con-
tinues starting at the new address specified by the branch operation.
The 6809 instruction set contains 18 branch instructions. Each of
these instructions is available in a short- or long-branch version
which utilizes relative addressing, as discussed in Chapter 2.
The last instruction category, miscellaneous, is made up of instruc-
tions that do not fit conveniently in any of the previously discussed
categories. Such instructions as jump (JMP), jump to subroutine
(JSR), software interrupt (SWI), return from interrupt (RTI), etc.,
are included in this category. Many of these instructions will be
familiar to 6800 users; however, there are a few surprises. The 6809
includes three separate software interrupts such that there will al-
ways be one available to the end user. Many 6800 firmware packages
used the one software interrupt available and left the end user with-
out this capability. The 6809 CWAI instruction replaces the 6800

93
WAI instruction. The CWAI instruction is similar to W AI; however,
it is a 2-byte instruction which allows you to clear any of the CCR
flags. Finally, the 6809 instruction set includes an instruction that
will allow you to synchronize the system software to an external
hardware process. This instruction is called SYNC and should prove
valuable in large system applications where rapid data transfers are
common.

OBJECTIVES
At the end of this chapter you will be able to do the following:

• Describe the three categories of 6809 conditional branch in-

structions.
• List each 6809 branch instruction along with its complement
( opposite) branch instruction.
• Understand how branch instructions are used in a program to
make decisions based on the results of arithmetic, logic, or test
operations.
• Explain what happens when CWAI is executed and how this
differs from the 6800 W AI instruction.
• Understand the difference between the three 6809 software in-
terrupts and explain what happens when any of the software
interrupts are executed.
• Understand what is meant by the term "absolute indirect ad-
dressing."
• Explain how to synchronize the main program to an external
hardware event by using the SYNC instruction.
• Understand what is meant by the "syncing state."
• Explain how the SYNC instruction differs from the CWAI in-
struction.
• Understand how to implement several 6800 instructions which
are not part of the 6809 instruction set.

BRANCH INSTRUCTIONS
The 6809 branch instructions are listed in Table 5-1. All of the
6809 branch instructions use relative addressing (refer to Chapter
2). Branch instructions can be divided into two general categories:
unconditional branches and conditional branches.
The unconditional branch is one that causes the program to
branch (or not branch) regardless of any conditions. In the 6809
these branches are the branch always (BRA), branch to subroutine
( BSR), and branch never (BRN) instructions. The BRA and BSR
instructions will cause the 6809 to branch to the destination address

94
 Table 5-1. 6809 Branch Instructions
Mnemonic Operation Branch Test
BCS BCS Branch if the carry (C) flag is set C= 1
lBCS
BEQ BEQ Branch if the register contents are Z= 1
lBEQ equal to the memory contents
(Z flag set)
BGE BGE Branch if the signedregistercontents N'tV=O
lBGE are greaterthan orequalto the signed
memory contents
BGT BGT Branch if the signed reg ister contents Z v (N 'I V) = 0
lBGT are greater than the signed memory
contents
BHI BHI Branch if the unsigned register con- CvZ=O
lBHI tents are higher than the unsigned
memory contents
BHS BHS Branch if the unsigned register con- C=O
lBHS tents are higher than or the same as
the unsigned memory contents
BlE BlE Branch ifthe signed register contents Z v (N 't V) = 1
lBlE are less than or equal to the signed
memory contents
BlO BlO Branch if the unsigned register con- C= 1
lBlO tents are lower than the unsigned
memory contents
BlS BlS Branch if the unsigned register con- C vZ = 1
lBlS tents are lower than or the same as
the unsigned memory contents
BlT BlT Branch if the signed register contents
lBlT are less than the signed memory
contents
BMI BMI Branch if minus (N flag set) N= 1
lBMI
BNE BNE Branch if the register contents Z=O
lBNE are not equal to the memory contents
(Z flag cleared)
BPl BPl Branch if plus (N flag cleared) N =0
lBPl
BRA BRA Branch always (unconditional) None
lBRA
BRN BRN Branch never None
lBRN
BSR BSR Branch to subroutine None
lBSR
BVC BVC Branch if the overflow (V) flag is V =0
lVBC cleared
BVS BVS Branch if the overflow (V) flag is set V=1
lBVS

95
regardless of any conditions. However, the BSR instruction is used
to call subroutines with the program counter's contents being saved
on the hardware (S) stack such that proper return to the main pro-
gram is accomplished. This instruction is very similar to the jump to
subroutine (JSR) instruction to be discussed shortly. The BRN in-
struction is new and was not available in the 6800. This instruction
is actually a 2- or 4-byte no-operation (NOP) instruction. The 6809
will cycle through the instruction byte ( s) and relative address offset
without altering its execution. On the surface you might think this is
a meaningless instruction and wonder why it was included in the
6809 instruction set. You can, however, bury or hide an instruction
op code as the relative address offset. For example, when the 6809
first cycles through the BRN instruction, it will read the buried (hid-
den) op code as a relative address offset and no operation will result.
Then, later in the program, you can jump back to the buried (hid-
den) op code for its execution. This saves programming steps and
is a useful trick to remember.
The remaining 6809 branch instructions are conditional branches.
The conditional branch is one which is dependent upon some condi-
tion as indicated by the condition code register. If the condition is
met, the branch will occur. If not, the program will continue to the
next sequential instruction without branching. Conditional branch
instructions will normally be used after one of the test or arithmetic/
logic instructions discussed in Chapter 4. However, these instruc-
tions can be used after any instruction that operates on a register,
setting or clearing the condition code register flags according to the
result of the operation. The branch will occur (or not occur) based
on the condition code register flag ( s) status at the time the condi-
tional branch instruction is encountered. Several of the conditional
branch instructions, such as the BEQ, BNE, BCS, BCC, BVS, and
BVC, involve a simple check of one of the condition code register's
status flags, and are obvious. For example, BEQ/BNE is a direct
check of the Z-flag status. We will refer to these as simple branches.
The remaining conditional branches can be subdivided into two
categories, signed conditional branches and unsigned conditional
branches. The signed branches are used when operating on twos
complement data. Unsigned branches are used for operating on non-
twos-complement data. The unsigned branches are not, in general,
useful after instructions such as LD, ST, INC, DEC, TST, CLR, or
COM.
Note from Table 5-1 that both the signed and unsigned branches
cause the program to alter its execution as the result of some logical
combination of the condition code register flags.
Finally, Table 5-2 lists the three categories of conditional branch
instructions just discussed, that is, simple, signed and unsigned. In

96
 Table 5-2. 6809 Conditional Branch Instructions
Simple Conditional Branches
Condition Complement Condition
BEQ BNE
BMI BPL
BCS BCC
BVS BVC
Signed Conditional Branches
Condition Complement Condition
BGT BLE
BGE BLT
BEQ BNE
Unsigned Conditional Branches
Condition Complement Condition
BHI BLS
BHS BLO
BEQ BNE

Table 5-2 each branch instruction has its complement (opposite)

branch condition listed next to it. For example, BEQ provides the
opposite test than that of BNE, BLT provides the opposite test than
that of BGE, and so on. In addition, note that BEQ/BNE falls into
all three categories of conditional branches. The branch instruction
op codes are given in Table 5-3.
Now, let's look at some examples involving branch instructions.
Verify their proper execution on your 6809-based system or trainer.
Example 5-1: Using the SEQ Instruction
Suppose the 6809 encounters the following instruction sequence in
your program:
LOY #
FC
50
LEAY,_Y
CMPY
00
00
[. BNE
Fa

What will happen?

This instruction sequence first loads the Y register immediately
with FC50. The Y register is then decremented by the LEAY instruc-

97
 Table 5·3. Branch Instruction Op Codes

Instructionl Relative 5 3 2 1 0
Forms OP ,,-,' # Description H N Z V C
BCC BCC
LBCC
24
10
24
3
5(6)
2
4
Branch C =0
Long branch
C=O
·· ·· ·· ·· ··
BCS BCS
LBCS
25
10
25
3
5(6)
2
4
Branch C = 1
Long branch
C=1
·· ·· ·· ·· ··
BEQ BEQ
LBEQ
27
10
27
3
5(6)
2
4
Branch Z = 1
Long branch
Z=1
·· ·• ·· ·· ··
BGE BGE
LBGE
2C
10
2C
3
5(6)
2
4
Branch ;;?;zero
Long branch ;;?;
zero ·· ·· ·· ·· ··
BGT BGT
LBGT
2E
10
2E
3
5(6)
2
4
Branch >zero
Long branch>
zero
·· ·· ·· ·· ··
BHI BHI
LBHI
22
10
22
3
5(6)
2
4
Branch higher
Long branch
higher
·· ·· ·· ·· ··
BHS BHS 24 3 2 Branch higher
or same · · · · ·
LBHS 10
24
5(6) 4 Long branch
higher or same · · · · ·
·· ·· ·· ·· ··
BLO BLO 25 3 2 Branch lower
LBLO 10 5(6) 4 Long branch
25 lower
BLS BLS 23 3 2 Branch lower
or same · · · · ·
LBLS 10
23
5(6) 4 Long branch
lower or same · · · ·• ·
·· ·· ·· ··
BLT BLT 20 3 2 Branch <zero
LBLT 10
20
5(6) 4 Long branch <
zero ·
·· ·· ·· ·· ··•
BMI BMI 2B 3 2 Branch minus
LBMI 10 5(6) 4 Long branch
2B minus
BNE BNE
LBNE
26
10
26
3
5(6)
2
4
Branch Z = 0
Long branch
Z=O
·· ·· ·· ·· ·
BPL BPL
LBPL
2A
10
2A
3
5(6)
2
4
Branch plus
Long branch
plus
·· ·· ·· ··• ··
·· ·· ·· ··
BRA BRA 20 3 2 Branch always
LBRA 16 5 3 Long branch
always ·
·· ·· ·· ··• ··•
BRN BRN 21 3 2 Branch never
LBRN 10 5 4 Long branch
21 never
BSR BSR 80 7 2 Branch to • • •
subroutine
LBSR 17 9 3 Long branch to
subroutine · · · · ·
BVC BVC
LBVC
28
10
28
3
5(6)
2
4
Branch V = 0
Long branch
V =0
·· ·· ·· ·· ··
BVS BVS
LBVS
29
10
29
3
5(6)
2
4
Branch V = 1
Long branch
V=1
·· ·· ·· ·· ··
98
tion. After decrementing, the Y register is compared immediately to
0000. Recall that the compare operation subtracts its operand from
the specified register (Y in this case) and sets or clears the condition
code register flags accordingly. In this example you are concerned
with the Z flag and it will be set only when the Y register contents
are 0000. The BNE instruction will cause the program to branch
back to the LEAY instruction until the Z flag is set. Therefore, the
program will loop until the Y register is decremented down to zero.
This type of routine can be used to create time delays within your
program. You might want to verify the correct relative address offset
( F8) for the BNE instruction by counting the number of bytes re-
quired by each instruction in the loop.
Example 5-2: Using the BLT Instruction
Suppose that the 6809 encounters the following instruction se-
quence:

CMPA, x+
[ BLT
FC
LDB,-X

What will happen?

In this example the contents of the memory location specified by
the X register are compared to the contents of accumulator A. As
long as the signed accumulator A contents are less than the signed
memory contents, the BLT instruction will cause the program to
branch back to the CMPA instruction. Note that the CMPA instruc-
tion uses auto-increment by 1, on the contents of the X register.
Therefore, each time the loop is executed, the X register contents are
incremented. Thus consecutive memory locations are "searched"
until a value is found that is less than or equal to the existing accu-
mulator A contents. Once the value is found, it is loaded into accu-
mulator B for further processing. To load the proper value the LDB
instruction must use a pre-decrement on the X register since the
CMPA instruction had previously post-incremented the X register.
Example 5-3: Using the BLO Instruction
What would happen if the BLT instruction were replaced with BLO
in Example 5-2?
The only difference is that the 6809 would not look at the accumu-
lator A and memory contents as twos complement signed numbers.
The branch would occur as long as the unsigned accumulator A con-

99
tents are less than the unsigned memory contents. Thus the program
would be searching consecutive memory locations for a value which
is less than or equal to the existing unsigned contents of accumula~
tor A.
Example 5-4: Character Search
Suppose you wish to search a memory table of 3210 (2016 ) characters
for a specific character. Once that character is found, you will store
its address in the Y register. This character you wish to locate is an
"S," which has an ASCII representation of 5316 • The character table
begins at memory location 0100.
The instruction sequence in Fig. 5-1 win accomplish the character
search. Note that no instruction addresses need to be specified. Thus

LOA #
53 Load character to find
LOX #
01 Load beginning table address
00
LOB # Load length of table
20
MPA'X+ Same character?
BEa
If no, compare next 05 If yes, save character

1
character OECB address in V-register
[ BNE
F9
CWAI

LEA~-l,X
CWAI
00

Fig. 5~1. Instruction sequence for character search.

the program is totally position independent. The X register is being

used as the pointer register and is incremented using the auto-incre-
ment CMPA instruction to point to each successive table value until
a match is made. The LEAY instruction. will then save the charac-
ter's address in the Y register. This instruction decrements the X reg-
ister before the address value is transferred to the Y register. This is
done since, at this point in the program, the X pointer is one ahead
of the actual character address.
Example 5-5: Computed Go To
Suppose you wish to vector to a table based on a vector control byte.
The control byte has only 1 bit set (logic 1). The logic 1 bit position
in the control byte determines which of eight table vectors is to be
used to transfer program execution to the table. Assume, for example

100

J
 LDA#
08 Load control byte
LDX #
00 Load beginning address
10 of vector table
CLRB
LBRN
DDB#
02
LSRA
[ BCC
If carry clear, check FB ~ If carry set, vector
next bit position JMP[B,Xj.............J to proper table

Fig. 5-2. Instruction sequence to access vector.

purposes, that bit 3 of the control byte is set and the eight vectors
are located in sixteen (2 bytes per vector) consecutive memory loca-
tions beginning at address 0100. (Therefore the vector we wish to
access is located at address 0106.) Write an instruction sequence
which will access the proper vector, based on the control byte, and
transfer the program execution to the corresponding table.
The instruction sequence in Fig. 5-2 will accomplish the given
task. The control byte is first loaded into accumulator A. Then the
index register is loaded with 0100, which is the beginning address
of the vector table. Accumulator B will be used as a constant offset
to locate the proper vector. Each time a control byte bit is tested via
the LSRA and BCC instructions, accumulator B will be incremented
by 2. Therefore, since bit 3 of the control byte is set, accumulator B
will contain 0616 when the branch loop is broken. Thus the vector
at address 0100 + 06, or 0106, will be accessed by the JMP instruc-
tion. By using indirect addressing with the JMP instruction, program
control will be transferred to the table which is "pointed to" by the
vector located at address 0106. Note the significance of the long
branch never instruction (LBRN). The ADDB instruction is not
executed the first time through the routine, since it forms the relative
address offset of the LBRN instruction. However, if the C Hag is clear
after the LSRA instruction, the routine will branch back to execute
the buried (hidden) op code (ADDB). This will allow the begin-
ning address of the vector table to be initially loaded into the X reg-
ister, rather than an address which is two less than the beginning
vector table address. Think about it! This is an excellent example of
using the BRN instruction to hide or bury an instruction op code.

MISCELLANEOUS INSTRUCTIONS
The remaining instructions in the 6809 instruction set we have
categorized as miscellaneous, since they do not fit into any of the

101
 Table 5-4. 6809 Miscellaneous Instructions
Mnemonic Operation Operation Symbol
CWAI AND CC, then wait CC /\ 1M M-+CC
for interrupt Wait for interrupt
JMP Jump EA-+PC
JSR Jump to subroutine None
NOP No operation None
RTI Return from interrupt None
RTS Return from subroutine None
SWI SWI1 Software interrupt 1 None
SWI2 Software interrupt 2 None
SWI3 Software interrupt 3 None
SYNC Synchronize to interrupt None

previously discussed instruction categories. These instructions are

listed in Table 5-4. Many of the instructions listed here should be
familiar to 6800 users; for example, jump (JMP), jump to subroutine
(JSR), no operation (NOP), return from interrupt (RTI), and re-
turn from subroutine (RTS) all perform essentially the same opera-
tions as in the 6800. The JMP and JSR instructions, however, can
now be used with direct, extended, or any of the indexed modes of
addressing, including indirect addressing. Consult one of the previ-
ously referenced 6800 texts for a detailed discussion of the above
instructions. The miscellaneous instructions for the 6809 that we in-
tend to present in detail here are new, or improved, over other 6800
family instructions. They are: wait (CWAI), software interrupts 1,
2, and 3 (SWIl, SWI2, SWI3), and synchronize with interrupt
(SYNC).
The 6809 wait (CWAI) instruction is similar to the 6800 wait
(\;YAI) instruction in that it puts the processor in a wait for inter-
.rupt state. However, the 6809 C\;YAI is a 2-byte instruction: the in-
struction op code followed by a data byte. \;Yhen the CWAI instruc-
tion is executed, its data byte is ANDed with the existing contents of
the condition code register. The result of the ANDing operation is
placed in the condition code register. This operation will allow you
to alter the contents of the condition code register prior to its stack-
ing. In addition, if the CWAI data byte is 00 11" you will clear the
condition code register. Clearing the condition code register may be
desirable if it is known that its contents will not be needed for any
subsequent interrupt service routine. This will allow the service rou-
tine to begin with a "clean" (clear) condition code register slate.
However, if the CWAI data byte is FF 16, the contents of the condi-
tion code register will remain unchanged.
The sequence of events associated with the CWAI instruction is

102
 ( CWAI )
S-12 CC
t-----,
S-11 A
S-10 t----::'8----1
S-9 DP
S-8 XH
S-7 Xl
S-6 YH
S-5 Yl
S-4 UH
S-3 Ul
S-2 PC H
STACK 6809
REGISTER S-l PCl
CONTENTS S

RESET NMI
SEQUENCE SEQUENCE

YES YES

Fig. 5-3. CWAI sequence of events.

shown in Fig. 5-3. When the 6809 encounters the CWAI instruction,
it ANDS the CWAI data byte with the contents of the condition code
register, placing the result in the condition code register. Then the
E Hag of the condition code register is set. Why? The E Hag is set
since the next operation is to stack all the internal register contents
in the S stack. Recall that the E Hag is used for unstacking purposes
to tell the 6809 that, when set (logic 1), all the registers (except S)
have been stacked by a previous stacking operation. Note from Fig.
5-3 that the order of register stacking is the same as for the PSH and
PUL instructions discussed in Chapter 4. This stacking order is the
same for all the automatic stacking operations that the 6809 per-
forms. After the internal registers are stacked on the S stack, the 6809
enters a wait loop. The wait loop may be broken only by any of the
four hardware interrupts-RESET, NMI, IRQ, or FIRQ. Note from
Fig. 5-3 that the I Hag in the condition code register must be cleared
to allow the IRQ interrupt to break the wait loop, and the F Hag

103
must be cleared to allow the FIRQ interrupt to break the loop. The
CWAI ANDing operation will allow you to have some control over
the "breaking" of the wait loop. For example, setting the I flag just
prior to CWAI and using a 1016 CWAI data byte to preserve the I
flag's status will prevent an IRQ interrupt from breaking the wait
loop. The same can be done with the F flag to prevent an FIRQ
from breaking the wait loop. On the other hand, you can use CWAI
to assure that an IRQ, FIRQ, or both will be enabled. For example,
a CWAI data byte of EF 16 will enable IRQ; BF 16 will enable FIRQ;
and AF 16 will enable both IRQ and FIRQ. The hardware interrupts
will be discussed in detail in the next chapter.
Example 5-6: Executing the CWAI Instruction
Suppose the 6809 encounters the following instruction sequence:

LOA #
40
TFR A, CC
CWAI
40

Determine the condition code register contents after CWAI is exe-

cuted.
Since accumulator A is :first loaded with 4016 and then transferred
to the condition code register, the F flag will set and all other CCR
flags will be cleared. The CWAI data byte, 40 16 , will preserve the
F -flag status during the CWAI ANDing operation. Thus an FIRQ in-
terrupt will not break the wait loop. In addition, the E flag is set as
a result of the CWAI operation. Therefore the condition code regis-
ter contents will be 110000002 , or C016 •
If 3C 16 is the CWAI op code, determine the correct op-code list-
ing for the above instruction sequence.
From the tables and :figures provided in previous chapters the
proper op-code listing is:
LDA instruction op code: 86
data byte: 40
TFR instruction op code: IF
post byte: 8A
CWA.I instruction op code: 3C
data byte: 40

If the S register contains E60016 prior to executing the above se-

quence, at what address will the condition code register contents be
found in the S stack? From Fig. 5-3 the CCR contents would be

104
stacked at address (E6oo16 - 12 10 ), or E5F4 16 • Verify the above re-
sults on your 6809-based system or trainer.

There are three levels of software interrupts available to the 6809.

They are: SWIl, SWI2, and SWI3. Recall that a software interrupt
is an instruction which will cause the processor to vector to an asso-
ciated interrupt service routine. Software interrupts are normally
used to insert breakpoints in a program for program debugging and
are also useful in single-step routines, operating system calls, and
software development systems. In addition, hardware interrupts can
be simulated with software interrupts. Three software interrupt
levels were provided in the 6809 since it was found that the one level
which was provided in the 6800 was often used by ROM monitor
packages and was therefore not available to the end user. However,
it is quite unlikely that commercial software packages will use all
three 6809 software interrupt levels and thus allow at least one soft-
ware interrupt to be available for user systems. (Motorola promises
never to use SWI2 and encourages other 6809 commercial software
manufacturers to do the same.)
The three 6809 software interrupts have priorities in the following
order: SWIl, SWI2, and SWI3. The sequence of events which is ini-
tiated with any of the three software interrupts is shown in Fig. 5-4.
Note that once the present instruction is completed, the E flag of the
condition code register is set, indicating that all of the 6809 registers
( except S) are to be stacked in the S stack in the order shown in Fig.
5-4. If, after stacking, the SWIl interrupt is being executed, the F
and I flags are set to mask out any FIRQ or IRQ hardware interrupts
which might occur during the SWll interrupt service routine. If an
SWI2 or SWI3 is being executed, FIRQ and IRQ hardware inter-
rupts will not be masked out unless you set the F and/ or I flags dur-
ing the interrupt service routine. The 6809 then acknowledges ac-
ceptance of the software interrupt to external devices by providing
a logic 1 (high) level on the bus status (BS) output line. (The use
of this line will be discussed shortly.) The proper interrupt vector
is then loaded into the program counter, BS is brought back to a logic
o (low) level, and the appropriate interrupt service routine is exe-
cuted. Once the service routine has been completed, execution must
be directed back to the main program. This is done by using a return
from interrupt (RTI) instruction as the last instruction in the inter-
rupt service routine. The RTI returns the 6809 to its previous status
by automatically unstacking the old register contents from the S
stack.
As mentioned previously, a software interrupt (or any interrupt
for that matter) causes the 6809 to vector to the appropriate inter-
rupt service routine. The interrupt vector is the beginning address

105
 5,12 CC
5-11 A
5-10 B
5-9 DP
5-8 XH
5-7 Xl
1- E 5-6 YH
5-5 Yl
5-4 UH
5-3 Ul
5TACK 6809 5-2 PC H
REGI5TER
CONTENT5
¢ 5·1 PCl
5

1 - F,I

0- BA
1 - B5 Fig. 5·4. SWI1, SWI2, and
SWI3 sequence of events.

LOAD INTERRUPT
VECTOR INTO
PC

0- B5

INTERRUPT
SERVICE
ROUTINE

CONTINUE
RTI MAIN
PROGRAM

101
 Table 5-5. Memory Map for the 6809 Interrupt Vectors
Vector Locations Vector Assignment Relative Priority
FFFO:FFF1
FFF2:FFF3
FFF4:FFF5
FFF6:FFF7
Reserved
SWI3
SWI2
FIRQ
j
Low

FFF8:FFF9 IRQ
FFFA:FFFB SWI1
FFFC:FFFD NMI
FFFE:FFFF RESET High

of the respective interrupt service routine. Each of the 6809 software

and hardware interrupts has a unique vector located in the last 16
memory address locations (FFFO-FFFF).
The 6809 vector map is given in Table 5-5. Note that each inter-
rupt vector is assigned a pair of addresses within the map. These
address locations are normally in ROM and, therefore, are fixed and
not alterable by the end-user. Since the 6809 «looks" to these ad-
dresses to fetch the vector, which in turn is another address, the term
absolute indirect addressing is sometimes associated with interrupt
vectoring. In addition, Table 5-5 indicates the relative priority of
each interrupt, with RESET assuming the highest priority. You will
also note that vector address FFFO:FFFI has been reserved by Mo-
torola for possibly some future application. The 6809 hardw;re in-
terrupts will be covered in the next chapter.
The last instruction that we need to discuss is the synchronize to
interrupt (SYNC) instruction. This instruction is used to synchronize
the system software to external hardware events, such as rapid data
transfers from if 0 devices. When the SYNC instruction is encoun-
tered, all execution is halted and the 6809 goes into a wait-for-inter-
rupt loop. This is referred to as the syncing state. During this sync-
ing state the 6809 address and data lines are in a high-impedance
(tri-state) state or are effectively disconnected from their external
buses. Now, if a hardware interrupt occurs, two things can happen:
1. If the interrupt is not masked and is active for 3 MPU cycles or
more, the 6809 will break the wait loop and execute the respec-
tive interrupt service routine.
2. If the interrupt is masked or is active for less than 3 MPU
cycles, the 6809 will simply continue execution of the main pro-
gram by executing the next sequential instruction.
In the first case the SYNC instruction behaves very much like the
CVVAI instruction, except that it does not cause the internal register
data to be stacked. Any normal interrupt, if not masked, will prob-
ably cause the sync state to be broken in this way.

107
 In the second case, however, the SYNC instruction can be used to
synchronize the main program with an external hardware process.
Recall that one of the main disadvantages to using interrupts is that
they are not synchronous with program execution, meaning that they
are not scheduled and can happen at any time within the main pro-
gram. The SYNC instruction provides you with a means of using in-
terrupts and at the same time allows you to schedule the interruption
for optimum system efficiency. For example, an if 0 device, such as
a high-speed disk, can use a 6809 interrupt request line (IRQ or
FIRQ) and activate the line to indicate it is ready for data transfer.
Prior to SYNC you will set the respective interrupt mask bit (lor F)
and thus mask out a normal interrupt request. But, the active if 0
device strobe will cause the next instruction to be executed instead
of the normal service routine for that interrupt. The next instruction
would begin the data transfer process and the main program would
continue. In this way the hardware and software activities are syn-
chronized and time is saved since no vectoring or stacking is in-
volved. The program in Example 5-7 illustrates this process.
Example 5-7: Using the SYNC Instruction
Suppose that you wish to load 10010 bytes of data into memory from
a disk system at a particular point in the program. The program in
Fig. 5-5 will accomplish this task.

ORCC # Set I flag

10
SYNC Sync state
LDB #
64 Load table length
DA $($$)

t
(Disc Address) Transfer disk data
Get next data byte if STA,X + into 10010 consecutive
transfer not complete DECB memory locations specified
BNE by the X register
F9(8)
ANDCC # Clear I flag
00

Fig. 5-5. Instruction sequence to load data into memory.

It is assumed that the disk system is using the IRQ (interrupt re-
quest) line to initiate the data transfer. The first instruction sets the
I Hag in the condition code register to mask out any normal IRQ in-
terrupt. The SYNC instruction then halts the main program execu-
tion until the IRQ line is activated by the disk system. When acti-
vated, the main program will cause 10010 (64 16 ) bytes of data to be
stored in 10010 (6416 ) consecutive memory locations specified by the

108
 Table 5·6. Miscellaneous Instruction Op Codes

Inherent DIrect Extended ImmedIate Indexed Relative 5 3 2 1 0

Instructlonl
Forms OP rv II OP rv II OP rv II OP rv II OP rv II OP rv II H N Z V C
CWAI 3C 20 2 1

JMP OE 3 2 7E 4 3 6E 3+ 2+
JSR 90 7 2 80 8 3 AD 7+ 2+

NOP 12 2 1
SWI SWI 3F 19 1
SWI2 10 20 2
3F
SWI3 11 20 2 Software Interrupt 3 •
3F
SYNC 13 ..2 1 Synchronize to
Interrupt
RTI 38 6/15 1 Return from 7
Interrupt
RTS 39 5 1 Return from
subroutine

...
i
X register using auto-increment indexed addressing. The main pro-
gram then clears the I flag and continues. If, during the sync state,
an emergency situation developed, any of the other hardware inter-
rupts (NMI, FIRQ, RESET) could be used to break the sync state.
The miscellaneous instruction op codes are listed in Table 5-6. A
complete description of all the 6809 instructions is provided in Ap-
pendix A, and a 6809 instruction set summary is provided in the last
appendix for quick reference.
Finally, as you are now probably aware, many of the 6800 instruc-
tion mnemonics are not included in the 6809 instruction set. For run-
ing 6800 software on 6809-based systems, the translations provided
in Table 5-7 can be made to provide functionally equivalent 6809
operations. Some of these translations have already been discussed.
This completes the discussion of the 6809 software. Before going
on, it is important that you understand the material that has been
presented in the last five chapters, especially the addressing modes

Table 5·7. 6800 Equivalent Instructions

6800 Instruction 6809 Equivalent
ABA PSHS B; ADDA ,S++
CBA PSHS B', CMPA ,S
CLC ANDCC #FE
CLI ANDCC #EF
CLV ANDCC #FD
CPX CMPX
DES LEAS -1,S
DEX LEAX -1,X
INS LEAS 1,S
INX LEAX 1,X
LDAA LDA
LDAB LDB
ORAA ORA
ORAB ORB
PSHA PSHS A
PSHB PSHS B
PULA PULS A
PULB PULS B
SBA PSHS B; SUBA ,s+
SEC ORCC #01
SEI ORCC #10
SEV ORCC #02
STAA STA
STAB STB
TAB TFR A,B; TST A
TAP TFR A,CC
TBA TFR B,A; TST A
TPA TFR CC,A
TSX TFR S,X
TXS TFR X,S
WAI CWAI #FF

110
(Chapter 2). If you still feel uncomfortable with programming the
6809, go over the material again. If at all possible, obtain a 6809-
based system or trainer to get some "hands-on" programming experi-
ence. Run the examples presented here on the system and make up
your own short routines. The more programming practice you get,
the better you'll understand how to use the 6809.

REVIEW QUESTIONS

1. The three 6809 unconditional branch instructions are ~ ~_

and _

2. In what ways are BSR and JSR similar? DiHerent?

3. Conditional branches can be divided into three categories. They are

, ~ , and ~ conditional branches.

4. BLO can be replaced with since the branch test is the same
for both branches.

5. The complement branch condition for BMI is _ for BGE is

_ _ _ _ _; and for BHI is _

6. The prime advantage to relative addressing is ,

7. What is the functional diHerence between the following two instructions:
BRA and JMP 3,PC
05

111
 8. Why is the E flag of the condition code register set during the execution
of CWAI?

9. You want to clear the I flag such that an interrupt request (IRQ) will be
acknowledged during CWAI. All other Hags should remain unchanged.
What would be the proper CWAI assembly code?

10. What 6800 code listing does the above CWAI code replace?

11. If bit 7 of the control byte in Example 5-5 were set, what vector address
would be accessed?

12. Which software interrupt automatically sets the F and I flags to mask out
FIRQ and IRQ interrupts?

13. Acceptance of an interrupt is indicated on the 6809's _ _~__ line.

14. The SWI2 interrupt vector is located at address _

15. An addressing mode which is sometimes associated with vectoring is

16. What instruction could be replaced by the following sequence:

PSHS ALL
JMP [FFF4]

17. Why is the above instruction sequence not exactly like SWI2?

18. What instruction could be replaced by PULS PC?

112
19. What instruction could be used in lieu of RTI?

20. What is the main purpose of the SYNC instruction?

21. When in the syncing state, what will happen if an FIRQ is received and
the F flag of the condition code register is set?

22. What would happen if the F flag is cleared in the previous question?

23. How does SYNC diHer from CWAI?

24. What is the 6809 equivalent of the 6800 ABA instruction?

25. What is the 6809 equivalent of the 6800 DEX instruction?

ANSWERS
1. Branch always (BRA), branch to subroutine (BSR ) and branch never
(BRN).
2. They are similar since they are both used to call subroutines and cause
the program counter contents to be saved on the S stack. In addition,
they both require the use of RTS as the last subroutine instruction for
proper return to the main program. They are different because BSR uses
relative addressing and JSR can use direct, extended or indexed addressing.
3. Simple, signed, and unsigned
4. BCS (reference Table 5-1)

113
 5. BPL,BLT,BLS
6. Position independence
7. There is no functional difference. The JMP instruction will cause the
program to branch to the same location as the BRA instruction. Note that
the JMP is using program counter relative addressing and therefore is
also position independent.
8. The E flag of the condition code register is set during the execution of
CWAI since all of the internal registers (except S) are stacked during this
operation.
9. CWAI #
EF
10. CLI
WAI
11. OOIE
12. SWIl
13. Bus status (BS) output line.
14. FFF4:FFF5
15. Absolute indirect addressing
16. SWI2
17. The E flag is not necessarily set for stacking. To set the E flag, the instruc-
tion ORCC #80 should be added prior to the PSHS instruction.
18. RTS
19. PULS ALL
20. To synchronize the main program with external hardware events such as
data transfers
21. The syncing state will be cleared and the next sequential instruction will
be executed.
22. The syncing state will be cleared and the FIRQ interrupt service routine
will be executed.
23. SYNC does not cause the 6809 registers to be stacked as does CWAI. In
addition, CWAI does not allow for external hardware synchronization as
does SYNC.
24. PSHS B
ADDA ,S+
25. LEAX -1, X

114
 CHAPTER 6

6809/6809Elnput and
Output Signals

INTRODUCTION
Now that you have completed the chapters about the 6809 soft-
ware, you are ready to begin learning about the hardware aspects
of both the 6809 and 6809E. It should be pointed out at this time
that everything which has been discussed to this point will apply
to both the 6809 and 6809E, except where noted otherwise. Recall
that the 6809E is the off-chip clock version of the 6809. Thus the
differences between the two devices are in the available i/o sig-
nals and not the instruction set. Because the 6809E does not require
a crystal connection, two extra status lines are available. These two
lines will facilitate multiprocessor system applications.
In this chapter we will discuss the 6809 and 6809E i/o signals
in detail. For convenience, these signals have been broken down
into five functional categories. They are: powerIclock, datal address,
bus status, bus timing, and control. You will find that both the 6809
and 6809E provide much better capabilities in all of these categories
than did the 6800. For example, by decoding only five lines you can
determine exactly which interrupt vector is being fetched and thus
provide a complete interrupt acknowledge to an i/o device. In ad-
dition, the direct memory access (DMA) capabilities of the 6809 are
greatly enhanced over the 6800 by the addition of the DMAREQ
control line. In this chapter we will discuss three types of DMA
which are available for the 6809 and 6809E. They are: halt mode,
cycle stealing, and bus multiplexing DMA. Now, let's begin our
discussion.

115
 OBJECTIVES
At the end of this chapter you will be able to do the following:

• Describe the crystal and clock requirements of both the 6809

and 6809E.
• Explain the four possible MPU states of the 6809/6809E.
• Decode five 6809/6809E i/o signals to determine which of the
interrupt vectors is being fetched.
• Design a decoding circuit to provide the above interrupt vector
acknowledgment signal.
• Explain the relationship between the two bus timing signals,
E and Q.
• Understand how the 6809 can be interfaced to slow- peripheral
devices, such as slow memories.
• Describe three different methods by which the 6809/6809E can
be used to provide direct memory access (DMA) to peripheral
devices.
• Explain the sequence of events associated with each of the
6809/6809E hardware interrupts.
• Understand the differences between the 6809 and 6809E i/o
signals.

6809 PIN-OUTS
The 6809 "footprint," or pin configuration, is shown in Fig. 6-1.
As stated earlier, the 6809 is a 4O-pin HMOS (high-density NMOS)
device available in either a standard plastic package (P suffix) or
ceramic package (L suffix). In discussing the pin functions we will
divide the pin-outs into the follOwing five functional categories:
power/ clock, datal address, bus status, bus timing, and control. A
detailed discussion of each follows:

Power/Clock
As with all 6800 family devices, the 6809 requires a single +5-Vdc
±5-percent supply voltage. Maximum current drain is 200 mA, for
a maximum power dissipation of 1 watt. The two power connec-
tions are Vss at pin 1 (ground) and V DD at pin 7 (+5 Vdc ).
The 6809 has an internal clock oscillator/driver and therefore does
not require an external clock source as does the 6800. However, you
must supply an external parallel-resonant crystal between pins 38
and 39 (EXTAL and XTAL) to provide crystal control of the internal
oscillator's frequency. The standard 6809 operates with a maximum
internal frequency of 1 MHz. There is, however, an internal circuit
that divides the external crystal frequency by 4 to obtain the inter-

116
 MC6809

(Vss) GROUND HALT

(NMI) NON-MASKABLE INTERRUPT XTAL
(IRQ) INTERRUPT REQUEST EXTAL
(FIRQ) FAST INTERRUPT REQUEST RESET
(BS) BUS STATUS (MREADY) MEMORY READY
(BA) BUS AVAILABLE Qout
(V DD ) +5-VOLT POWER Eout
AO (DMAREQ) DMA REQUEST
A1 R/IN
A2 DO
A3 D1
A4 D2
A5 D3 DATA LINES
A6 14 D4
ADDRESS LINES A7 15 D5
A8 16 D6
17 D7

I
A9
18
;~:
A10
A11 19 ADDRESS LINES
A12 20 A13

Fig. 6-1. 6809 pin configuration.

nal operating frequency. Therefore a 4-MHz crystal must be used

to obtain a I-MHz internal operating frequency. Actually, you can
even use an inexpensive 3.58-MHz tv color-burst crystal and thus
provide an internal operating frequency of 0.895 MHz, which is
fast enough for many applications. The 6809 is also available in a
1.5-MHz version, the 68A09, and a 2.0-MHz version, the 68B09.
For a maximum operating frequency these two versions would re-
quire crystals of 6 MHz and 8 MHz, respectively.
Now a word about speed. Many microprocessors boast very high
clock frequencies as a selling point with the idea being that MPU
cycle time, and therefore overall processing speed, is greatly en-
hanced. This is true to some extent; however, they are not telling
the whole story. Clock frequency (MPU cycle time) alone is not
the only factor which controls the speed of a processor. A better
gauge of overall speed is processor throughput. This term takes into
account not only MPU cycle time, but other important factors such
as architecture, instruction set efficiency, addressing capabilities,
bus timing, etc. Because of these factors the processing throughput
of the 6809 is very high when compared with competitive devices.
Therefore the 6809's internal clock frequency need not be above
2 MHz to achieve an equal or better performance than that of its
competitors. At the same time, inherent high-frequency problems
are avoided. In any event, if an application does require superhigh
processing speeds, the solution is in a multiprocessor system and
not one processor with a lOO-MHz clock. Furthermore, the "bottom

117
line" is what the application requires. Once a processor( s) can do
the job in the time required, processor speed ceases to be an im-
portant design consideration.

Y1 C in Coul
4MHz 24 pF 24 pF (8) Component values.
6MHz 20 pF 20 pF
8 MHz 18 pF 18 pF
'--

Fig. 6-2. 6809 crystal connections.

The required 6809 crystal connections are shown in Fig. 6-2.

Note that two capacitors (C in and Cout) need to be connected from
the crystal's pins to ground. This connection will ensure optimum
chip performance. In addition, to minimize distortion the crystal
should be mounted as close as possible to the EXTAL and XTAL pins.
The crystal vendor specifications are given in the 6809 specification
sheet (refer to Appendix C). Motorola recommends that LC net-
works not be used in lieu of a crystal and also warns that the inter-
nal oscillator may take as long as 20 milliseconds to become opera-
tional after power-up.
You may also drive the 6809 with an external TTL or CMOS clock
signal. If this is desired, the signal must be applied to pin 38 (EXTAL)
with pin 39 (XTAL) grounded. The external clock signal will be di-
vided by 4 to establish the internal operating frequency.
DatalAddress
As you are now probably aware, there are eight data and sixteen
address pins located as shown in Fig. 6-1. Each pin will drive one
standard low-power Schottky (LS) TTL load plus eight 6800 family
devices at the rated bus speed. More than eight 6800-series devices
can be driven if the clock speed is reduced to lower the capacitive

118
loading effect of the bus. The data lines will typically drive 130 pF
and the address lines 90 pF. Both the data and address lines are
internally three-state buffered. The particular on/ off state of any
given line is a function of the various 6809 control signals. The asso-
ciated control signals and data/address bus timing will be discussed
shortly.
Bus Status
Two of the 6809's pins are used to communicate the MPU status
to peripheral devices. They are: bus status (BS) at pin 5 and bus
available (BA) at pin 6. Bus available (BA) provides an indication
of the three-state logic status of the data, address and R/W lines.
If BA=O, the processor is running and the data, address and R/W
three-state logic is on. If BA=I, the processor is in a halt condition
and the data, address, and R/W three-state logic are off or in the
high-impedance state, thereby effectively disconnecting the proces-
sor from the external data and address buses and making those buses
available to external devices. However, BA=1 does not imply that
the datal address bus structure will be free for more than one MPU
cycle. Bus status (BS) is used together with BA to indicate the MPU
state. There are four possible logic combinations of these two lines
and thus four unique MPU states. They are: normal (or running),
interrupt acknowledge (lACK), SYNC acknowledge, and halt (or
bus grant).
The above MPU states are shown with their respective BA/ BS
logic in Table 6-1. The normal or running state is obvious and needs
no further discussion. The interrupt acknowledge (lACK) state will
provide an indication (via BA/BS) to external devices that one of
the 6809 interrupts (RESET, NMI, IRQ, FIRQ, SWIl, SWI2, or
SWI3) has been accepted. The obvious use for the lACK state is to
provide an external i/o device with an indication that its interrupt
has been accepted. This can be done with external decoding logic
to detect the BA=O, BS=1 (lACK) state. In addition, if address
lines AI, A2, and A3 are also decoded with BA/ BS, the decoding
logic can indicate exactly which interrupt has been accepted. Recall
that when an interrupt is accepted, its interrupt vector is fetched.

Table 6·1. MPU States

Bus Bus
Available Status
MPU State (BA) (BS)
Normal o o
Interrupt acknowledge o 1
Sync acknowledge 1 o
Halt/Bus grant 1 1

119
Since each interrupt has a unique vector address assignment, one
of fourteen addresses (FFF2-FFFF) will be placed on the address
bus when the vector is fetched. Thus the BA/ BS logic will indicate
that an interrupt has been accepted and address lines AI-A3 will
indicate exactly which interrupt vector is being fetched. The simple
74154 decoding circuit shown in Fig. 6-3 could be used for this

15
14

••
A3 o •
A2 C 74154 •
•
A1 B
••
A • Fig. 6-3. lACK decoding
circuit.

2
1

G1
o
G2

BA-~~--~

BS--~

purpose. Here an active (low) output on line 2 would indicate that

an SWI3 interrupt has been accepted since SWI3 has an interrupt
vector assignment of FFF2:FFF3; an active output on line 8 would
indicate that an IRQ has been accepted since IRQ has a vector as-
signment of FFF8: FFF9, and so on. Address line AO does not need
to be decoded since all the interrupt vector addresses begin with an
even address and therefore Al is the least significant line whiCh
needs to be decoded. You could even use the active output of this
circuit to turn off the ROM containing the interrupt vectors. Then,
load your own vector on the data bus and thereby redefine the in-
terrupt service routine locations. Thus an external device can define
its· own interrupt vector.
The SYNC acknowledge state indicates that the 6809 is in the
syncing state as the result of a SYNC instruction. The syncing state

120
was discussed in the previous chapter. In the next chapter you will
see how this state is decoded to provide external hardware synchro-
nization.
The halt (or bus grant) MPU state means exactly what it says.
The MPU has halted all execution and the data, address and R/ W
lines are in their high-impedance state, thus making the data and
address buses available for external use such as direct memory ac-
cess (DMA). This state will normally exist as the result of a low
level on the DMAREQ or HALT pins (to be discussed presently).
Another line which could be considered a status line is the read/
write (R/W~ line at pin 32. This line serves the same purpose as
the 6800 R/W line, that is, to indicate the direction of data transfer
on the data bus. If R/W = 1, the 6809 is performing a read opera-
tion, while R/W = 0 indicates a write operation is being performed.
This line is three-state and is placed in its high-impedance state
whenever BA = 1, indicating that the data bus is available for ex-
ternal use. Another use for the R/W line is to determine valid mem-
oryaddresses. Recall that the 6800 has a valid memory address line
(VMA) which is used to indicate the validity of addresses placed
on the address bus. You had to use this line in your external decod-
ing circuits such that all external devices were disabled if a nonvalid
address (VMA=O) existed on the address bus. The 6809 does not
have a VMA line. Instead, when the 6809 is not using the data bus
for data transfer, it will place FFFF16 on the address bus and out-
put R/W = 1 and BS = O. This will replace the 6800 VMA function
since external decoding circuits can be designed to recognize the
above conditions as a nonvalid memory address state. Note that the
nonvalid memory address condition is distinguished from a RESET
interrupt vector fetch by the bus state (BS) line, since BS = 1 for a
vector fetch.

Bus Timing
The E out (pin 34) and Qout (pin 35) lines provide external clock
signals for timing and synchronization. E out is the standard 6800
family timing signal similar to the4J2 clock signal on the 6800.
When E out goes high, this indicates to i/o devices that the address
information has been placed on the address bus to provide a suffi-
cient setup time and that data is being placed on the data bus. This
line defines the MPU cycle and should be part of any external de-
coding scheme. The Qout line is a quadrature clock signal which
leads E out by 90°. The relationship between E out and Qout is shown
in Fig. 6-4. The frequency of each equals the internal operating fre-
quency, but they are displaced by 90° and thus provide four sepa-
rate clock edges for interfacing purposes. The 6809 read/write tim-
ing diagrams are shown in Fig. 6-5. Note that address information

121
Eout
START CYCLE
_--""""\J
END CYCLE

°out __1 "\

Fig. 6-4. Relationship between Eout
and Qouto
DAT~A----
ADDRESS
STABLE STABLE

E 2.4V

o 2.4V

RtW
ADDR
~-+----tACC - - - - - + I

DATA

MRDY
DMAIBREO

NOTVALID ~
(A) Read data from memory or peripherals.

j
E 2.4V
O.5V

o 2.4V.
O.5V

R/IN

ADDR
BA,BS
tooW-....,1
2.4V~""""""""""""""""""===~~~
DATA >--------cs:': DATA VALID
O.5V .....,............................_~H'""=n.:

NOTVALID ~

(B) Write data to memory or peripherals.

Fig. 6·5. Read and write timing diagrams.

122
is valid at the leading edge of Quut with data being valid during
E out . Data, in or out, is latched with the falling edge of E out •
The memory ready (MREADY) line (pin 36) is used in conjunc-
tion with the E uut and Qout timing signals. Recall that data is valid
on the data bus as long as E out is high. For some i/o devices, espe-
cially slow memories, this is not long enough to satisfy the data
setup, access, and hold time requirements of the device. Therefore
some means must be provided to stretch the E out and Qout pulses
such that slow memories will have time to respond to the 6809's
signals. This is the function of the MREADY line. By holding
MREADY low, you can stretch the E out and Qout pulses to extend
data access time. As long as MREADY is held low, the data valid
period will be extended until the MREADY line is returned high.
However, the maximum stretch period is 10 microseconds. (A 100-
microsecond stretch period can be obtained from a special-order
6809, at a higher price.) The effect of MREADY on E out and Qout
is shown in Fig. 6-6. Some of the 6809s produced early in the prod-
uct cycle (mask numbers G7F, T5A, P6F, and T6j\1) require that
the MREADY signal be synchronized with the crystal frequency.
Consult the 6809 specification in Appendix C for a synchronization
circuit, if you have one of these earlier devices.

I
,MAXIMUM
10p.s j
I ,~i
\_---~
r

MREADY
\\\\\\\\
Fig. 6·6. Effects of MREADY on E ont and Onnt.

Control
The remaining 6809 pins are used for control purposes. Our dis-
cussion will begin with HALT and DMAREQ and end with the
6809 hardware interrupts. The HALT pin provides for a hardware
salt of the 6809 operation. When you supply a logic 0 state to
pin 40, the 6809 will stop running at the end of the current instruc-
tion. When this happens the three-state buffers on the data, ad-
dress, and R/W lines will go into their high-impedance state and
effectively disconnect the 6809 from the external data and address
buses. As long as a low level exists at pin 40, the 6809 will remain
halted without any loss of internal register data, the E ollt and Qout
bus timing signals will continue normal operation, and the BA/BS

123
 logic will indicate the HALT' MPU state. When halted, the 6809
will not respond to any external control~s ex~ DMAREQ
(to be discussed shortly). However, if RESET or NMI interrupts
are received, they will be latched for execution after the halt mode.
The HALT function is normally used for hardware troubleshooting
and program debugging, since it allows an external device to con-
trol program execution one step at a time. It can also be used for a
halt mode direct memory access (DMA), since an external device
can gain control of the external buses. When not in use, you can
connect the HALT pin to the +5-volt dc supply for uninterrupted
system operation.
DMAREQ (pin 33) provides for another external method of stop-
ping the 6809. This line will normally be used to allow fast access
to the bus for direct memory access (DMA) or dynamic memory
refresh. It is appropriate at this time to say a few words about di-
rect memory access. This technique provides a means for high-speed
data transfers directly between a peripheral device, such as a Hoppy
disc, and memory without going through the MPU. The direct mem-
ory access function is normally controlled by a single-chip direct
memory access controller (DMAC). The DMAC takes bus control
away from the MPU and controls the data transfer directly between
memory and a selected peripheral device. The Motorola 6800 fam-
ily DMAC is the MC6844.
With the 6809, DMA can be performed by one of three methods.
They are: halt mode, cycle stealing, and bus multiplexing. With
halt-mode DMA the DMAC pulls the 6809 HALT pin low and takes
control of the address and data buses. The 6809 remains halted un-
til the data transfer is completed. The bus timing signals (E011t and
QOllt) will continue to provide timing for the data transfer. Cycle-
stealing DMA is accomplished when the DMAC pulls the DMAREQ
line (pin 33) low. When this happens the 6809 will stop instruction
execution at the end of the current cycle and acknowledge the DMA
request by setting both the BA and BS bus status lines. The 6809
address, data, and R/W lines will then be placed in the high-imped-
ance state and the DMAC can then take control of the bus structure.
The DMAC will have up to fifteen MPU cycles for data transfer
before the 6809 will automatically steal the bus structure for one
MPU cycle to refresh the internal MPU registers. When this hap-
pens the BA line will be cleared to signal the DMAC to get off the
bus structure. After one cycle, control will be transferred back to
the DMAC, provided that the DMAREQ line (pin 33) is still held
low. This process will be repeated until DMAREQ is returned to
a high (logic 1) level. The DMAREQ sequence of events is sum-
marized in Fig. 6-7. The third method of D MA, bus multiplexing,
provides that DMA peripheral devices be gated onto the bus struc-

124
Fig. 6·7. DMAREQ sequence
of events.

125
hue when E is low (MPU data not valid). With this method the
Ollt

6809 shares the bus structure (50/50) with the DMA peripheral
devices. This method is less efficient than the other two and requires
more external decoding logic. Therefore it is less often used. Con-
sult the 6809 specification in Appendix C for halt-mode (HALT)
and cycle-stealing (DMAREQ) timing diagrams. In a typical ap-
plication, DMA peripherals such as floppy discs would use the halt-
mode of DMA, with the cycle-stealing DMA used to refresh dy-
namic memory. Dynamic memory devices require refreshing every
2 milliseconds and are very high priority. Recall that the 6809 will
respond to DMAREQ when in the halt mode.
The last four 6809 pins that remain to be discussed represent the
four 6809 hardware interrupts: RESET, non-maskable interrupt
( NMI ), fast interrupt request ( FIRQ ), and interrupt request
(IRQ). Refer to Fig. 6-1 for their respective pin assignments. All
but one of these should be familiar to 6800 users. The new kid on
the block is ,FIRQ, and our previous discussions have introduced
you to this one. Now, let's discuss each interrupt in more detail.
First, note from Fig. 6-1 that they are all "barred" ( - - ), meaning
that they are all active low. However, only NMI is edge triggered
and thus activated by a high-to~low transition on pin 2. The other
three (RESET, FIRQ, and IRQ) are all level triggered and must
remain low for at least one MPU cycle to be properly clocked or
sensed by the 6809.
RESET is used to initialize or restart the system. It provides a
starting point for program execution by placing the address of the
first instruction to be executed in the program counter. A reset sub-
routine, located in ROM, will be required to perform the initiali-
zation task. Reset is always required after power is applied to the
system and should be held low until the internal clock oscillator is
fully operational, and then released. Recall that it may take up to
20 milliseconds for the internal clock to become operational. This
is not normally a problem with a manual reset; however, it must be
considered for automatic resets. The RESET pin uses a Schmitt-
trigger input and therefore a simple RC network can be used to
reset the system. However, this Schmitt-trigger input requires a
minimum of 4.0 Vde to represent a high (logic 1) level, whereas
other 6809 signals may use the standard TTL-compatible 2.4 Vdc
as a minimum value to represent a higU!ogic 1) state. An advan-
tage of using an RC network on the RESET input is that, because
of the RC time constant, other peripheral devices will have had
enough time to completely reset themselves before the 6809 com-
pletes its reset routine and begins any peripheral initialization rou-
tines. For example, when the 6809 starts up and initializes a pe-
ripheral interface adapter (PIA), you can be assured that the PIA

126
 Fig. 6·8. RESET sequence
of events.

is no longer in its own reset mode. The sequence of events which

take place when RESET (pin 37) is active is shown in Fig. 6-8.
When RESET becomes active for at least one MPU cycle the pres-
ent instruction is aborted and the direct page register is cleared.

127
 S-12 CC
NMI S-11 A
S-10 B

! S-9
S-8
S-7
DP
XH
XL
1 - E S-6 YH
S-5 YL

~
S-4 UH
S-3 UL
STACK 6809 S-2 PC H
REGISTER
CONTENTS
Q S-1 PCL
S

!
1 - F,I

!
0- BA Fi~ 6·9. NMI sequence
1 - BS
of events.

!
FETCH
INTERRUPT
VECTOR
(FFFC:FFFD)

!
0- BS

~
NMI
SERVICE
ROUTINE

!
MAIN
RTI PROGRAM

All of the other hardware interrupts (NMI, IRQ, and FIRQ) are
either masked out or disarmed. However, if a non-maskable inter-
rupt (NMI) occurs during the reset sequence, its active edge will
be latched (saved) and the NMi sequence of events (Fig. 6-9)
will be executed immediately after any instruction which loads the

128
S register (LDS; EXG R, S; TFR R, S; LEAS 1, X; etc.). The only
event which can inter~he reset sequence is a HALT or
DMAREQ. If no active HALT or DMAREQ exists, the bus status
signals, BA and BS, will be cleared to indicate the MPU-running
state. When RESET goes back high (to 4.0 volts) the bus status
signals ~ill indicate an interrupt acknowledge (BA=O, BS=l). The
RESET interrupt vector will then be fetched from address FFFE:
FFFF, BS will be cleared to indicate the MPU-running state and
the reset interrupt service routine will be executed. Now, if HALT
or DMAREQ is active during the initial reset sequence, the halt-
mode or cycle-stealing mode of DMA will take place. If RESET
goes back high during a DMA operation, the 6809 will complete
the reset sequence after the DMA operation is completed. Note:
HALT or DMAREQ may interrupt the reset sequence; however,
RESET will not interrupt HALT or DMAREQ.
The 6809 non-maskable interrupt (NMI) is very similar to the
6800 NMI. As the name implies, this inter~cannot be masked
by the programmer. The only time that an NMI is not accepted is
during the reset operation. Recall from our discussion of RESET
that the NMI logic is disarmed during the reset sequence. How-
ever, any NMI occurring during the reset operation will be latched
( saved), with the NMI sequence occurring after the first load into
the S register. In addition, if a non-maskable interrupt occurs dur-
ing the HALT operation, the active NMI state will be latched and
the NMI sequence will not be executed until after the MPU is re-
leased from the HALT state. The NMI sequence of events is
shown in Fig. 6-9. The E Hag is set to indicate that all of the internal
registers are to be stacked. The registers are then stacked in the
order shown. The F and I Hags are set to mask out any FIRQ or
IRQ (maskable) interrupts such that the NMI sequence will not be
interrupted by a maskable-type interrupt. However, another active
NMI could interrupt an existing NMI sequence since NMI is not
masked by the execution of the NMi sequence. If this is allowed
to occur repeatedly before the sequence can be completed, the
stack will definitely overHow. When the NMI interrupt vector is
fetched at address FFFC:FFFD, the bus status lines (BAIBS)
indicate an interrupt acknowledge (lACK). Once the vector is
fetched and loaded into the program counter, the bus status (BS)
line is cleared to indicate the normal MPU running state and the
NMI interrupt service routine is executed. When the service rou-
tine has been completed, execution must be directed back to the
main program. This is done by inserting a return from interrupt
(RTI) instruction as the last instruction in the interrupt service
routine. The RTI returns the 6809 to its previous status by unstack-
ing the old register contents.

129
 S 12 CC
--t
IRQ S-11 A
S-10 B

t
S-9 DP
S-8 XH
S-7 Xl
1 - E S-6 YH
S-5 Yl
UH

!
S-4
S-3 Ul
S-2 PC H
STACK 6809
REGISTER
CONTENTS
Q S-1
S
PCl

!
1 - I

t
0- BA Fig. 6-10. IRQ sequence
1 - BS of events.

t
FETCH
INTERRUPT
VECTOR
(FFF8:FFF9)

~
0- BS

~
IRQ
SERVICE
ROUTINE

~
MAIN
RTI PROGRAM

The two 6809 maskable interrupts are the normal 6800-t~n­

terruE!....!.equest (IRQ) and the new fast interrupt request (FIRQ).
The IRQ..~~.9uence of events is shown in Fig. 6-10. You may mask
out the IRQ by setting the I flag of the condition code register.

130
If the I Hag is cleared (logic 0), the interrupt will be accepted.
On~ccepted, the sequence of events for IRQ is similar to that
of NMI. The E Hag is set and all of the internal registers are stacked
on the S stack in the order shown. Then, the I Hag is set to mask out
any further IRQs until the present sequence is completed. Note,
however, that the F Hag is not set and therefore the IRQ sequence
may be interrupted by a fast interrupt request (FIRQ). You can
therefore conclude that FIRQ is of higher priority than TIITJ. When
the IRQ interrupt vector is fetched at address FFF8:FFF9, the bus
status lines indicate an interrupt acknowledge (lACK) MPU state.
Once the vector has been fetched, the bus status (BS) line is cleared
to indicate the normal running MPU state and the IRQ interrupt
service routine is executed. Again, you must use the RTI instruction
at the end of your interrupt service routine to get back to the main
program.
The sequence of events for FIRQ is shown in Fig. 6-11. Note the
differences from the IRQ sequence (Fig. 6-10). The E Hag is cleared
to indicate that only the program counter and condition code reg-
ister are to be stacked. Both the F and I H~are set such that !he
sequence will not be interrupted by any IRQs or further FIRQs.
However, your interr~ service routine could clear the I Hag if
the automatic FIRQ/IRQ priority was not desired. The remaining
events are the same as those of the IRQ sequence except that the
FIRQ interrupt vector is located at address FFF6: FFF7. As stated
earlier, the advantage of FIRQ over IRQ is in saving time when all
the internal register data need not be saved during the interrupt.
If additional register data need to be saved, you can always use
PSHS/PULS in your FIRQ interrupt service routine.

6809E PIN-OUTS
The 6809E, sister to the 6809, is also a 40-pin HMOS device and
is available in either a plastic (P) package or ceramic (L) package.
This device is intended primarily for multiprocessor system use,
since it provides extra signal lines for additional MPU status infor-
mation. An example of the 6809E's use in a multiprocessor system
will he given in the next chapter. The 6809E footprint is shown in
Fig. 6-12. Two extra signal lines (BUSY and LIC) are provided in
lieu of the standard 6809 crystal connect pins (XTAL and EXTAL).
Moreover, the 6809E includes an advanced valid memory address
( AVMA) line in place of the 6809 memory ready (MREADY) line
and a three-state control (TSC) line replaces the 6809 DMAREQ
line. As stated earlier, the 6809E is an off-chip clock version of the
6809. Therefore you must supply the required E in and Qin clock
signals at pins 34 and 35, respectively. The phase relationship be-

131
 FIRQ

!
0- E

! S-3
S-2
CC
PC H
STACK
PC,CC c> S·1
S
PCl

!
1 - F,I

~
0- BA
1 - BS Fig. 6-11. FIRQ sequence
of events.

!
FETCH
INTERRUPT
VECTOR
(FFF6:FFF7)

!
0- BS

!
FIRQ
SERVICE
ROUTINE

!
MAIN
RTI
PROGRAM

tween E in and Qin is the same as that of E out and Qout for the stan-
dard 6809 (Refer to Fig. 6-4). The Qin pin (pin 35) is fully TTL
compatible. However, the E in pin (pin 34) drives internal MOS
circuits which require levels which are above and below normal
TTL values. Fig. 6-13 shows a circuit which will provide the proper

132
 MC6809E

(V ss ) GROUND HALT
(NMI) NON-MASKABLE INTERRUPT TSC
(IRQ) INTERRUPT REQUEST (L1C) LAST INSTRUCTION CYCLE
(FIRQ) FAST INTERRUPT REQUEST 4..--------, RESET
(BS) BUS STATUS 5 '-------' (AVMA) VALID MEMORY ADDRESS
(BA) BUS AVAILABLE 6..--------, Ein
Y
(V OO ) + 5-VOLT POWER 7 '-------' Q out
AO 8..---------, BUSY
S
A1 9 '-------' R/W
A2 10 DO
U
A3 11 1·....- - - - ' 01
A4 12 02
PC
1 ' - - - - -.....
A5 13 03
14
04 DATA LINES
ADDRESS LINES A6
A7 15 05
A8 16 06

:::I
A9 17 07
A10 18
A11 19 ADDRESS LINES
A12 20 A13

Fig. 6-12. 6809E pin configuration.

Ein/Qin phase relationships and levels from one oscillator. The Einl
Qin lines from this circuit can be applied directly to pins 34 and 35,
respectively, of the 6809E. The EoutlQout lines will provide the

I
I 4f c OSC

I
J Q J Q
+5V
L-.c 74LS73(A) L-.c 74LS73(B)
680fl

~K Q K Q

I 74LS04

START OF '/4 V2 3/4 END OF

CYCLE CYCLE CYCLE CYCLE CYCLE

Ein
I ,
J '---
Qjn
If \
I r\

Fig. 6-13. 6809E clock generator circuit.

138
proper TTL signals for external timing. Note that the oscillator
frequency is four times the desired clock frequency (fe ). The clock
frequency obtained from this circuit will drive the 6809E directly
and is not divided by 4 with internal 6809E logic. The standard
operating frequency for the 6809E is 1 MHz (f e = 1 MHz). How-
ever, the 6809E is also available in 1.5-MHz (68A09E) and 2-MHz
(68B09E) versions.
Two additional status lines, BUSY (pin 33) and last instruction
cycle (LIC, pin 38) are provided with the 6809E. The BUSY out-
put line indicates that the 6809E is accessing memory. This line will
be high through the entire read/ write cycle, then return low when
the cycle is completed. In multiprocessor systems this signal is used
to supervise the system, so that only one processor has access to
global memory or peripheral devices at a given time.

• global memory I peripheral device-that amount of memory or

a peripheral device which is common to more than one, or to
all the processors in a multiprocessor system. Just the opposite
of a dedicated memory or peripheral device.

Of course, external bus arbitration logic will be required to inter-

pret the various MPU status signals and arbitrate the global mem-
ory Iperipherals between the processors.
The last instruction cycle (LIC) status line will also facilitate the
use of the 6809E in multiprocessor systems. Pin 38 will be activated
( high) during the last MPU cycle of any instruction. Therefore the
next cycle will be an op-code fetch. This line may be used to signal
multiprocessor bus arbitration logic that an MPU is about to com-
plete its instruction cycle and thus provide a head start for the arbi-
tration process. The 6809E also includes an advanced valid memory
address (AVMA) output line at pin 36. It will go to a: logic 1 state
when the 6809E is about to use the datal address bus structure.
A low-to-high transition at pin 36 indicates that the MPU will use
the bus structure during the following bus timing cycle. Thus in a
shared-bus system, other devices, such as DMACs and MPUs, are
altered so that the bus structure must be relinquished.
Finally, the 6809E three-state control (TSC) line (pin 39) is
similar to the 6809 DMAREQ line (.Ein 33). When TSC is active
high the 6809E address, data, and R/W lines will be placed in their
high-impedance state. When TSC is active (high) the MPU input
clock signals (Einl Qin) must be stopped, then restarted when TSC
is brought back low. Thus TSC can be used to provide a cycle-
stealing mode of DMA or for dynamic memory refresh. The re-
maining 6809E pins provide the same functions as their 6809 coun-
terparts, which have already been discussed. Furthermore, as stated

134
earlier, there is no difference between the 6809E and 6809 instruc-
tion sets.
That concludes our discussion of the 6809/6809E hardware. In
the next chapter some interfacing hints and ideas as well as some
special applications of both the 6809 and 6809E will be given.

REVIEW QUESTIONS
1. A 3.2·MHz crystal would provide a 6809 internal clock frequency of

2. How must the XTAL and EXTAL pins be connected to drive the 6809 with
an external TTL or CMOS clock signal?

3. The best measure of overall MPU speed is

4. What is the drive capability of each 6809/6809E data and address line?

5. The three 6809 bus status lines are _ ____, and _

6. The bus available (BA) line is at a level when the MPU

address and data lines are in their high-impedance state.
7. The four MPU states which are represented by the BA and BS status

lines are ~ _ _~_ ~ , and _

8. Suppose BA=O, BS=I, and A3 A2 Al = 110. What is the MPU doing?

9. Which 74154 output line would be active in Fig. 6·3 for the conditions
given in Question 8?

135
10. Which MPU state will be indicated on the bus status lines when a low
level (logic 0) is applied to the DMAREQ pin?

11. How does the 6809 indicate a nonvalid memory address?

12. How is the nonvalid memory address state distinguished from a RESET
interrupt vector fetch?

13. What is the relationship between EOll t (E in) and QOll t (Q in) ?

14. When is data valid on the 6809/6809E data bus?

15. What is the function of the 6809 MREADY pin?

16. What will happen if a non-maskable interrupt (NMI) occurs when a low
level is being applied to the HALT pin?

17. What will happen if a low level is applied to the DMAREQ pin when the
HALT pin is low?

18. A device which controls the DMA function is called a , and is

represented by the Me in the 6800 family.

19. The three ways that direct memory access can be accomplished with the

6809 are: _~~~_ ~ ~, and _

136
20. Using the DMAREQ line for cycle-stealing DMA, the MPU will steal the

address/data bus structure every ,_ _~_ MPU cycles to refresh the

internal register data.
21. The only 6809/6809E hardware interrupt which is edge triggered is the

_~ _ _ interrupt.
22. How long should RESET be held low when power is applied to the
system?

23. A high (logic 1) level is represented on the RESET pin by , _

volts.
24. The only two events which will interrupt the reset sequence are _

and .

25. What events could interrupt the NMI sequence?

26. What are the diHerences between the IRQ and FIRQ sequences of events?

27. 'Vhich interrupt is of higher priority, IRQ, or FIRQ?

28. The 6809E is best applied to systems.

29. The three additional bus status lines available to the 6809E are

_ _ _ _-), and _

30. The 6809E line which is similar to the 6809 DMAREQ line is _

ANSWERS
1. 0.8 MHz

137
 2. The TTL or CMOS signal is applied to EXTAL with XTAL connected to
ground. The applied frequency must be four times the desired clock fre-
quency.
3. Processor throughput
4. One standard Schottky TTL load plus eight 6800 family devices at the
rated bus speed
5. Bus available (BA), bus status (BS), read/write (R/W)
6. High
7. Normal, interrupt acknowledge (lACK), SYNC acknowledge and halt/bus
grant
8. BA=O and BS=1 represents the interrupt acknowledge (lACK) MPU
state and indicates that an interrupt vector is being fetched. Since A3 A2 Al
= 1102, the lower four address lines (A3 A2 Al AO) will represent either
11002 (C16) or 110116 (D16). In either case the non-maskable interrupt
(NMI) vector is being fetched. Note the status of AO does not have to be
known to decode the proper interrupt vector.
9. Line 12
10. Halt/bus grant
11. Address lines AO-A15 are all high (FFFF16), R/W = 1, and BS = 0
12. BS=O for a nonvalid memory address and BS=1 for a RESET interrupt
vector fetch
13. Eont (Eln) is similar to the 6800 <1>2 clock. Qont (Qln) is called the quadra-
ture clock. Eont (E 1n ) and Qont (Qln) are all the same frequency; however,
Qont (Qin) leads Eont (E 1n ) by 90° or ~~ clock cycle.
14. When E ont (Eln) is at a logic 1 level (high)
15. To stretch the Eont and Qont pulses a maximum of 10 microseconds such that
slow peripheral devices will have time to respond to the 6809's signals.
16. The HALT state will not be interrupted. However, the active NMI state
will be latched and the NMI sequence will be executed when the HALT
pin returns high.
17. The DMAREQ sequence of events (Fig. 6-7) will be executed.
18. Direct memory access controller (DMAC), MC6844
19. Halt-mode (HALT pin), cycle-stealing (DMAREQ pin), and bus multi-
plexing (external logic)
20. Fifteen
21. Non-maskable (NMI)

22. Until the internal clock oscillator becomes fully operational (approximately
20 milliseconds)

23. A minimum of 4 volts

24. HALT and DMAREQ

138
25. Any of the following:
Another NMI
RESET
DMAREQ
HALT
26. a. !!!Q sets the E Hag, FIRQ clears the E Hag.
b. lliQ stacks all internal registers; FIRQ stacks only PC and CCR.
c. !!!Q sets the I Hag; FIRQ sets both the F and I Hags.
d. !.!!!Lvector is at address FFF8:FFF9;
FIRQ vector is at address FFF6:FFF7.
27. FIRQ
28. Multiprocessor
29. BUSY, LIe, and AVMA
30. Three-state control (TSC)

139
 CHAPTER 7

6809/6,809E
Interfacing and Applications

INTRODUCTION
You are now ready to apply your knowledge of the 6809 to the
"real world." Interfacing the 6809 is very similar to interfacing the
6800. The major difference is in the use of the bus status (BS) and
DMAREQ signals, which were discussed in the previous chapter.
We will begin our discussion by developing a minimum 6809 system
consisting of scratch-pad RjW memory, ROM, and a peripheral in-
terface adapter (PIA). The 6820 j 6821 PIA will be used in just about
every 6809 system; thus a thorough understanding of this device
should be attained. A complete discussion of the PIA is provided in
Appendix B, if a review is needed.
Since the 6809 is mainly a systems device, most of our discussion
in this chapter will center on 6809 systems applications. After devel-
oping a minimum system we will discuss an expanded system which
provides serial data communication for crt's, modems, and printers
along with mass storage via a floppy disc system. Such a system can
stand alone or can be integrated into a multiprocessor system. The
1980s will see the development of many multiprocessor systems with
8-bit devices, such as the 6809, handling dedicated tasks and 16-bit
devices, such as the 68000, providing system control and supervision.
You will see how the 6809 can be interfaced to a 16-bit data bus for
such multiprocessor applications. In addition, you will see how the
6809E can be used in an 8-bit multiprocessor system. A 6809 data
acquisition system will also be presented.
Finally, for any new processor to be marketable the manufacturer

140
must develop a broad family of devices which support the processor.
To this end Motorola has developed a complete line of support de-
vices for the 6800. All of these devices are also directly compatible
with the 6809. In addition, several new devices are being developed
specifically for the 6809. For example, the 6809 has been referred to
as "a SOO-horsepower engine with a three-gallon gas tank" because it
is capable of addressing only a 64K memory space. However, Mo-
torola has developed a 6829 Memory Management Unit (MMU)
which expands the 6809 address space to 2 megabytes. This device,
along with others, will be presented in this chapter. Furthermore, in
an effort to support understanding of the 6809, Motorola has mar-
keted the MEK6809D4 evaluation system. One version of the system,
the D4A, is complete with power supply, hex keypad, and LED dis-
play module. Another version, the D4B, can be interfaced directly to
a crt data terminal. Both systems contain an excellent ROM monitor
(D4BUG) to provide efficient engineering evaluation or student
learning of the 6809. A general description of the D4A will be pro-
vided in this chapter. Now, let's open up the unending world of 6809
applications.

OBJECTIVES
At the end of this chapter you will be able to do the following:

• Develop a minimum 6809 system.

• Expand the minimum system to provide serial data communica-
tion, parallel data communication and mass storage via a floppy
disc system.
• Understand how parallel 16-bit data can be communicated to a
6809-based system.
• Design a 6809-based data acquisition system.
• Explain how a 6809 can be integrated into a multiprocessor
system.
• Describe the new 6809 family devices.
• Understand the major features of the MEK6809D4 evaluation
system.

A MINIMUM 6809 SYSTEM

A minimum 6809 microcomputer system would consist of read/
write memory (R/W), read-only memory (ROM), and parallel in-
terface device. Such a system is shown in Fig. 7-1. In this system we
are using all 6800 family devices such that device compatibility is
ensured. A 6810 is being used to provide 128 bytes of scratch-pad
R/W memory. For many dedicated applications this is all that is

141
 +5Vdc
vee 16 16
AO-A15
V ss
6809
MPU
XTAL

CJ 8 8
DO-D7
EXTAL 13

CONTROU
STATUSI
TIMING
6810 6830 6821
128 BYTE 1K BYTES PIA
R/W ROM PARALLEL
MEMORY 1/0
(pages FC,
AS REQUIRED (page 00) (page 50)
FD,FE,FF)

AS REQUIRED

Fig. 7-1. Minimum 6809 microcomputer system.

required. The ROM function is being provided by a 1K 6830 chip.

The 6830 is a mask-programmed ROM that will contain the interrupt
vectors, interrupt service routines, and subprograms required by the
specific application. Parallel interfacing to the 6809 is provided via
a 6821 peripheral interface adapter (PIA). An associated memory
map for this circuit is shown in Fig. 7-2. Note that we have assigned
the 6810 RfW memory to page zero (addresses 0000-007F), the
6821 PIA to page 50 (addresses 5000-5003) and the 6830 ROM to
pages FC, FD, FE, and FF (addresses FCOO-FFFF). The only criti-
cal assignment here is for the ROM, since the 6809 interrupt vectors
are located at addresses FFFO-FFFF.
The PIA has two 8-bit channels or ports that may be connected to
peripheral devices. These ports can be programmed as either input
or output ports. In fact, each bit within the port can be separately
programmed for either input or output data transfers. Once the PIA
is initialized by configuring the port lines, you will simply treat each
port as if it were a separate memory location. Then data can be
transferred between the 6809 and an if 0 device (via the PIA) by
using any of the 6809 load and store instructions. In addition, the
two PIA ports can be configured for all input or all output and 16-bit
data transferred by writing a small routine which would load or store
byte-size data between the two PIA ports and one of the 6809 16-bit
registers.
Now let's look at a couple of examples which involve 16-bit paral-
lel data communication for our minimum 6809 system. A complete
review of the PIA is provided in Appendix B, if needed.

142
 0000
6810 R/W MEMORY
Page 00
OOlF

NOT USED

Fig. 7-2. Minimum 6809

system memory map.

5000
PIA - Page 50
5003

NOT USED

FCOO

6830 ROM
Pages FC, FD, FE AND FF

FFFF

Example 7-1: 16-Bit Data Input

Using the system in Fig. 7-1 and its associated memory map (Fig.
7-2), write a routine which will input data to accumulator D from a
16-bit input device.
Let's assume that the PIA has already been initialized to configure
both ports (A and B) for input. Now, for 6800 systems you would
normally connect RSO (pin 36) of the PIA to address line AO, and
RSI (pin 35) to address line AI. This would result in the PIA mem-
ory map in Table 7-1. However, when interfacing the PIA to the
6809, if you reverse the above connections such that RSO is con-
nected to Al and RSI is connected to AO, then the PIA memory map
in Table 7-2 will result. Thus DRA and DRB are assigned to con-
secutive memory locations, and any of the load or store instructions
which are associated with the 6809 16-bit registers (LDD, STD,
LDX, STX, etc.) can be used to transfer 16-bit data between the
6809 and PIA. With this in mind, the following program will ac-
complish the given task:

143
 Table 7·1. PIA Memory Map for RSO to AO and RS1 to A1
PIA
Address Register Selected
5000 DDRA or DRA *
5001 CRA
5002 DDRB or DRB *
5003 CRB
'Depends on bit 2 of the control register.

LDA #
50
TFR A,DPR
LDD $
00
Note that we nrst store the PIA page number (50) into the direct
page register. Then direct addressing can be used to input the l6-bit
data directly into accumulator D. The port A data will form the most
signincant data byte and port B data will form the least significant
byte.
Example 7-2: Data Input Synchronization
Now suppose that your PIA is connected as shown in Fig. 7-3. You
want to synchronize the data input operation with the peripheral in-
put device such that each time the peripheral device interrupts the
6809 via CAl of the PIA, the 6809 will read a l6-bit data word and
store it in a memory location specified by the X register. In addition,
you want to provide complete handshaking with the input device.
Therefore you must acknowledge the data read operation via CA2 of
the PIA. Write a routine which will properly initialize the PIA, then
read a block of 10010 (6416 ) l6-bit data words using the synchroniza-
tion handshake method described above.
The routine in Fig. 7-4 will accomplish the given task. As in the
previous example it is assumed that the PIA is assigned to addresses
5000-5003 with RSO connected to Al and RSI connected to AO. The
routine nrst configures the PIA. The port A control register (CRA)

Table 7·2. PIA Memory Map for RSO to A1 and RS1 to AO

PIA
Address Register Selected
5000 DDRA or DRA *
5001 DDRB or DRB *
5002 CRA
5003 CRB
'Depends on bit 2 of the control register.

144
 16

16·BIT
PERIPHERAL
INPUT
DEVICE

Fig. 7-3. Sixteen-bit input synchronization.

is configured such that an interrupt request (IRQ) will be generated

to the 6809 when CAl is active high. Furthermore, CA2 will go high
when the interrupt is received, then go back low when the data is
read such that the handshake is complete. Once the PIA is initialized,
the I flag of the condition code register is set and the 6809 is placed

LDA#
50
TFR A,DPR
J- Load DPR with PIA
page number

CLRA ]
CLRB
Select DDRA and DDRB
STD$
02
STD$ ~ Configure ports A and B
00 ----.J for input

LDA#
27 } Configure CRA for
LDB # input handshaking
Fig. 7-4. Routine for data 04 via CA I and CA2.
input synchronization. STD$ Set CRB bit 2
02
ORCC# --1
Set I flag
10 --F
SYNC Syncing state
LDB #

}
C8 Read 10010 (64 16) 16-bit
LDY$ data words from PIA and
00 store in 200 10 (C8 16)
STY,X+ + consecutive 8-bit
DECB memory locations
BNE specified by X register
F4
ANDCC# ~
Clear syncing state
00 -S

145
in the syncing state by the SYNC instruction. Each time CAl is
active, the 6809 will read the l6-bit word into the Y register and then
store the data in two consecutive memory locations specified by the
X register. The routine will then branch back to the syncing state
until another IRQ is received. The read cycle will repeat until 10010
(64 16 ) 16-bit words have been read and stored in 20010 (C8 16 ) con-
secutive 8-bit memory locations. Note that a complete handshake
takes place between the 6809 and input device (via the PIA) each
time a data word is transferred.

In the coming years you will be seeing many 6809s being used in
multiprocessor 16-bit systems. The 6809s will handle dedicated tasks,
while a 16-bit microprocessor, such as the MC68000, will supervise
the system activity. Thus 16-bit data transfers similar to the ones
just shown will be quite common in such a system. The 16-bit
peripheral input device in Example 7-2 could be a 16-bit processor.

AN EXPANDED 6809 SYSTEM

As you are now aware the 6809 is a very versatile, high-perform-
ance microprocessor. Because of its software and hardware efficiency
it can be easily expanded in ways that first- and second-generation
devices (such as the 6800, 8080, etc.) could not, without sacrificing
performance. Such things as time sharing, high-level language inter-
pretation (Pascal, BASIC, FORTRAN, COBOL) can be performed
efficiently.
An expanded 6809 system is shown in Fig. 7-5. Here, most func-
tions of a microcomputer are provided. Note the use of the various
6800 family devices. Direct memory access is provided for the 6843
floppy disc controller (FDC) via the 6844 direct memory access con-
troller (DMAC). Serial communication for a crt, modem, and printer
is provided via the 6850 asynchronous communications interface
adapter (ACIA). Parallel i/o is provided via the 6821 PIAs. A sys-
tem such as this can be stand-alone or easily interfaced with a 16-bit
68000 system via the PIA interfaces as previously discussed. In fact,
several 6809 systems such as this could interface to a 68000 system-
a topic for another book. The expansion and application possibilities
are almost endless and only limited by the imagination.

MULTIPROCESSOR SYSTEMS
Multiprocessor systems will be the wave of the future. Many ded-
icated system functions can be handled by separate processors, each
a complete system in its own right. The separate processor systems
will contain dedicated R/W memory, ROM, and peripheral devices.

146
 16
16

EXTAL
OMAREO t-------i
Eoul
°out
R/W
6309
SA
SS
IRO
FIRO
16 NMI
RESET
HALT
MREAOY
00-07

RfW
MEMORY

Fig. 7-5. An expanded 6809 microcomputer system.

However, each dedicated system will share a common address/ data

bus structure and feed into a large system containing global memory
and peripherals that are shared by all the system processors. In many
cases the total system operation will be supervised by a 16-bit pro-
cessor, such as the MC68000. The system processor will coordinate
the dedicated processor activities in much the same way that an en-
gineering supervisor or project director coordinates the activities of
others to get the job done in the most efficient way possible.
As discussed earlier, the 6809E has been specially designed for
multiprocessor system applications. As you know, the 6809E has
extra status lines (LIC and BUSY) which are particularly suited for
multiprocessor systems. A simple multiprocessor system using two
6809Es is shown in Fig. 7-6. Obviously, many of the interfacing de-
tails are left out in this diagram and the actual system diagram
would be much more complicated. Fig. 7-6, however, should give
you the basic idea of a multiprocessor system.

REMOTE DATA ACQUISITION

Another common use of a processor like the 6809 is for automated
data acquisition. A typical 6809-based data acquisition system is

147
 ~2 {2

a:
DEDICATED DEDICATED wO
~~~
~

MEMORY MEMORY
0
Z AND AND <DOO
PERIPHERALS PERIPHERALS °oz
~if

8 DATA DATA , 8
16, , ADDR ADDR ' 16
5 ... STATUS STATUS' 5
4 ... ' CONTROL CONTROL'
, ,4
,
3 ... '
INTI I I liNT
, ,3

2
,, BUS ARBITRATION LOGIC CONTROL = RESET
HALT
VMA
TSC
a--' STATUS = R/IN

<{ a:
Cf)
:::l
f-
g: BA
BS
0 <{ Z
/' 2 f-
<{ 0 f- a f-
z BUSY
o <{ Cf) 0
L1C
, if
I~ I ~61 ~5 I 4 '3 INT = NMI
FTRQ
IRQ
2 GLOBAL MEMORY
CLOCK
GEN , ... AND
PERIPHERALS

Fig. 7·6. 6809E multiprocessor system.

shown in Fig. 7-7. A system such as this could be stand-alone or

part of a larger data acquisition and analysis system. Many manu-
facturing processes use some form of automated data acquisition to
obtain information about a produ'ct and its associated production
process. Individual product data are analyzed by a local system such
as the one in Fig. 7-7 for immediate product disposition. In addition,
a simple ongoing statistical analysis can be performed at the local
system for a given production run to provide the engineering staff
with up-to-the-minute product and process-related information. Cur-
rent information such as this can keep a process from getting out of
control, especially in high-volume production runs. A local system
can also be made to control process variables to automatically com-
pensate for changing product characteristics. In many cases, several
local systems will "feed" into a larger multiprocessor system which
will provide further engineering analysis, reporting, and permanent
data storage. For example, several of these 6809-based systems could
feed a larger 68000-based system.
Now let's take a closer look at the system shown in Fig. 7-7. First,
sufficient R/W memory is supplied for scratch-pad calculations and
temporary data storage. A ROM monitor will provide the routine
system operating software required for data analysis and communi-

148
 R/W
MEMORY ROM

+5VdC~VCC
~VSS AO-A15 I AS~AS~
REQUIR~~EQU;R~~
,
1~
r'-
16
"11 DXTAL
cp" C1
..... 6809
~ EXTAL MPU
:D AS REQUIRED CONTROL/
-~------'STATUS/TIMING

t~
CD
g ~...-oo;JIC---:----,BA

~!
;- 1 BS 07
8 ~.
8
e-
ll)
S'
~----:7"'--.., FIRQ 00- 1- 7' }5 - 8 ;NVERSION
A'4 }8
c
Il)
n
.a
'RQA
CA1
, I
1
~

r- CQNVERTER~
AID 1 4:1 r=
t====
ANALOG

In
!0" MUX INPUT

::s
en
'<
~
~
TTY
OR
CRT 0 20mA
TO
EIA
tJ Rx
6850
ACIA
PORT A
6821
PIA
8
START
CONVERSION

I
CHANNEL
SELECT

PORTSI < ~
~

, ~

1
~
J"START CONVERSION (SYNCING STATE) 1
,
~
~

.
...
CD ! .. CONTROL/STATUS/TIMING AS REQUIRED
cations. A high-level language interpreter could also be provided in
the local system ROM to enhance local engineering data analysis.
Operator communication is provided via a teletypewriter (tty) and/
or crt data terminal. Interfacing these devices to the 6809 would
require a 6850 ACIA for serial/parallel translations and external
logic to establish the required RS-232C (EIA) or 20-mA current-loop
serial communication formats. Four analog inputs are multiplexed
with a 4: 1 multiplexer circuit. Channel selection can be accom-
plished by using any two of the PIA port B data lines as output lines.
Anyone of the four analog inputs may then be selected by writing
the proper Is and Os to the respective port B data register (DRB)
bits. The A/ D converter will convert the selected analog signal to
digital. The digital information is then fed to port A of the PIA. A
syncing routine will be used to control the data transfer. After the
PIA is properly initialized, you will insert a SYNC instruction in
your program. When the 6809 executes the SYNC, BA=l and BS=O
to indicate the syncing state. The external digital logic will decode
BA/BS to provide a low-to-high transition to the A/D converter.
This transition will signal the conversion process to begin. Once the
analog signal has been converted to a digital byte of information, the
A/D converter will activate CAl on the PIA to provide an active
FIRQ for the 6809. If the F flag has been previously set, the 6809
will clear the syncing state and execute the next sequential program
instruction, which will read the port A data. Then, a branch back to
the SYNC instruction will cause the process to be repeated for the
next data byte. Thus a complete handshake is provided between the
6809 and A/D converter for each data byte transferred. All the soft-
ware details should now be familiar to you and you should now have
no trouble writing a routine which will properly configure the PIA
and acquire the data in the manner just described.

THE 6809 FAMILY

In addition to the peripheral devices that have already been dis-
cussed, there are many more devices which support the 6809. As
stated earlier, the 6809 is directly compatible with the existing 6800
family. A listing of existing 6800 family peripheral control devices
which will support the 6809 is provided in Table 7-3. Any of these
devices can be used with the 6809 in much the same way that they
are used with the 6800. Consult The Complete Motorola Microcom-
puter Data Library, Motorola Semiconductor Products, Inc., Box
20912, PhoeniX, Arizona 85036, for specifications and interfacing de-
tails of the devices listed in Table 7-3. Also, the M6800 Applications
Manual, available from Motorola, might be helpful along with other
6800 family application notes and texts.

150
 Table 7·3. 6800 Family Peripherals That Are Directly
Compatible With the 6809
Part Number Device
6821 Peripheral interface adapter
6828 Priority interrupt controller
6840 Programmable timer module
6843 Floppy disc controller
6844 DMA controller
6845 Crt controller
6846 ROM ilo timer
6847 Video display generator
6850 Asynchronous communication interface adapter
6852 Synchronous serial data adapter
6854 Advanced data link controller
6859 Data security device
6860 0- to 600·bps digital modem
6862 2400-bps modulator
68488 General-purpose interface adapter
68120 Intelligent peripheral controller
68540 Error detection and correction circuit

At the time of this printing, Motorola is in the process of develop-

ing additional peripheral devices to support the 6809. These devices
include a memory management unit (MC6829), floating-point ROM
(MC6839) and serial DMA processor (MC6842). The 6829 memory
management unit (MMU) permits you to expand the 64K address
space of the 6809 to a maximum of 2 megabytes as shown in Fig.

5 10 2M-BYTE
16 (A11'~15) (PA1~-PA20)
680916809E
MPU , J
, 6829
MMU , , ~ ADDRESS
SYSTEM
21 BUS

'11 ~ 11
I (AO-A10) J (AO-A10)

Fig. 7-8. Expanding from 65K to 2M bytes using the 6829 MMU.

7-8. The 6829 MMU combines the 11 lower 6809 address lines (AO-
A10) with ten address lines (PA11-PA20) of its own to form the
2-megabyte address space. This space consists of 1024 pages of 2K
bytes each. The 6829 address lines (PA11-PA20) specify the page
number, and the lower 11 6809 address lines (AO-A10) specify the
particular byte within the page. An internal mapping R/W memory
uses the upper five 6809 address lines (A11-A15) along with the
contents of an internal5-bit task register to form the ten most signifi-

151
cant address lines (PA11-PA20) of the 2-megabyte address space.
Dp to eight 6829s can be used in a system.
The 6839 floating-point ROM will facilitate the use of high-level
languages, such as Pascal, BASIC, and FORTRAN, on 6809-based
systems. The 6839 includes such floating-point operations as add,
su1:?tract, multiply, divide, square root, absolute value, negate, and
routines which provide binary/decimal conversions and allow you
to convert between integer and floating-point values.
Finally, the 6842 serial direct memory access (SDMA) processor
provides direct memory access for high-speed serial data links. Serial
data transfer rates of up to 4 megabits per second are possible. 'Nlany
future multiprocessor systems will be relying on a serial data link
for communication between processors. The SD'NfA can be used for
this purpose. The 6842 SDMA is a serial device, while the 6844
DMAC, which was previously discussed, is a parallel D'NIA device.
A brief product description of each of these new 6809 family de-
vices is provided in Appendix C. Consult the respective device data
sheets, obtainable from :Motorola Semiconductor Products, Inc., for
additional device information and interfacing details.

THE MEK6809D4 MICROCOMPUTER

EVALUATION SYSTEM
In an effort to support understanding of the 6809 and provide an
engineering evaluation tool, Motorola has marketed a relatively-Iow-
cost evaluation system built around the 6809. The MEK6809D4 sys-
tem is pictured in Fig. 7-9. In this section we intend on providing a
general description of the D4 system. In addition, some helpful hints
and examples will be provided to enhance your understanding of the
system operation. The following discussion will complement the
system instruction manual. Refer to the manual for additional infor-
mation and system details.
There are two different MEK6809D4 models available: the D4A
and D4B. The D4A evaluation system consists of two boards: an
MEK6809D4 microcomputer board and an MEK68KPD keypad/
power/ display board. In addition, a wall-outlet type transformer is
supplied with the system such that no external power supply is re-
quired for the minimum system configuration. The D4B model is a
single-board system and is intended for use with an RS-232C serial
terminal. All the associated RS-232C interface circuitry is provided
with the system. The user, however, must supply +12 V, +5 V and
-12 V power from an external source. We will confine our discussion
here to the self-contained D4A system.
A functional layout of each D4A board, with numbered refer-
ences, is provided in Figs. 7-10 and 7-11. An explanation of each
numbered reference follows.

152
 (A) MEK68KPD keypad/power/display board.

(B) MEK6809D4 microcomputer board.

Courtesy Motorola Semiconductor Products, Inc.
Fig. 7-9. MEK6809D4A microcomputer evaluation system.

MEK68KPD Keyboard/Power/Display Board (Fig. 7-10)

1. Hex keyboard-This allows the operator to enter data in hexa-
decimal (white keys) and system commands (blue keys).
When a key is depressed, a non-maskable interrupt (NMI) is
generated to the 6809. The NMI service routine then searches
for (decodes) the closed key. All of the keys are single func-
tion. A discussion of each key function will be given shortly.
2. Seven-segment LED display-This is an output display which
consists of 8 seven-segment LED displays. The system will dis-

153
 J J2 l
DISPLAYS
@I ~kAUX~
~~~~~~[@ ~~ I
USER PIA CONN CONN
'U'
If::jl _,
'WI IQI 1i::::J1

@I~
lr-"J ~

WIRE·WRAP AREA
CD ®
KEYPAD
E20 :.0::
~E§]E9~~
0000~
0~~~~
POWER SUPPLY
II ~- EXT +5V
(2) 0-- RED
C2JIT][]@]§ 0-- GREEN
@]0[I]~~ E3
--<::}- I -0-- BLACK
Fig. 7·10. MEK68KPD keyboard /power/display board.

RS·232C INTERFACE
® ItID STOP PIA

STOP COMPARATOR
®
ADDRESS
DECODE R/W MEMORY

®w
LOGIC
@

~~~
XTAL

EJ I (j) 6809
ABC 0

J3D~
ROM
-----------------, (j)
(2)
EDGE CONNECTOR BUFFERS

E F G H

M·70 BUS CONNECTOR

Fig. 7·11. MEK6809D4 microcomputer board.

play internal register, external memory, and address informa-

tion in addition to various user prompts to facilitate the use of
the system. The 8 displays use a multiplexing scheme to dis-
play messages and multiple characters.
3. Keypad/display PIA-This PIA is dedicated to the system and
serves two functions: keypad decoding and character display.
When a key is depressed, an interrupt is generated to the 6809.
Port B of the PIA then scans the keypad to determine in which
column the depressed key is located. Keypad data is input via
port A. In addition, for the display function the LED character
designations are output via port A and the displays are sequen-
tially enabled (multiplexed) by port B at a rapid rate to pre-

154
 vent display flickering. The keypad/ display PIA is assigned to
addresses EOF8-EOFB as follows:
ORA/DORA EOF8
CRA EOF9
DRB/DDRB EOFA
CRB EOFB
4. User PIA-This PIA is entirely available for user configuration
and use. All of the port A and port B data lines, along with their
associated control lines (CAl, CA2, CB1, CB2), are brought
out to the adjacent J2 edge connector. See the system user's
manual for the proper connector pin assignments. The user PIA
is assigned to addresses EOFC-EOFF as follows:
ORA/DORA EOFC
CRA EOFD
DRB/DDRB EOFE
CRB EOFF
5. Power supply-The MEK68KPD contains two +5-Vdc power
supplies. One supply is used to drive the 8 LED displays via
regulator VR1 and the other used to supply power for the D4A
logic via regulator VR2. An external 18-V center-tap trans-
former is supplied with the system and is to be connected as
shown in Fig. 7-10.
CAUTION: The on-board supply is designed to provide only
enough power for the minimum system configuration. If addi-
tional devices are added, an external supply is required. To con-
nect an external supply you must first remove the E2 and E3
connecting links. This will prevent damage to the on-board
supply regulators. Then, connect the external TTL quality +5-
Vdc source to the J1 connector as shown in Fig. 7-10.
6. Wire-wrap area-This area is provided for you to wire-wrap
your own external devices to the system. Both ground and +5-
Vdc supply buses are provided in this region for convenience.
The 6809 data, address, timing, status, and control signals are
available at the KPD and AUX connectors on the microcomputer
module board. See the system user's manual for the proper con-
nector pin assignments.
MEK6809D4 Microcomputer Board (Fig. 7-11)
1. 6809 MPU and crystal-This is the microprocessor· «heart" of
the system together with its 4x crystal, which establishes the
internal clock frequency.
2. Clock select-The jumper connector (J3) provides for selec-
tion of either internal or external clock control. See the system
user's manual for the proper jumper connections.

155
 3. R/W memory-Sockets are provided for 5K bytes of R/W
memory via five pairs of 2114 (lKx4) or equivalent R/W
memory chips. The minimum system includes two 2114s (lK
bytes) to provide for storing variables and to support the sys-
tem stack. These two chips are assigned to addresses E400-
E7FF. Any additional user R/W memory address assignments
are determined by the R/ W memory map connector.
4. R/W memory map-This is a jumper connector (]2) which
allows mapping of the additional user R/W memory in any
one of 16 possible 4K-byte blocks within the 64K-byte memory
space. See the system user's manual for the proper jumper
connections.
5. ROM-Eight ROM/EPROM sockets, A through H, are pro-
vided in this area for up to 48K bytes of ROM or EPROM.
Theminimum system includes one MCM68332 ROM (4Kx8),
which provides the system monitor called D4BUG. Any addi-
tional ROM address assignments are determined by the map-
ping ROM and RO"A-I type connector. ROM sockets A through
D will normally be used for larger ROMs (4K-8K) containing
editor/ assembler type programs. ROM sockets E and F can
be used for smaller (lK, 2K, or 4K) user ROMs/EPROMs of
the singleor triple supply variety. ROM socket G is reserved
for a special 2K ROM (R2-RS-232) required for the RS-232C
interface which is available on the D4B version of the
MEK6809D4 system. ROM socket H is reserved for the 4K
D4BUG ROM on both the D4A and D4B system versions.
6. Mapping ROM-The mapping ROM is provided with both the
D4A and D4B systems. This ROM provides you with a unique
and flexible means of mapping the eight ROM devices into
the 64K memory space. See the system user's manual for the
ROM mapping details.
7. ROM type connectors (J4 and J5)-These are jumper connec-
tors which allow you to select anyone of the following ROM
type options for ROM sockets A through G:

ROM/EPROM Sockets A through D

2Kx8 single supply (MCM2716, TMS2616, MCM68A316E)
4Kx8 single supply (MCM25A32, TMS2532, MCM68A332)
8Kx8 single supply (MCM68A764, MCM68A364)

ROM/EPROM Sockets E through H

1Kx8 triple supply (MCM2708, TMS2708)
2Kx8 triple supply (TMS2716)
2Kx8 single supply (MCM2716, TMS2516, MCM68A316E)
4Kx8 single supply (MCM25A32, TMS2532, MCM68A332)

156
 Connector J5 configures sockets A through F, and the J4 con-
nector configures sockets G and H. Note the extreme flexibility
that you have in the selection of the type of ROM to be used
in your system. See the system user's manual for the proper
jumper connections for your ROM configuration.
8. RS-232C interface-With the D4B system this area provides
the required RS-232C interfacing devices (ACIA, baud rate
generator, etc.). The sockets in this area will be omitted or
empty with the D4A system.
9. Stop PIA and comparator-The D4 system provides you with
a stop-an-address capability via a PIA and associated com-
parator logic. The purpose of a stop address is to enable a user
program to be executed until a certain predetermined address
is reached. The stop address is stored in the stop address PIA
ports A and B. When the address on the address bus is the
same as the stop address, the comparator generates a non-
maskable (NMI) interrupt via CAl of the PIA to stop the
program execution. The stop PIA is automatically initialized
as part of the system reset routine. -
10. Cassette interface-This will provide you with a means to in-
terface an inexpensive cassette recorder to the system. The
D4BUG monitor provides for the proper data formatting and
recovery functions via the P / Land FS keys on the keypad.
Data is stored and recovered by D4BUG software in a Kansas
City Standard, 300- or 1200-bps data format.
11. KPD connector-This 24-pin connector interfaces the micro-
computer board to the MEK68KPD board. The 6809 data and
selected address/ control lines are provided via this connector.
All the signals supplied to this connector are buffered. See the
system user's manual for the respective pin assignments.
12. AUX connector-This 16-pin connector is provided to allow
you to extend all of the 6809 address and control signals to the
MEK68KPD, for use in the wire-wrap area. All the signals
supplied to this connector are buffered. See the system user's
manual for the respective pin assignments.
Finally, the key functions of the ~1EK68KPD keypad are sum-
marized in Fig. 7-12. The control keys will allow you to do the fol-
lowing:

• Reset the system.

• Insert and delete breakpoints in your program.
• Display and alter the internal 6809 register contents.
• Examine and alter the contents of any R/vV memory location.
• Single-step a program.
• Calculate both 8- and 16-bit relative address offsets.

157
 Reset System causes (?) Used with Fs to change number
prompt in left-most display. of times in stop-address
Clears A,B,CC,DP,X.Y.U. routine.
Sets I & F flags.
I Loads E600 into S.
~unch/Load data between
nemory and cassette recorder.

Single step, beginning with PC

I contents. Also used with Fs
to enter breakpoints.

Memory examine and change.

Back-up register display and
memory examine routines.

Escape from any routine and

revert to register display
routine.

Display register contents. Press

GO to advance and M to backup.

Execute program at address

entered. Advance register
display, memory examine, and
breakpoint routines.

Fig. 7-12. D4A key functions.

• Punch (record) a cassette tape with a program in memory.

• Load (read) a cassette tape into memory.
• Provide for RjW memory and ROM hardware paging.
• Escape from a system routine without executing a reset opera-
tion.
• Select a program stop address and the number of times that this
address is executed before the program stops.
• Define up to 16 special user functions.
Refer to the system user's manual for a detailed explanation of
how to accomplish the above tasks. As you can see, the D4A is a very
versatile and powerful system. The following hints might be helpful
when you first begin to work with your D4A:
1. User memory for the minimum system is located at addresses
E400-E7FF.
2. The reset operation will always clear the program counter
(PC), accumulator A, accumulator B, X register, Y register, U
register, and direct page register (DPR). In addition, the F and
I Hags are lutomatically set with all other Hags cleared (CCR=
5016 ) and the hardware stack pointer (S register) is loaded
with the value E600. The reset operation will also erase any
breakpoints which have inserted into the user program.

158
 3. After "GO," depressing "EX" will automatically enter the reg-
ister display routine without altering any of the internal register
contents. Then, pressing "GO" will advance the register dis-
play and pressing "M" will back up the display routine.
4. The system stack begins at address E6oo. If the S register is
loaded with a non-R/W memory address value or there is not
enough R/W memory available to stack the internal register
contents, the display will indicate "Bad SP??"
5. The system uses SWIl for the breakpoint routine.
6. To use SWI2, store the SWI2 interrupt service routine vector
at address E777: E778.
7. To use SWI3, store its interrupt service routine vector at ad-
dress E775:E776.
8. The single-step function (T / B) sets the E flag.
The following will help familiarize you with your D4A and illus-
trate the versatility of both the 6809 and D4A system.
Example 7-3: Using the SWI2 Interrupt
Step 1: Load the program in Fig. 7-13 into the D4 system beginning
at address E400. Refer to the D4 user's manual for the pro-
gram loading procedure.
NOTE: Do not press RS (reset) after entering the program, use the
escape (EX) key.
Step 2: Depress RD and set the program counter to the beginning
address of the above program (E4oo).
Step 3: Depress T / B. The first instruction was executed and the D4
HEX HEX MNEMONICI OPERATION
ADDRESS CONTENTS CONTENTS REMARKS

E400 C6
E401 BB LDS#
BB }
E402 86 LDA # Main Program
E403 AA AA
E404 1F TFR A,CC
E405 8B 8B
E406
E407
10
3F
SWI2 J Software Interrupt (SWI2)
E408 3C CWAI#
E409 FF FF
•
•
E500 CE LDU #
E501
E502
E503
CC
CC
3B
CC
CC
RTI
} SWI2 Interrupt
Service Routine

•
•
E777
E778
E5
00
E5
00
J Our SWI2 Interrupt
Vector

Fig. 7-13. Program for Example 7-13.

159
 is now in the register display routine. The program counter
contents should be the address of the next instruction to be
executed (E402).
Step 4: Verify that accumulator B was loaded with the value BB
by depressing the GO key twice. Also, at this time, you
might want to note the contents of the other registers by
successiv~ly pushing the GO key.
Step 5: Depress T / B a second time. Verify the proper PC contents
( E404) and that accumulator A was loaded with the value
AA.
Step6: Single step the program a third time and verify that the
accumulator A value of AA was transferred to the direct
page register (DP).
Step 7: Single step the program again and observe the PC contents
of FDBC. Why? Because the software interrupt (SWI2)
was just executed and the processor was vectored to this
address by the SWI2 software interrupt vector located at
address FFF4: FFF5. Escape (EX) from the register dis-
play routine and verify that the SWI2 vector, located at
address FFF4:FFF5, is FDBC.
Step 8: The SWI2 instruction also caused the internal register data
to be stacked. The S stack pointer was originally set to E600
by the reset operation. Thus, examine memory locations
E600 through E5F4 and verify the correct register stacking
and the proper stacking order. Note also that the S register
now contains E5F4. You should find the registers stacked in
the following manner:
S-12~ E5F4 CCR
S-ll ~ E5F5 A
S-10~ E5F6 B
S·9 ~ E5F7 DPR
S-8 ~ E5F8 XII
S-7 ~ E5F9 XL
S-6 ~ E5FA Yn
S-5 ~ E5FB YL
S-4 ~ E5FC Un
S-3 ~ E5FD UL
S-2 ~ E5FE PC H
S-l ~ E5FF PC L
S ~ E600
Step 9: Now, return to the register display routine by depressing
EX, then RD. The PC should still contain FDBC, which is
in ROM. Continue to single step through this ROM routine
until the PC contains address E500. Note that E500 is our

160
 SWI2 interrupt vector. You might say that the ROM routine
converted the system SWI2 interrupt vector (FDBC) lo-
cated at FFF4:FFF5 to our SWI2 interrupt vector (E500)
located at address E777:E778. If you want a real challenge
and learning experience, interpret the ROM routine instruc-
tions which begin at address FDBC to understand how the
above vector conversion is accomplished.
Step 10: With the PC set at E500, single step the program and verify
that the U register was loaded with the value CCCC by our
SWI2 interrupt service routine.
Step 11: Single step the program again. This time, the RTI instruc-
tion was executed and therefore control was returned back
to the main program. Verify that the original register data
has been restored as a result of the unstacking operation
caused by the RTI instruction.
Step 12: You might want to rewrite the program to use the SWI3
interrupt. To do this, you must insert the SWI3 op code at
address E406: E407 and an interrupt vector of your choos-
ing at address E775:E776. Remember to also include an in-
terrupt service routine.
Example 7-4: Buried Op Code and Computed Vector Fetch
Step 1: Load the program in Fig. 7-14 into the D4 system beginning
at address E400.
Step 2: The program is from Example 5-5. Turn back to this example
and review the program explanation.
Step 3: The vector table in the program of Fig. 7-14 begins at ad-
dress FFFO, which is the beginning of the 6809 vector table.
Thus, we will be using a control byte to determine which of
the 6809 vectors will be accessed by the program. Because

HEX HEX MNEMONICI OPERATION

ADDRESS CONTENTS CONTENTS REMARKS

E400 86 LDA# ~
E401
E402
E403
Control Byte
8E
FF
LOX #
FF
J-
Control Byte~ Load control byte
Load beginning
address of vector
E404 FO FO table
E405 5F CLRB
E406 10 LBRN
E407 21
E408 CB ADDB # Vector to table
E409 02 02 determined by
R40A 44 LSRA control byte
R40B 24 BCC
R40C FB FB
R40D 6E JMP[B,Xj
E40E 95 95
Fig. 7-14. Program for Example 7-14.

161
 of the fixed 6809 vector table mapping, the control byte will
access the 6809 vectors in the following manner:
C antral Byte Vector Accessed
00 Reserved
02 SWI3
04 SWI2
08 FIRQ
10 IRQ
20 SWIl
40 NMI
80 RESET
Step 4: Insert 80 at address E401 for the control byte. This should
access the RESET interrupt vector.
Step 5: Execute the program. A question mark ( ?) should appear in
the left-most display as the result of the accessed reset oper-
ation.
Step 6: You might want to access the other interrupt vectors by
changing the control byte. In all cases you will end up in the
respective interrupt service routine located in ROM. The dis-
play will either remain blank or revert to the register display
routine, depending on the particular interrupt which is being
accessed.
Step 7: Now, create your own vector table in RjW memory as in
Example 5-5. Remember to also include some type of vector
service routine such that you can verify proper vectoring.
Try it! In addition, go back and execute the text examples on
your D4. In this way you will gain a better understanding of
both the 6809 and the D4 system.

162
 APPENDIX A

6809/6809E Instruction Set

The following pages contain detailed definitions of the 59 executable instruc-

tions. These pages are provided through the courtesy of Motorola Semiconductor
Products, Inc., Austin, Texas.

A-1. Nomenclature
Operation Notation
-E-= is transferred to EB = Boolean exclusive OR
/\ = Boolean AND = (overline) = Boolean NOT
V = Boolean OR = concatenation
Register Notation
ACCA = A = accumulator A
ACCB = B = accumulator B
ACCX = either ACCA or ACCB
ACCA:ACCB = D = double accumulator
IX = X = index register X
IY = Y = index register Y
SP =
S= hardware stack pointer
US = U = user stack pointer
DPR = DP = direct page register
CCR = CC = condition code register
PC = program counter
R= a register before the operation: A, B, D, X, Y, U, S, PC,
DP, or CC (usually, only a subset of registers is legal,
these are specified by "Register Addressing Mode" in the
individual instructions)
R'= a register after the operation.
ALL= all registers, Le., A, B, D, X, Y, U, S, PC, DP, and CC
zz= a pointer register, Le., X, Y, U, S
MSB= most significant bit
MS byte = most significant byte
LS byte = least significant byte
IXH= ms byte of index X
IXL= Is byte of index X

163
A-2. Definitions of Executable Instructions
Add ACCS into IX ABX
Source Form: ABX
Operation: IX' ~ IX + ACCB
Condition Codes: Not affected.
Description: Adds the 8-bit unsigned value in accumulator B into the X index
register.
Addressing Mode: Inherent

Add with Carry Memory into Register ADC

Source Forms: ADCA P; ADCB P
Operation: R' ~ R+M +C
Condition Codes: H: Set IFF the operation caused a carry from bit 3 in the
alu.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF the operation caused an 8-bit twos complement
arithmetic overflow.
C: Set IFF the operation caused a carry from bit 7 in the
alu.
Description: Adds the contents of the carry Hag and the memory byte into an
8-bit register.
Register Addressing Mode: Accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Add Memory into Register-8 Bits ADD

Source Forms: ADDA P; ADDB P
Operation: R' ~ R +M
Condition Codes: H: Set IFF the operation caused a carry from bit 3 in the
alu.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF the operation caused an 8-bit twos complement
arithmetic overflow.
C: Set IFF the operation caused a carry from bit 7 in the
alu.
Description: Adds the memory byte into an 8-bit register.
Register Addressing Mode: Accumulator

164
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Add Memory into Register-16 Bits ADD

Source Form: ADDD P
Operation: R' ~ R + M:M+l
Condition Codes: H: Not affected.
N: Set IFF bit 15 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF there was a 16-bit twos complement arithmetic
overflow.
C: Set IFF the operation on the MS byte caused a carry from
bit 7 in the alu.
Description: Adds the 16-bit memory value into the 16-bit accumulator.
Register Addressing Mode: Double accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Logical AND Memory into Register AND

Source Forms: ANDA P; ANDB P
Operation: R' ~ RAM
Condition Codes: H: Not affected.
N: Set IFF bit 7 of result is set.
Z: Set IFF all bits of result are clear.
V: Cleared.
C: Not affected.
Description: Performs the logical AND operation between the contents of ACCX
and the contents of M, and the result is stored in ACCX.
Register Addressing Mode: Accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Logical AND Immediate Memory into CCR AND

Source Form: ANDCC #XX
Operation: R' ~ RAMI
Condition Codes: CCR' ~ CCR A MI

165
Description: Performs a logical AND between the CCR and the MI byte and
places the result in the CCR.
Register Addressing Modes: CCR
Memory Addressing Mode: Memory immediate

Arithmetic Shift Left ASL

Source Form: ASL Q

Operation: C' ~ b 7, b 7' ... bI' ~ ba ... bo, bo' ~ 0

Condition Codes: H: Undefined.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Loaded with the result of (b7 EB ba) of the original op-
erand.
C: Loaded with bit 7 of the original operand.
Description: Shifts all bits of the operand one place to the left. Bit 0 is loaded
with a zero. Bit 7 of the operand is shifted into the carry Hag.
Addressing Modes: Accumulator
Direct
Indexed
Extended

Arithmetic Shift Right ASR

Source Form: ASR Q

Condition Codes: H: Undefined.

N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of result are clear.
V: Not affected.
C: Loaded with bit 0 of the original operand.
Description: Shifts all bits of the operand right one place. Bit 7 is held constant.
Bit 0 is shifted into the carry Hag. The 6800/01/02/03/08 processors do affect
the V Hag.
Addressing Modes: Accumulator
Direct
Indexed
Extended

166
Branch on Carry Clear Bee
Source Forms: BCC dd; LBCC DDDD
Operation: TEMP ~ MI
=
IFF C 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the C bit and causes a branch if C is clear.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: When used after a subtract or compare on unsigned binary values,
this instruction could be called "branch if the register was higher or the
same as the memory operand."

Branch on Carry Set Bes

Source Forms: BCS dd; LBCS DDDD
Operation: TEMP ~ MI
IFF C = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the C bit and causes a branch if C is set.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: When used after a subtract or compare on unsigned binary values,
this instruction could be called "branch if the register was lower than the
memory operand."

Branch on Equal BEQ

Source Forms: BEQ dd; LBEQ DDDD
Operation: TEMP ~ MI
IFF Z = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the Z bit and causes a branch if the Z bit is set.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation, this instruction will
branch if the compared values-signed or unsigned-were exactly the same.

Branch on Greater Than or Equal to Zero BGE

Source Forms: BGE dd; LBGE DDDD

167
Operation: TEMP ~ MI
IFF [N EB V] = 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes a branch if N and V are either both set or both clear, i.e.,
branch if the sign of a valid twos complement result is-or would be-positive.
M emory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on twos complement
values, this instruction will «branch if the register was greater than or equal
to the memory operand."

Branch on Greater BGT

Source Forms: BGT dd; LBGT DDDD
Operation: TEMP ~ MI
IFF Z V [N EB V] = 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes a branch if (N and V are either both set or both clear)
and Z is clear. In other words, branch if the sign of a valid twos complement
result is-or would be-positive and nonzero.
M emory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on twos complement
values, this instruction will «branch if the register was greater than the mem-
ory operand."

Branch if Higher BHI

Source Forms: BHI dd; LBHI DDDD
Operation: TEMP ~ MI
IFF [C V Z] = 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes a branch if the previous operation caused neither a carry
nor a zero result.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on unsigned binary
values this instruction will «branch if the register was higher than the mem-
ory operand." Not useful, in general, after INC/DEC, LD/ST, TST/CLR/
COM.

168
Branch if Higher or Same BHS
Source Form: BHS dd; LBHS DDDD
Operation: TEMP ~ MI
IFF C= 0 then PC' ~ PC + MI
Condition Codes: Not affected.
Description: Tests the state of the C bit and causes a branch if C is clear.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: When used after a subtract or compare on unsigned binary values,
this instruction will «branch if register was higher than or same as the
memory operand." This is a duplicate assembly-language mnemonic for the
single machine instruction BCe. Not useful, in general, after INC/DEC,
LD/ST, TST/CLR/COM.

Bit Test BIT

Source Form: BIT P
Operation: TEMP ~ R 1\ M
Condition Codes: H: Not affected.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Cleared.
C: Not affected.
Description: Performs the logical AND of the contents of ACCX and the con-
tents of M and modifies condition codes accordingly. The contents of ACCX
or M are not affected.
Register Addressing Mode: Accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Branch on Less Than or Equal to Zero BlE

Source Form: BLE dd; LBLE DDDD
Operation: TFMP ~ MI
IFF Z V [N EB V] = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes a branch if the exclusive OR of the N and V bits is 1 or
=
if Z 1. That is, branch if the sign of a valid tWos complement result is-or
would be-negative.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative

169
Comments: Used after a subtract or compare operation on twos complement
values, this instruction will "branch if the register was less than or equal to
the memory operand."

Branch on Lower BlO

Source Form: BLO dd; LBLO DDDD
Operation: TEMP ~ MI
IFF C = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the C bit and causes a branch if C is set.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: When used after a subtract or compare on unsigned binary values,
this instruction will "branch if the register was lower" than the memory op-
erand. Note that this is a duplicate assembly-language mnemonic for the
single machine instruction BCS. Not useful, in general, after INC/DEC,
LD/ST, TST/CLR/COM.

Branch on Lower or Same BlS

Source Form: BLS dd; LBLS DDDD
Operation: TEMP ~ MI
IFF (C VZ) = 1 then PC' ~PC+ TEMP
Condition Codes: Not affected.
Description: Causes a branch if the previous operation caused either a carry
or a zero result.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on unsigned binary
values, this instruction will "branch if the register was lower than or the
same as the memory operand." Not useful, in general, after INC/DEC, LD/
ST, TST/CLR/COM.

Branch on Less Than Zero Bll

Source Forms: BLT dd; LBLT DDDD
Operation: TEMP ~ MI
IFF [N ffi V]= 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes a branch if either, but not both, of the N or V bits is l.
That is, branch if the sign of a valid twos complement result is-or would be-
negative.

170
M emory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on twos complement
binary values, this instruction will "branch if the register was less than the
memory operand."

Branch on Minus 8MI

Source Form: BMI dd; LBMI DDDD
Operation: TEMP ~ MI
IFF N = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the N bit and causes a branch if N is set. That is,
branch if the sign of the twos complement result is negative.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after an operation on twos complement binary values, this
instruction will "branch if the (possibly invalid) result is minus."

Branch if Not Equal BNE

Source Forms: BNE dd; LBNE DDDD
Operation: TEMP ~ MI
IFF Z = 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the Z bit and causes a branch if the Z bit is clear.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after a subtract or compare operation on any binary values,
this instruction will "branch if the register is (or would be) not equal to the
memory operand."

Branch on Plus BPL

Source Form: BPL dd; LBPL DDDD
Operation: TEMP ~ MI
IFF N= 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the N bit and causes a branch if N is clear.
That is, branch if the sign of the twos complement result is positive.

171
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after an operation on twos complement binary values, this
instruction will "branch if the possibly invalid result is positive."

Branch Always BRA

Source Forms: BRA dd; LBRA DDDD
Operation: TEMP ~ MI
PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Causes an unconditional branch.
M emory Assessing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative

Branch Never BRN

Source Form: BRN dd; LBRN DDDD
Operation: TEMP ~ MI
Condition Codes: Not affected.
Description: Does not cause a branch. This instruction is essentially a NO-OP,
but has a bit pattern logically related to BRA.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative

Branch to Subroutine BSR

Source Form: BSR dd; LBSR DDDD
Operation: TEMP ~MI
SP' ~SP-l, (SP) ~PCL
SP' ~SP-l, (SP) ~PCH
PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: The program counter is pushed onto the stack. The program
counter is then loaded with the sum of the program counter and the memory
immediate offset.
Memory Addressing Mode: Memory immediate

Effective Addressing Modes: Relative

Long relative

172
Branch on Overflow Clear BVC
Source Form: BVC dd; LBVC DDDD
Operation: TEMP ~ MI
IFF V = 0 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state. of the V bit and causes a branch if the V bit is
clear. That is, branch if the twos complement result was valid.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after an operation on twos complement binary values, this
instruction will «branch if there was no overflow."

Branch on Overflow Set BVS

Source Form: BVS dd; LBVS DDDD
Operation: TEMP ~ MI
IFF V = 1 then PC' ~ PC + TEMP
Condition Codes: Not affected.
Description: Tests the state of the V bit and causes a branch if the V bit is set.
That is, branch if the twos complement result was invalid.
Memory Addressing Mode: Memory immediate
Effective Addressing Modes: Relative
Long relative
Comments: Used after an operation on twos complement binary values, this
instruction will «branch if there was an overflow." This instruction is also
used after ASL or LSL to detect binary floating-point normalization.

Clear CLR
Source Form: CLR Q
Operation: TEMP ~ M
M ~OO16
Condition Codes: H: Not affected.
N: Cleared.
z: Set.
V: Cleared.
c: Cleared.
Description: ACCX or M is loaded with 00000000. The C flag is cleared for 6800
compatibility.
Addressing Modes: Accumulator
Direct
Indexed
Extended

173
Compare Memory from a Register-8 Bits CMP
Source Form: CMPA P; CMPB P
Operation: TEMP ~ R - M [Le., TEMP ~ R + :M + 1]
Condition Codes: H: Undefined.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Set IFF the operation caused an 8-bit twos complement
overflow.
C: Set IFF the subtraction did not cause a carry from bit 7
in the ALU.
Description: Compares the contents of M from the contents of the specified
register and sets appropriate condition codes. Neither M nor R is modified.
The C flag represents a borrow and is set inverse to the resulting binary
carry.
Register Addressing: Accumulator
Memory Addressing: Immediate
Direct
Indexed
Extended
Flag Results: (N EB V) = 1 R .LT. M (twos complement)
C = 1 R .LO. M (unsigned)
Z = 1 R.EQ.M
Compare Memory From a Register-16 Bits CMP
Source Forms: CMPD P; CMPX P, CMPY P; CMPU P; CMPS P
Operation: TEMP ~ R - M:M+l [Le., TEMP ~ R + M:M+l +1]
Condition Codes: H: Unaffected.
N: Set IFF bit 15 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF the operation caused a 16-bit twos complement
overflow.
c: Set IFF the operation on the MS byte did not cause a
carry from bit 7 in the ALU.
Description: Compares the l6-bit contents of M:M+l from the contents of the
specified register and sets appropriate condition codes. Neither R nor M:M+l
is modified. The C flag represents a borrow and is set inverse to the resulting
binary carry.
Register Addressing: Double accumulator
Pointer (X, Y, S, or U)
Memory Addressing: Immediate
Direct
Indexed
Extended
Flag Results: (N EB V) = 1 R .LT. M (twos complement)
C = 1 R .LO. M (unsigned)
Z = lR.EQ.M
174
Complement COM
Source Form: COM Q
Operation: M' ~ 0 +M
Condition Codes: H: Not affected.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Cleared.
C: Set.
Description: Replaces the contents of M or ACCX with its ones complement
(also called the logical complement). The carry Hag is set for 6800 com-
patibility.
Memory Addressing Modes: Accumulator
Direct
Indexed
Extended
Comments: When operating on unsigned values, only BEQ and BNE branches
can be expected to behave properly. When operating on twos complement
values, all signed branches are available.

Clear and Wait for Interrupt CWAI

Source Form: CWAI #$XX

Operation: CCR ~ CCR /\ MI (Possibly clear masks)

Set E (Entire state saved)
SP' ~ SP - 1, (SP) ~ PCb FF =
Enable neither
SP' ~ SP - 1, (SP) ~ PCH EF = Enable IRQ
SP' ~ SP - 1, (SP) ~ USL BF = Enable FIRQ
SP' ~ SP - 1, (SP) ~ USH .AF =
Enable both
SP' ~ SP - 1, (SP) ~ IYL
SP' ~SP -1, (SP) ~IYH
SP' ~ SP - 1, (SP) ~ IXL
SP' ~ SP - 1, (SP) ~ IXH
SP' ~ SP - 1, (SP) ~ DPR
SP' ~SP -1, (SP) ~ACCB
SP' ~SP -1, (SP) ~ACCA
SP' ~SP -1, (SP) ~CCR
Condition Codes: Possibly cleared by the immediate byte.
Description: The CWAI instruction ANDs an immediate byte with the condition
code register, which may clear interrupt mask bit( s), stacks the entire ma-
chine state on the hardware stack, and then looks for an interrupt. When a
( non-masked) interrupt occurs, no further machine state will be saved
before vectoring to the interrupt handling routine. This instruction replaced
the 680(Ys CLI WAI sequence, but does not tri-state the buses.
Addressing Mode: Memory immediate

175
Comments: An FIRQ interrupt may enter its interrupt handler with its entire
machine state saved. The RTI will automatically return the entire machine
state after testing the E bit of the recovered CCR.

Decimal Addition Adjust DAA

Source Form: DAA
Operation: ACCA' ~ ACCA + CF( MSN) :CF( LSN)
where CF is a correction factor, as follows:
The CF for each nibble (bcd digit) is detennined separately, and
is either 6 or O.
Least Significant Nibble:
CF(LSN) =
6 IFF l)H 1 =
or 2)LSN > 9
Most Significant Nibble:
CF(MSN) =
6 IFF l)C 1 =
or 2)MSN > 9
or 3)MSN > 8 and LSN >9
Condition Codes: H: Not affected.
N: Set IFF MSB of result is set.
Z: Set IFF all bits of the result are clear.
V: Not defined.
C: Set if the operation caused a carry from bit 7 in the ALD,
or if the carry Hag was set before the operation.
Description: The sequence of a single-byte add instruction on ACCA (either
ADDA or ADCA) and a following DAA instruction results in a bcd addition
with appropriate carry Hag. Both values to be added must be in proper bcd
form (each nibble such that: 0 ~ nibble ~ 9). Multiple-precision additions
must add the carry generated by this DA into the next higher digit during
the add operation immediately prior to the next DA.
Addressing Mode: ACCA

Decrement DEC
Source Form: DEC Q
Operation: M' ~ M - 1 [i.e., M' ~ M + FFl o]
Condition Codes: H: Not affected.
N: Set IFF bit 7 of result is set.
Z: Set IFF all bits of result are clear.
V: Set IFF the original operand was 10000000.
C: Not affected.
Description: Subtract one from the operand. The carry Hag is not affected,
thus allowing DEC to be a loop counter in multiple-precision computations.
Memory Addressing Modes: Accumulator
Direct
Indexed
Extended
Comments: When operating on unsigned values only BEQ and BNE branches

176
 can be expected to behave consistently. When operating on two complement
values, all signed branches are available.

Exclusive OR EOR
Source Forms: EORA P; EORB P
Operation: R' ~ R E9 M
Condition Codes: H: Not affected.
N: Set IFF bit 7 of result is set.
Z: Set IFF all bits of result are clear.
V: Cleared.
C: Not affected.
Description: The contents of memory is exclusive-oRed into an 8-bit register.
Register Addressing Modes: Accumulator
Memory Addressing Modes: Direct
Extended
Immediate
Indexed

Exchange Registers EXG

Source Form: EXG R1, R2
Operation: R1 ~ R2
Condition Codes: Not affected (unless one of the registers is CCR).
Description: Bits 3-0 of the immediate byte of the instruction define one register,
while bits 7-4 define the other, as follows:
0000 = A:B 1000 = A
0001 =X 1001 = B
0010 =Y 1010 = CCR
0011 =US 1011 = DPR
=
0100 SP 1100 = Undefined
0101 =PC 1101 = Undefined
0110 =Undefined 1110 = Undefined
0111 =Undefined 1111 = Undefined
Registers may only be exchanged with registers of like size, Le., 8-bit with
8-bit, or 16-bit with 16-bit.
Addressing Modes: Inherent

Increment INC
Source Form: INC Q
Operation: M' ~ M +1
Condition Codes: H: Not affected.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF the original operand was 01111111.
C: Not affected.

177
Description: Add one to the operand. The carry Hag is not affected, thus allow-
ing INC to be used as a loop counter in multiple-precision computations.
Memory Addressing Modes: Accumulator
Direct
Indexed
Extended
Comments: When operating on unsigned values, only the BEQ and BNE
branches can be expected to behave consistently. When operating on twos
complement values, all signed branches are correctly available.

Jump to Effective Address JMP

Source Form: JMP
Operation: PC' ~ EA
Condition Codes: Not affected.
Description: Program control is transferred to the location equivalent to the
effective address.
Addressing Modes: Direct
Indexed
Extended

Jump to Subroutine at Effective Address JSR

Source Form: JSR
Operation: SP' ~ SP - 1, (SP) ~ PCL
SP' ~SP -1, (SP) ~PCH
PC' ~EA

Condition Codes: Not affected.

Description: Program control is transferred to the effective address after storing
the return address on the hardware stack.
Addressing Modes: Direct
Indexed
Extended

Load Register from Memory-8 Bit LD

Source Forms: LDA P; LDB P
Operation: R' ~ M
Condition Codes: H: Not affected.
N: Set IFF bit 7 of loaded data is set.
Z: Set IFF all bits of loaded data are clear.
V: Cleared.
C: Not affected.
Description: Load the contents of the addressed memory into the register.
Register Addressing Mode: Accumulator

178
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Load Register from Memory-16 Bit LO

Source Form: LDD P; LDX P; LDY P; LDS P; LDU P
Operation: R' ~ M:M+l
Condition Codes: H: Not affected.
N: Set IFF bit 15 of loaded data is set.
Z: Set IFF all bits of loaded data are clear.
V: Cleared.
C: Not affected.
Description: Load the contents of the addressed memory (two consecutive
memory locations) into the 16-bit register.
Register Addressing Modes: Double accumulator
Pointer (X, Y, S, or U)
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Load Effective Address LEA

Source Form: LEAX, LEAY, LEAS, LEAD
Operation: R' ~ EA
Condition Codes: H: Not affected.
N: Not affected.
Z: LEAX, LEAY: Set IFF all bits of the result are clear.
LEAS, LEAU: Not affected.
V: Not affected.
c: Not affected.
Description: Form the effective address to data using the memory addressing
mode. Load that address, not the data itself, into the pointer register.
LEAX and LEAY affect Z to allow use as counters and for 6800 INX/DEX
compatibility. LEAD and LEAS do not affect Z to allow for cleaning up the
stack while returning Z as a parameter to a calling routine, and for 6800
INS/DES compatibility.
Register Addressing Mode: Pointer (X, Y, S, or D)
Memory Addressing Mode: Indexed

Logical $hift Left LSL

Source Form: LSL Q

179
Operation: C' ~ b 7 , b/ ... bt' ~ b6 ... bo, bo' ~ 0
Condition Codes: H: Undefined.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Loaded with the result of (b7 EB b 6) of the original op-
erand.
C: Loaded with bit 7 of the original operand.
Description: Shifts all bits of ACCX or M one place to the left. Bit 0 is loaded
with a zero. Bit 7 of ACCX or M is shifted into the carry flag. This is a
duplicate assembly-language mnemonic for the single machine instruction
ASL.
Addressing Modes: Accumulator
Direct
Indexed
Extended

Logical Shift Right LSR

Source Form: LSR Q

ob- = - I T
b
J
7 o
Operation: C' ~ bo, bo' ... b o' ~ III ... !h, !h' ~ 0
Condition Codes: H: Not affected.
N: Cleared.
Z: Set IFF all bits of the result are clear.
V: Not affected.
C: Loaded with bit 0 of the original operand.
Description: Performs a logical shift right on the operand. Shifts a zero into
bit 7 and bit 0 into the carry flag. The 6800 processor also affects the V flag.
Addressing Modes: Accumulator
Direct
Indexed
Extended

Multiply Accumulators MUL

Source Form: MUL
Operation: ACCA':ACCB' ~ ACCA X ACCB
Condition Codes: H: Not affected.
N: Not affected.
Z: Set IFF all bits of the result are clear.
V: Not affected.
C: Set IFF ACCB bit 7 of result is set.
Description: Multiply the unsigned binary numbers in the accumulators and
place the result in both accumulators. Unsigned multiply allows multiple-
precision operations. The carry flag allows rounding the MS byte through the
sequence: MUL,ADCA # O.

180
Addressing Modes: Inherent

Negate NEG
Source Form: NEG Q
Operation: M' ~ 0 - M i.e., M' ~ M + 1
Condition Codes: H: Undefined.
N: Set IFF bit 7 of result is set.
z: Set IFF all bits of result are clear.
V: Set IFF the original operand was 10000000.
C: Set IFF the operation did not cause a carry from bit 7 in
the ALU.
Description: Replaces the operand with its twos complement. The C flag
represents a borrow and is set inverse to the resulting binary carry. Note that
8016 is replaced by itself and only in this case is V set. The value 0016 is also
replaced by itself, and only in this case is C cleared.
Addressing Modes: Accumulator
Direct
Indexed
Extended
Flag Results: (N EB V) = 1 if 0 .LT. M (twos complement)
C = 1 if 0 .LO. M (Unsigned)
Z = 1 if 0 .EQ. M
No Operation NOP
Source Form: Nap
Condition Codes: Not affected.
Description: This is a single-byte instruction that causes only the program counter
to be incremented. No other registers or memory contents are affected.
Addressing Modes: Inherent

Inclusive OR Memory into Register OR

Source Forms: ORA P; ORB P
Operation: R' ~ RV M
Condition Codes: H: Not affected.
N: Set IFF high-order bit of result is set.
Z: Set IFF all bits of result are clear.
V: Cleared.
C: Not affected.
Description: Performs an inclusive-oR operation between the contents of ACCX
and the contents of M and the result is stored in ACCX.
Register Address Mode: Accumulator
Memory Address Modes: Immediate
Direct

181
 Indexed
Extended

Inclusive OR Memory-Immediate into CCR OR

Source Form: GReC #XX
Operation: R ~ R V MI
Condition Codes: CCR' ~ CCR V MI
Description: Performs an inclusive OR operation between the contents of CCR
and the contents of MI, and the result is placed in CCR. This instruction
may be used to set interrupt masks (disable interrupts) or any other flag ( s).
Register Addressing Mode: CCR
Memory Addressing Mode: Memory immediate

Push Registers on the Hardware Stack PSHS

Source Form: PSHS register list
PSHS #Label

~luIY~
push order-

Operation: IFF B7 of MI set, then: SP' ~ SP - 1, (SP) ~ PCL

SP' ~SP -1, (SP) ~PCH
IFF B6 of MI set, then: SP' ~ SP - 1, (SP) ~ USL
SP' ~ SP - 1, (SP) ~ USH
IFF B5 of MI set, then: SP' ~ SP - 1, (SP) ~ IYL
SP' ~ SP -1, (SP) ~IYH
IFF B4 of MI set, then: SP' ~ SP - 1, (SP) ~ IXL
SP' ~ SP - 1, (SP) ~ IXH
IFF B3 of MI set, then: SP' ~ SP - 1, (SP) ~ DPR
IFF B2 of MI set, then: SP' ~ SP - 1, (SP) ~ ACCB
IFF Bl of MI set, then: SF' ~ SP - 1, (SP) ~ ACCA
IFF BO of MI set, then: SP' ~ SP - 1, (SP) ~ CCR

Condition Codes: Not affected.

Description: Any, all, any subset, or none of the MPU registers are pushed onto
the hardware stack (excepting only the hardware stack pointer itself).
Memory Addressing Mode: Memory immediate

Push Registers on the User Stack PSHU

Source Form: PSHU register list
PSHU #Label

~
push order-

182
Operation: IFF B7 of MI set, then: US' ~ us - 1, (US) ~ PCL
US' ~ US -1, (US) ~PCH
IFF B6 of MI set, then: US' ~ US - 1, (US) ~ SPL
US' ~ US -1, (US) ~SPH
IFF B5 of MI set, then: US' ~ US - 1, (US) ~ IYL
US' ~ US -1, (US) ~IYH
IFF B4 of MI set, then: US' ~ US - 1, (US) ~ IXL
US' ~ US - 1, (US) ~ IXH
IFF B3 of MI set, then: US' ~ US - 1, (US) ~ DPR
IFF B2 of MI set, then: US' ~ US - 1, (US) ~ ACCB
IFF Bl of MI set, then: US' ~ US - 1, (US) ~ ACCA
IFF BO of MI set, then: US' ~ US - 1, (US) ~ CCR

Condition Codes: Not affected.

Description: Any, all, any subset, or none of the MPU registers are pushed
onto the user stack (excepting only the user stack pointer itself).
M emo-ry Addressing Mode: Memory immediate

Pull Registers from the Hardware Stack PULS

Source Form: PULS register list
PULS #LABEL

~
-pull order

Operation: IFF BO of MI set, then: CCR' ~ (SP), SP' ~ SP + 1

IFF Bl of MI set, then: ACCA' ~ (SP), SP' ~ SP + 1
IFF B2 of MI set, then: ACCB' ~ (SP), SP' ~ SP + 1
IFF B3 of MI set, then: DPR' ~ (SP), SP' ~ SP + 1
IFF B4 of MI set, then: IXH' ~ (SP), SP' ~ SP + 1
IXL' ~ (SP), SP' ~ SP + 1
IFF B5 of MI set, then: IYH' ~ (SP), SP' ~ SP + 1
IYL' ~ (SP), SP' ~ SP + 1
IFF B6 of MI set, then: USH' ~ (SP), SP' ~ SP + 1
USL' ~ (SP), SP' ~ SP + 1
IFF B7 of MI set, then: PCH' ~ (SP), SP' ~ SP + 1
PCL' ~ (SP), SP' ~ SP + 1
Condition Codes: May be pulled from stack; otherwise unaffected.
Description: Any, all, any subset, or none of the MPU registers are pulled from
the hardware stack (excepting only the hardware stack pointer itself). A
single register may be "PULLED" with condition flags set by loading auto-
increment from stack (EX: LDA, S+).
Memory Addressing Mode: Memory immediate

Pull Registers From the User Stack PULU

Source Form: PULU register list
PULU #LABEL

~
- pull order

183
Operation: IFF BO of MI set, then: CCR' ~ (US), US' ~ US + 1
IFF BI of MI set, then: ACCA' ~ (US), US' ~ US + 1
IFF B2 of MI set, then: ACCB' ~ (US), US' ~ US + 1
IFF B3 of MI set, then: DPR' ~ (US), US' ~ US + 1
IFF B4 of MI set, then: IXH' ~ (US), US' ~ US + 1
IXL' ~ (US), US' ~ US + 1
IFF B5 of MI set, then: IYH' ~ (US), US' ~ US + 1
IYL' ~ (US), US' ~ US + 1
IFF B6 of MI set, then: SPH' ~ (US), US' ~ US + 1
SPL' ~ (US), US' ~ US + 1
IFF B7 of MI set, then: PCH' ~ (US), US' ~ US + 1
PCL' ~ (US), US' ~ US + 1
Condition Codes: May be pulled from stack; otherwise unaffected.
Description: Any, all, any subset, or none of the MPU registers are pulled from
the user stack (excepting only the user stack pointer itseU). A single register
may be "PULLED" with condition flags set by doing an auto-increment load
from the stack (EX: LDX, U++).
Memory Addressing Mode: Memory immediate

Rotate Left ROL

Source Form: ROL Q

~
Operation: C' ~ b 7, ~' ••• bl' ~~ ... bo, bo' ~ C
Condition Codes: H: Not affected.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Loaded with the result of (b7 ffi be) of the original op-
erand.
c: Loaded with bit 7 of the original operand.
Description: Rotate all bits of the operand one place left through the carry
Hag; this is a 9-bit rotation.
Addressing Modes: Accumulator
Direct
Indexed
Extended

Rotate Right ROR

Source Form: ROR Q

~
184
Operation: C' ~ bo, b6' ... bo' ~ b7 ... In., b/ ~ C
Condition Codes: H: Not affected.
N: Set IFF bit 7 of result is set.
Z: Set IFF all bits of result are clear.
V: Not affected.
C: Loaded with bit 0 of the previous operand.
Description: Rotates all bits of the operand right one place through the carry
Hag; this is a 9-bit rotation. The 6800 processor also affects the V Hag.
Addressing Modes: Accumulator
Direct
Indexed
Extended

Return from Interrupt RTI

Source Form: RTI
Operation: CCR' ~ (SP), SP' ~ SP + 1
IFF CCR bit E is CLEAR then: ~ (SP), SP' +1
~ SP
ACCB' ~ (SP), SP' +1
~ SP
DPR' ~ (SP), SP' +1
~SP
IXR' ~ (SP), SP' +1
~ SP
IXL' ~ (SP), SP' +1
~ SP
IYH' ~ (SP), SP' +1
~ SP
IYL' ~ (SP), SP' +1
~ SP
USR' ~ (SP), SP' +1
~ SP
USL' ~ (SP), SP' +1
~ SP
PCR' ~ (SP), SP' +1
~ SP
PCL' ~ (SP), SP' +1
~ SP
IFF CCR bit E is clear then:
PCR' ~ (SP), SP' ~ SP + 1
PCL' ~ (SP), SP' ~ SP + 1

Condition Codes: Recovered from stack.

Description: The saved machine state is recovered from the hardware stack
and control is returned to the interrupted program. If the recovered E bit
is clear, it indicates that only a subset of the machine state was saved (return
address and condition codes) and only that subset is to be recovered.
Addressing Mode: Inherent

Return from Subroutine RTS

Source Form: RTS
Operation: peR' ~ (SP), SP' ~ SP +1
PCL' ~ (SP), SP' ~ SP +1
Condition Codes: Not affected.
Description: Program control is returned from the subroutine to the calling pro-
gram. The return address is pulled from the stack.
Addressing Mode: Inherent

185
Subtract with Borrow ssc
Source Forms: SBCA P; SBCB P
Operation: R' ~ R - M - C [Le., R' ~ R + M + C]
Condition Codes: H: Undefined.
N: Set IFF bit 7 of the result is set.
z: Set IFF all bits of the result are clear.
V: Set IFF the operation causes an 8-bit twos complement
overflow.
C: Set IFF the operation did not cause a carry from bit 7 in
the ALU.
Description: Subtracts the contents of M and the borrow (in the carry flag)
from the contents of an 8-bit register, and places the result in that register.
The C flag represents a borrow and is set inverse to the resulting binary carry.
Register Addressing Mode: Accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Sign Extended SEX

Source Form: SEX
Operation: If bit 7 of ACCB is set
then ACCA' ~ FF 16
else ACCA' ~ 0016
Condition Codes: H: Not affected.
N: Set IFF the MSB of the result is set.
Z: Set IFF all bits of ACCD are clear.
V: Not affected.
C: Not affected.
Description: This instruction transforms a twos complement 8-bit value in ACCB
into a twos complement 16-bit value in the double accumulator.
Addressing: Inherent

Store Register Into Memory-8 Bits ST

Source Form: STA P; STB P
Operation: M' ~ R
Condition Codes: H: Not affected.
N: Set IFF bit 7 of stored data was set.
Z: Set IFF all bits of stored data are clear.
V: Cleared.
C: Not affected.
Description: Writes the contents of an MPU register into a memory location.
Register Addressing Modes: Accumulator

186
Memory Addressing Modes: Direct
Indexed
Extended

Store Register into Memory-16 Bits ST

Source Form: STD P; STX P; STY P; STS P; STU P
Operation: M':M+I' ~ R
Condition Codes: H: Not affected.
N: Set IFF bit 15 of stored data was set.
Z: Set IFF all bits of stored data are clear.
V: Cleared.
C: Not affected.
Description: Writes the I6-bit register into consecutive memory locations.
Register Addressing Modes: Double accumulator
Pointer (X, Y, S, or U)
Memory Addressing Modes: Direct
Indexed
Extended

Subtract Memory from Register-8 Bits SUB

Source Forms: SUBA P; SUBB P
Operation: R' ~ R - M [i.e., R' ~ R + M+ I]
Condition Codes: H: Undefined.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Set IFF the operation caused an 8-bit twos complement
overflow.
c: Set IFF the operation did not cause a carry from bit 7 in
the alu.
Description: Subtracts the value in M from the contents of an 8-bit register.
The C flag represents a borrow and is set inverse to the resulting binary carry.
Register Addressing Mode: Accumulator
Flag Results: (N EB V) =
I if R .LT. M (twos complement)
C = I if R .LO. M (unsigned)
Z = I if R .EQ. M
Memory Addressing Modes: Immediate
Direct
Indexed
Extended

Subtract Memory from Register-16 Bits SUB

Source Form: SUBD P
Operation: R' ~ R - M:M+I [i.e." R' ~ R + M:M+I + I]

187
Condition Codes: H: Unaffected.
N: Set IFF bit 15 of result is set.
z: Set IFF all bits of result are clear.
V: Set IFF the operation caused a 16-bit twos complement
overflow.
c: Set IFF the operation on the MS byte did not cause a
carry from bit 7 in the alu.
Description: This information subtracts the value in M:M+l from the 16-bit
accumulator. The C flag represents a borrow and is set inverse to the re-
sulting binary carry.
Register Addressing Mode: Double accumulator
Memory Addressing Modes: Immediate
Direct
Indexed
Extended
Subtract Sets: (N EEl V) = 1 if R .LT. M (twos complement)
C = 1 if R .LO. M (unsigned)
Z = 1 if R .EQ. M
Software Interrupt SWI
Source Form: SWI
Operation: Set E (Entire state will be saved)
SP' ~ SP - 1, (SP) ~ PCL
SP' ~ SP - 1, (SP) ~ PCH
SP' ~ SP - 1, (SP) ~ USL
SP' ~ SP - 1, (SP) ~ USH
SP' ~ SP -1, (SP) ~IYL
SP' ~SP -1, (SP) ~IYH
SP' ~ SP - 1, (SP) ~ IXL
SP' ~ SP - 1, (SP) ~ IXH
SP' ~ SP - 1, (SP) ~ DPR
SP' ~SP-l, (SP) ~ACCB
SP' ~ SP - 1, (SP) ~ACCA
SP' ~ SP - 1, (SP) ~ CCR
Set I, F (mask interrupts)
PC' ~ (FFFA):(FFFB)
Condition Codes: Not affected.
Description: All of the MPU registers are pushed onto the hardware stack (ex-
cepting only the hardware stack pointer itself), and control is transferred
through the SWI vector.
Addressing Mode: Absolute indirect

Software Interrupt 2 SWI2

Source Form: SWI2
Operation: Set E (Entire state saved)
SP' ~ SP - 1, (SP) ~ PCL
SP' ~ SP - 1, (SP) ~ PCH

188
 SP' +- SP - 1, (SP) +- USL
SP' +- SP - 1, (SP) +- USH
SP' +- SP - 1, (SP) +- IYL
SP' +- SP - 1, (SP) +- IYH
SP' +- SP - 1, (SP) +- IXL
SP' +- SP - 1, (SP) +- IXH
SP' +- SP - 1, (SP) +- DPR
SP' +- SP - 1, (SP) +- ACCB
SP' +- SP - 1, (SP) +- ACCA
SP' +- SP - 1, (SP) +- CCR
PC' +- (FFF4):(FFF5)
Condition Codes: Not affected.
Description: All of the MPU registers are pushed onto the hardware stack (ex-
cepting only the hardware stack pointer itself), and control is transferred
through the SWI2 vector. SWI2 is available to the end user and must not
be used in packaged software.
Addressing Mode: Absolute indirect

Software Interrupt 3 SWI3

Source Form: SWI3
Operation: Set E (Entire state will be saved)
SP' +- SP - 1, (SP) +- PCL
SP' +- SP - 1, (SP) +- PCH
SP' +- SP - 1, (SP) +- USL
SP' +- SP - 1, (SP) +- USH
SP' +- SP - 1, (SP) +- IYL
SP' +- SP - 1, (SP) +- IYH
SP' +- SP - 1, (SP) +- IXL
SP' +- SP - 1, (SP) +- IXH
SP' +- SP - 1, (SP) +- DPR
SP' +- SP - 1, (SP) +- ACCB
SP' +- SP - 1, (SP) +- ACCA
SP' +- SP - 1, (SP) +- CCR
PC' +- (FFF2):(FFF3)
Condition Codes: Not affected.
Description: All of the MPU registers are pushed onto the hardware stack (ex-
cepting only the hardware stack pointer itself), and control is transferred
through the SWI3 vector.
Addressing Mode: Absolute indirect

Synchronize to External Event SYNC

Source Form: SYNC
Operation: Stop processing instructions
Condition Codes: Unaffected.
Description: When a SYNC instruction is executed, the MPU enters a SYNCING
state, stops processing instructions, and waits on an interrupt. When an in-
terrupt occurs, the SYNCING state is cleared and processing continues. If

189
 the interrupt is enabled, and the interrupt lasts three cycles or more, the
processor will perform the interrupt routine. If the interrupt is masked or is
shorter than three cycles, the processor simply continues to the next instruc-
tion (without stacking registers). While SYNCING, the address and data
buses are tri-state.
Addressing Modes: Inherent
Comments: This instruction provides software synchronization with a hardware
process. Consider the high-speed acquisition of data:
FAST SYNC WAIT FOR DATA _____ interrupt

LDA DISC DATA FROM DISC AND CLEAR INTER-

RUPT
STA ,X+ PUT IN BUFFER
DECB COUNT IT, DONE?
BNE FAST GO AGAIN IF NOT.
The SYNCING state is cleared by any interrupt, and any enabled interrupt
will probably destroy the transfer (this may be used to provide MPU response
to an emergency condition). The same connection used for interrupt-driven
i/0 service m~y thus be used for high-speed data transfers by setting the
interrupt mask and using SYNC.

Transfer Register to Register TFR

Source Form: TFR Rl,~

Operation: R2 ~ Rl
Condition Codes: Not affected (unless R2 CCR). =
Description: Bits 7-4 of the immediate byte of the instruction define the source
register, while bits 3-0 define the destination register, as follows:
0000 = A:B 1000 = A
0001 =X 1001 = B
0010 =Y 1010 = CCR
0011 = US 1011 = DPR
0100 = SP 1100 = Undefined
0101 = PC 1101 = Undefined
0110 = Undefined 1110 = Undefined
0111 = Undefined 1111= Undefined
Registers may only be transl ~r:ed between registers of like size, Le., 8-bit
to 8-bit, and 16-bit to 16-bit.
Addressing Modes: Inherent

Test TST
Source Form: TST Q
Operation: TEMP ~ M- 0
Condition Codes: H: Not affected.
N: Set IFF bit 7 of the result is set.
Z: Set IFF all bits of the result are clear.
V: Cleared.
C: Not affected.

190
Description: Set condition code Hags N and Z according to the contents of M,
and clear the V Hag. The 6800 processor clears the C Hag.
Memory Addressing Modes: Accumulator
Direct
Indexed
Extended
Comments: The TST instruction provides only mllllIllum information when
testing unsigned values; since no unsigned value is less than zero, BLO and
BLS have no utility. While BHI could be used after TST, it provides exactly
the same control as BNE, which is preferred. The signed branches are
available.

191
 APPENDIX B

The ,6820/6821 Peripheral

Interface Adapter (PIA)

6821 FUNCTIONAL DESCRIPTION

Before entering into a detailed discussion of the PIA pin assignments and
interfacing requirements, let us take a look at the PIA from a functional view-
point. A functional diagram of the 6821 is shown in Fig. B-l. First, note the
PIA can be looked at functionally as having two sides-a 6809 side and a
peripheral side. The 6809 side includes the data, address, and control lines
which interface to the 6809 data, address, and control buses. The peripheral side
contains two i/ 0 port~ (A and B) which will interface to peripheral devices.
Each port contains eight data lines which may be configured independently
as input or output. This allows for a high degree of interfacing flexibility. The
procedure for port configuration will be discussed shortly. Internally, the PIA
contains six 8-bit registers. Three registers apply to port A and three apply
to port B. Each group of three registers has the same function with respect to
its respective port. Each group of three registers contains a data register (DRA
or DRB, data direction register (DDRA or DDRB), and control register (CRA
or CRB). A discussion of each follows.
Data Registers (DRA and DRB)
Each data register acts as a temporary 8-bit storage register for data being
transferred between the 6809 and the i/o device connected to the PIA chip.
Each of the 8 bits in the data registers is connected to one of the i/o port
data lines. Recall that each port contains eight i/o data lines. For example,
port A contains eight data lines, PAO through PA7. Therefore, bit 0 of DRA
is tied to PAO, bit 1 of DRA is tied to PAl, and so on. The same arrangement
is used for the DRB bits and lines PBO through PB7. The register bits are
latched when used for output operations and they are unlatched (simple gates)
when they are used for input.
Data Direction Registers (DDRA and DDRB)
The data direction registers are 8-bit registers which define the port lines
as being used for either input or output operations. Each bit within the DDR

192
configures its corresponding port data line. A 1 in a DDR bit will cause its
corresponding port line to be configured as an output line, while a 0 will cause
it to be configured as an input line. For example, if DDRA bit 3 contains a 1,
the PA3 line will be configured as an output data line. If DDRA bit 4 con-
tained a 0, the PA4 line would be configured as an input data line. The ports

6809 SlOE IPERIPHERAL SlOE

DATA REGISTER A
DATA DIRECTION REG A

CONTROL REG A

682016821
PIA

DATA REGISTER B
DATA DIRECTION REG B

CONTROL REG B

Fig. B-1. Functional diagrams of the 6820/6821 PIA.

are configured by storing a data byte into each data direction register. To
configure port A as an input port and port B as an output port, you would store
00 in DDRA and FF in DDRB. Remember that since the data direction register
and the data register are considered to be memory locations, they are loaded
with memory-reference instructions.
Control Registers (CRA and CRB)
The control registers are 8-bit registers which are used for a variety of
control functions. Each bit within the register controls a particular function.
The control register will allow four of the peripheral control lines of the PIA
to be used for interrupt servicing and polling routines. The control register is
also used to select either the DR or DDR for use in a data transfer operation.
A more detailed discussion of the control register is included later in this
appendix.

6820/6821 PIN ASSIGNMENTS

The PIA is a 40-pin integrated circuit. The various pin assignments are
shown in Fig. B-2. A functional description of each pin follows.
V ss (Ground: Pin 1)
Pin 1 should be connected to the system ground.

193
 Vss 1 CA1
PAO 2 CA2
PA1 3 IROA
PA2 4 IROB
PA3 5 RSO
PM 6 RS1
PA5 7 RESET
PA6 8 00
PA7 9 01
682016821
PBO 10 PIA 02
PB1 11 03
PB2 12 04
PB3 13 05
PB4 14 06
PB5 15 07
PB6 16 E
PB7 17 CS1
CB1 18 CS2
CB2 19 CSO
Vee 20 R/W

Fig. B-2. Pin assignments of the 6820/6821 PIA.

Port A Data Lines (PAo-PA7: Pins 2-9)

As stated earlier, each of these lines may be used as an input or an output
line. The use of a particular line is determined through proper selection of
individual bits in the data direction register (DDRA).
Data will be transferred into the 6809 through the lines that have been con-
figured as input. This will be accomplished when a load instruction is executed,
transferring the information from the PIA port input lines to the 6809 internal
register that is being loaded. In the input mode, each input data line represents
a maximum of one TTL load.
Data will be output to the i/o devices through the data lines that have been
configured as output lines. This output transfer will be accomplished with a
store instruction which, when executed, will transfer data from the desired 6809
register to data register A (DRA). The data that has been stored in DRA will
then appear on the port A data lines which have been configured as output
lines. With the 6820 the port A lines only have CMOS drive capabilities and
must be buffered to provide drive for TTL devices. With the 6821, they are
directly compatible.
Port B Data Lines (PBO-PB7: Pins 10-17)
These lines are used very similar to the port A data lines. You may configure
each of the lines as being either an input or an output line through the use
of data direction register B (DDRB). With the 6820 one major difference
between ports A and B is that when the port B lines have been configured as
output, they are TTL compatible and each may be used as a source of up to 1
milliampere at 1.5 volts to directly drive the base of a transistor switch. With the
6821 both ports have TTL drive capabilities.

194
Interrupt Input-Port B (CB1: Pin 18)
This is an input-only line used to set bit 7 of control register B which is
used as a flag to indicate that a peripheral wishes to interrupt the 6809. This
will be discussed in more detail later in this appendix (see PIA Control Reg-
isters) .
Peripheral Control-Port B (CB2: Pin 19)
This line can be programmed through the use of control register B to act
as an interrupt input or as a peripheral control output to provide handshaking.
When in the output mode it is TTL compatible, and when configured as an
interrupt input it represents one TTL load. This pin will be discussed in more
detail later in this appendix (see PIA Control Registers).
Vee (Pin 20)
This pin is connected to the system +5-volt dc power supply.
Read/Write (R/W: Pin 21)
This pin is connected directly to the R/W line on the 6809. A low state
on this line allows data to be transferred from the 6809 to the PIA. A high state
allows for data transfer from the PIA to the 6809. Data will only be transferred
when the proper address and enabling pulse are present at the PIA. PIA ad-
dressing and enabling will be discussed shortly.
Chip Selects (CSO, CS2, CS1: Pins 22-24)
These pins are used in the same way that the chip-select signals were used
on the 6810 R/W memory and 6830 ROM chips. They will partially decode
the address bus to select the PIA. To select the PIA, CSO and CSI must be
high and CS2 must be low.
Enable (E: Pin 25)
This pin is used to supply a timing signal to the PIA and, therefore, is
normally connected directly to the E clock. To completely enable the PIA,
the chip selects must be held in their active state for the duration of the E pulse.
Data (00-07: Pins 33-26)
These pins are connected directly to the eight data bus lines DO through D7.
The data bus lines are bidirectional and allow data transfer between the 6809
and PIA. The output drivers are three-state buffered and remain in their high-
impedance state except when a PIA read operation is being performed.
Reset (Reset: Pin 34)
A high-to-Iow transition at this pin will cause all register bits in the PIA
to be reset to a logical 0 state. It can be used with a power-on reset signal or
tied to the 6809 reset interrupt pin to reset the PIA when the entire system
is reset.
Register Selects (RSO, RS1: Pins 36, 35)
These two lines are used to select the various registers within the PIA. They
are normally tied to address lines AO and Al and are used in conjunction with
the control registers to select the specific register that is desired. This selection
process is discussed in the next section of this appendix.
Interrupt Requests (IRQA, IRQB: Pins 38,37)
These are output lines that can be wire-oRed together to be connected
directly to the 6809 IRQ line. When an if 0 device generates an interrupt, an
interrupt flag bit of the respective PIA control register will be set which, in

195
turn, causes the respective IRQ line to go low. This generates an interrupt re-
quest that is sent to the 6809. Each of these lines has two interrupt flag bits
in its respective control register that can cause the IRQ line to go low. Each
of these internal flags corresponds to a particular peripheral interrupt line;
CAl and CA2 correspond to port A and CBl and CB2 correspond to port B.
Once an internal interrupt flag has been set, the IRQ line will remain low
until the flag is cleared by servicing the interrupt with a PIA read or write
operation. Therefore, an interrupt request is not lost if the I flag in the 6809
condition code register is set, which disables it from recognizing interrupts. These
lines could also connect to the 6809 FIRQ or NMI lines.
Peripheral Control (CA2: Pin 39)
This line is used in essentially the same way as the CB2 line (pin 19). It
can be programmed through the use of control register A to act as an interrupt
input line or it may be used as a peripheral control output line. When in the
output mode it is TTL compatible, and when configured as an interrupt input
it represents one TTL load. A more detailed discussion of this pin function
will follow in this appendix (see PIA Control Registers).
Interrupt Input (CA1: Pin 40)
This line is similar to the CBl line (pin 18). It is an input-only line used
to set bit 7 of control register A which is used as a flag to indicate a peripheral
interrupt. This, in turn, will cause the IRQA line to go low, generating an
interrupt request.

PIA INTERFACING AND ADDRESSING

Fig. B-3 shows how the various pins would be utilized to interface the PIA
to the 6809. The PIA data lines would be connected directly to the 6809 data
lines DO through D7. For control, the following PIA lines would be connected
directly to the corresponding signals on the 6809 control bus: R/W, RESET,
IRQA, IRQB, +5V, and GND.
Chip Selection
To access the PIA, you will use the PIA register-select, chip-select, and
enable lines. Recall that the chip-select pins along with the enable pin will
select the PIA. To provide timing between the 6809 and the PIA, you will
connect the E clock to the PIA enable pin (E). The remaining chip selects
(CSO, CSl, and CS2) are tied to the 6809 address bus to provide partial de-
coding for the chip.
Register Selection
The register select pins, RSO and RSl, are connected to address lines Al
and AO, respectively. Recall that these pins are used to select one of six
registers within the PIA. This creates a problem since there are only four
possible logic combinations for these two pins. However, we wish to select one
of six registers. The solution to the problem is the PIA control register. The
register selection process is shown in Fig. B-4. The RSI bit is used to access
either port A or port B. If RSI is low, port A will be selected, but if RSI is
high, port B will be selected. The RSO bit narrows the selection still further
by selecting either the control register or the data register/data direction
register of the selected port. If RSO is high, the control register will be selected,
but if RSO is low, either the data register or the data direction register will be
selected, depending upon the status of bit 2 of the respective control register.
If bit 2 of the control register is low and RSO is low, the data direction register

196
 DO CA1} A CONTROLS
D1 A DATA CA2
D2
D3 DATA DIRECTION REG A PAO
D4 PA1
D5 PA2
D6 PA3
PM
~lD7
CONTROL REG A
I I
U
'11
ca' PA5
ID
~ en -' r RSO PA6

l
en ::;) 0
-a ::;) co a:: RS1 PAl
); co en
en
-, ()
<t:
f-
Li.J
a::
::!.g <t:
Cl
Cl en PBO
CD ~ Cl ::;)

~Cll
m en
<t: co esa
CS2 PB1
n, ~ PB2
~~
, 0 CS1 PB3
(3
iii" E B DATA PB4
Cf)
Cll
3
R/W PB5
o'
0 RESET DATA DIRECTION REG B PB6
:::l
0-
c IROA PBl
U
s;
t:=
IROB
"tJ
+ 5V
(3
0-
c
U
GND I CONTROL REG B
I CB2)
CB1
J
B CONTROLS

....
CD
'fl
;-
..... ~
...
U)
ClIt
A SIDE B SIDE

."
cp'
m
I
CRA2* =1 CRA2 =0 CRB2* =1 CRB2 =0
~

.."
S;
CD
CO

..~
en
RSO :. 0 RSO =1 RSO =0 RSO =1
!!.
~
0'
?

RS1 =0 RS1 =1
oo
c
it
Ul
'<
I
ro *CRA2 is BIT 2 of control register A
el.
::T DATA PATH BETWEEN MPU AND PIA REGISTERS CRB2 is BIT 2 of control register B
o
9
will be selected. However, if bit 2 of the control register is high, the data
register is selected. For example, suppose RS1 = 1, RSO = 0, and bit 2 of control
register B is low. With these conditions, the data direCtion register of port B
(DDRB) will be selected.
Fig. B-5 shows how a PIA might be connected to the 6809 system. It is
necessary only to allocate four addresses to select any register in the PIA. In
this example we have used addresses 5000 through 5003. Naturally we are
only partially decoding the address bus since from the decoding chart you can
see that the PIA will be enabled for addresses 5000 through 7FFF. This does
not create a problem as long as no other chips are assigned to any of these

A15 A12 A11 A8 A7 A4 A3 AO

I eS2! esa I • IeS1! ~~ ~
5-7 'O-F O-F O-F

+5V

DO DO
••
07 •
07
A1 RSO
AO RS1
A14 eso
6820/6821
A12 eS1 PIA
A15 eS2
E E
R/W R/W
RESET RESET
Key:eS == 1
IROA
=
CS 0
IROB RS = 1 or 0
• = not used
Fig. B-S. PIA pin connections and decoding chart.

addresses. Using this decoding scheme the information in Fig. B-6 shows how
the PIA would respond to addresses 5000 through 5003 and which register
would be selected for each address. Note that with addresses 5000 and 5001,
the data direction or data register can be selected. The specific register that is

PIA REGISTER
ADDRESS CSO CS1 CS2 RS1 RSO SELECTED
5000 0 0 DORA or ORA·
5001 0 1 OORB or ORB·
5002 0 0 eRA
5003 0 1 eRB

·Oepends on bit 2 of the control register.

Fig. B-6. Example of PIA register selection.

199
selected will depend on the status of bit 2 in the respective control register. The
control registers are selected with addresses 5002 and 5003.

PIA INITIALIZATION AND SERVICING

Prior to using the PIA for data transfer you must initialize it by defining
the port lines as either input or output lines. As you saw in the first part of this
appendix this is accomplished by the Is and Os placed in the bits in each data
direction register (DDR). Recall that if a 1 existed in a DDR bit, its corre-
sponding port line would be configured as an output data line, while if a 0
existed its port line would be an input data line. To initialize the PIA you
will have to execute an initialization program that will store a binary number
in each data direction register and, thus, configure each port. The initialization
procedure will be as follows:
1. Clear bit 2 of both control registers.
2. Store a number in DDRA to configure port A.
3. Store a number in DDRB to configure port B.
4. Set bit 2 of control register A (eRA).
5. Set bit 2 of control register B (CRB).

In the above procedure, Step 1 clears bit 2 of both control registers so that
the data direction register will be selected rather than the data register. The
ports will then be configured by storing a binary number in each data direction
register (Steps 2 and 3). After each port has been configured, bit 2 of the
control register is set such that the data register will be selected for subsequent
data transfer.

Example B-1: PIA Initialization

The following program will configure port A as an 8-bit input port and port
B as an output port. We will assume that the PIA has been assigned to addresses
5000 through 5003 and that the system have been reset prior to executing the
initialization routine.
LOA #
50
TFR A,DPR
LDD #
00
FF
STD $
00
LDD #
04
04
STD $
02

First, resetting the system will reset the PIA if the RESET pin on the PIA
is connected to the system reset, as is usually the case. This will cause all of the
registers in the PIA to be cleared, and therefore the first step of the initialization
procedure is accomplished. The initialization routine first stores the PIA page
number (50) into the direct page register such that direct addressing can be
used for data transfers. Port A is then configured as an input port and port B
as an output port by storing the accumulator D contents (OOFF) to address
5000. Note that since DDRA and DDRB are assigned to consecutive memory

200
locations, the STD instruction will store 00 to address 5000 (DDRA) and FF
to address 5001 (DDRB). Bit 2 of both control registers is then set by storing
0404 to address 5002:5003.
Example B-2: PIA Data I/O
Assuming that the PIA has been configured as in Example B-1, the following
routine will input data from port A, then output the same data to port B.
LDA $
00
STA $
01
To input data from port A, you can use any load instruction which addresses
the port A data register (DRA at address 5000). The data register will be
selected rather than the data direction register since you have already set bit 2
of the control register in your initialization program. To output the data to
port B, you will use a store instruction that addresses the port B data register
(DRB at address 5001). This is a velY simple program since data is just being
transferred from an input to an output port. Once the data is in the 6809,
however, you have the full power of the 6809 instruction set available to
analyze that data to determine the output conditions.
PIA Control Registers
Now we will discuss the control registers of the PIA in more detail. Besides
the bit-2 function of the control register which has already been discussed, the
control register is used mainly for control of interrupts. The bit format of each
control register is shown in Fig. B-7. Actually, each control register is identical
in format and function. Therefore we will confine our discussion to control
register A, keeping in mind that the function of control register B is the same.
Our discussion will begin with bit 0 (CRA-0) and bit 1 (CRA -1) .

7 6 5 I 4 I 3 2 1 I 0
DORA
CRA IROA1 IROA2 CA2 CONTROL CA1 CONTROL
ACCESS

7 6 5 I 4 I 3 2 1 I 0
DDRB
CRB IROB1 IROB2 CB2 CONTROL CB1 CONTROL
ACCESS

Courtesy Motorola Semiconductor Products, Inc.

Fig. B-7. Control register format.

Bits 0 and 1 (CRA-O and CRA-I) of the control register are labeled CAl
Control since they are used to define the effect and active state of the CAl pin
on the PIA. Recall that CAl is an input-only pin that can be used by an i/o
device to generate interrupt requests. When the pin is activated, the interrupt
flag bit (CRA-7) of the control register will be set, indicating an interrupt re-
quest has been generated. Bit 0 (CRA-O) of the control register will determine
the effect of setting this flag. If CRA-O is set (1), the flag will cause the IRQA
output pin to go low, thu~erating an interrupt request to the 6809. If
CRA-O is cleared (0), the IRQA pin will remain high, masking out any inter-
rupt request. Thus CRA-O determines whether the interrupt mode for the port
is active or inactive. Bit 1 of control register A (CRA-l) defines the active state
of pin CAL If CRA-1 is set (1), a low-to-high transition on the CAl pin

201
will cause the interrupt flag bit (CRA-7) of the control register to be set. If
CRA-l is cleared (0), a high-to-Iow transition will cause the interrupt flag to
be set. Thus, either a positive pulse or a negative pulse may be used to generate
an interrupt signal. Fig. B-8 summarizes the function of these two control
register bits.

CRA·1 CRAoO INTERRUPT INPUT INTERRUPT FLAG MPU INTERRUPT REQUEST

(CRB·1) (CRBoO) CA1(CB1) CRA·7(CRB·7) IRQA(lRQB)

0 0 I ACTIVE SET HIGH ON 1 OF CAl (CB1) DISABLED - iRa REMAINS HIGH

GOES LOW WHEN THE INTERRUPT FLAG

0 1 I ACTIVE SET HIGH ON I OF CAl (CB1)
BIT CRA-7 (CRB-7) GOES HIGH

1 0 t ACTIVE SET HIGH ON t OF CAl (CB1) DISABLED - fRO REMAINS HIGH

GOES LOW WHEN THE INTERRUPT FLAG

1 1 1 ACTIVE SET HIGH ON t OF CAl (CB1)
BIT CRA-7 (CRB-7) GOES HIGH

Notes: 1. t indicates positive transition (low to high).

2. I indicates negative transition (high to low).
3. The interrupt flag bit CRA-7 is cleared by the MPU Read of the A Data Register and
CRB-7 is cleared by the MPU Read of the B Data Register
4. If CRA-O (CR~S low when an interrupt occurs (interrupt disabled) and is later brought
high, ilm1i (IROB) occurs after CRA-O (CRB-O) is written to a "one."

Courtesy Motorola Semiconductor Products, Inc.

Fig. 8-8. Function of control register bits 0 and 1.

Bit 2 of the control register (CRA-2) has already been discussed and is used
entirely for register selection. Bits 3, 4, and 5 of the control register (CRA-3,
CRA-4, and CRA-5) are labeled CA2 Control since they are used to define
the function, effect, and active states of the CA2 pin on the PIA. Recall that
the CA2 pin can be designated as either input or output. This designation is
accomplished by CRA-5 of the control register. When CRA-5 is cleared, the
CA2 pin is configured as an input line. When CRA-5 is set, CA2 is designated
as an output line.
CA21nput
When configured as an input line, the CA2 pin is used as an interrupt line
similar to CAL In this mode an active level on CA2 will cause bit 6 (CRA-6)
of the control register to be set. CRA-6 is the interrupt flag used in conjunction
with the CA2 pin in the same way that CRA-7 is used in conjunction with
CAL When being used as an interrupt input, the CA2 active state and effect are
defined by bits 3 and 4 of the control register (CRA-3 and CRA-4). CRA-3
is used to determine the effect of setting the CRA-6 flag similar to the way
CRA-O was used in conjunction with the CRA-7 flag. If CRA-3 is set, the
CRA-6 flag will cause the IRQA pin to go low, thus generating an interrupt
request to the 6809. If CRA-3 is cleared, the IRQA pin will remain high, thus
masking out the interrupt request. Bit 4 of control register A (CRA-4) will
define the active state of pin CA2 similar to the way CRA-l defines the active
state of CAL If CRA-4 is set (1), a low-to-high transition on the CA2 pin will
cause the interrupt flag bit (CRA-6) to be set. If CRA-4 is cleared (0), a
high-to-Iow transition will cause the interrupt flag bit to be set. Fig. B-9 sum-
marizes the function of these control register bits when CA2 is used as an
input line.
CA2 Output
Recall that CA2 will be configured as an output line when bit 5 of the
control register is set. When CA2 is designated as an output line, the interrupt

202
 CONTROL OF CA2 AND CB2 AS INTERRUPT INPUTS CRA5(CRB5) IS LOW

CRA·5 CRA·4 CRA·3 INTERRUPT INPUT INTERRUPT FLAG MPU INTERRUPT REQUEST
(CRB·5) (CRB·4) (CRB·3) CA2(CB2) CRA·6(CRB·6) IRQA(IRQB)

0 0 0 I ACTIVE SET HIGH ON I OF CA2 (CB2) DISABLED - IRQ REMAINS HIGH

GOES LOW WHEN THE INTERRUPT FLAG

0 0 1 I ACTIVE SET HIGH ON I OF CA2 (CB2) BIT CRA-6 (CRB-6) GOES HIGH

0 1 0 1 ACTIVE SET HIGH ON I OF CA2 (CB2) DISABLED - rna REMAINS HIGH

GOES LOW WHEN THE INTERRUPT FLAG
0 1 1 1 ACTIVE SET HIGH ON I OF CA2 (CB2) CRA-6 (CRB-6) GOES HIGH

Notes: 1. 1 indicates positive transition (low to high).

2. I indicates negative transition (high to low)
3. The interrupt flag bit CRA-6 is cleared by the MPU Read of the A Data Register and CRB-6
IS cleared by the MPU Read of the,S Data Register
4. If CRA-3 (CRB-3) is low when an interrupt occurs (interrupt disabled) and is later brought
high, iimA (IROB) occurs after CRA-3 (CRB-3) is written to a "one. "
Courtesy Motorola Semiconductor Products, Inc.
Fig. B-9. Function of control register bits when CA2 is used as an input line.

Hag (CRA -6) will be cleared and remain in that state as long as bit 5 is set.
You will use CA2 as an output for polling and handshaking routines. Hand-
shaking or polling requires the use of status bits that would indicate when a
peripheral device has requested service and when the 6800 has completed the
service. The use of CAl as an input and CA2 as an output as shown in Fig.
B-lO will provide the proper status levels to permit handshaking between the
6809 and a peripheral device. The procedure will be as follows.

ADDRESS

I ~/
PORT A
I\J
V:-NPUT DATA
(pAO-PA7)

CA1
CA2

6809
~
DATA \
(00-07) vi PIA
PERIPHERAL
DEVICE

OUTPUT DAT-t\
PORT B
(PBO-PB7)y

CB1
CB2

I ~~
CONTROL

Fig. B-10.Complete input and output handshaking using the PIA.

203
 1. The peripheral device will generate an interrupt by activating the CAl
line on the PIA, signaling that it has data to give the 6809.
2. The CAl interrupt causes the interrupt flag bit CRA-7 to set.
3. The interrupt flag causes an interrupt request to be generated to the 6809
and also causes CA2 to go high.
4. When the interrupt request is acknowledged, the 6809 will read the data
from the port A data register (DRA).
5. After the read operation takes place, the CA2 line will go low and CRA-7
is cleared, signaling the peripheral that the interrupt has been serviced
and that the 6809 is ready for more data. Thus, the handshake is complete.
To achieve this complete handshake, CRA-5 must be set with CRA-3 and CRA-4
cleared. Therefore bits .5, 4, and 3 of control register A would be 100.
If you do not desire to use interrupts and decide to use programmed if 0,
CAl could be eliminated from Fig. B-lO and CA2 would be used as an output
to signal the peripheral device. Here, the peripheral device would make data
available on a continuing basis to the PIA port, but it needs to know when the
6809 has read the data from the data register so that new data can be supplied.
This is a partial handshake. In this mode, CA2 will normally be high, then go
low after a read-port A operation is executed. It will remain low for one
enable signal (E) cycle. To achieve this mode, CRA-5 and CRA-3 must be set
with CRA-4 cleared. Therefore, bits 5, 4, and 3 of control register A would
be 101.
There are two other possibilities for the output condition of CA2. They are:
1. CRA-5, CRA-4, CRA-3 110 =
2. CRA-5, CRA-4, CRA-3 = 111
In the first case the CA2 output line will be held in a low state and in the
second case CA2 will be held high.
When CA2 and CB2 are used as output lines, they have slightly different
functions. When handshaking, port A will be used completely as an input port
and port B will be used as an output port. Therefore, CA2 will indicate when
the 6809 has read (loaded) data from the port A data register (DRA) and
CB2 will indicate when the 6809 has written (stored) data into the port B
data register (DRB). Figs. B-l1 and B-12 summarize the functions of CA2

CRA·5 IS HIGH

CA2
CRA·5 CRA-4 CRA·3
CLEARED SET
HIGH WHEN THE INTERRUPT FLAG BIT
LOW ON NEGATIVE TRANSITION OF E AFTER
1 0 a AN MPU READ "A" DATA OPERATION.
CRA-? IS SET BY AN ACTIVE TRANSITION
OF THE CAl SIGNAL.

LOW ON NEGATIVE TRANSITION OF E AFTER HIGH ON THE NEGATIVE EDGE OF THE FIRST
1 0 1 AN MPU READ "A" DATA OPERATION. "E" PULSE WHICH OCCURS DURING A DESELECT.

LOW WHEN CRA-3 GOES LOW AS A RESULT ALWAYS LOW AS LONG AS CRA-3 IS LOW.
1 1 a OF AN MPU WRITE TO CONTROL REGISTER" A".
WILL GO HIGH ON AN MPU WRITE TO CONTROL
REGISTER" A" THAT CHANGES CRA-3 TO "ONE".

ALWAYS HIGH AS LONG AS CRA-3 IS HIGH

HIGH WHEN CRA-3 GOES HIGH AS A RESULT
1 1 1 WILL BE CLEARED AS AN MPU WRITE TO CONTROL
OF AN MPU WRITE TO CONTROL REGISTER" A".
REGISTER" A" THAT CLEARS CRA-3 TO A"ZERO"

Courtesy Motorola Semiconductor Products, Inc.

Fig. 8-11. Control of CA-2 as an output

204
 CRB·5 IS HIGH

CB2
CRB·5 CRB-4 CRB·3
CLEARED SET

LOW ON THE POSITIVE TRANSITION OF THE HIGH WHEN THE INTERRUPT FLAG
1 0 0 FIRST EPULSE FOLLOWING AN MPU WRITE BIT CRB-? IS SET BY AN ACTIVE TRANSITION
"B" OATA REGISTER OPERATION. OF THE CB1 SIGNAL.

LOW ON THE POSITIVE TRANSITION OF THE HIGH ON THE POSITIVE EDGE OF THE FIRST
1 0 1 FIRST E PULSE AFTER AN MPU WRITE "E" PULSE FOLLOWING AN "E" PULSE WHICH
"B" DATA REGISTER OPERATION. OCCURED WHILE THE PART WAS DESELECTED.

ALWAYS LOW AS LONG AS CRB-3 IS LOW.

LOW WHEN CRB-3 GOES LOW AS A RESULT OF WILL GO HIGH ON AN MPU WRITE IN CONTROL
1 1 0
AN MPU WRITE IN CONTROL REGISTER "B". REGISTER "B" THAT CHANGES CRB-3 TO "ONE".
ALWAYS HIGH AS LONG AS CRB-3 IS HIGH.
WILL BE CLEARED WHEN AN MPU WRITE HIGH WHEN CRB-3 GOES HIGH AS A RESULT OF
1 1 1
CONTROL REGISTER" B" RESULTS IN AN MPU WRITE INTO CONTROL REGISTER "B".
CLEARING CRB-3 TO "ZERO"

Courtesy Motorola Semiconductor Products, Inc.

Fig. 8-12. Control of C-2 as an output.

and CB2, respectively, when used as an output line. The following examples
should help to clarify the preceding discussion.
Example 8-3
Suppose you store the hex number 27 into control register B. How will this
control port B? The control register would be configured as shown below:
CRB-? CRB-6 CRB-5 CRB-4 CRB-3 CRB-2 CRB-1 CRB-O

This configuration will provide complete data output handshaking through port
B. The following is a description of each bit function:

CRB-O set will cause an interrupt to be generated when the interrupt flag
( CRB-7) is set.
CRB-l set will cause the CRB-7 interrupt flag to set on a low-to-high transi-
tion of the CBl pin.
CRB-2 set selects the data register of port B.
CRB-3 and CRB-4 cleared permits CB2 to go high when the interrupt flag bit
is set by an active transition of CBl and to go low after the 6800 stores data
to the port B data register.
CRB-5 set designates CB2 as an output line.
C RB-6 cleared as a result of CRB-5 being set.
CRB-7 cleared to be used as an interrupt flag for CAL
Example 8-4
Suppose you store the hex number 27 into control register A. How will this
control port A? The control register bit structure would be the same as control
register B was in Example B-3. However, here CA2 would go high after an
interrupt is generated on CAl and go low after a read (load) operation has
been performed on the port A data register. Therefore this would provide for
complete data input handshaking through port A.
Example 8-5
Suppose you store the hex number OF into control register A. How will this
control the port? The control register bit structure would be as shown below:

205
 CRA-7 CRA-6 CRA-5 CRA-4 CRA-3 CRA-2 CRA-1 CRA-O

CRA-O set will cause an interrupt to be generated when the interrupt flag bit
( CRA-7) is set.
CRA-J set will cause the CRA-7 interrupt flag to set on a low-to-high transi-
tion of the CAl pin.
CRA-2 set selects the data register of port A.
CRA-3 set will cause an interrupt to be generated when the interrupt flag bit
( CRA-6) is set.
CRA-4 cleared will cause the CRA-6 interrupt flag bit to set on a high-to-Iow
transition of CA2.
CRA-5 cleared designates CA2 as an input pin.
CRA-6 cleared to be used as an interrupt flag for CA2.
CRA-7 cleared to be used as an interrupt flag for CAL

Fig. B-13 summarizes the control register bit functions.

REVIEW QUESTIONS
1. List the six internal registers of the PIA.

~---, -----, ,------, '~~._-, ' ~ - - - , ~ - - _ .

2. The PIA has ~_~_ programmable data lines. (How many?)

3. Draw the flowchart of the register selection process.

4. What type of integrated-circuit technology is used to manufacture the

PIA? _
5. To configure PAO through PA3 as input and PA4 through PA7 as output,

DDRA must contain ~----(J6).

6. Port of the PIA can always be used to drive the base of a tran-
sistor directly.
7. Two pins on the PIA that are always used as interrupt inputs are

____ and _
~

8. Bit _ _~_ of the control register designates CA2 (CB2) as input or

output.

206
 Determine Active CAl (Cal) Transition for Setting
Interrupt Flag IRQAIB)l -(bit b7)
o IRQA(B)l set by high-to-low transition on
CA1ICBlI
1 IRQA(B)l set by low-to-high transition on
CA1ICBli

I CAl (CB1) Interrupt Request Enable/Disable

bO = 0 Disables I RGA(B) MPU Interrupt by CA 1 (CB1)
active transition. 1
1 Enable I ROA(B) MPU Interrupt by CA 1 (CB1)
IRQA(B) 1 Interrupt Flag (bit b7)
Goes high on active transition of CA 1 (CB1); Automatically 1. I RGAlB) will occur on next (MPU generated) positive
cleared by MPU Read of Output Register A(Bl. May also be transition of bO if CAl lCB1) active transition occurred
cleared by hardware Reset. while interrupt was disabled.

I
L b7 I b6 I b5
'---------------L
I I bl I
~
b<j> I
I
IRQAIBl111RQAIBI21
Flag Flag
CA21CB21
Control
I DDR
Access
I CA11CBlI
Control
I

IRQA(B)2 Interrupt Flag (bit b61

I
T T'-------------,
I
CA2 (CB2) Established as Input (b5 co 0): Goes high on active Determines Whether Data Direction Register Or Output
transition of CA2 (CB2); Automatically cleared by MPU Read Register is Addressed
of Output Register A(B). May also be cleared by hardware
Reset. b2 eo 0 Data Direction Register selected.
CA2 (CB2) Established as Output (b5 1): IRQA(B)2 =- 0,
not affected by CA2 lCB2) transitions b2 = 1 Output Register selected

I I
CA2 (CB2) Established as Output by b5 = 1
CA2 (CB21 Established as Input by b5 = 0
(Note that operation of CA2 and CB2
output functions are not identical) b4 b3

L
~CA2
Read Strobe With CA 1 Restore

CA2 goes Iowan first high·to-

1 CA2 (CB2) Interrupt Request Enable/
Disable

b3 = 0 Disables I ROA(B) MPU

Interrupt by CA2 (CB2)
low E transition following an
MPU Read of Output Register active transition. l
A; returned high by next
active CA 1 transition. b3 = 1 Enables I ROA(S) MPU
Interrupt by CA2 (CB2)
b3 = 1 Read Strobe with E Restore active transition.
CA2 goes Iowan first high-to-
low E transition following an 1. IRGA(B) will occur on next (MPU
MPU Read of Output Register generated) positive transition of b3
A; returned high by next if CA2 (CB2) active transition
high-to·low E transition. occurred white interrupt was
disabled
~CB2
-------..... Determi.nes Active CA2 (CB2) Transition
Write Strobe With Cel Restore
for Setting I nterrupt Flag I ROA(B)2
CB2 goes on Iowan first low- (bit b6)
to high E transition following
an MPU Write into Output b4 '7 0 I RQA(B)2 set by high-to-Iow
Register B; returned high by transition on CA2 (CB2l.
the next active CBl transition
b4 = 1 I ROA(B)2 set by low-to-high
Write Strobe With E Restore
transition on CA2 {CB2L
CB2 goes Iowan first low-to·
high E transition following an
b3 MPU Write into Output
Register B; re~urned hig~ ~y the

l next low-to-hlgh E tranSition.

Set/Reset CA2 (CB2)

CA2 (CB2) goes low as MPU writes

b3 = 0 into Control Register
CA2 (CB2l goes high as MPU writes
b3 = 1 into Control Register.

Courtesy Motorola Semiconductor Products, Inc.

Fig. 8-13. Control register bit functions.

207
 9. When CA2 (CB2 ) is used as an interrupt input, bit of the
control register is used as the CA2 (CB2) interrupt Hag bit.

10. The E (enable) pin of the PIA is usually connected to the _ _-+--~.
11. A high-to-Iow transition on the Reset pin of the PIA will cause what to
happen?

12. How are the interrupt request pins (IRQA and IRQB) usually connected?

13. Write an initialization program to configure port A as an output port and

and port B as an input port. Assume the PIA is assigned to addresses 8000
through 8003 and a reset has occurred prior to the program execution.

14. Assuming the PIA has been initialized as in problem 12, write a program
to input data from port B, and output the complement of that data to
port A.

208
15. When would CA2 (CB2) be used as an output pin?

16. Describe what is meant by complete handshaking.

17. How would the PIA ports be configured to provide complete input and
output handshaking?

18. Bit 7 of control register A is labeled and what is its function?

19. When CAl (CBl) and CA2 (CB2) are used as interrupt inputs, bits

and of the control register are used to define the

active levels of these pins.
20. To provide complete input handshaking, bits 5, 4, and 3 of CRA must be

ANSWERS
1. Data Register A (DRA)
Data Direction Register A (DDRA)
Control Register A (CRA)
Data Register B (DRB)
Data Direction Register B (DDRB)
Control Register B (CRB)
2. 16
3.
. . .1- - - - - PIA -------,1
PORT A PORT B

I RSI
I I
iRSI'Oi i • ,

RSO' 0 RSO' I RSO' 0 RSO' I

I I I I
DORA OR ORA CRA DDRB OR ORB CRB
(DEPENDS ON CRA-21 (DEPENDS ON CRB-21

4. NMOS
5. F016
6. B
7. CAl and CBl

209
 8. Five
9. Six
10. E clock
11. All internal PIA registers will be cleared.
12. Wire-oRed together, then connected to the 6809 IRQ/FIRQ lines.
13.
LDA #
80
TFR A,DPR
LDD #
FF
00
STD $
00
LDD #
04
04
STD $
02
14.
LDA $
01
COMA
STA $
00
15. To provide complete or partial handshaking between the 6809 and a
peripheral device.
16. A peripheral device requests service from the 6809; the 6809 acknowledges
the request and signals the peripheral device when the service is completed.
17. Port A as an input port with CAl as an interrupt input line and CA2 as
an output peripheral control line. Port B as an output port with CBl as an
interrupt input line and CB2 as an output peripheral control line.
18. Bit 7 of control register A is the CAl interrupt request flag for port A
( IRQAl ). It is used as an interrupt flag for interrupts generated on pin
CAL
19. One and four
20. 100

210
 APPENDIX C

Specification Sheets

The following specification sheets are provided through the cour-

tesy of Motorola Semiconductor Products, Inc., Austin, Texas.
MC6809/ MC68A09/MC68B09 MC6842
MC6809E/MC68A09E/MC68B09E MEK6809EAC
MC6829 MEK6809D4/ MEK68KPD
MC6839

211
 MC6809/MC68A09/MC68B09

HMOS
(HIGH DENSITY N-CHANNEL. SILICON-GATE)

8-BIT
MICROPROCESSING
UNIT

8-BIT MICROPROCESSING UNIT

The MC6809 is a revolutionary high performance 8-bit microprocessor
which supports modern programming techniques such as position in-
dependence, reentrancy, and modular programming.
This third-generation addition to the M6800 family has major architectural
improvements which include additional registers. instructions and addressing
modes.
The basic instructions of any computer are greatly enhanced by the
presence of powerful addressing modes. The MC6809 has the most complete
set of addressing modes available on any 8-bit microprocessor today
The MC6809 has hardware and software features which make it an ideal
processor for higher level language execution or standard controller applica-
tions.

MC6800 COMPATIBLE
• Hardware - Interfaces with All M6800 Peripherals
• Software - Upward Source Code Compatible Instruction Set and
Addressing Modes
ARCHITECTURAL FEATURES
• Two 16-bit Index Registers
• Two 16-bit Indexable Stack Pointers
• Two 8-bit Accumulators can be Concatenated to Form One 16-8it
Accumulator
• Direct Page Register Allows Direct Addressing Throughout Memory
HARDWARE FEATURES
• On Chip Oscillator 14 x fo XT AU
• DMA/BREO Allows DMA Operation or Memory Refresh PIN ASSIGNMENT
• Fast Interrupt Request Input Stacks Only Condition Code Register
and Program Counter
• MRDY Input Extends Data Access Times for Use With Slow
Memory
• Interrupt Acknowledge Output Allows Vectoring By Devices VSS HALT
• SYNC Acknowledge Output Allows for Synchronization to External
NMI XTAL
Event
• Single Bus-Cycle RESET iRO EXTAL
• Single 5-Volt Supply Operation FIRQ RESET
• NMI Blocked After RESET Until After First Load of Stack Pointer BS MROY
• Early Address Valid Allows Use With Slower Memories
BA 0
• Early Write-Data for Dynamic Memories
SOFTWARE FEATURES Vee E
• 10 Addressing Modes AO OMA/BREO
• M6800 Upward Compatible Addressing Modes At R/W
• Direct Addressing Anywhere in Memory Map
A2 00
• Long Relative Branches
• Program Counter Relative A3 01
• True Indirect Addressing A4 02
• Expanded Indexed Addressing: A5 03
0, 5, 8, or 16-bit Constant Offsets
A6 04
8, or 16-bit Accumulator Offsets
Auto-Increment/Decrement by 1 or 2 A7 05
• Improved Stack Manipulation AS 06
• 1464 Instructions with Unique Addressing Modes
A9 07
• 8 x 8 Unsigned Multiply
AlD Al5
• 16-bit Arithmetic
• Transfer/Exchange All Registers All Al4
• Push/ Pull Any Registers or Any Set of Registers Al2 Al3
• Load Effective Address

212
 MC6809/MC68A09/MC68B09

MAXIMUM RATINGS
Rating Symbol Value Unit This device contains circuitry to protect the
inputs against damage due to high static
Supply Voltage - 0.3 to + 7.0 Vdc
VCC voltages or eleCtrlc fields; however, It is ad
Input Voltage Vin -0.3 to + 7.0 Vdc vised that normal precautions be taken to
Operating Temperature Range o to+ 70 'c avoid application of any voltage higher than
Storage Temperature Range -55 to + 150 'c maximum rated voltages to this high im-
Thermal Resistance Ceramic 50 'C/W pedance circuit
Plastic 100 'C/W

ELECTRICAL CHARACTERISTICS IVCC = 50 V ±5%, VSS = 0 TA = 0 to 70'C unless otherwise noted I

Characteristic Symbol Min Typ Max Unit
Logic, EXtal, VSS + 20 VCC
Input High Voltage VIH Vdc
RESET V~~ + 4.0 VCC
Input Low Voltage Logic, EXtal, i'iESTI VIL VSS - 03 VSS + 08 Vdc
Input Leakage Current
Logic lin 1.0 2.5 ~Adc
IVin ~ 0 to 5.25 V, VCC = maxi
Output High Voltage
IILoad = - 205 ~Adc, VCC = mini 00-07 VSS + 2.4
VOH Vdc
IILoad = - 145 ~Adc, VCC = mini Ao-A15, R/W, 0, E VSS + 2.4
IILoad = - 100 ~Adc, VCC = mini 8A, BS VSS + 2.4
Output Low Voltage
VOL VSS + 0.5 Vdc
IILoad = 2.0 mAdc, VCC = min)
Power Dissipation Po 1.0 W
Capacitance' (in
IV in = 0, TA = 25'C, f = 1.0 MHzI 00-07 10 15
pF
Logic Inputs, EXtal 7 10
AO-A15, R/W, BA, BS Cout 12 pF
Frequency of Operation MC6809 4
MC68A09 fXTAL 6 MHz
ICrystal or External Input I MC68B09 8
Three-State 10ff Statel Input Current 00-07 2.0 10
ITSI ~Adc
IV ,n = 0.4 to 2.4 V, VCC = maxi AO-A15, R/W 100

READ/WRITE TIMING I Reference Figures 1 2,7,8 9 10,11,12,13 and 141

MC~ MC68A09 MC68B09
Characteristic Symbol Unit
Min Typ Max Min Typ Max Min Typ Max
Cycle Time tr.yr. 1000 667 500
Total Up Time tUT 975 640 480
Peripheral Read Access Time
tACC 695 440 320
IUT - tAD - tDSR = tACC
Data Setup Time I Readl IDSR 80 60 40
Input Data Hold Time IDHR 10 10 40
Output Data Hold Time tDHW 30 30 30
Address Hold Time
IAH 20 20 20
IAddress, R/WI
Address Delay lAD 200 140 110
Data Delay Time IWritel tDDW 225 180 145
Elow 10 Ohioh Time tAVS 250 165 125
Address Valid to 0hloh lAO 50 25 15
Processor Clock Low tPWEL 450 295 210
Processor Clock High IpWEH 450 280 220
MRDY Set Up Time tPCSM 125 125 125
Interrupts Set Up Time Ipr.S 200 140 110
HALT Set Up Time tPCSH 200 140 110
RESET Sel Up Time IpCSR 200 140 110
~SetUpTime Ipr.SD 125 125 125
Crystal Osc Start Time IRC 100 100 100
E Rise and Fall Time tEr, tEf 5 25 5 25 5 20
Processor Control Rise/ Fall tPCr, tpCf - 100 100 100
o Rise and Fall Time tOr, tOt 5 25 5 25 5 20
o Clock High IPWOH 450 280 220

213
 MC6809/MC68A09/MC68B09

FIGURE 1 - READ DATA FROM MEMORY OR PERIPHERALS

1 4 - - - - - - - - - teye ---------~

05V

2.4 V

R/W

ADDR
SA, SS' I""""::-~'_+-+_--------_---_+++->--.....-

Data ----------------c:::C\
~NotValld

FIGURE 2 - WRITE DATA TO MEMORY OR PERIPHERALS

R/W
---+~...l....I:::::.;.--+-----_t_--------H"""..>....>

ADDR
SA, SS·_~'--"1...o:::::_....:::>"t-_+_-------------++...--

Data

[SSSJ Not Valid

'Hold time for SA, SS not specified

214
 MC6809/MC68A09/MC68B09

FIGURE 3 - MC6809 EXPANDED BLOCK DIAGRAM

~VCC
~VSS

IR

DMA/BREO
Riw

HALT
BA
BS
XTAL

EXTAL
MROY

E
Q

FIGURE 4 - BUS TIMING TEST LOAD PROGRAMMING MODEL

As shown in Figure 5, the MC6809 adds three registers to
the set available in the MC6800. The added registers include
4.75 V a Direct Page Register, the User Stack painter and a second
Index Register.

ACCUMULATORS lA, B, D)
MM06150 The A and 8 registers are general purpose accumulators
Test POint ~~_---f'III-"" or Equiv which are used for anthmetic calculations and manipulation
of data
MM0700J Certain instructions concatenate the A and 8 registers to
or Equiv form a single 16-bit accumulator. ThiS is referred to as the D
Register, and is formed with the A Register as the most
Significant byte

DIRECT PAGE REGISTER (DP)

The Direct Page Register of the MC6809 serves to enhance
C = 30 pF for BA, BS R ~ 11.7 kO for 00-07 the Direct Addressing Mode. The content of this register ap-
130 pF for 00-07, E, Q 16.5 kO for Ao-A15, E, Q, R/W pears at the higher address outputs IAB-A 151 during direct
90 pF for Ao-A15, R/W 240 for BA, BS Addressing Instruction execution. ThiS allows the direct
mode to be used at any place in memory, under program
control. To ensure 6800 compatibility, all bits of this register
are cleared during Processor Reset

215
 MC6809/M C68A09/MC68B09

FIGURE 5 - PROGRAMMING MODEL OF THE MICROPROCESSING UNIT

15
x- Index Register }
Y - Index Register
1---------~------_____4 Pomter Registers
U - User Stack Pointer
S - Hardware Stack Pointer
PC Program Counter

A I Accumulators
v
D

DP Direct Page Register

7 0
IElF I H I I I N Iz I IC I
V cc - CondItion Code RegIster

INDEX REGISTERS IX, Y) FIGURE 6 - CONDITION CODE REGISTER FORMAT

The Index Registers are used in indexed mode of address-
mg. The 16-blt address in this register takes part in the
calculation of effective addresses. This address may be used
to pomt to data directly or may be modlfed by an optional Carry
constant or register offset. DUring some indexed modes, the Overflow
contents of the index register are incremented and Zero
decremented to point to the next item of tabular type data ' - - - - - - Negative
All four painter registers IX, Y, U, SI mav be used as index L-- IRQ Mask
registers ' - - - - - - - - Half Carry
L-- FIRQ Mask
STACK POINTER (U, S) ' - - - - - - - - - - - - Entire Flag
The Hardware Stack Painter lSI is used automatically by
the processor during subroutine calls and interrupts. The
stack pointers of the MC6809 point to the top of the stack, In
contrast to the MC6800 stack pointer, which pointed to the
next free location on the stack. The User Stack POinter lUI is
controlled exclusively by the programmer thus allowing CONDITION CODE REGISTER
arguments to be passed to and from subroutines with ease. DESCRIPTION
Both Stack Pointers have the same indexed mode address- BITO (CI
Ing capabilities as the X and Y registers, but also support
Bit a IS the carry flag, and IS usually the carry from the
Push and Pull instructions. This allows the MC6809 to be us-
binary ALU. C is also used to represent a 'borrow' from sub-
ed efficiently as a stack processor. greatly enhancing its abili-
tract like instructions ICMP, NEG, SUB, SBCI and is the
ty to support higher level languages and modular programm-
complement of the carry from the binary ALU
ing

PROGRAM COUNTER BIT 1 (VI

The Program Counter is used by the processor to point to Bit 1 IS the overflow flag, and is set to a one by an opera-
the address of the next instruction to be executed by the pro- tion which causes a signed two's complement arithmetic
cessor. Relative Addressing is provided allowing the Pro- overflow. This overflow IS detected in an operation in which
gram Counter to be used like an index register in some situa- the carry from the MSB in the ALU does not match the carry
tions from the MSB-1

CONDITION CODE REGISTER BIT 2 III

The Condition Code Register defines the State of the Pro- Bit 2 IS the zero flag, and is set to a one If the result of the
cessor at any given time. See Figure 6 prevIous operation was identically zero

216
 MC6809/MC68A09/MC68B09

BIT 3 (N) READ/WRITE (R/W)

Bit 3 is the negative flag, which contains exactly the value This signal indicates the direction of data transfer on the
of the MSB of the result of the preceding operation. Thus, data bus. A low indicates that the MPU is writing data onto
a negative two's-complement result will leave N set to a one the data bus. R/W is made high impedance when BA is
high. RIW is valid on the rising edge of 0 Refer to Figures 1
BIT 4 (I) and 2
Bit 4 IS the IRO mask bit. The processor will not recognize
Interrupts from the IRO line if this bit IS set to a one. NMI, RESET
FIRO, iR'O, RESET, and SWI all are set I to a one, SWI2 and A low level on thiS Schmitt-trigger input for greater than
SWI3 do not affect I. one bus cycle will reset the M PU, as shown in Figure 7. The
Reset vectors are fetched from locations FFFE16 and FFFF16
BIT 5 (HI !Table 1) when Interrupt Acknowledge is true,
Bit 5 is the half-carry bit, and is used to Indicate a carry (SA • BS = 11. During initial power-on, the Reset line should
from bit 3 In the ALU as a result of an S-blt addition only be held low until the clock oscillator IS fully operational. See
IADC or ADDI This bit is used by the DAA instruction to Figure S
perform a BCD decimal add adjust operation. The state of Because the MC6809 Reset pin has a Schmitt-trigger input
this flag IS undefined in all subtract-like instructions With a threshold voltage higher than that of standard
peripherals, a simple RIC network may be used to reset the
BIT 6 IF) entire system. This higher threshold voltage ensures that ail
peripherals are out of the reset state before the Processor.
Bit 6 IS the FIRO mask bit. The processor will not
recognize interrupts from the FIRO line if this bit is a one
NMI, FIRO, SWI, and RESET all set F to a one iRQ, SWI2
HALT
and SWI3 do not affect F
A low level on this input pin will cause the MPU to stop
running at'the end of the present instruction and remain
BIT 7 IE)
halted indefinitely without loss of data. When halted, the BA
Bit 7 IS the entire flag, and when set to a one indicates that output is driven high indicating the buses are high im-
the complete machine state (all the registersl was stacked, pedance BS is also high which indicates the processor is in
as opposed to the subset state IPC and CCI. The E bit of the the Halt or Bus Grant state. While halted, the MPU will not
stacked CC IS used on a return from interrupt (RTI) to deter- respond to external real-time requests IFIRO, iRQI although
mine the extent of the unstacklng. Therefore, the current E DMA/BREO will always be accepted, and NMI or RESET will
left ,n the Condition Code Register represents past action be latched for later response. During the Halt state 0 and E
continue to run normally. If the MPU is not running (RESET,
DMA/BREOI, a halted state (BAeBS=11 can be achieved
by pulling HALT low while RESET is still low. If DMA/BREO
MC6809 MPU SIGNAL and HALT are both pulled low, the processor will reach the
DESCRIPTION last cycle of the instruction (by reverse cycle stealing) where
the machine will then become halted. See Figure 9
. POWER (VSS, VCC)
Two pins are used to supply power to the part VSS is
BUS AVAILABLE, BUS STATUS IBA, BS)
ground or 0 volts, while VCC IS + 5.0 V ± 5%
The Bus Available output is an indication of an internal
ADDRESS BUS (Ao-A15) control Signal which makes the MOS buses of the MPU high
Sixteen pins are used to output address information from impedance. ThiS signal does not imply that the bus will be
the MPU onto the Address Bus. When the processor does available for more than one cycle. When BA goes low, an ad-
not require the bus for a data transfer, it will output address ditional dead cycle Will elapse before the MPU acquires the
FFFF16, Riw = 1, and BS = 0; this is a "dummy access" or bus.
VMA cycle. Addresses are valid on the rising edge of 0 (see The Bus Status output signal, when decoded with BA,
Figures 1 and 21. All address bus drivers are made high- represents the MPU state (valid with leading edge of 01
impedance when output Bus Available (BAI is high. Each pin
will drive one Schottky TTL load or four LS TTL loads, and MPU State
MPU State Definition
typically 90 pF. BA BS
0 0 Normal (Runningl
DATA BUS (00-07)
0 1 Interrupt or RESET Acknowledge
These eight pins provide communication with the system
1 0 SYNC Acknowledge
bi-directional data bus. Each pin will drive one Schottky TTL
load or four LS TTL loads, and typically 130 pF. 1 1 HALT or Bus Grant

217
....
N
CD
FIGURE 7 - RESET TIMING

. ' . 8~ !e-",---¥m. '~m. ,+' ,3+ . ,+" . 5-1-,' . 8+" , 7+" . 8+" , 3+",. '0-1

&~,e'S8 I
.-k",....--------------\\.~, ;D/$${~=,1-'8(-S8----------

3:
8A~ ~:~:; ::~~; = ",:,,~:c. H
()
Q)
CD
o
8S~~ r---\ II r---\L- _ CD

·Note: Parts with data codes prefixed by 7F will come out of RESET one cycle sooner than shown i()
0)
CD
FIGURE 8 - CRYSTAL CONNECTIONS ANO OSCILLATOR START UP o»
MC6809 Nominal Crystal Parameters" CO
3.58 MHz 4.00 MHz 6.0 MHz 8.0 MHz i()
RS 600 500 30-50 0 20-400
Q)
Co 35 pF 6.5 pF 4-6 pF 4·6 pF (ll)
C, 0.015 pF 0.025 pF 0.01-0.02 pF 001-002 pF aI
>30K >20 K >20 K
o
0 >40K CO
All parameters are 10%
RESET----f----c>~ "NOTE: These are representative AT-cut crystal parameters only
types of cut may also be used
Crystals of other

tRC~
MC6809 -------il DI 39

~~
381 Yl I 39

D .l- 38~CE-------J39
Cin ::c TCout
Co
 MC6809/MC68A09/MC68B09

FIGURE 9 - HALT AND SINGLE INSTRUCTION

EXECUTION FOR SYSTEM DEBUG

2nd To Last l.dS! Cycle

Cycle Of Ot

I"C~~:'o, .. I.C:;',~o, ..I. ~;;,~ ..I. Dead Instruction Instruct,on Dead

)}---~~ ~~~~---e.,!"'.~C,-,,VO-,-I' ••
."!4f--,-F,=,,-,-h.~I E-,-,e-'-""-"tte.""I.t-c-,-YC_"-'.'!"I.I----H'_he~d

o~

E~
t~'PCSH 'PCI
HALT 201.1 Y.2..BV~ ~, -,,-,,-~.

Ad::;"~\-, ~.....- _
FelCh becule

R/W~)-'-------~--'------
-------'"~)-'
--------,\'-----~/
_ _ _ _ _ _~~S \ ;'---

~~':~> ~>----
InstructIon

Interrupt Acknowledge is indicated during both cycles of a recognition of an NM I, the entire machine state is saved on
hardware-vector-fetch IRESET, NMI, FIRQ, iRQ, SWI, the hardware stack. After reset, an NMI will not be recogniz-
SWI2, SW131. This signal, plus decoding of the lower four ed until the first program load of the Hardware Stack POinter
address lines, can provide the user with an indication of lSI The pulse width of NMIIow must be at least one E cycle
which interrupt level is being serviced and allow vectoring by If the NMI input does not meet the minimum set up With
device. See Table 1 respect to Q, the interrupt will not be recognized until the
Sync Acknowledge IS indicated while the MPU IS waitmg next cycle. See Figure 10
for external synchronization on an interrupt line
Halt/Bus Grant is true when the MC6809 is In a Halt or Bus FAST-INTERRUPT REQUEST (FIRQ)"
Grant condition A low level on this input pin Will initiate a fast Interrupt se-
quence, proVided its mask bit IFI in the CC IS clear. This se-
TABLE 1: MEMORY MAP FOR INTERRUPT VECTORS quence has priority over the standard Interrupt Request
(lRm, and IS fast in the sense that It stacks only the contents
Memory Map For of the condition code register and the program counter. The
Vector Locations Interrupt Vector Interrupt service routine should clear the source of the Inter-
Description rupt before doing an Rn See Figure 11
MS LS
FFFE FFFF RESET INTERRUPT REQUEST (iRQ)"
FFFC FFFD NMI A low level Input on this pin will initiate an Interrupt Re-
FFFA FFFB SWI quest sequence provided the mask bit I I) in the CC is clear
FFF8 FFF9 iRO Since IRQ stacks the entire machine state it provides a
FFF6 FFF7 FiRi5 slower response to Interrupts than FIRQ. IRQ also has a
FFF4 FFF5 SWI2 lower priority than FIRQ Again, the interrupt service routine
should clear the source of the interrupt before dOing an RTI
FFF2 FFF3 SWI3
See Figure 10
FFFO FFFI Reserved

"NOTE: NMI, FIRQ and IRQ requests are latched by the fail-
NON MASKABLE INTERRUPT (NMI)" ing edge of every Q, except during cycle steal-
A negative edge on this input requests that a non- ing operations le.g., DMAI where only NMI is
maskable interrupt sequence be generated. A non-maskable latched. From this pOint, a delay of at least one bus
interrupt cannot be inhibited by the program, and also has a cycle Will occur before the interrupt is serviced by
higher priority than FIRQ, IRQ or software interrupts During MPU

219
 MC6809/MC68A09/MC68B09

I
i
i
i
-1
i 1
-1 t
i i
Cl
z
-! t
~
i= i t
Ii:
~
f-
1 i-
~

I~
i t
c
z
~

,~
i t
~
I
1 i
w
a::
:::>
Cl
-t !
u::

1 t
1 t
i t
1 1
I~

i ~ '"
~ci3
I~

t
11
I~
~~ i~l~

220
 MC6809/MC68A09/M C68B09

XTAL, EXTAL
These inputs are used to connect the on-chip oscillator to the MPU into a Halt mode to three-state the machine, but
an external parallel-resonant crystal. Alternately, the pin MRDY will not stretch the clocks.
EXTAL may be used as a TTL level input for external timing
by grounding XT AL. The crystal or external frequency is four
times the bus frequency. See Figure 8. Proper RF layout
techniques should be observed in the layout of printed circuit DMA/BREQ
boards. The DMA/BREQ input provides a method of suspending
execution and acquiring the MPU bus for another use, as
E, a shown in Figure 14. Typical uses include DMA and dynamic
memory refresh.
E is similar to the MC6800 bus timing signal <1>2; 0 is a
Transition of DMA/BREQ should occur during Q. A low
quadrature clock signal which leads E. 0 has no parallel on
level on this pin will stop instruction execution at the end of
the MC6800. Addresses from the MPU will be valid with the
the current cycle. The MPU will acknowledge DMA/BREQ
leading edge of Q. Data is latched on the falling edge of E.
by setting BA and BS to a one. The requesting device will
Timing for E and 0 is shown in Figure 12.
now have up to 15 bus cycles before the MPU retrieves the
bus for self-refresh. Self-refresh requires one bus cycle with
MRDY a leading and trailing dead cycle. See Figure 15.
This input control signal allows stretching of E and 0 to Typically, the DMA controller will request to use the bus
extend data-access time. E and 0 operate normally while by asserting DMA/BREQ pin low on the leading edge of E.
MRDY is high. When MRDY is low, E and 0 may be stretch- When the MPU replies by setting BA and BS to a one, that
ed in integral multiples of quarter (1/4) bus cycles, thus cycle will be a dead cycle used to transfer bus mastership to
allowing interface to slow memories, as shown in Figure the DMA controller.
13(A). A maximum stretch is 10 microseconds. During non- False memory accesses may be prevented during any dead
valid memory access lVMA cycles) MRDY has no effect on cycles by developing a system DMAVMA signal which is
stretching E and 0; this inhibits slowing the processor during LOW in any cycle when BA has changed
"don't care" bus accesses. MRDY may also be used to When BA goes low leither as a result of DMA/BREQ =
stretch clocks lfor slow memory) when bus control has been HIGH or MPU self-refresh), the DMA device should be taken
transferred to an external device (through the use of HALT off the bus. Another dead cycle will elapse before the MPU
and DMA/BREQI. accesses memory, to allow transfer of bus mastership
NOTE: Four of the early production mask sets (G7F, T5A, without contention.
P6F, T6M) require synchronization of the MRDY input with
the 4f clock. The synchronization necessitates an external
oscillator as shown in Figure 13 lBI. The negative transition
of the MRDY signal, normally derived from the chip select MPU OPERATION
decoding, must meet the tPCSM timing. With these four During normal operation, the MPU fetches an instruction
mask sets, MRDY's positive transition must occur with the from memory and then executes the requested function.
rising edge of 4f. This sequence begins at RESET and is repeated indefinitely
In addition, on these same mask sets, MRDY will not unless altered by a special instruction or hardware occur-
stretch the E and 0 signals if the machine is executing either rence. Software instructions that alter normal MPU opera-
a TFR or EXG instruction during the HALT high to low transi- tion are: SWI, SWI2, SWI3, CWAI, RTI and SYNC. An in-
tion. If the MPU executes a CWAI instruction, the machine terrupt, HALT or DMA/BREQ can also alter the normal ex-
pushes the internal registers onto the stack and then awaits ecution of instructions. Figure 16 illustrates the flow chart for
an interrupt. During this waiting period, it is possible to place the MC6009.

FIGURE 12 - EtQ RELATIONSHIP

Start of Cycle End of Cycle (Latch Datal

I
I 1

E ~:--",O.,,-5":"V -,/r----------.~
I I
I+-tAvsj 1
I 24V \ 1
o I ......_ _..J..I _

I Address Valid I

221
 MC6809/MC68A09/MC68B09

FIGURE 13lAl - MRDY TIMING

\"------'/ \"------'/
/
MRDY

FIGURE 13(8) - MC6809 MRDY SYNCHRONIZATION

+5V

+5

RESET Vee EXTAL""38"--- -------,

+5
To
System 24
as
Required

MC6809

MRDY Stretch
Stretch = 07 RC

XTAL 12

Data and Address Bus to System as Required (RAM and Peripherals)

222
 MC6809/MC68A09/MC68B09

FIGURE 14 - TYPICAL DMA TIMING « 14 CYCLES)

MPU DEAD DMA DEAD MPU

2.0 V

~tPCSD
------------------"""""
BA, BS
\-------
DMAVMA"
\'----~/ \,--_~r
ADDR
IMPUI
-J»)-------------------------<C
IDAS~~I------------«I... ....J)>-----

FIGURE 15 - AUTO-REFRESH DMA TIMING (> 14 CYCLES)

(REVERSE CYCLE STEALING)

IDEAD I
.... t - - - - - - - - 1 4 DMA CyCleS--------~.IDEADIMPulocJ.__DMA-
I I I I I I
I I I I I I
I
Q I
I
5M"ATi3illii \ : I
BA, BS ---r
I
I
I
,..-+:- - - - -
DMAVMA .--\...J...------------------------lJ---\J:------

*5"M"AV'M'A is a signal which is developed externally, but is a system requirement for OMA

223
~
FIGURE 16 - FLOWCHART FOR 6809 INSTRUCTIONS

~.l'

s:
o
~
o
~
s:
o
0)
C»
»
o
~
s:
o
0)
C»
I:D
o
CD

M6809 Interrupt Structure

Bus State BA BS
Running 0 0
Interrupt or Reset Acknowledge 0 1
Sync 1 0
Halt/ Bus Grant 1 1
NOTE: Asserting RESET will result In entering the reset sequence from any pOint in the flow chart
 MC6809/MC68A09/MC68B09

ADDRESSING MODES

The basic instructions of any computer are greatly EXTENDED INDIRECT

enhanced by the presence of powerful addressing modes. As a special case of indexed addressing (discussed
The MC6809 has the most complete set of addressing modes below), one level of indirection may be added to Extended"
available on any microcomputer today. For example, the Addressing. In Extended Indirect. the two bytes following
MC6809 has 59 basic instructions; however, it recognizes the postbyte of an Indexed instruction contain the address of
1464 different variations of instructions and addressing the data.
modes. The addressing modes support modern programm- LOA [CAT]
ing techniques. The following addressing modes are LOX [$FFFE]
available on the MC6809:
STU [DOG]
Inherent (Includes Accumulator)
Immediate
Extended DIRECT ADDRESSING
Extended Indirect Direct addressing is similar to extended addressing except
Direct that only one byte of address follows the opcode. This byte
specifies the lower 8 bits of the address to be used. The up-
Register
per 8 bits of the address are supplied by the direct page
Indexed
register. Since only one byte of address is required in direct
Zero-Offset
addressing, this mode requires less memory and executes
Constant Offset
faster than extended addressing. Of course, only 256 loca-
Accumulator Offset tions (one page) can be accessed without redefining the con-
Auto Increment/Decrement
tents of the DP register. Since the DP register is set to $00 on
Indexed Indirect Reset. direct addressing on the MC6809 is compatible with
Relative direct addreSSing on the M6800. Indirection is not allowed In
Short/ Long Relative Branching direct addressing. Some examples of direct addressing are'
Program Counter Relative Addressing LOA $30
SETDP $10 (Assembler directive)
INHERENT (INCLUDES ACCUMULATOR)
LOB $1030
In this addressing mode, the opcode of the instruction
contains all the address information necessary Examples of LOD < CAT
Inherent Addressing are: ABX, DAA, SWI, ASRA, and
CLRB. NOTE: < is an assembler directive which forces direct
addressing
IMMEDIATE ADDRESSING
In Immediate Addressing, the effective address of the data
is the location immediately following the opcode (i.e., the REGISTER ADDRESSING
data to be used in the instruction immediately follows the op- Some opcodes are followed by a byte that defines a
code of the instruction!. The MC6809 uses both 8 and 16-bit register or set of registers to be used by the instruction. This
immediate values depending on the size of argument is called a postbyte Some examples of register addressing
specified by the opcode. Examples of instructions with Im- are:
mediate Addressing are: TFR X, Y Transfers X into Y
LOA 1$20 EXG A, B Exchanges A with B
LOX I$FOOO PSHS A, B, X, Y Push Y, X, B and A onto S
LOY ICAT PULU X, Y, D Pull 0, X, and Y from U
NOTE: 1 signifies Immediate addressing, $ signifies hexa-
decimal value
INDEXED ADDRESSING
EXTENDED ADDRESSING
In all indexed addressing, one of the pointer registers (X,
In Extended Addressing, the contents of the two bytes im-
Y, U, S, and sometimes PC) is used in a calculation of the ef-
mediately following the opcode fully specify the 16-bit effec-
fective address of the operand to be used by the instruction.
tive address used by the instruction. Note that the address
Five basic types of indexing are available and are discussed
generated by an extended instruction defines an absolute ad-
below. The postbyte of an indexed instruction specifies the
dress and is not position independent. Examples of Extended
basic type and variation of the addressing mode as well as
Addressing include'
the pointer register to be used. Figure 17 lists the legal for-
LOA CAT mats for the postbyte. Table 2 gives the assembler form and
STX MOUSE the number of cycles and bytes added to the basic values for
LDD $2000 Indexed addressing for each variation.

225
 MC6809/MC68A09/MC68B09

FIGURE 17 - INDEXED ADDRESSING POSTBYTE Zero-Offset Indexed - In this mode, the selected pointer
REGISTER BIT ASSIGNMENTS register contains the effective address of the data to be used
Indexed by the Instruction. This is the fastest indexing mode
Post-Byte Register B~
Addressing
Examples are
7 6 5 4 3 2 1 0 Mode
a R R x x x x x EA - ,R + 5 Bit Offset
LOO a,x
LOA 5
1 R R a a a a a ,R +
1 R R I a a a 1 ,R+ +
1 R R a a a 1 a ,- R
Constant Offset Indexed - In this mode, a
1 R R I a a 1 1 ,- - R
two's-complement offset and the contents of one of the
1 R R I a 1 a a EA ~ ,R + a Offset pOinter registers are added to form the effective address of
1 R R I a 1 a 1 EA ~ ,R + ACCB Offset the operand The pointer register's Initial content IS un-
1 R R I a 1 1 a EA - ,R + ACCA Offset changed by the addition
1 R R I 1 a a a EA = ,R + B Bit Offset Three sizes of offsets are available
1 R R I 1 a a 1 EA - ,R + 16 Bit Offset 5 -bit {-16 to + 151
1 R R I 1 a 1 1 EA - ,R + 0 Offset 8 -bit 128 to + 1271
1 x x I 1 1 a a EA - .PC + 8 Bit Offset 16-blt {- 32768 to + 327671
1 x x I I 1 a 1 EA - ,PC + 16 Bit Offset
The two's complement 5-bit offset IS Included In the
1 R R 1 1 1 1 1 EA - [ Address] post byte and, therefore, IS most efftcient in use of bytes and
'-v- ~ cycles. The two's complement 8-blt offset IS contained In a
L

C
Add.reSSlng. Mode Field single byte follOWing the postbyte. The two's complement
16-blt offset IS In the two bytes following the postbyte. In
- Indirect Field
most cases the programmer need not be concerned with the
(Sign bit when b7 = 01
size of this offset since the assembler will select the optimal
size automatically
Register Field RR Examples of constant-offset IndeXing are
oo~ X LOA 23,X
01 ~ y
LOX - 2,5
10= U
11 = S LOY 300,X
LOU CAT,Y
x = Don't Care

TABLE 2 - INDEXED ADDRESSING MODE

Non Indirect Indirect
Type

Constant Offset From R No Offset

Forms Assembler
Form
R
Postbyte
OP Code
1RR00100
-a a
+ +
#
Assembler
Form
[,RI
Postbyte
OP Code
1RR101OO
-a
+

3
+
#

12's Complement Offsets 1 5 Bit Offset n, R ORRnnnnn 1 a defaults to 8-blt

8 Bit Offset n, R IRR01000 1 1 [n, RI 1RR11000 4 1
16 Bit Offset n, R 1RR01oo1 4 2 In, RI 1RR11oo1 7 2
Accumulator Offset From R A Register Offset A, R 1RR00110 1 a [A, Ri 1RR10110 4 a
(2's Complement Offsets) 8 Register Offset B, R 1RRoo101 1 0 [8, Rl 1RRlO101 4 a
o Register Offset 0, R 1RR01011 4 a [0, RI lRR11011 7 a
Auto Increment/Decrement R Increment By 1 ,R + 1RROOOOO 2 a not allowed
-
Increment By 2 ,R + + 1RROOOO1 3 a LR + + I 1RR10001 6 a
Decrement By 1 ,- R 1RROOOlO 2 a not allowed
Decrement By 2 - R lRROOO11 3 a [, - - RI lRR10011 6 a
Constant Offset From PC 8 Bit Offset 11, PCR 1xx011oo 1 1 In, PCRI 1xx111oo 4 1
12's Complement Offsetsl 16 Bit Offset n, PCR 1xx01101 5 2 In, peR] 1xx11101 8 2
Extended Indirect 16 Bit Address - - - - In] 1 10011111
-----~
5 2
R~X,Y,UorS RR
x ~ Don't Care 00 ~ X
01 = Y
lO=U
11 ~ S

~ and; indicate the number of additional cycles and bytes tor the particular variatlor.

226
 MC6809/MC68A09/MC68B09

Accumulator-Offset Indexed - This mode is similar to All modes of indexed Indirect are included except those
constant offset indexed except that the two's-complement which are meaningless (e.g., auto increment/decrement by
value in one of the accumulators lA, B or Dl and the con- 1 indirect). Some examples of indexed indirect are
tents of one of the pointer registers are added to form the ef- LDA [,Xl
fective address of the operand. The contents of both the ac-
LDD [lO,SJ
cumulator and the pointer register are unchanged by the ad-
dition. The postbyte specifies which accumulator to use as LDA [B,Y]
an offset and no additional bytes are required. The advan- LDD [,X+ +]
tage of an accumulator offset is that the value of the offset
can be calculated by a program at run-time.
Some examples are:
RELATIVE ADDRESSING
LDA B,Y The bytelsl following the branch opcode is (are) treated as
LDX D,Y a signed offset which may be added to the program counter
LEAX B,X If the branch condition is true then the calculated address
Auto Increment/Decrement Indexed - In the auto incre- IPC + signed offset I is loaded into the program counter
ment addressing mode, the pointer register contains the ad- Program execution continues at the new location as in-
dress of the operand. Then, after the pointer register is used dicated by the PC; short 11 byte offset I and long 12 bytes off-
it is incremented by one or two. This addressing mode is setl relative addressing modes are available. All of memory
useful in stepping through tables, moving data, or for the can be reached in long relative addressing as an effective ad-
creation of software stacks. In auto decrement, the pointer dress is interpreted modulo 216 Some examples of relative
register is decremented prior to use as the address of the addressing are
data. The use of auto decrement is similar to that of auto in-
crement; but the tables, etc., are scanned from the high to
low addresses. The size of the increment/ decrement can be BEQ CAT (shortl
either one or two to allow for tables of either B or 1f3..bit data BGT DOG Ishortl
to be accessed and is selectable by the programmer. The CAT LBEQ RAT Iiong)
pre-decrement, post-increment nature of these modes allow DOG LBGT RABBIT lIongl
them to be used to create additional software stacks that
behave identically to the U and S stacks.
Some examples of the auto increment/decrement ad-
dressing modes are:
LDA ,X+ RAT NOP
RABBIT NOP
STD ,Y+ +
LDB ,- Y
LDX ,- - S

INDEXED INDIRECT PROGRAM COUNTER RELATIVE

All of the indexing modes with the exception of auto in- The PC can be used as the pointer register with B or 1f3..bit
crement/ decrement by one, or a ± 4-bit offset may have an signed offsets. As in relative addressing, the offset is added
additional level of indirection specified. In indirect adddress- to the current PC to create the effective address. The effec-
ing, the effective address is contained at the location tive address is then used as the address of the operand or
specified by the contents of the Index register plus any off- data. Program Counter Relative Addressing is used for
set. In the example below, the A accumulator is loaded in- writing position independent programs. Tables related to a
directly using an effective address calculated from the Index particular routine will maintain the same relationship after
register and an offset. the routine is moved, if referenced relative to the Program
Before Execution Counter. Examples are:
A = XX Idon't carel
X=$FOOO
LDA CAT, PCR
$0100 LDA [$10,Xl EA is now $F010
LEAX TABLE, PCR
$F010 $F1 $F150 is now the
$F011 $50 new EA Since program counter relative is a type of indexing, an
$F150 $AA additional level of indirection is available
After Execution
A = $AA Actual Data Loaded LOA [CAT, PCR]
X=$FOOQ LDU [DOG, PCR]

227
 MC6809/MC68A09/MC68B09

MC6809 INSTRUCTION SET

The instruction set of the MC6809 is similar to that of the LEAX/ LEA Y/ LEAU / LEAS
MC6800 and is upward compatible at the source code level The LEA (Load Effective Address) works by calculating
The number of opcodes has been reduced from 72 to 59, but the effective address used in an indexed instruction and
because of the expanded architecture and additional ad- stores that address value, rather than the data at that ad-
dressing modes, the number of available opcodes Iwith dif- dress, in a pointer register. This makes all the features of the
ferent addressing modesI has risen from 197 to 1464. internal addressing hardware available to the programme!.
Some of the new instructions and addressing modes are Some of the implications of this instruction are illustrated in
described in detail below: Table 3.
The LEA instruction also allows the user to access data in
PSHU/PSHS a position independent manner. For example:
The push instructions have the capability of pushing onto LEAX MSG1, PCR
either the hardware stack lSI or user stack lUI any single LBSR PDATA !Print message routine)
register, or set of registers with a single instruction
PULU/PULS MSGl FCC 'MESSAGE'
The pull instructions have the same capability of the push This sample program prints: 'MESSAGE'. By writing
instruction, in reverse order. The byte immediately following MSG1, PCR, the assembler computes the distance between
the push or pull opcode determines which register or the present address and MSG1. This result is placed as a
registers are to be pushed or pulled. The actual PUSH/PULL constant into the LEAX instruction which will be indexed
sequence is fixed; each bit defines a unique register to push from the PC value at the time of execution. No matter where
or pull, as shown in below the code is located, when it is executed, the computed offset
from the PC will put the absolute address of MSG 1 into the X
- Pull Order Push Order- pointer register. This code is totally position independent.
PC U Y X DP B A CC
FFFF .... - increasing memory address .... OOOO
MUL
PC S Y X DP B A CC
Multiplies the unsigned binary numbers in the A and B ac-
TFR/EXG cumulator and places the unSigned result into the 16-bit D
Within the MC6809, any register may be transferred to or accumulator. This unsigned multiply also allows multiple-
exchanged with another of like-size; i.e., B-bit to S-bit or precision multiplications
16-M to 16-bit. Bits 4-7 of postbyte define the source
register, while bits 0-3 represent the destination register. Long And Short Relative Branches
These are denoted as follows· The MC6809 has the capability of program counter relative
0000 - D 0101 - PC branching throughout the entire memory map. In this mode,
0001 - X 1000 - A If the branch is to be taken, the S or 16-bit signed offset is ad:
0010 - Y 1001 - B ded to the value of the program counter to be used as the ef-
fective address. This allows the program to branch anywhere
0011 - U 1010 - CC in the 64K memory map. Position independent code can be
0100 - S 1011 - DP easily generated through the use of relative branching. Both
NOTE: All other combinations are undefined and INVALID short IB-bit) and long 116-bit) branches are available.

TABLE 3 - LEA EXAMPLES

Instruction Operation Comment

LEAX 10, X X+ 10 - X Adds 5-bit constant 10 to X
LEAX 500, X X+ 500 - X Adds 16-bit constant 500 to X
LEAY A, Y Y+ A - Y Adds S-bit accumulator to Y
LEAY D, Y Y+ D - Y Adds 16-bit D accumulator to Y
LEAU - 10, U U- 10 - U Subtracts 10 from U
LEAS - 10, S S- 10 - S Used to reserve area on stack
LEAS 10, S S+ 10 - S Used to 'clean up' stack
LEAX 5, S S+ 5 - X Transfers as well as adds

228
 MC6809/MC68A09/MC68B09

SYNC next byte, so this technique considerably speeds

After encountering a Sync instruction, the MPU enters a throughput.! Next, the operation of each opcode will follow
Sync state, stops processing instructions and waits for an in- the flow chart. VMA IS an indication of FFFF16 on the ad-
terrupt. If the pending interrupt IS non-maskable INMI) or dress bus, R/Vii = 1 and 8S = O. The following examples il-
maskable lFIRO, IRO) with its mask bit IF or Il clear, the pro- lustrate the use of the chart; see Figure 19.
cessor will clear the Sync state and perform the normal inter-
rupt stacking and service routine. Since FIRO and IRO are LBSR IBranch takenl
not edge-triggered, a low level with a minimum duration of
three bus cycles IS required to assure that the interrupt will Cycle # 1 opcode Fetch
be taken. If the pending interrupt is maskable IFIRO, IRO! 2 opcode +
with its mask bit (F or Il set, the processor will clear the Sync 3 opcode +
state and continue processing by executing the next inline 4 VMA
instruction. Figure 18 depicts Sync timing 5 VMA
6 ADDR
7 VMA
Software Interrupts 8 STACK (write!
A Software Interrupt is an Instruction which will cause an 9 STACK (writel
interrupt, and its associated vector fetch. These Software In-
terrupts are useful In operating system calls, software DEC IExtended!
debugging, trace operations, memory mapping, and soft-
ware development systems. Three levels of SWI are available Cycle # 1 opcode Fetch
on this MC6809, and are prioritized in the following order: 2 opcode +
SWI, SWI2, SWI3 3 opcode +
4 VMA
5 ADDR (readl
16-Bit Operation 6 VMA
7 ADDR Iwritel
The MC6809 has the capability of processing 16-bit data.
rhese instructions include loads, stores, compares, adds,
subtracts, transfers, exchanges, pushes and pulls MC6809 INSTRUCTION SET TABLES

The instructions of the M C6809 have been broken down

CYCLE-BY-CYCLE OPERATION into five different categories They are as follows
The address bus cycle-by-cycle performance chart il- 8-Bit operation (Table 41
lustrates the memory-access sequence corresponding to 16-Bit operation (Table 51
each possible instruction and addressing mode in the Index register/stack pOinter Instructions (Table 61
MC6809. Each instruction begins with an opcode fetch. Relative branches (long or shortl ITable 71
While that opcode is being internally decoded, the next pro- Miscellaneous instructions (Table 81
gram byte is always fetched. IMost Instructions will use the Hexadecimal Values of instructions ITable 91

229
tIo

FIGURE 18 - SYNC TIMING

Sync

SYNC Acknowledge

~
o
(7)
(ll)
o
~~ ( !e
Fetch ~
o
(7)

''"
- )
" I , c=x::=x:=:c=
(ll)

o»
R/W ( ) !e
BA ==:x==J.. I (. ~
o
BS~
(7)
d (ll)
m
iRO{
FiRQ
See Note 2 o
CD
NMI tpcs

NOTE: 1. If the associated mask bit is set when the interrupt is requested, this cycle will continue the instruction fetched from the previous cycle. However, if
the interrupt ,s accepted INMI or an unmasked FiRO or iRQI the opcode address (placed on the bus from cycle m + 11 remains on the bus and inter-
rupt processing continues with this cycle as (m + 21 on Figures 10 and 11 (Interrupt Timing!.
2. If mask bits are clear, IRO and FIRO must be held low for three cycles to guarantee interrupt to be taken, although only one cycle is necessary to
bring the processor out of SYNC
 FIGURE 19 - ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE

~
Opeode (Fetch)

long Short Immediate DireCI Exte~ded Indexed I

~_------4~ O_P_c0.Ld_e~' ------4~ ~_"""
Branch Branch &
Inherent I I __ __ __ _ _- '
s:::
I
Opcode +
I
VMA PC + 16-81t Extended ' No Offset n
VMA
Opcode +
~
ACCA Offsel
ACCS Offset
Auto
Inc/IDee
Auto
Inc/IDec I I
R + 16-B!I R + 0
I Ind"ect
0)
CD
o
~ : ~ ~:~ By 1 Sy 2
I I !e
PC + 8 BII I ~ Opc~de + Opc~de + Ope~de + OpCOjde + s:::
V~A Opcolde + Opc~de + Opco/de + Opcode + n
0)
V~A V~A V~A V~A V~A CD
VMA VMA VMA VMA VMA VMA »
o
!e
s:::
n
0)
CD
IJJ
ADDR
o
CD
VMA
I
Steck (Write'
Steck (Write'

...t: NOTES: 1. All subsequent PAGE 2 and PAGE 3 opcodes will be Ignored after inttlal opcode fetch
2. Write operation during store instruction
 MC6809/MC68A09/MC68B09

FIGURE 19 - ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE (CONTINUED)

Inherent Page

AS LA ASX RTS TFR EXG MUL PSHU PULU SWI CWAI RTI
AS LS PSHS PULS SWI2
AS RA SWI3
AS RS
CL RA
CL RS
CO MA VMA ADDR STACK
CO MS VMA I
DA A VMA VMA VMA VMA
DE CA VMA VMA VMii
DE CS
IN CA
I I I
VMA VMA STACK 12"STACK 12"STACK 1
IN CS I VMA VMA
I (W~lle) (Wnte)
LS LA VMA VMii E

~
{STACK}12 I
LS LB VMA VMA
LS RA STACK
I VMA VMA
(Write) 0
VMA {VJA} )
LS RB STACK VMA VMA
NE GA VMA VMA
NE GS
NO P
VMA
VMA VMA VECTOR
I
VECTOR
I
RO LA VMA VECTOR VECTOR
2"STACK

P'
RO LS VMA VMA
RO RA
RO RS I CK

S EX {STACK} 12
(Write) 0

I
STACK STACK

j j j
•

232
 MC6809/MC68A09/MC68B09

FIGURE 19 - ADDRESS BUS CYCLE-BY-CYCLE PERFORMANCE (CONTINUED)

Non-Inherents

END

ADCA LOD ASL TST ADDD JSR STD

ADCB LDS ASR CMPD STS
ADDA LDU CLR CMPS STU
ADDB LOX COM CMPU STX
ANDA LDY DEC CMPX STY
ANDB INC CMPY
BITA ANDCC LSL SUBD
BITB ORCC LSR
CMPA NEG
CMPB ROL
EORA ROR
EORB
LDA
LDB
ORA
ORB
SBCA
SBCB
STA
STB
SUBA
SUBB
TSTA
TSTB
VMA
STACK
(Write)

'l
ADDR + STACK ADDR+
ADDR+ VMA

'I"'

233
 MC6809/MC68A09/MC68B09

TABLE 4 - 8-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

Mnemonicls) Operation
ADCA, ADCB Add memory to accumulator with carry
ADDA, ADDB Add memory to accumulator
ANDA, ANDB And memory with accumulator
ASL, ASLA, ASLB Arithmetic shift of accumulator or memory left
ASR, ASRA, ASRB Arithmetic shift of accumulator or memory right
BITA, BITB Bit test memory with accumulator
CLR, CLRA, CLRB Clear accumulator or memory location
CMPA, CMPB Compare memory from accumulator
COM, COMA, COMB Complement accumulator or memory location
DAA Decimal adjust A accumulator
DEC, DECA, DECB Decrement accumulator or memory location
EORA, EORB Exclusive or memory with accumulator
EXG Rl, R2 Exchange Rl with R2IRl, R2 = A, B, CC, DPI
INC, INCA, INCB Increment accumulator or memory location
LDA, LDB Load accumulator from memory
LSL, LSLA, LSLB Logical shift left accumulator or memory location
LSR, LSRA, LSRB Logical shift right accumulator or memory location
MUL Unsigned multiply (A x B - D)
NEG, NEGA, NEGB Negate accumulator or memory
ORA, ORB Or memory with accumulator
ROL, ROLA, ROLB Rotate accumulator or memory left
ROR, RORA, RORB Rotate accumulator or memory right
SBCA, SBCB Subtract memory from accumulator with borrow
STA, STB Store accumulator to memory
SUBA, SUBB Subtract memory from accumulator
TST, TSTA, TSTB Test accumulator or memory location
TFR Rl, R2 Transfer Rl to R2 IR1, R2 = A, B, CC, DPI

NOTE: A, B, CC or DP may be pushed to (pulled from) either stack with PSHS, PSHU
(PULS, PULUJ instructions.

TABLE 5 - 16-BIT ACCUMULATOR AND MEMORY INSTRUCTIONS

Mnemonic(s) Operation
ADDD Add memory to D accumulator
CMPD Compare memory from 0 accumulator
EXG D, R Exchange D with X, Y, S, U or PC
LDD Load D accumulator from memory
SEX Sign Extend B accumulator into A accumulator
STD Store D accumulator to memory
SUBD Subtract memory from 0 accumulator
TFR D, R Transfer D to X, Y, S, U or PC
TFR R, 0 Transfer X, Y, S, U or PC to D

NOTE: D may be pushed (pulled) to either Slack with PSHS, PSHU (PULS, PULU)
instructions.

234
 MC6809/MC68A09/MC68B09

TABLE 6 - INDEX REGISTER/STACK POINTER INSTRUCTIONS

Mnemonic(s) Operation
CMPS, CMPU Compare memory from stack pointer
CMPX, CMPY Compare memory from index register
EXG Rl, R2 Exchange D, X, Y, 5, U or PC with D, X, Y, 5, U or PC
LEAS LEAU Load effective address into stack oointer
LEAX, LEAY Load effective address Into index reQister
LDS, LOU Load stack pointer from memory
LDX, LDY Load index register from memory
PSHS Push A, B, CC, DP, D, X, Y, U, or PC onto hardware stack
PSHU Push A, B, CC, DP, D, X, Y, 5, or PC onto user stack
PULS Pull A, B, CC, DP, D, X, Y, U or PC from hardware stack
PULU Pull A, B, CC, DP, D, X, Y, 5 or PC from hardware stack
STS, STU Store stack pointer to memory
STX, STY Store index register to memory
TFR Rl, R2 Transfer D, X, Y, 5, U or PC to D, X, Y, 5, U or PC
ABX Add B accumulator to X (unsigned)

TABLE 7 - BRANCH INSTRUCTIONS

Mnemonicls) Operation
SIMPLE BRANCHES
BEQ, LBEQ Branch if equal
BNE, LBNE Branch If not equal
BMI, LBMI Branch if minus
BPL, LBPL Branch if plus
BCS, LBCS Branch if carry set
BCC, LBCC Branch if carry clear
BVS, LBVS Branch If overflow set
BVC, LBVC Branch if overflow clear
SIGNED BRANCHES
BGT, LBGT Branch if greater (signed)
BGE, LBGE Branch if areater than or equal (sianed)
BEQ, LBEQ Branch if equal
BLE, LBLE Branch if less than or equal (signed)
BLT, LBLT Branch if less than (signed)
UNSIGNED BRANCHES
BHI, LBHI Branch if higher (unsigned)
BHS, LBHS Branch if higher or same (unsigned)
BEQ, LBEQ Branch If equal
BLS, LBLS Branch if lower or same (unsigned)
BLO, LBLO Branch if lower (unsignedl
OTHER BRANCHES
BSR, LBSR I Branch to subroutine
BRA, LBRA I Branch always
BRN, LBRN I Branch never

TABLE 8 - MISCELLANEOUS INSTRUCTIONS

Mnemonic(s) Operation
ANDCC AN D condition code register
CWAI AND condition code reQister, then wait for interrupt
NOP No operation
ORCC OR condition code register
JMP Jump
JSR Jump to subroutine
Rli Return from interrupt
RTS Return from subroutine
SWI, SWI2, SWI3 Software interrupt (absolute indirect)
SYNC Synchronize with interrupt line

235
 MC6809/MC68A09/MC68B09

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES

OP Mnem Mode - OP Mnem Mode - OP Mnem Mode -

:
00 NEG Direct 6 30 LEAX Indexed 4+ 2+ 60 NEG Indexed 6+ 2+
01 31 LEAY 4+ 2+ 61
02 32 LEAS 4+ 2+ 62
03 COM 33 LEAU Indexed 4+ 2+ 63 COM 6+ 2+
04 lSR 34 PSHS Inherent 5+ 2 64 lSR 6+ 2+
05 35 PUlS 5+ 2 65
06 ROR 36 PSHU 5+ 2 66 ROR 6+ 2+
07 ASR 37 PUlU 5+ 2 67 ASR 6+ 2+
08 ASL. lSl 36 66 ASl, lSl 6+ 2+
09 ROl 39 RTS 5 69 ROl 6+ 2+
OA DEC 3A ABX 3 6A DEC 6+ 2+
OB 3B RTI 6,15 6B
OC INC 3C CWAI 20 6C INC 6+ 2+
OD TST 3D MUl 11 6D TST 6+ 2+
OE JMP 3E 6E JMP 3+ 2+
OF ClR Direct 3F SWI Inherent 19 6F ClR Indexed 6+ 2+

10 Page 2 40 NEGA Inherent 2 70 NEG Extended 7

11 Page 3 41 71
12 NOP Inherent 42 72
13 SYNC lnherent 43 COMA 73 COM
14 44 lSRA 74 lSR
15 45 75
16 lBRA RelatIve 46 RORA 76 ROR
17 lBSR Relative 47 ASRA 77 ASR
1B 4B ASlA, lSLA 78 ASl, lSl
19 DAA Inherent 49 ROlA 79 ROl
lA ORCC Immed 4A DECA 7A DEC
1B 4B 7B
1C ANDCC Immed 4C INCA 7C INC 7
10 SEX Inhe.ent 4D TSTA 7D TST 7
1E EXG 4E 7E JMP 4
1F TFR Inherent 4F ClRA Inherent 2 7F ClR Extended 7

20 BRA Relative 50 NEGB Inherent 2 80 SUBA Indexed

21 BRN 51 B1 CMPA
22 BHI 52 82 SBCA
23 BlS 53 COMB 83 SUBD
24 BHS, BCC 54 lSRB 84 ANDA
25 BlO, BCS 55 85 BITA
26 BNE 56 RORB 86 lDA
27 BEQ 57 ASRA 87
28 BVC 58 ASlB, lSLB 86 EORA
29 BVS 59 ROlB 89 ADCA
2A BPl 5A DECB 8A ORA
2B BMI 5B BB ADDA
2C BGE 5C INCB Be CMPX Immed
2D BlT 5D TSTB BD BSR Relative
2E BGT 5E BE lDX Immed
2F BlE Relative 5F ClRB Inherent 2 BF

lEGEND
- Number of MPU cycles Iless possible push pull or Indexed-mode cycles)
I Number of program bytes
• Denotes unused opcode

236
 MC6809/MC68A09/MC68B09

TABLE 9 - HEXADECIMAL VALUES OF MACHINE CODES ICONTINUED)

OP Mnem Mode - OP Mnem Mode - OP Mnem Mode -

90 SUBA Direct C6 LDB 2 FC LDD ed
91 CMPA C7 FD STD Extr :
92 SBCA CB EORB FE LDU

T
93 SUBD C9 ADCB FF STU Extended 6
94 ANDA CA ORB
95 BITA CB ADDS Page 2 and 3 Machine
96 LDA CC LDD Codes
97 STA CD
9B EORA CE LDU Immed 1021 LBRN Relative 5 4
99 ADCA CF 1022 LBHI 5161 4
9A ORA 1023 LBLS 5161 4
9B ADDA DO SUBB Di ect 1024 LBHS, LBCC 5161 4
9C CMPX Dl CMPB 1025 LBCS, LBLO 5161 4
9D JSR D2 SBCB 1026 LBNE 5161 4
9E LDX D3 ADDD 1027 LBEQ 5161 4
9F STX Direct D4 ANDB 1028 LBVC 5161 4
D5 BITB 1029 LBVS 5161 4
AO SUBA Indexed 4+ 2+ D6 LDB 102A LBPL 5161 4
Al CMPA 4+ 2+ D7 STB 102B LBMI 5161 4
A2 SBCA 4+ 2+ D8 EORB 102C LBGE 5161 4
A3 SUBD 6+ 2+ D9 ADCB 102D LBLT 5161 4
A4 ANDA 4+ 2+ DA ORB 102E LBGT 5161 4
A5 BITA 4+ 2+ DB ADDB 102F LBLE Relative 5161 4
A6 LDA 4+ 2+ DC LDD 103F SWI2 Inherent 20 2
A7 STA 4+ 2+ DD STD 1083 CMPD ed 5 4
Imr
A8 EORA 4+ 2+ DE LDU lOBC CMPY 5 4
A9 ADCA 4+ 2+ DF STU Direct lOBE LDY Immed 4 4
AA ORA 4+ 2+ 1093 CMPD 7 3
ADDA 4+ 2+ EO SUBB Indexed 4+ l09C CMPY Dft 7 3
AB 2+
AC CMPX 6+ 2+ El CMPB 4+ 2+ l09E LDY 6 3
AD JSR 7+ 2+ E2 SBCB 4+ 2+ l09F STY Direct 6 3
AE LDX 5+ 2+ E3 ADDD 6+ 2+ lOA3 CMPD ed 7+ 3+
Indexed 5+ 2+ E4 ANDB lOAC CMPY In1' 7+ 3+
AF STX 4+ 2+
E5 BITB 4+ 2+ 10AE LDY 6+ 3+
BO SUBA Extended 5 E6 LDB 4+ 2+ lOAF STY Indexed 6+ 3+

~
B1 CMPA 5 E7 STB 4+ 2+ 10B3 CMPD 4
10BC CMPY Extred 4
B2 SBCA 5 E8 EORB 4+ 2+
B3 SUBD 7 E9 ADCB 4+ 2+ lOBE LDY 4
B4 ANDA 5 EA ORB 4+ 2+ lOBF STY Extended 7 4
B5 BITA 5 EB ADDB 4+ 2+ 10CE LDS Immed 4 4
B6 LDA 5 EC LDD 5+ 2+ lODE LDS Direct 6 3
B7 STA 5 ED STD 5+ 2+ 10DF STS Direct 6 3
BB EORA 5 EE LDU 5+ 2+ lOEE LDS Indexed 6+ 3+
B9 ADCA 5 EF STU Indexed 5+ 2+ 10EF STS Indexed 6+ 3+
BA ORA 5 lOFE LDS Extended 7 4.
BB ADDA 5 FO SUBB Extended 5 lOFF STS Extended 7 4
BC CMPX 7 Fl CMPB 5 113F SWI3 Inherent 20 2
BD JSR B F2 SBCB 5 1183 CMPU Immed 5 4
BE LDX 6 F3 ADDD 7 118C CMPS Immed 5 4
BF STX Extended 6 F4 ANDB 5 1193 CMPU Direct 7 3
F5 BITB 5 119C CMPS Direct 7 3
CO SUBB 2 F6 LDB 5 l1A3 CMPU Indexed 7+ 3+

T
C1 CMPB 2 F7 STB 5 llAC CMPS Indexed 7+ 3+
C2 SBCB 2 F8 EORB 5 11B3 CMPU Extended B 4
C3 ADDD 4 F9 ADCB 5 l1BC CMPS Extended 8 4
C4 ANDB 2 FA ORB 5
C5 BITB Immed 2 FB ADDB Extended 5

NOTE: All unused opcodes are both undefined and illegal

237
 MC6809/MC68A09/MC68B09

~::::::::::::::::::J
MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 51.69 52.45 2.035 2.065
B 13.12 14.22 0.540 0.560
C 3.94 5.08 0155 0.200
0 036 0.56 0.014 0022
F 102 1.52 0.040 0060
G 254 BSC 0.100 BSC
H 1.65 2.16 0.065 0.085
J 0.20 038 0.008 0.015
K 292 3.43 0115 0135
L 15.24 BSC 0.600 BSC
M 0° 15° 0° 15°
N 0.51 102 0.020 0.040

NOTES
1. POSITIONAL TOLERANCE OF LEADS 101,
SHALL BE WITHIN 0.25 mm (0.010) AT
MAXIMUM MATERIAL CONDITION, IN P SUFFIX
RELATION TO SEATING PLANE AND PLASTIC PACKAGE
EACH OTHER. CASE 711
2. DIMENSION L TO CENTER OF LEADS
WHEN FORMED PARALLEL
3. DIMENSION B ODES NOT INCLUDE
MOLD FLASH

MILLIMETERS INCHES
DIM MIN MAX MIN MAX
A 50.29 51.31 1.9BO 2.020
B 14.94 15.34 0.588 0.604
C 3.05 4.06 0.120 0.160
0 0.38 0.53 0.015 0.021
F 0.76 1.40 0.030 0.055
G 2.54 BSC 0.100 BSC
H 0.76 1.78 0.030 0.070
J 0.20 0.33 O.OOB 0.013
K 2.54 4.19 0.100 0.165
L 14.99 15.49 0.590 0.610
M - 100 - 100
N 1.02 1.52 0.040 0.060

NOTES:
1. LEADS, TRUE POSITIONED WITHIN 0.25 mm
(0.010) OIA (AT SEATING PLANE), AT MAX
MAT'L CONDITION.
2. DIMENSION "L" TO CENTER OF LEADS
WHEN FO RMED PARALLEL.
L SUFFIX
CERAMIC PACKAGE
CASE 715

238
 MC6809E/MC68A09E/MC68B09E

HMOS
(HIGH DENSITY N-CHANNEL, SILICON-GATE)

a-BIT
MICROPROCESSING
UNIT

a-BIT MICROPROCESSING UNIT

The MC6809E IS a revolutionary high performance S-bit microprocessor
which supports modern programming techniques such as position In-
dependence, reentrancy, and modular programming
This thrrd-generation addition to the M6800 family has major architectural
improvements which include additional registers, Instructions and addressing
modes
The basIc Instructions of any computer are greatly enhanced by the
presence of powerful addressing modes. The MC6809E has the most com-
plete set of addresSing modes available on any S-blt today
The MC6809E has hardware and software features make it an ideal
processor for higher level language execution or standard conti oller applica-
tions
MC6800 COMPATIBLE
• Hardware - Interfaces with All M6800 Perrpherals
• Software - Upward Source Code Compatible Instruction Set and
Addressing Modes
ARCHITECTURAL FEATURES
• Two l6-bit Index Registers
• Two 16-bit Indexable Stack POinters
• Two S-bit Accumulators can be Concatenated to Form One 16-Blt
Accumulator
• Drrect Page Register Allows Direct AddreSSing Throughout Memory
HARDWARE FEATURES PIN ASSIGNMENT
• External Clocking (~ 1)
• Fast Interrupt Request Input Stacks Only Condition Code Register HALT
and Program Counter
TSC
• Interrupt Acknowledge Output Allows Vectorrng By DeVices
• SYNC Acknowledge Output Allows for Synchronization to External
Event RESET
• Single Bus-Cycle RESET
• Single 5-Volt Supply Operation AVMA
• NMI Blocked After RESET Until After First Load of Stack Pointer
• Early Address Valid Allows Use With Slower Memories
• Early Write-Data for Dynamic Memorres
• BUSY Signal Supports Tightly Coupled Multiprocessor Systems
SOFTWARE FEATURES
• 10 AddreSSing Modes
• M6800 Upward Compatible Addressing Modes
• Drrect AddreSSing Anywhere In Memory Map
• Long Relative Branches
• Program Counter Relative 02
• True Indirect AddreSSing 03
• Expanded Indexed Addressing
04
0, 5, or l6-blt Constant Offsets
8, or Accumulator Offsets 05
Auto-Increment/Decrement by 1
06
• Improved Stack Manipulation
• 59 Instruction Mnemonics Of
• S x S UnSigned Multiply AI5
• 16-blt Arrthmetic
• Transfer/Exchange All Registers
• Push/ Pull Any Registers or Any Set of Registers
• Load Effective Address

239
 MC6809EJMC68A09EJMC68B09E

TYPICAL MULTIPROCESSOR SYSTEM

2
~
{ t Lr-
MC6809E Dedicated Dedicated MC6809E
Processor Memory Memory Processor
No.1 and and No.2
Penpherals Penpherals

a Data a Data
116 ADDR
II ,16 ADDR
5 Status 5 Status Control = RESET
4 Control 4 Contr HALT
AVMA
31nt 3 Int BREQ
I II II I Status= R/W
BA
Clock Bus Arbitration BS
Generator Logic BUSY
L1C
Int= NMI
FIRQ
IRQ
~
0
lX)
"
<J)

'"
J.,. E
'"

Global
~ Memory and
Peripherals

MODERN SOFlWARE TECHNIQUES

Available to the MC6809/MC6809E User

• Position Independent Programs - Program Executes Properly Anywhere in the Address Space

• Module Programs - Programs Easily Divided Into Small Manageable Modules

• Re-Entrant Programs - A Routine Usable By Interrupt and Non-Interrupt Programs Without Losing Data

• Structured High Level Languages - More Efficient Compilers and Compiler Generated Code

• Recursive Routines
 MC6829

HMOS
(HIGH DENSITY N-CHANNEl, SILICON-GATE)

MEMORY
MANAGEMENT
UNIT (MMUI

MEMORY MANAGEMENT UNIT

The principle function of the MC6829 Memory Management Unit

(MMU) is to expand the address space of the MC6809 from 64K bytes to
a possible maximum of 2 Megabytes. Each MMU is capable of handling
four different concurrent tasks including DMA. The MMU can also pro-
tect the address space of one task from modification by another task.
Memory address space expansion is accomplishdd by applying the up-
per five address lines of the processor IAll-A15) along with the con-
tents of a five-bit task register to an internal high-speed mapping RAM.
The MMU output consists of ten physical address lines (PA2o-PAlll
which, when combined with the eleven lower address lines of the pro-
cessor (A lo-AOl, forms a physical address space of 2 Mbytes. Each task
is assigned memory in increments of 2 k bytes up to a total of 64 k
bytes. In this manner, the address spaces of different tasks can be kept
separate from one another. The resulting simplification of the address
space programming model will increase the reliability of a complex
multi-process system. PROPOSED PIN ASSIGNMENT

• Expands Memory Address Space from 64K to 2 Megabytes Vss PAll

A15 2
• Each MMU is Capable of Handling 4 Separate Tasks
A14 3

• Up to B MMUs can be Used in a System

PA15

• Task Isolation and Write Protection

RA 7
• Provides Efficient Memory Allocation; 1024 Pages of 2 k Bytes Each

• Designed to be Used with DMA RS4 10

RS3 11
• Fast, Automatic on Chip Task SWitching
RS2 12

• Allows Interprocess Communication Through Shared Resources RSl 13

RSO 14

• Simplifies Programming Model of Address Space KVA 15

• Increases System Reliability

E 17

BA 18
• 6809/6800 Bus Compatible
BS 19

RESEr 20
• Single 5-Volt Power Supply

241
 MC6829

LOGICAL TO PHYSICAL ADDRESS MAPPING EXAMPLES

Task Logical Address Physical Address

Fixed Map'
FFFF Page 0 1FFFFF

Task 0
10SI
,
r-
-It---~'__
~/~,
pa_ge_l- - - - - - 1

IXXXJ

"-----------~-'/ ~'----------------I
,-_ _ Shared Task
FFFF

Task 1

1XXXJ1--------------1e--------
IDMAI
~---------'
L----===::::::::~{=========~

TaskF~FFI
IUser! 1 - ,- - - - - - - - - - ,
r=-=--== ~I--------------i

IXXXJ ' - - _ _ _ _ _ _ _ _ _ ---~~==================~

• Each Page Equals 2 k Bytes
Physical Addresses $1FFBOO-$lFFFFF Always Contain the MMU Registers

TYPICAL SYSTEM CONFIGURATION

Logical Address Lines

AD-Al0
, ;1/
/
11 lihYSICal Address Lines

Al1-A15 '\

MC6809
~ Chip
Select 1 f-- F1i'i
MMU
I Main
Memorv
BA, BS "1'10
t
t
~
MMU
00-07
" '1
F1i'i I--

'\ "- BA, BS

1'8 "2
BUsSlatef
Lines Data Bus
Data

242
 MC6839

HMOS
(HIGH DENSITY N-CHANNEL, SILICON-GATE)

M6809 FLOATING
POINT ROM

• Totally Position Independent

• No Absolute RAM Used IRe-Entrant)

• Operands in Registers or on the Stack (PASCAU

• Compatible with Proposed IEEE Standard

• Single, Double, and Double Extended Formats

• Includes the FolloWing Operations

Add
Subtract
Multiply
Divide
Remainder
Square Root
Integer Part
Absolute Value
Negate
Compare
Convert Integer - Floating Point
Convert Binary- Decimal

243
 MC6842

HMOS
SERIAL DIRECT
MEMORY ACCESS
PROCESSOR

SERIAL DIRECT MEMORY ACCESS PROCESSOR

The MC6842 Serial Direct Memory Access (SDMA) processor pro-

vides a high speed serial link between microprocessors or intelligent
controliers in distributed processing systems. Using IB M's Syn-
chronous Data Link Control (SDLC) protocol, the MC6842 is capable of
handling multidrop, point-to-point, or loop configurations. Many HDLC
protocol features are also supported.
The SDMA accepts commands from the local microprocessor to
either transfer data or issue link-level commands. The SDMA issues and PROPOSED PIN ASSIGNMENT
responds to most link-level commands, ensures data integrity and
validation, and handles some error recovery.
Vss
• Up to 4M Bit/Sec Rate Vcc/Mode
TDATA
• External Data Recovery
RDATA
• External Clocks
TXCLK
• DMA Command and Data Chaining RXCLK

• SDLC Protocol lACK

MCLK
• HDLC
MREADY
• Full/Half Duplex Operation
SIM
• Separate DMA Channel for Transmit and Receive DMAVMA

• Normal or Systems Address Detection m

CTS
• MC6809, MC6800 Bus Compatible
D7
• NRZ/NRZI Data D6

D5
• Internal Bit and Byte Synchronization
A5 D4
• Point-to-Point, Multidrop, and Loop Modes
A6
• CRC Generator and Detection

• Primary/Secondary Configurations

• External Power for Loop Mode

• Initialization Control Pin (SIM)

• Vectored Interrupt Capability (lACK)

244
 MC6842

BLOCK DIAGRAM

h-T7...,.,r-rTTT7...,.,r-r""''''''T7...,.,r-r-,--r'''i~ Address
Bus

Serial
Lines

245
 MEK6809AC

EDITOR ASSEMBLER FOR THE MEK6809D4B

The MEK6809EAC is a software package designed to operate in conjunction with systems based on the MEK6809D4
Microcomputer Module It is available in audio cassette form recorded at 300 Baud. It is compatible with the tape format of the
MEK6809D4

General Features
• ROMabie
• Assembles both 6800 and 6809 mnemonics to 6809
object
• Able to Operate with 04 or Stand-Alone 6809
• Self-Sizing of Memory
• Can Read Tapes Produced by MEK6802EA Using
MEK681/0
• Serial or Parallel Printer Supported
• Interactive Editor
• Uses MEK6809D4 Cassette for Program Storage
• Uses MEK68R2D for Video Display

Editor Commands and Features

• Append Text Files from Audio Cassette
• Punch Text Files to Audio Cassette
• Print Text Files on Optional Printer
• Find Beginning of Text File
• Move Through Text File One or More Characters at a
Time
• Find End of Text File
• Move Through Text File One or More Lines at a Time
• Insertl Delete Character Strings
• Search for a Character String
• Change Character String
• Insertl Delete Lines
• Chain Editor Commands

Assembler Commands and Features

• Speed Control of Assembly Listing Allows Examination
on CRT Screen
• Paging and Space Control of Listing
• Pseudo Opcodes for Assembler Control
• Produce Assembly Listing on Screen or Printer
• List Symbols
• Output Object Code to Audio Cassette
• Output Object Code to Memory

246
 MEK6809AC

MEMORY MAP TYPICAL CONFIGURATIONS

The illustration below depicts the optional memory maps The MEK6809EA can be used in a variety of system con-
for typical systems using the M EK6809EAC figurations, but each must contain baSIC items. Included in
these are an MC6809 type microprocessor, a monitor ROM
1D4BUG), I/O devices, and sufficient Read/Write memory
(RAM) for the task to be accomplished
MEK6l109EAC MEMORY MAP The M EK6809D4B furnishes both the M C6809 M PU and
the monitor ROM required. If an RS-232C compatible ter-
Side 1 Side 2 minal is available, the MEK6809D4B also provides the I/O in-
terface required. An alternative to the terminal consists of an
FFFF FFFF
D4BUG D4BUG MEK68R2D together with a CRT monitor lor modified TV
EBOO EBOO set) and an ASCII encoded keyboard
EOFF EOFF
The RAM requirements can be met with an MEK68MM16
I/O I/O
116K byte) or MEK68MM32 (32K byte) dynamic memory
EOOO Eooo
9FFF CFFF module. The latter provides Significantly more buffer
CRT Screen Edltor/ space, needed for larger programs
Refresh Assembler Side two of the MEK6809EAC contains a version of the
Aooo
9AM 9FFF Editor/ Assembler which is suitable for operation from ROM
9000
CRT Screen or EPROM. This offers the user the opportunity to have this
8FFF Refresh code programmed into EPROMs. These can then be inserted
OptIonal RAM
BODO into the user ROM sockets provided on the MEK6809D4B
Text
Buffer 7FFF (The EPROMs required for this would be three 4K x B or six
Optional 2K x 8 single supply types. Multiple supply versions can be
4000
3FFF Text used if slight modifications are made to the MEK6809D4BI
Buffer Population of the user RAM sockets on the MEK6809D4B
Normal 2000 provide text buffer space for small programs. Assuming an
Text Buffer lFFF RS-232C terminal is available, this combination results in a
Normal
3000 single-board program development station.
Text Buffer
2FFF 033C The use of any multi-board configuration will require a
Editor/ 033B backplane. Alternatives available include the MEK68CMB
Assembler
0100 Card Cage/Motherboard combination, and the MEK68MB5
OOFF Scratch Motherboard with stand-alone card guides. If the less expen-
Scratch sive MEK68MB5 is chosen, it can be upgraded later with the
0000 0000 MEK68CC.

247
 MEK6809D4/MEK68KPD

MEK6809D4
MEK68KPD

The MEK6809D4 Advanced Microcomputer Evaluation Board and MEK68KPD Keypad/Display Unit provide the necessary hard-
ware and firmware for a computer system based on the Motorola MC6809 High Performance Microprocessor. The system forms an
evaluation tool to facilitate the application of Motorola microprocessors and associated components.
The MEK6809D4A is used with an MEK68KPD and is complete with a power supply. The MEK6809D4B requires an external
power supply and is used with RS-232 terminal or an MEK68R2D CRT Interface plus a CRT and an ASCII keyboard.
The user can prototype dedicated systems plus write and evaluate software programs in machine language, using a cassette
recorder/player for data storage. Provisions are made for extensive system expansion.

MEK6809D4

MEK68KPD

248
 MEK6809D4/M EK68KPD

PRODUCT FEATURES

MEK6lmD4 DIMENSIONS
• MC6809 High Performance Microprocessor • MEK680904:
• D4BUG Monitor Firmware 14K) Expandable to 6K Two-Sided PC Board
309.8 mm (12 in) Wide by
• Direct Memory Access
177.8 mm (7 in) High by
• Interrupt by Device 1.59 mm (0.062 in) Thick
• Audio Cassette Interface, 300 or 1200 Baud
• MEK68KPD:
• Optional RS-232 Port with MC6B50 ACIA Two-Sided PC Board
• System RAM, 512 Bytes Expandable to 1K 304.8 mm (12 in) Wide by
• User RAM, 512 Bytes Expandable to 4K 157.5 mm (6.2 in) High by
1.59 mm (0.062 in) Thick
• RAM/ROM Page Select Register
• ROM Mapping Technique
• All I/O and Memory Fully Decoded
• Stop-On-Address Comparator SUPPLY VOLTAGES (±5%1
• System Clock Internal or External • MEK680904:
• Test Signal and Control Logic for Bidirectional Address 5 Vdc at 2.0 A max (with all optionsl
Bus + 12 Vdc at 25 mA max
- 12 Vdc at - 23 mA max
• Control and Status Lines
• System Buffers • MEK68KPD:
120 Vac.60 Hz, produces 18 Vac lcll input to board. An
MEK68KPD on-board regulator provides power required to operate
the KPD plus D4 board in minimum configuration.
• Eight 7-Segment Displays
• 25-Key Keypad
• On-Board Power Supply ENVIRONMENTAL
• User PIA, MC6821 Op6rating Temperature: O°C to 55°C (32°F to 131°;=)
• Wire-Wrap Area
• H,-Pin Auxiliary Socket Relative Humidity: to 80% without condensation

HIGHLIGHTS
• System buffers are used between sections of the store and recover Kansas City Standard 300-baud or
MEK680904 board and between the board and its edge 1200-baud format cassette tape data.
connectors. • Interrupt driven stop-on-address comparator.
• Hardware RAM and ROM page select register. • System clock derived from 3.579 MHz on-board XT AL
• 4K static User RAM leight sockets) may be mapped with or from a 4 x TTL compatible external source.
jumpers to appear at any 4K block in the 6411. basic mem- • "Test" signal and logic provided to allow control of on-
ory space, and in addition may be jumpered to appear on board memory and I/O, from an external processor
a selected "RAM Page/or Pages" as controlled by a 3- through the 7a-pin edge connector.
bit hardware RAM Page register. • Control and status lines provided for flexible hardware
• Eight 24-pin ROM sockets may be configured to accept control of MPU and Bus Decode/Drive logic. This allows
combinations of ROM/EPROM types including 1K x 8 for:
single or triple supply.EPROMs or ROMs, 2K x 8 single • Testing and Debug
or triple supply EPROMs or ROMs, 4K x 8 ROMs or • Interrupts (RESET, NMI, IRQ, FIRQ)
EPROMs, or 8K x 8 ROMs or EPROMs. • Interrupt Vectoring by Device (IVE, STKOP)
• A ROM-based mapping technique is used to allow com- • Interrupt Disable (IRQE, FIRQE)
pletely general address mapping of the eight ROM sock- • HALT and Bus Request (BREQ)
ets anywhere in the 64K basic memory space with 1K • Slow Memory (MEMRDY)
resolution. In addition, the sockets may be mapped on ·DMA
any "ROM Page/or Pages" as controlled by a 3-bit
hardware ROM page register. The following features are standard on the MEK6809D4B
• All memory and I/O on the board is fully decoded, so that and may be included as options on the MEK6809D4A:
address space not specifically required on the 04 is avail- 1. RS-232 compatible serial port including buffered
able for off-board mapping. handshake signals.
• A - 12 volt to - 5 volt regulator is provided to allow use 2. Baud rate generator prOViding baud rate clocks for 110,
of 3-supply EPROMs on the 04. Supply voltages of + 12, 300, 600, 1200, 4800, and 9600 baud rates.
- 12, and + 5 must be provided by the user. 3. Address, data, and control lines fully buffered at bus
• Hardware is provided which allows Monitor software to interface.

249
 MEK6809D4/MEK68KPD

MODEL TYPES

MEK6809D4 MOKEP M-60 and M-70 products are compatible with the
MEK6909D4A - This variation has no RS-232 circuitry or D4B thus allowing expansion to an ASCII keyboard interface
address and data buffers to the edge connector. The D4A is to the microcomputer system. The MEK68KPD (with its on-
intended for use with the MEK68KPD Keypad/Display Unit board power supply disconnected I may be used with the
which has an on-board power supply to operate the system. MEK6809D4B.
No RAMs are provided in the "User RAM" array. A 4K
monitor program is provided.
MEK6809D4B - This variation is intended for use with an
RS-232 serial terminal or an MEK68R2D CRT interface as the MEK68KPD
system terminal. The D4B has RS-232 circuitry and data and The MEK68KPD is the Keypad/Display unit intended for
address buffers. use with the M EK6809D4 board and interfaces electrically
To operate the RS-232 interface, the user must supply with the MEK6809D4. Standard interface to the 04 is via a
+ 12 V, + 5 V, and -12 V power A 4K + 2K monitor is pro- 24-conductor cable and plug assembly supplied with the
vided. No RAMs are provided in the "User RAM" array. KPD unit.

EXPANSION

With the rapid adva')cements in the microprocessor in- MEK68EP EPROM Programmer Module
dustry, there is a vital need to provide educational and The MEK68EP has provisions for programming both single
evaluation material to help engineering/technical personnel and triple power supply types of 1K, 2K, and 4K EPROMs.
stay abreast of this technology
In response to this need Motorola Memory Systems has
MEK68RR ROM/RAM Module
evolved a series of kit boards intended for the educational
evaluation of the MC6800 family of integrated circuits. The The MEK68RR has provisions for eight ROM sockets
series is called "MOKEP" Ifor Motorola Kit Expansion Pro- which may be configured to accept 1K, 2K, 4K, or 8K single
ducts) and includes the following wide range of boards: or triple supply ROMs or EPROMs. The board also has
sockets for up to 8K bytes of static RAM

MEK68CC Card Cage

MEK68MM16/MM32 16K/32K Memory Modules
The MEK68CC is used with the MEK68MB5 Motherboard.
The MEK68MM16 has 16K bytes of RAM and the
MEK68MB5 Motherboard Module MEK68MM32 has 32K bytes. The MEK68MM boards employ
16K dynamic RAMs and a hidden refresh technique to
The MEK68MB5 Motherboard Module has provisions for
achieve the low cost, low power consumption, and high
ten card slots on 5/8" centers, with alternate slots populated
density of dynamic memory systems, while appearing as
with 7a-Pin connectors.
static memory to the system. The MEK68MM fully supports
the RAM paging technique of the 04 Microcomputer
MEK68CMB Card Cage/Motherboard
Module, allowing up to eight boards or 256K bytes of RAM
The MEK68CMB can accomodate ten cards of the MOKEP to be used in one system.
series. The card cage is identical to the MEK68CC. The
motherboard is a fully populated version of the MEK68MB5
MEK6809EA Editor/Assembler
without the stand-alone card guides. The completed
assembly measures 8-1/4" high by 7-1/4" wide by 13-1/4" The MEK6809EA Editor/Assembler provides the user of
deep. the MEK6809D4B with the ability to enter, assemble, edit
and save assembly language programs for execution on the
MEK68R2/R2D/R2M Programmable CRT Interface Modules M6809. The editor may also be used to enter and edit text
The MEK68R2/R2D/R2M Programmable CRT Interface files that will not be assembled for execution. The assembler
Modules are used in conjunction with other products in the will accept both M6800 and M6809 mnemonics. The object
MOKEP family to form a microcomputer system. The code from the assembler can be placed in memory or saved
MEK68R2D is to be used with the MEK6809D4 Microcom- on tape. The MEK68R2D display and stand alone terminals
puter Module and an MEK68MB series Motherboard. All are supported by software.
units feature software programmable line and character for-
mat, upper and lower case 5 x 7 matrix display, MEK68WW/WWl Wirewrap Modules
semigraphics, and up to 4K of screen display memory. All The MEK68WW is used with the MEK6800AB Adapter
modules provide an interface for an ASCII keyboard. Motherboard, and interfaces directly with the 6D-Pin bus of
the AB. The MEK68WW1 utilizes a 7a-pin bus, directly inter-
MEK68IO Input/Output Module facing with the MEK68MB series motherboards. Either pro-
The MEK6810 is supplied with a 3JQ/1200 Baud cassette duct can be used as a card extender. Both are supplied with
interface, two MC6850 ACIAs, an MCl4411 Baud Rate components required for buffering of address, data, and
Generator, and one MC6821 PIA. control buses.

250
 MEK6809D4/MEK68KPD

MEK6809D4 AC Operating Conditions and Characteristics

AC OPERATING CHARACTERISTICS IBus)

Parameter Symbol Min Nom Max Unit
Cycle Time t cyc 1100 1130
Address Setup tAO 25
Address Hold 3 tAH 10 30
Write Data Valid IDVW 250
Write Data Hold IDHW 10 30
E 1</>2) Low Time l,t,2L 500
E 1</>2) High Time l,t,2H 500
E Low to 0 High lEO 275
o High Time tOH 500

AC OPERATING CONDITIONS IBus)

Parameter

Access Time

Read Data Hold3

NOTES: 1) Operating temperatures TA=25°C

2) Timing measured at edge connector 150% points)
3) Measured from falling edge of E 1</>2)
41 Measured from rising edge of (</>2)

MEK8lI09D4 TIMING DIAGRAM

251
 MEK6809D4/MEK68KPD

SOFnNAREFEATURES

• Memory Change/ Display • Stop-On-Address

• Register Change/ Display • Escape from All Functions
• Breakpoint Editor • 16 User Special Functions
• 4K Monitor in Position Independent Code • Additional Features on D4B
(6K for MEK6809D4B Version) • Memory Dump to Examine Blocks of Data
• Trace Single Step and User Line • Memory Fill
• Memory Search
• Go to User Program
• Memory Move
• Ca'culate Offset • ASCII Entry
• Cassette Punch/LoadlVerify

The MEK6809D4 operating system allows the development Stop on Address

and operation of User-defined programs. The basic monitor In de-bugging programs, it is often advantageous to be
program interfaces with an MEK68KPD Keypad/Display Unit able to halt the machine when a specific address is en-
and IS contained in a 4K Byte ROM (MCM68332 or countered. A typical example of the use of this function is to
equivalent). This ROM is factory installed in all versions of determine the reason for an inadvertent lor incorrect! change
the MEK6809D4 assembled units. of a memory location during the running of a User program.
A second 2K Byte ROM IMCM68316E or equivalent) is The Stop On Address function is implemented on the
used with an MEK68R2D CRT Monitor/ ASCII Keyboard In- MEK6809D4 by circuitry which compares the MPU Address
terface or RS-232 compatible terminal. This additional 2K Outputs with User-entered data in the Stop On Address
ROM is provided in the MEK6809D4B version. Register. Providing the SOA function is armed, a Non-
The monitor program source listings, complete with com- Maskable interrupt is generated when a comparison is
ments, are available from Motorola. The monitor program is achieved.
written in highly subroutined, position independent code. Depending on the type of instruction (more specifically,
These source listings provide a valuable starting point for upon the timing relationship of the address assertion in the
many types of user programs. instruction cycles!, the NMI may be recognized at the end of
The monitor program provides the following functions: the previous instruction. Control then passes to the monitor,
allowing the User to determine that one of two specific in-
Examine/Change Memory Location structions has accessed the specified memory location.
This allows the user to open any memory location and In some instances it is desirable to allow the program to
display the contents. New data may then be entered if stop only on the Nth time an address is encountered. The
desired, assuming Read/Write memory is present at the MEK6809D4 can implement this function. It is also possible
selected location. If an attempt is made to write into an in- to output a tflgger pulse each time the address is en-
valid location, the new data will be displayed together with countered, rather than stopping program execution
the fixed data at the invalid location. Only the new data is
displayed when a valid change of Read/Write memory is ac- Breakpoints
complished The SOA function is implemented in hardware. Software
After the Examine/Change step, the User has the option methods of program execution interruptions include the set-
of automatically opening either the next or previous loca- ting of breakpoints at desired locations in the program. This
tion - or escaping to the monitor program. effectively substitutes a Software Interrupt for the instruc-
tion at that location
Examine/Change Registers Up to eight breakpoints can be set in the User program
This function allows the User to Examine/Change two ex- (provided the program is in RAM!. As with SOA, the User
ternal registers plus those areas of the Stack RAM cor- has the option of allowing N-l breakpoints to be bypassed if
responding to the storage locations of the nine internal desired. (The maximum value of N for either SOA or break-
registers of the MC6809. This has the effect of allowing the poi nts is 255)
User to Examine/Change these registers. The User can set, clear, or examine breakpoints via the
This function differs from Memory Examine/Change in Breakpoint Editor function.
that the registers are displayed in a set sequence. Register
designation as well as contents are displayed to facilitate use Trace Instruction
of the function. This function allows the User to step through a program
The two external registers are incorporated on the one instruction at a time. At the end of each instruction, the
MEK6809D4 to perform operations not inherent with the Examine/Change Register routine is automatically entered,
MC6809. and the new Program Counter value is displayed.

252
 MEK6809D4/MEK68KPD

Trace Line User Program Control

The MEK6809D4 de-bug routines include functions to
It is often desirable to trace through a program while
allow the User to Go To, Continue, or Abort User Programs.
treating a subroutine as a single instruction. One obvious ex-
ample of this is the situation wherein all subroutines have Offset Calculation
previously been thoroughly de-bugged. The MEK6809D4 de-
In generation or modification of programs, it is often
bug routines allow this to be accomplished in either of two
necessary to calculate the offset from the location of a jump
ways.
or branch instruction to its destination. Some indexed mode
One of these (software method) involves a comparison of instructions also use relative offsets. The Examine/ Change
each instruction in a subroutine until the instruction follow- Memory Location includes a subfunction to allow this to be
ing the subroutine is encountered. Thus, the portion of the easily accomplished.
program from a.subroutine call to its return is treated as one The User opens the location of the offset, types the offset
instruction as far as the Trace function is concerned. Nested command, then enters the desired destination address. The
subroutines are automatically handled by the monitor pro- MEK6809D4 calculates the required offset, displays it, and
gram. enters the data in the appropriate memory locationls!. The
Offset Calculation supports both short and long offsets.
The second Trace Line option uses the SOA circuitry. This
has an advantage over the software method in that Punch/Load/Verify Audio Cassette
subroutine execution is in real time. This is particularly The Audio Cassette interface is a modified Kansas City
helpful in de-bugging time-dependent I/O routines. lit is also Standard version capable of operation at either 300 or 1200
desirable for long subroutines, since the software method Baud. The interface allows any of the three functions
greatly increases the run time of a subroutine.! Its disadvan- (Punch, Load or Verify with Memory) to operate with or
tage is that program execution often continues for one in- without an optional offset. This is particularly useful for User
struction after the return. programs written in position Independent code.

ADDED D4B SOFTWARE FEATURES

Memory Dump After the mask has been specified, the search function will
The memory dump command allows the user to display btl performed over the specified address range.
blocks of memory with ASCII equivalents. The display for- Each time the comparison algorithm is successful, the ad-
mats differ slightly depending on the display device con- dress of the first location of the match is displayed. If the list
figuration. The ending address must be a larger hexadecimal of successful addresses is being displayed too quickly, the
number than the beginning address or a warning will be listing may be temporarily halted by typing (ESCAPE) as in
issued, followed by a new request for a begin address. The the memory dump command.
dump command cannot proceed until a satisfactory address
range has been specified. Memory Move
Allows the user to move a block of data from one area in
memory to a new area.
Memory Fill The beginning and ending addresses are entered the same
Allows the user to fill a block of memory with a four byte way as in memory dump. FollOWing entry of the end ad-
pattern. The beginning and ending addresses are entered as dress, a message will appear requesting entry of the new
in the memory dump command. beginning address where the block of data is to be moved.

ASCII Entry
Memory Search Allows a user to store ASCII data to memory quickly and
Allows search of a specified block of memory for a 4 byte easily without having to look up each ASCII character to
pattern subject to a corresponding 4 byte mask. For all bits in determine its hexadecimal equivalent.
the mask which are zero, the corresponding bit in the pattern Features are incorporated to assist in setting up messages
is considered to be "don't care." for the D4BUG callable subroutine "PDATA."

MEK68l9D4 DESCRIPTION

CPU ROM
The CPU consists of an MClBl9 high performance The ROM system consists of eight ROM sockets which
microprocessor, a 3.579 MHz crystal, and buffers which in- may be configured to accept various combinations of ROM
terface the MClBl9 to other circuit blocks on the D4 Board. types. These include single or triple power supply varieties of
The MC6809 supports programming techniques such as 1K, 2K, 4K, or BK x 8 ROMs or EPROMs.
position independence, re-entrancy, and modular program- The ROM type configurations are controlled by mini-
ming. The MClBl9 has hardware and software features jumpers which may be easily moved without the need for any
which make it a suitable processor for higher level language tools.
execution or standard controller application.

253
 MEK6809D4/MEK68KPD

MEK6809D4 BLOCK DIAGRAM

Mapping of the eight ROMs in memory space is ac- The Data Bus System
complished by a mapping ROM which is used as a program- There are four bi-directional data buffers used in the 04; a
med logic array. A paging technique allows up to 192K bytes ROM buffer, RAM/IO buffer, Edge buffer, and MPU buffer
of ROM to be used In the 04 system Each buffer has an enable and a direction input. Control logic
configures these buffers to route data between sections of
RAM the 04 board
There are two groups of 1K x 4 RAMs. One group is the
stack RAM and the other is the user RAM. The Stop-Dn-Address Circuit
The stack RAM is used mainly for the 04 operating system The purpose of a stop address is to enable a user program
stack and scratch RAM. Also, 512 bytes are available for user to be executed until a certain address is reached.
RAM application. This RAM is always located in the 04 The address to be stopped on is stored and when the
system at memory location $E4OO through $E7FF. board address bus bits coincide, an output results. This
The user RAM is a 4K x 8 block of memory that can be causes a nonmaskable interrupt to occur which switches the
positioned anywhere in the 04 memory map, using jumper microprocessor to a service routine.
connectIons. When a coincidence of address occurs, an NMI is not
It is possible to disable the eight user RAM sockets to necessarily generated. In these cases, the comparator output
allow use of a MOKEP MEK68MM Memory Board for system is available at a test point to provide a trigger signal to an
expansion. oscilloscope.
Another jumper, when removed, prevents the user RAM
from being written into (write protect), but the stack RAM is The RS-232 Circuit
not affected. With the jumper in place, read and write to the The RS-232 specification defines a standard for intercon-
user RAM is normal. necting computer terminals of different makes. The ACIA
converts the parallel data on the buses to serial data. The
The Address Bus System serial data is then translated into RS-232 levels.
In some microprocessor systems, the address flow is from
the microprocessor through buffers and to the motherboard The Cassette Circuit Interface
bus. The 04 uses a more complex arrangement that permits The 04 uses very few components to interface a tape
disabling the microprocessor. This allows addresses to be recorder to its operating system. Most of the cassette opera-
fed to the 04 from an external source, to access board com- tion occurs in software, to create tapes and recover data
ponents and permits OMA (direct memory access) for some from tapes. The tape information consists of a stream of
applications. 1200 and 2400 Hz serial audio data.

254
 M EK6809D4/M EK68KPD

MEK68KPD BLOCK DIAGRAM

MEK68KPD DESCRIPTION

The MEK68KPD Includes a 25-key keypad, eight The display consists of eight seven-segment LEDs with a
7-segment LED displays, an on-board + 5 volt power supply, character height of 0.5 Inches. The grouping of the displays
and an uncommitted MC6821 PIA. ProvIsions are made to is in a 4-2-2 linear array A sUitable anti-glare filter IS provided
allow disconnection of the on-board regulators when an ex with each MEK68KPD
ternal + 5 volt supply IS used. A wire-wrap area is provided The PIAs used on the KPD are fully decoded via a
for custom circuitry and a 16-pln socket allows for additional Peripheral Chip Select signal and Address lines AO-A2 from
signals to be brought to or from thiS wire-wrap area the M EK6809D4. Data IS furnished via the input cable

ORDERING INFORMATION

Part Number Features Prerequisites

MEK6809D4A No ADDR/Data Buffers/No RS-232 MEK68KPD
MEK6809D4B ADDR and Data Buffers/ RS-232 INTFC RS-232 Termina! and Power Supply or
MEK68R2D, CRT, ASCII Keyboard and
Power Supplies

255
 APPENDIX D

MC6809
Instruction Set Summary

The following pages are provided through the courtesy of Moto-

rola, Inc., Austin, Texas.

256
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

6809 PROGRAMMING MODEL

C PC I PROGRAM COUNTER

I A B I ACCUMULATORS

'-- ,/
o
UO DIRECT PAGE REGISTER

I
FH I NZV CC - CONDITION CODE
CARRY-BORROW
OVERFLOW
ZERO
NEGATIVE
IRQ INTERRUPT MASK
HALFCARAY
FAST INTERRUPT MASK
ENTIRE STATE ON STACK

Simple Conditional Branches

6809 STACKING ORDER Condition Complement
BEQ BNE
PUll ORDER BMI BPl
~ BCS BCC
CC BVS BVC
INCREASING 6809 VECTORS
A
MEMORY FFFE Restart
B Signed Conditional Branches
FFFC NMI
DP ConditiOn Complement
L XHi
FFFA
FFF8
SWI
IRQ
BGT BlE
X lo BGE BlT
FFF6 FIRQ
YHi BEQ BNE
FFF4 SWI2
Ylo BlE BGT
FFF2 SWI3
U/S Hi BlT BGE
FFFO Reserved
U/S lo
PC Hi Unsigned Conditional Branches
PC lo Conditjon Complement
i BHI BlS
PUSH ORDER BHS BlO
BEQ BNE
BlS BHI
BlO BHS

257
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

HEXADECIMAL AND DeCIMAL CONVERSION

HOW TO USE THE TABLES

CONVERSION TO DECIMAL Find the decimal welghls lor correspondmg

hexadeCimal characters beginning with Ihe least stgnlhcanl character The
sum 01 the decimal wetghl 1$ the decllnal yalue 01 the hexadecimal number

CONVEASION TO HEXADECIMAL Flfld the highest decimal value In the

lab'e whICh IS lOwer than or equal to the decimal number to be converted
The corresponding hexadeCImal characler 1$ the most signthcani character
SUbtract Ihe deCimal value found Irom the decimal number to be converted
With the dI"erence. repeat the process 10 lind subsequent hexadecimal
characlers

POWERS OF TWO
HEXADECIMAL AND DECIMAL CONVERSION

'5 BYTE 8 7 BYTE 0

'" 1
"0
2 1
'5 CHAR 1211 CHAR 8 7 CHAR 4 3 CHAR 0 4 2
HEX DEC HEX DEC HEX DEC HEX DEC 8 3
'6 4
o
,
0
4 096 ,
0 o0
256 ,
o
16
0
1 ,
0 32
64
5
6
2 8 192 2 512 2 32 2 2 '28 7
3 12 288 3 768 3 48 3 3 256 8
4 16 384 4 1 024 4 64 4 4 5'2 9
5 20 480 5 1 280 5 80 5 5 1,024 10
6 24 576 6 1 536 6 96 6 6 2.048 11
7 28 672 7 1 792 7 112 7 7 4.096 '2
8 32 768 8 2 048 8 128 8 8 8.192 13
9 36 864 9 2 304 9 144 9 9 16.384 '4
A 40 960 A 2 560 A 160 A 10 32.768 '5
B 45 056 B 2 816 B 176 B 11 65.536 16
C 49 152 C 3 072 C 192 C 12 131.072 '7
D 53 248 D 3 328 D 208D 13 262.144 18
E 57 344 E 3 584 E 224 E 14 524.288 19
F 61 440 F 3 840 F 240 F '5 1.048.576 20

ASCII CHARACTER SET (7-BIT CODE)

MS
CHAR 0 1 2 3 4 5 6 7
LS 001 010 011 101 110
CHAR
000 '00
"'
0 INDEXED ADDRESSING
NUL DLE SP @
POST BYTE REGISTER
,
0000
SOH DC' Q BIT ASSIGNMENTS
0001
2 INDEXED
STX DC2 POST-BYTE REGISTER BIT ADDRESSING
0010
7 6 5 4 3 2 1 0 MODE
3
ETC DC3 0 X X X X X X X EA - • A , 4 BIT OFFSET
0011
4 1 X X 0 0 0 0 0 R+
0100
EDT DC<
1 X X X 0 0 0 , ,A++
5 1 X X 0 0 0 1 0 ,-R
ENQ NAK
010'
1 X X X 0 0 1 1 ,--R
6
ACK SYN X X 1 EA -.R, o OFFSET
0110 1 X 0 0 0
7 1 X X X 0 , 0 1 EA ,R ~ ACeS OFFSET
,
eo
BEL ETB
0111
X X X 0 1 1 0 EA =--' ,A :!: ACCA OFFSET
8
BS CAN 1 X X X 1 0 0 0 EA - ,R , 7 BIT OFFSET
'000
1 X X X 1 0 1 EA -'" ,R 15 BIT OFFSET
9 HT EM , 0
, 1 EA - .R , D OFFSET)
::!:

'001
A
1
1
X
X
X
X
X
X , 0
1 0 0 EA '-" , PC ~ 7 BIT OFFSET
1010
SUB
, X X X 1 1 0 1 EA =, PC, 15 BIT OFFSEl
B
1011
ESC 1 X X 1 1 1 1 , EA - ,ADDRESS

~
C
FS i. ADDRESSING MODE FIELD
I FIELD
D FOR 87 = 1: INDIAECT
CR GS
1101 FOA 87 -= 0: SIGN B!T
E
1110
F
SO RS
• REGISTER FIELD
OQR
01:R =- Y
= X

SI VS DEL IO,R = U
1111
11:R = S

258
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

PUSH/PULL POST BYTE

CCA
A
'-- B
L...- DPA
L-- X

'-----------y
'-- S/U
'------ PC

TRANSFERI EXCHANGE POST BYTE

I ~O~AC~ I D~STI~AT!ON I
REGISTER FIELD
0000 = D (A:B) 1000 = A
0001 = X 1001 = B
0010 = Y 1010 = CCA
0011 = U 1011 = DPA
0100 = S
0101 = PC

OP MNEM MODE - II OP MNEM MODE - II OP MNEM MODE - II

00 NEG DIRECT 6 2 1C ANDCC IMMED 3 2 2E BGT RELATIVE 3 2

1'13 COM 6 2 10 SEX INHERENT 2 1 2F BLE RELATIVE 3 2
1'14 LSR 6 2 1E EXG f 8 2 31'1 LEAX INDEXED 4 2
ROR 6 2 1F TFR INHERENT 7 2 31 LEAY 4 2
1'16
1'17
1'18
ASR
ASL/LSL
6
6
2
2
21'1
21
BRA
BRN
RELATIVE 3
3
2
2
32
33
LEAS
LEAU
I
INDEXED
4
4
2
2
1'19 ROL 6 2 22 BHI 3 2 34 PSHS INHERENT 5 2
0A DEC 6 2 23 BLS 3 2 35 PULS 5 2
l'JC INC 6 2 24 BHS/BCC 3 2 36 PSHU 5 2
1'10 TST 6 2 25 BLO/BCS 3 2 37 PULU 5 2
I'JE JMP 3 2 26 BNE 3 2 39 RTS 5 1
I'JF CLR DIRECT 6 2 27 BEQ 3 2 3A ABX 3 1
12 NOP INHERENT 2 1 28 BVC 3 2 3B RTI 6/15 1
13 SYNC INHERENT 2 1 29 BVS 3 2 3C CWAI 21 2
16 LBRA RELATIVE 5 3 2A BPL 3 2 3D MUL 11 1
17 LBSR RELATIVE 9 3 2B BMI 3 2 3F SWI 19 1
19 OM INHERENT 2 1 2C BGE 3 2 41'1 NEGA 2 1
1A ORCC IMMED 3 2 20 BLT RELATIVE 3 2 43 COMA INHERENT 2 1

259
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

OP MNEM MODE ~
# OP MNEM MODE ~
# OP MNEM MODE - #

44 LSRA INHERENT 2 1 50 TSTB INHERENT 2 1 77 ASR EXTENDED 7 3

46 RORA 2 1 5F CLRB INHERENT 2 1 78 ASLlLSL 7 3
47 ASRA 2 1 60 NEG INDEXED 6 2 79 ROL 7 3
48 ASLA/LSLA 2 1 63 COM 6 2 7A DEC 7 3
49 ROLA 2 1 64 LSR 6 2 7C INC 7 3
4A DECA 2 1 66 ROR 6 2 70 TST 7 3
4C INCA 2 1 67 ASR 6 2 7E JMP 4 3
40 TSTA 2 1 68 ASLlLSL 6 2 7F CLR EXTENDED 7 3
4F CLRA 2 1 69 ROL 6 2 80 SUBA IMMED 2 2
50 NEGB 2 1 6A DEC 6 2 81 CMPA 2 2
53 COMB 2 1 6C INC 6 2 82 SBCA 2 2
54 LSRB 2 1 60 TST 6 2 83 SUBD 4 3
56 RORB 2 1 6E JMP 3 2 84 ANDA 2 2
57 ASRA 2 1 6F CLR INDEXED 6 2 85 BITA 2 2
58 ASLB/LSLB 2 1 70 NEG EXTENDED 7 3 86 LOA 2 2
59 ROLB 2 1 73 COM 7 3 88 EORA 2 2
5A DECB
INHERENT
2 1 74 LSR I 7 3 89 ADCA 2 2
5C INCB 2 1 76 ROR EXTENDED 7 3 8A ORA IMMED 2 2

OP MNEM MODE ~
# OP MNEM MODE ~
# OP MNEM MODE ~

8B ADDA IMMED 2 2 9E LOX DIRECT 5 2 B0 SUBA EXTENDED 5 3

8C CMPX IMMED 4 3 9F STX DIRECT 5 2 B1 CMPA 5 3
80 BSR RELATIVE 7 2 A0 SUBA INDEXEC 4 2 B2 SBCA 5 3
8E LOX IMMED 3 3 A1 CMPA 4 2 B3 SUBD 7 3
90 SUBA DIRECT 4 2 A2 SBCA 4 2 B4 ANDA 5 3
91 CMPA 4 2 A3 SUBD 6 2 B5 BITA 5 3
92 SBCA 4 2 A4 ANDA 4 2 B6 LOA 5 3
93 SUBD 6 2 A5 BITA 4 2 B7 STA 5 3
94 ANDA 4 2 A6 LOA 4 2 B8 EORA 5 3
95 BITA 4 2 A7 STA 4 2 B9 ADCA 5 3
96 LOA 4 2 A8 EORA 4 2 BA ORA 5 3
97 STA 4 2 A9 ADCA 4 2 BB ADDA 5 3
98 EORA 4 2 AA ORA 4 2 BC CMPX 7 3
99 ADCA 4 2 AB ADDA 4 2 BD JSR 8 3
9A ORA 4 2 AC CMPX 6 2 BE LOX 6 3
9B ADDA 4 2 AD JSR 7 2 BF STX EXTENDED 6 3
9C CMPX 6 2 AE LOX 5 2 Gil SUBB IMMED 2 2
90 JSR DIRECT 7 2 AF STX INDEXED 5 2 C1 GMPB IMMED 2 2

260
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

OP MNEM MODE ~
# OP MNEM MODE ~

# OP MNEM MODE ~
#

C2 SBCB IMMED 2 2 D7 STB DIRECT 4 2 E9 ADCB INDEXED 4 2

C3 ADDD 4 3 D8 EORB 4 2 EA ORB 4 2
C4 AN DB 2 2 D9 ADCB 4 2 EB ADDB 4 2
C5 BITS 2 2 DA ORB 4 2 EC LDO 5 2
C6 LOB 2 2 DB ADDB 4 2 ED STD 5 2
C8 EORB 2 2 DC LDD 5 2 EE LOU 5 2
C9 ADCB 2 2 DD STD 5 2 EF STU INDEXED 5 2
CA ORB 2 2 DE LDU 5 2 F0 SUBB EXTENDED 5 3
CB ADDB 2 2 DF STU DIRECT 5 2 F1 CMPB 5 3
CC LDD 3 3 E0 SUBB INDEXED 4 2 F2 SBCB 5 3
CE LOU IMMED 3 3 E1 CMPB 4 2 F3 AODD 7 3
D0 SUBB DIRECT 4 2 E2 SBCB 4 2 F4 ANDB 5 3
01 CMPB 4 2 E3 ADDD 6 2 F5 BITB 5 3
02 SBCB 4 2 E4 AN DB 4 2 F6 LDB 5 3
03 ADDD 6 2 E5 BITB 4 2 F7 STB 5 3
D4 ANDB 4 2 E6 LDB 4 2 F8 EORB 5 3
05 BITB 4 2 E7 STB 4 2 F9 ADCB 5 3
06 LOB DIRECT 4 2 E8 EORB INDEXED 4 2 FA ORB EXTENDED 5 3

OP MNEM MODE ~

# OP MNEM MODE - # OP MNEM MODE - #

FB ADDB EXTENDED 5 3 102E LBGT RELATIVE 5(6) 4 10CE LOS IMMED 4 4

I
FC LDD 6 3 102F LBLE RELATIVE 5(6) 4 10DE LDS DIRECT 6 3
FD STD 6 3 103F SWI/2 INHERENT 20 2 10DF STS DIRECT 6 3
FE LDU 6 3 1083 CMPD IMMED 5 4 10EE LDS INDEXED 6 3
FF STU EXTENDED 6 3 108C CMPY t 5 4 10EF STS INDEXED 6 3
1021 LBRN RELATIVE 5 4 108E LDY IMMED 4 4 10FE LOS EXTENDED 7 4
1022 LBHI 5(6) 4 1093 CMPD DIRECT 7 3 10FF STS EXTENDED 7 4
1023 LBLS 5(6) 4 109C CMPY 7 3 113F SWI/3 INHERENT 20 2
1024
1025
LBHS/LBCC
LBCS/LBLO
5(6) 4
5(6) 4
109E LOY
109F STY
I
DIRECT
6
6
3
3
1183 CMPU
118C CMPS
IMMED
IMMED
5
5
4
4
1026 LBNE 5(6) 4 10A3 CMPD INDEXED 7 3 1193 CMPU DIRECT 7 3
1027 LBEQ 5(6) 4 10AC CMPY 7 3 119C CMPS DIRECT 7 3
H'l28
1029
LBVC
LBVS
5(6) 4
5(6) 4
lllAE LOY
10AF STY
I
INDEXED
6
6
3
3
11A3 CMPU
l1AC CMPS
INDEXED
INOEXED 7
7 3
3
102A LBPL 5(6) 4 10B3 CMPD EXTENDED 8 4 11B3 CMPU EXTENDED 8 4
102B LBMI
102C LBGE
1020 LBLT RELATIVE
5(6) 4
5(6) 4
5(6) 4
10BC CMPY
10BE LOY
1eBF STY
I
EXTENDED 7
8
7
4
4
4
11BC CMPS EXTENDED 8 4

281
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

6809 ADDRESSING MODES

r- .---
INHERENT DIRECT EXTENDEC IMMEDIATE INDEXED' RELATIVE 53210
INSTRUCTION/
FORMS OP - II OP - II OP - II OP - II OP - II OP
_5
II DESCRIPTION HN !zlv
ABX 3A 3 1 B + X-- X
(UNSIGNED)
·.·..
ADC ADCA 99 4 2 B9 5 3 89 2 2 A9 4+ 2+ A+M+C--A tt ttt
AOCB 09 4 2 F9 5 3 C9 2 2 E9 4+ 2+ B+M+C--B tt ttt
ADD ADDA 9B 4 2 BB 5 3 8B 2 2 AB 4+ 2+ A+M--A tt ttt
ADDB DB 4 2 FB 5 3 pB 2 2 EB 4+ 2+ B + M-- B tt ttt
AOOO 03 6 2 F3 7 3 ~3 4 3 E3 ~+ 2+ o +·M:M + 1--+ 0 tt ttt
AND ANOA 94 4 2 B4 5 3 84 2 2 A4 4+ 2+ AAM--A •t to·
ANOB 04 4 2 F4 5 3 C4 2 2 E4 4+ 2+ BAM--B •t to·
ANOCC 1C 3 2 CC A IMM --+ CC 1
ASL ASLA 48 2 1 tttt 8
ASLB
ASL
58 2 1
08 6 2 78 7 3 68 6+ 2+
:}otilIIITII:l.-
M c b, bo
tttt
tttt
0 8
8
ASR ASRA 47 2 1 8 t t • t
ASR 57 2 1 A~O 8 t t • t
ASR 07 6 2 77 7 3 67 6+ 2+ ~ b7 bo c 8 t t • t
BCC BCC
LBCC
24 3 2 Branch C=O
105(6) 4 Long Branch
··..·..
· ..
24 C=O

BCS BCS
LBCS
25 3 2 Branch C = 1
10 5(6) 4 Long Branch
·. · ..
· .·..
25 C= 1
BEQ BEQ
LBEQ
27 3 2 Branch Z=O
105(6 4 Long Branch
27 Z=O
··..··....
BGE BGE
LBGE
2C 3 2 Branch ;,. Zero
105(6) 4 Long Branch
2C Zero
;,.
· .·· ....
·.
BGT BGT
LBGT
2E 3 2 Branch > Zero
10 5(6) 4 Long Branch >
2E Zero
·.··....
·.
BHI BHI
LBHI
22 3 2 Branch Higher
105(6) 4 Long Branch
· .··....
·.
22 Higher
BHS BHS 24 3 2 Branch Higher ·. ·..
LBHS
24
or Same
10 5(6) 4 Long Branch
Higher or Same
·.· ..
BIT BITA 95 4 2 B5 5 3 85 2 2 AS 4+ 2+ Bit Test A (M A A)
• t to·
• t to·
··..··....
BITB 05 4 2 F5 5 3 C5 2 2 E5 4+ 2+ Bit Test B (M f\ B)
2F 3 2 Branch ., Zero
BLE BLE
LBLE 105(6 4 Long Branch .,
2F Zero

262
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

INHERENT DIRECT EXTENDED MMEDIATE INDEXED' RELATIVE 5 ~ P D

INSTRUCTION I
FORMS PP - ;; OP - ;; OP - ;; OP ;; PP - -
;; OP _5 ;; DESCRIPTION H~ ZV
BlO BlO
lBlO
25 3 2 Branch lower
105(6) 4 long Branch
·..
··..·..
25 lower
BlS BlS 23 3 2 Branch lower · . · ..
· . · ..
or Same
lBlS 105(6) 4 long Branch
23 lower or Same
BlT BlT
lBlT
20 3 2 Branch < Zero
105(6) 4 long Branch
20 Zero
< · . ·· ....
·.
BMI BMI
lBMI
2B 3 2 Branch Minus
105(6) 4 long Branch
..
··.. ·· ..
2B Minus
BNE BNE
lBNE
26 3 2 Branch ZtO
10 5(6) 4 long Branch
26 ZtO
··.. ·..
·..
BPl BPl
lBPl
2A 3· 2 Branch Plus
10 5(6) 4 long Branch
· .·· ....
·.
2A , Plus
BRA BRA
lBRA
20 3
16 5
2 Branch Always
3 LongBranchAlways
··.. ·· ....
BRN BRN
lBRN
21 3
10 5
2 Branch Never
4 long Branch Never
··.. ·· ....
21

BSR BSR 80 7 2 Branch to · . · ..

lBSR 17 9
Subroutine
3 long Branch to
Subroutine
·.·..
BVC BVC
lBVC
28 3 2 Sranch V=O
10 5(6) 4 Long Branch
28 V=O
··.. ··....
BVS BVS
lBVS
29 3 2 Branch V = 1
105(6) 4 long Branch
29 V= 1
·· .. ·· ....
ClR ClRA 4F 2 1 O~A ·0 1 00
ClRB 5F 2 1 O~ B ·0 1 00
ClR OF 6 2 7F 7 3 6F ~+ 2+ O~M
• 0 1 00
CMP CMPA 91 4 2 B1 5 3 81 2 2 A1 4+ 2+ Compare M from A 8 t t t t
CMPB 01 4 2 F1 5 3 ~1 2 2 El ~+ 2+ Compare M from B 8 t t t t
CMPD 10 7 3 10 8 4 10 5 4 10 7+ 3+
A3
Compare M: M + 1
from 0
• t t t t
93 B3 83
CMPS 11
9C
7 3 11
BC
8 4 11
8C
5 4 11 7+ 3+
AC
Compare M: M + 1
from S
• t t t t
CMPU 11 7 3 11 8 4 11 5 4 11 7+ 3+ Compare M: M + 1 • t tt t
93 B3 83 A3 fromU
CMPX 9C 6 2 BC 7 3 8C 4 3 ~C 6+ 2+ Compare M: M + 1
• tttt
from X
CMPY 10
9C
7 3 10
BC
8 4 10
8C
5 4 10 7+ 3+
AC
Compare M: M + 1 •
from Y
tttt

263
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

INHERENT DIRECT EXTENDEC IMMEDIATE INDEXED' RELATIVE 53 2 1 b

INSTRUCTION/ I- 1-1-
FORMS OP - II OP II OP ~
II OP f.c OP
~-
II OP~
5
II DESCRIPTION
~

- HN ZVC
COM COMA 2 1 A-+A
43 • t to 1
COMB 2 1 B-+B
53 • t t01
COM 03 6 2 73 7 3 63 6+ 2+ M-+ M • t t01
CWAI 3C 20 2 CC t IMM -+CC; 1
Wait for Interrupt
DAA 19 2 1 Decimal Adjust A • t tot
DEC DECA 4A 2 1 A-1-+A
• t t t •
DECB 5A 2 1 B-1-+B
• t t t •
DEC OA 6 2 7A 7 3 6A 6+ 2" M-1-+M • t t t •
EOR EORA 98 4 2 B8 5 3 88 2 2 A8 4+ 2+ AvM-+A
• t to·
EORB D8 4 2 F8 5 3 C8 2 2 E8 4+ 2+ BVM-+B • t to·
EXG
INC
R1, R2
INCA
1E
4C
7
2
2
1
R1 .... R2'
A+1-+A
· . · ..
• t t t •
INCB 5C 2 1 B+1-+B
• t t t •
INC OC 6 2 7C 7 3 6C 6+ 2+ M+ l-+M
• t t t •
JMP OE 3 2 7E 4 3 6E 3+ 2+ EA' -+ PC ·. ··....
JSR
LO LDA
90
96
7
4
2 BD
2 B6 5
8 3
3 86 2 2 A6
AD 7+ 2+
4+ 2+
~umptoSubroutine
M-+A
·. to·
• t
LOB D6 4 2 F6 5 3 C6 2 2 E6 4+ 2+ M-+B to·
• t
LDD DC 5 2 FC 6 3 CC 3 3 EC 5+ 2+ M: M + 1 -+ D to·
• t
LDS 10 6 3 10 7 4 10 4 4 10 6+ 3+ M: M + 1 -+ S to·
• t
DE FE CE EE
LDU DE 5 2 FE 6 3 CE 3 3 EE 5+ 2+ M: M t 1 -+ U
• t to·
LDX 9E 5 2 BE 6 3 8E 3 3 AE 5+ 2+ M: M + 1 -+ X • t to·
LDY 10 6 3 10 7 4 10 4 4 10 6+ 3+ M: M + 1 -+ Y
• t to·
9E BE 8E AE

LEA LEAS
LEAU
32
33
4+
4+
2
2+
EA'-+
EA'-+
S
U ···...··....
LEAX
LEAY
48 2 1
30
31
4+
4+
2
2
EA'-+
EA'-+
X
Y ·. t ••
t ••
LSL LSLA • t t t t
LSLB 58 2 1 BD~~o
A} -
• t t t t
08 6 2 78 7 3 68 6+ 2+ M C b7 bo
LSL • t t t t

~
LSR LSRA 44 2 1 ·0 t • t
LSRB 54 2 1
M b7 bo c
0
} 0 -IIlIIIID-+ • 0 t • t
LSR 04 6 2 74 7 3 64 6+ 2+ • t
MUL 3D 11 1 AxB-+D
(Unsigned)
·.
• 0 t
t • 9

NEG NEGA 40 2 1 A+1-+A 8 t t t t

NEGB 50 2 1 8+1-+B 8 t t t t
NEG 00 6 2 70 7 3 60 6+ 2+ M+1-+M 8 t t t t
NOP 12 2 1
2 AA 4+ 2+
No Operation
AvM-+A
· . ·..
OR ORA 9A 4 2 BA 5 3 8A 2 • t to·
2 EA 4+ 2+ BVM-+B
ORB DA 4 2 FA 5 3 CA 2 • t to·
ORCC 1A 3 2 CC v IMM -+ CC 7
PSH PSHS 34 5+" 2 Push Registers on ·. ·..
PSHU 36 5+" 2
S Stack
Push Registers on
U Stack
· . ·..

264
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

INHERENT DIRECT EXTENDED MMEDIATE INDEXED' RELATIVE 53 21 0

INSTRUCTION/
OP OP -# lop # lop
- OP-_5
# -
DESCRIPTION 12111 C It.. I"
· .· ..
FORMS PP #~
# #
PUL PULS 35 5+ 2 Pull Registers from

PULU 37 5+ 2
S Stack
Pull Registers from
U Stack
·. ·..
··· ~~~
~ }UJ.-rnIIIIIlJ
~ ~ ~
ROL ROLA 49 2 1
ROLB 59 2 1 ~ ~ ~
ROL 09 6 2 79 7 3 69 6+ 2+ M C b7 .- bo ~ ~ ~
t• ~
~}LO--+d}J •• tt t • t
ROR RORA 46 2 1
1

RTI
RORB
ROR
56 2

3B /15 1
06 6 2 76 7 3 66 6+ 2+ M
Return From
·~ t • t
C b7 --+ bo

7
Interrupt
RTS 39 5 1 Return From
Subroutine
·. ·..
SBC SBCA 92 4 2 B2 5 3 82 2 2 A2 4+ 2+ A-M-C--+A 8 ~ ~ t t
SBCB 02 4 2 F2 5 3 C2 2 2 E2 4+ 2+ B-M-C--+B 8 t tt~
SEX 10 2 1 Sign Extend B
into A
• t to'
ST STA 97 4 2 B7 5 3 A7 4+ 2-+ A--+ M
• t to'
STB 07 4 2 F7 5 3 E7 4+ 2-+ B--+M
• t to.
STD DO 5 2 FD 6 3 ED 5+ 2+ 0--+ M: M + 1
• t ~0•
STS 10
OF
6 3 10
FF
7 4 10
EF
6+ 3+ S--+ M:M + 1
• t to'
STU OF 5 2 FF 6 3 EF 5+ 2+ U--+ M:M + 1
• t to'
STX 9F 5 2 BF 6 3 AF 5+ 2+ X--+ M: M + 1
•t ~0•
STY 10
9F
6 3 10
BF
7 4 10
AF 6+ 3+
Y--+ M:M + 1
• t to'

SUB SUBA 90 4 2 BO 5 3 80 2 2 AD 4+ 2+ A-M--+A 8 ttt ~

SUBB DO 4 2 FO 5 3 CO 2 2 EO 4+ 2+ B-M--+B 8 ~ t t t
SUBD 93 6 2 B3 7 3 83 4 3 A3 6+ 2 0- M: M + 1 --+ 0 •tttt
SWI SWI'
SWI2'
3F 19
10 20
1
2
Software Interrupt 1
Software Interrupt 2 ·. ·· ....
·.
SWI3'
3F
11 20
3F
2 Software Interrupt 3 · .·..
SYNC 13 ~2 1 Synchronize to
Interrupt
·.· ..
TFR
TST
R1, R2
TSTA
1F
40
7
2
2
1
R1--+ R2'
Test A
·. · .. ~ 0 •
•t
TSTB 50 2 1 Test B
• t to'
TST 00 6 2 70 7 3 60 6+ 2+ TestM • t to'

265
 MC6809 MICROPROCESSOR
INSTRUCTION SET SUMMARY

INDEXED ADDRESSING MODES

NON INDIRECT INDIRECT

Assembler Post-Byte + + Assembler Post-Byte + +
TYPE FORMS Form OP Code - II Form OPCode - II
CONSTANT OFFSET FROM R NO OFFSET ,R 1RR00100 0 0 [, R] hRR10100 3 0
5 BIT OFFSET n, R ORRnnnnn 1 0 defaults to 8-bit
8 BIT OFFSET n, R 1RR01oo0 1 1 [n, RI 1RR11000 4 1
16 BIT OFFSET n, R 1RR01001 4 2 [n, RI 1RR11oo1 7 2
ACCUMULATOR OFFSET FROM R A-REGISTER OFFSET A,R 1RR00110 1 0 [A, R] 1RR10110 4 0
B-REGISTER OFFSET B,R 1RROO101 1 0 [B, R] 1RR10101 4 0
D-REGISTER OFFSET D,R 1RR01011 4 0 [D,R] 1RR11011 7 0
AUTO INCREMENTIDECREMENT R INCREMENT BY 1 ,R+ 1RRooOOO 2 0 not allowed
INCREMENT BY 2 ,R++ 1RROOOO1 3 0 [, R++I 11RR10001 6 0
DECREMENT BY 1 .-R 1RROOO10 2 0 notal/owed
DECREMENT BY 2 ,--R 1RROOO11 3 0 [, --RI 1RR1oo11 6 0
CONSTANT OFFSET FROM PC 8 BIT OFFSET n, PCR 1XX01100 11 [n, PCRl 1XX11100 4 1

16 BIT OFFSET n, PCR 1XX01101 5 2 [n, PCR] 1XX11101 8 2

EXTENDED INDIRECT 16 BIT ADDRESS - - - - [n] 10011111 5 2
R = X, Y, U, or S
X = DON'T CARE

NOTES:
1. Given in the table are the base cycles and byte counts. To determine the total cycles and byte counts add the values
from the '6809 indexing modes' table.
2. R1 and R2 may be any pair of 8 bit or any pair of 16 bit registers.
The 8 bit registers are: A, B, CC, DP
The 16 bit registers are: X, Y, U, S, 0, PC
3. EA is the effective address.
4: The PSH and PUL instructions require 5 cycles plus 1 cycle for each byte pushed or pulled.
5. 5(6) means: 5 cycles if branch not taken, 6 cycles if taken.
6. SW1 sets I&F bits. SW12 and SW13 do not affect I&F.
7. Conditions Codes set as a direct result of the instruction.
8. Value of half-carry flag is undefined.
9. Special Case-Carry set if b7 is SET.

LEGEND:
OP Operation Code (Hexadecimal); Z Zero (byte)
Number of MPU Cycles; V OverflOW, 2's complement
II Number of Program Byles; C Carry from bit 7
+ Arithmetic Plus; t Test and set if true, cleared otherwise
Arithmetic Minus; Not Affected
Multiply CC Condition Code Register
M Complement of M; Concatenation
Transfer Into; v Logical or
H Half-carry from bit 3; 1\ Logical and
N Neg~tive (sign bit) v Logical Exclusive or

266
 Index

A B
Accumulator Branch
addressing, see Inherent addressing and miscellaneous instructions,
offset, indexed addressing, 32-34 93-114
branch instructions, 94-101
Accumulators A, B, D, 53-54 introduction, 93-94
Addressing miscellaneous instructions,
mode field, post byte, 24, 35-40 101-111
modes, 6809, 23-50 objectives, 94
direct addressing and direct page questions and answers, 111-114
register, 26-27 relative addressing, 27-30
inuexed addressing, 32-34 Bus
accumulator-offset, 34 status, pin-outs, 119-121
auto-increment/decrement, 34 timing, pin-outs, 121-123
constant-offset, 33
zero-offset, 33 C
indirect addressing, 40-43 Carry flag, CCR, 55
inherent, immediate, and Chip structure, 6809,20
extended addressing, 25-26 Concepts, fundamental 6809, 7 ~22
introduction, 23-24 chip structure, 20
objectives, 24 evolution and design philosophy,
post-byte, 24, 35-40 8-11
addressing mode field, 35-36 improvements, 11-19
5-bit offset field, 36-37 architectural, 11-14
indirect field, 36 hardware, 16-19
pointer register field, 36 software, 14-16
questions and answers, 45-50 introduction, 7
register addressing, 43-45 objectives, 7-8
relative addressing, 27-32 questions and answers, 20-22
branch relative, 27-30 Conditional branch, 96
PC relative, 30-32 Condition code register, 55-56
Applications and interfacing, 6809/ Constant-offset, indexed addressing,
6809E, 140-162 33
expanded 6809 system, 146 Control, pin-outs, 123-131
family, 6809, 150-152 D
introduction, 140-141 Data
microcomputer evaluation system, /address, pin-outs, 118-119
152-162 movement instructions and registers,
MEK68KPD,153-155 6809,51-72
MEK6809D4 board, 155-162 data movement instructions, 57-68
minimum 6809 system, 141-146 internal register format, 53-56
multiprocessor systems, 146-147 accumulators, A, B, D, 53-54
objectives, 141 condition code register, 55-56
remote data acquisition, 147-149 direct page register, 55
Architectural improvements, 6809, program counters, 55
11-14 S register, 54-55
Arithmetic, logic, and test instructions, U register, 54
73-92 X register, 54
arithmetic instructions, 74-79 Y register, 54
introduction, 73 introduction, 51-52
logic instructions, 80-82 objectives, 52
objectives, 74 questions and answers, 68-72
questions and answers, 89-92 Design philosophy and evolution, 8-11
test instructions, 82-88 Direct
Auto-increment/decrement, indexed addressing and the direct page
addressing, 34 register, 26-27

268
Direct-cont Intelligence, 93
page register, 55 Interfacing and applications, 6809/
6809E, 140-162
E expanded 6809 system, 146
Evolution and design philosophy, family, 6809, 150-152
6809,8-11 introduction, 140-141
Expanded 6809 system, 146 microcomputer evaluation system,
Extended addressing, 25-26 152-162
minimum 6809 system, 141-146
F multiprocessor systems, 146-147
Family, 6809, 150-152 objectives, 141
Fast interrupt request flags, CCR, 56 remote data acquisition, 147-149
5-bit offset field, post byte, 36-37 MEK68KPD, 153-155
Fundamental 6809 concepts, 7-22 MEK6809D4 board, 155-162
chip structure, 20 Internal register format, 53-56
evolution and design philosophy, accumulators, A, B, D, 53-54
8-11 condition code register, 55-56
improvements, 11-19 direct page register, 55
architectural, 11-14 program counters, 55
hardware, 16-19 S register, 54-55
software, 14-16 U register, 54
introduction, 7 X register, 54
objectives, 7-8 Y register, 54
questions and answers, 20-22 Interrupt flag, CCR, 56
H
L
Half-carry flag, CCR, 56 Logic, arithmetic, and test instructions,
Hardware improvements, 6809, 16-19 73-92
I arithmetic instructions, 74-79
Immediate addressing, 25 introduction, 73
Improvements, 6809, 11-19 logic instructions, 80-82
architecture, 11-14 objectives, 74
hardware, 16-19 questions and answers, 89-92
software, 14-16 test instructions, 82-88
Indexed addressing, 32-34 Long-branch instructions, 28
accumulator offset, 34
auto-increment/decrement, 34 M
constant-offset, 33 Microcomputer evaluation system,
zero-offset, 33 152-162
Indirect MEK68KPD, 153-155
addressing, 16,40-43 MEK6809D4 board, 155-162
field, post byte, 36 Minimum 6809 system, 141-146
Inherent addressing, 25 Miscellaneous and branch instructions,
Input and output signals, 6809/6809E, 93-114
115-139 branch instructions, 94-101
introduction, 115 introduction, 93-94
objectives, 116 miscellaneous instructions, 101-111
pin-outs objectives, 94
6809, 116-131 questions and answers, 111-114
bus status, 119-121 Multiprocessor systems, 146-147
bus timing, 121-123
control, 123-131 N
data/address, 118-119 Negative flag, CCR, 56
power/clock, 116-118
6809E, 131-135
questions and answers, 135-139 o
Instructions, data movement, see Data Op codes, 63, 64
movement instructions Output and input signals, 6809/6809E,
Instruction set 115-139
6809/6809E, 163-192 introduction, 115
summary, MC6809, 256-267 objectives, 116

269
Output and input signals, 6809/ Registers and data movement
6809E-cont instructions-cont
pinouts U register, 54
6809, 116-131 X register, 54
bus status, 119-121 Y register, 54
bus timing, 121-123 introduction, 51-52
control, 123-131 objectives, 52
dataladdress, 118-119 questions and answers, 68-72
power/clock, 116-118 Relative addressing, 27-32
6809E, 131-135 branch relative, 27-30
questions and answers, 135-139 PC relative, 30-32
p Remote data acquisition, 147-149
PC relative addressing, 30-32 S
Peripheral interface adapter (PIA), Short branching, 28
6820/6821, 192-210 Software improvements, 6809, 14-16
functional description, 6821, Specification sheets, 211-255
192-193 MC6809/MC68A09/MC68B09,
initialization and servicing, 200-206 211-238
interfacing and addressing, 196-200 MC6809E/MC68A09E/
pin assignments, 6820/6821, MC68B09E, 239-240
193-196 MC6829, 241-242
questions and answers, 206-210 MC6839,243
Pin-outs MC6842,244-245
6809, 116-131 MEK6809EAC, 246-247
bus MEK6809D4/MEK68KPD, 248-255
status, 119-121 S register, 54-55
timing, 121-123 Stack processor, 60
control, 123-131
data/address, 118-119 T
power/clock, 116-118
6809E, 131-135 Test, arithmetic, and logic instructions,
Pointer register field, post byte, 36 73-92
Post byte, 24, 35-40 arithmetic instructions, 74-79
addressing mode field, 35-36 introduction, 73
5-bit offset field, 36-37 logic instructions, 80-82
indirect field, 36 objectives, 74
pointer register field, 36 questions and answers, 89-92
Power/clock, pin-outs, 116-118 test instructions, 82-88
Program Twos complement overflow Hag, 55-56
counter, 55
position independence, 9 U
re-entrancy, 9 Unconditional branch, 94-95
U register, 54
R
Register addressing, 43-45 x
Registers and data movement X register, 54
instructions, 51-72
data movement instructions, 57-68 y
internal register format, 53-56 Y register, 54
accumulators A, B, D, 53-54
condition code register, 55-56 z
direct page register, 55 Zero
program counter, 55 Hag, CCR, 56
S register, 54-55 -offset, indexed addreSSing, 33

270
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 The Blacksburg Group
According to Business Week magazine (Technology July 6, 1976) large scale integrated circuits
or LSI "chips" are creating a second industrial revolution that will quickly involve us all. The
speed of the developments in this area is breathtaking and it becomes more and more difficult to
keep up with the rapid advances that are being made. It is also becoming difficult for newcomers
to "get on board."

It has been our objective, as The Blacksburg Group, to develop timely and effective educational
materials and aids that will permit students, engineers, scientists and others to quickly learn how
to apply new technologies to their particular needs. We are doing this through a number of
means, textbooks, short courses, and through the development of educational "hardware" or
training aids.

Our group members make their home in Blacksburg, found in the Appalachian Mountains of
southwestern Virginia. While we didn't actively start our group collaboration until the Spring
of 1974, members of our group have been involved in digital electronics, minicomputers and
microcomputers for some time.

Some of our past experiences and on-going efforts include the following:

-The development of the Mark-S computer, an SOOS-based device that was featured in Radio-
Electronics magazine in 1974, and generally recognized as the first widely available hobby
computer. We have also designed several SOSO-based computers, including the Mini·Micro De·
signer (MMD·1). More recently we have been working with SOS5-based computers and the TRS-SO.

-The Blacksburg Continuing Education Series™ covers subjects ranging from basic electronics
through microcomputers, operational amplifiers, and active filters. Test experiments and examples
have been provided in each book. We are strong believers in the use of detailed experiments and
examples to reinforce basic concepts. This series originally started as our Bugbook series and many
titles are now being translated into Chinese, Japanese, German and Italian.

-We have pioneered the use of small self-contained computers in hands-on courses aimed at
microcomputer users. The solderless breadboarding modules developed for use in circuit design
and development make it easy for people to set up and test digital circuits and computer inter·
faces. Some of our technical products are marketed by Group Technology, ltd., Check, VA 24072,
USA. (703) 651·3153.

-Our short course programs have been presented throughout the world, covering digital elec-
tronics through TRS-SO computer interfacing. Programs are offered through the Blacksburg Group
and the Virginia Tech Extension Division. Each course offers a mix of lectures and hands-on
laboratory sessions. Courses are presented on a regular basis in Blacksburg, and at various times
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For additional information about course offerings, we encourage you to write or call Dr. Chris
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Mr. David Larsen is on the faculty of the Department of Chemistry at Virginia Polytechnic Insti-
tute and State University. Dr. Jonathan Titus and Dr. Christopher Titus are with The Blacksburg
Group, Inc., all of Blacksburg, Virginia.