REN ASI4U-Datasheet DST 20160126
REN ASI4U-Datasheet DST 20160126
REN ASI4U-Datasheet DST 20160126
indication modes
• Several data pre-processing functions, including Extended Power Application with IR-Addressing Option
+24V
•
U5R
Clock watchdog for high system security
LED1
LED2
Related Products 0V IRD
GND
• SAP5 Universal AS-Interface IC +0V
DATA- OUT
POWER- ON
SHUT- DOWN
RESET
U5RD
CLK
ASI4U/ASI4U-E/ASI4U-F
UOUT
INPUT DI(3:0)
STAGE
DATA-IN
P - PULSE
RECEIVE I/O
ASIP N - PULSE RESET STAGE DSR
DATA- STRB
REC- RESET DIGITAL
LOGIC PARAM OUTPUT
PST
STRB STAGE
SEND-D
ASIN
TRANSMIT
PARAM
SEND- SBY
IN
THERMAL / INPUT
PWR_FAIL
LOGIC
FAULT_IN
OVER- LOAD STAGE
OUT
LED
AC
PARAM
OVERLOAD
OUT
PROTECTION OVER- HEAT
Typical Applications IRD_IN P(3:0)
CMOS AC OUTPUT DIG ANA OUTPUT
INPUT CURRENT
•
STAGE INPUT STAGE
AS-i Master Modules STAGE INPUT
STAGE
Ordering Information
RoHS Minimum
Ordering Code Type Package Ta [°C] Packaging
Conform Order
ASI4UE-G1-ST Standard SSOP28 -25 to 85 Y Tube (47 parts/tube) 470
ASI4UE-G1-SR Standard SSOP28 -25 to 85 Y Tape & Reel (1500 parts/reel) 1500
ASI4UE-G1-SR-7 Standard SSOP28 -25 to 85 Y Tape & Reel 7” (500 parts/reel) 500
ASI4UE-G1-MT Master SSOP28 -25 to 85 Y Tube (47 parts/tube) 470
ASI4UE-G1-MR Master SSOP28 -25 to 85 Y Tape & Reel (1500 parts/reel) 1500
ASI4UE-E-G1-ST Standard SOP28 -25 to 105 Y Tube (27 parts/tube) 270
ASI4UE-E-G1-SR Standard SOP28 -25 to 105 Y Tape & Reel (1000 parts/reel) 1000
ASI4UE-F-G1-ST Standard SSOP28 -40 to 85 Y Tube (47 parts/tube) 470
ASI4UE-F-G1-SR Standard SSOP28 -40 to 85 Y Tape & Reel (1500 parts/reel) 1500
Contents
1 Important Safety Advice ................................................................................................................................... 7
1.1. AS-i-Safety Applications ............................................................................................................................ 7
1.2. Repair of ASI-Safety Modules ................................................................................................................... 7
2 General Device Specifications ......................................................................................................................... 8
2.1. Absolute Maximum Ratings (Non-Operating) ............................................................................................ 8
2.2. Operating Conditions ............................................................................................................................... 10
2.3. Quality Standards .................................................................................................................................... 10
3 Basic Functional Description .......................................................................................................................... 11
3.1. Functional Block Diagram ........................................................................................................................ 11
3.2. General Operational Modes .................................................................................................................... 13
3.3. Slave Mode .............................................................................................................................................. 14
3.3.1. AS-Interface Communication Channel ............................................................................................. 14
3.3.2. IRD Communication Channel ........................................................................................................... 15
3.3.3. Parameter Port Pins .......................................................................................................................... 15
3.3.4. Data Port Pins ................................................................................................................................... 16
3.3.5. Data Input Inversion .......................................................................................................................... 16
3.3.6. Data Input Filtering ............................................................................................................................ 16
3.3.7. Fixed-Data Output Driving ................................................................................................................ 16
3.3.8. Synchronous Data I/O Mode............................................................................................................. 17
3.3.9. 4 Input / 4 Output Processing in Extended Address Mode ............................................................... 17
3.3.10. AS-i Safety Mode .............................................................................................................................. 17
3.3.11. Enhanced LED Status Indication ...................................................................................................... 18
3.3.12. Communication Monitor/Watchdog ................................................................................................... 18
3.3.13. Write Protection of ID_Code_Extension_1 ....................................................................................... 18
3.3.14. Summary of Master Calls .................................................................................................................. 18
3.4. Master Mode ............................................................................................................................................ 21
3.5. EEPROM ................................................................................................................................................. 22
4 Detailed Functional Description...................................................................................................................... 25
4.1. AS-i Receiver ........................................................................................................................................... 25
4.2. AS-i Transmitter ....................................................................................................................................... 26
4.3. Addressing Channel Input IRD ................................................................................................................ 26
4.3.1. General Slave Mode Functionality .................................................................................................... 26
4.3.2. AC Current Input Mode ..................................................................................................................... 28
4.3.3. CMOS Input Mode ............................................................................................................................ 28
4.3.4. Master, Repeater, and Monitor Modes ............................................................................................. 29
4.4. Digital Inputs – DC Characteristics .......................................................................................................... 30
4.5. Digital Outputs - DC Characteristics ........................................................................................................ 30
List of Figures
Figure 2.1 Ptot = f(Ta) ............................................................................................................................................ 9
Figure 3.1 ASI4U Functional Block Diagram ..................................................................................................... 11
Figure 3.2 Conventional Application for AS-i IC with One External Coil ............................................................ 15
Figure 3.3 Application for AS-i IC with Two External Coils ................................................................................ 15
Figure 3.4 Data Path in the Master, Repeater, and Monitor Modes .................................................................. 21
Figure 4.1 Simplified Receiver Comparator Threshold Setup ........................................................................... 25
Figure 4.2 Addressing Channel Input (IRD), Photo-Current Waveforms ........................................................... 28
Figure 4.3 Timing Diagram Parameter Ports P[3:0] and PST ............................................................................ 32
Figure 4.4 Timing Diagram Data Ports DO[3:0], DI[3:0] and DSR..................................................................... 35
Figure 4.5 Input Path at Data Port ..................................................................................................................... 35
Figure 4.6 Principles of Input Filtering ............................................................................................................... 36
Figure 4.7 Principle of AS-i Cycle Input Filtering (Example for Slave with Address 1) ...................................... 37
Figure 4.8 Flowchart – Input DI3, DI2, and DI1 in Safety Mode ........................................................................ 43
Figure 4.9 Flowchart – Input DI0 in Safety Mode .............................................................................................. 44
Figure 4.10 Flowchart – Data_Exchange_Disable .............................................................................................. 45
Figure 4.11 Power-On Behavior (All Modes) ....................................................................................................... 50
Figure 4.12 Timing Diagram External Reset via DSR ......................................................................................... 51
Figure 4.13 Manchester-II-Coded Modulation Principle ...................................................................................... 54
Figure 5.1 Standard Application Circuit with Bi-directional Data I/O ................................................................. 61
Figure 5.2 Extended Power Application Circuit with IR-Addressing Option ...................................................... 62
Figure 5.3 ASI4U Master/Repeater Mode Application ....................................................................................... 63
Figure 6.1 ASI4U Package Pin Assignment ...................................................................................................... 65
Figure 6.2 SOP28 Package Outline Dimensions ............................................................................................... 66
Figure 6.3 SSOP28 Package Outline Dimensions ............................................................................................ 67
Figure 6.4 Package Marking .............................................................................................................................. 68
List of Tables
Table 2.1 Absolute Maximum Ratings ................................................................................................................ 8
Table 2.2 Operating Conditions ........................................................................................................................ 10
Table 2.3 Crystal Frequency ............................................................................................................................. 10
Table 3.1 Assignment of Operational Modes.................................................................................................... 14
Table 3.2 ASI4U Master Calls and Related Slave Responses ......................................................................... 19
Table 3.3 Signal Assignments for Data I/O and Parameter Port Pins .............................................................. 21
Table 3.4 EEPROM Contents ........................................................................................................................... 22
Table 4.1 Receiver Parameters ........................................................................................................................ 25
Table 4.2 Transmitter Current Amplitude.......................................................................................................... 26
Table 4.3 IRD AC Current Input Parameters .................................................................................................... 28
Table 4.4 IRD Current/Voltage Mode Switching ............................................................................................... 29
Table 4.5 IRD CMOS Input Mode Levels ......................................................................................................... 29
Table 4.6 Polarity of Manchester-II Signal at IRD in Master Mode................................................................... 29
Table 4.7 DC Characteristics of Digital High Voltage Input Pins ...................................................................... 30
Table 4.8 DC Characteristics of Digital High Voltage Output Pins ................................................................... 30
Table 4.9 Timing Parameter Port ...................................................................................................................... 31
Table 4.10 Parameter Port Output Signals in Master, Repeater, and Monitor Modes ....................................... 33
Table 4.11 Timing Data Port Outputs ................................................................................................................. 34
Table 4.12 Data Input Filter Time Constants ...................................................................................................... 36
Table 4.13 Input Filter Activation by Parameter Port Pin P1 .............................................................................. 37
Table 4.14 EEPROM Configuration for Different Input Modes ........................................................................... 38
Table 4.15 Activation States of Synchronous Data IO Mode ............................................................................. 39
Table 4.16 Meaning of Master Call Bits I0, I1, I2, and I3 in Ext_Addr_4I/4O_Mode .......................................... 41
Table 4.17 Control Signal Inputs in the Master, Repeater, and Monitor Modes................................................. 45
Table 4.18 Error Signal Outputs in Monitor Mode .............................................................................................. 45
Table 4.19 Power Failure Detection at FID (Master Mode and Monitor Mode) .................................................. 46
Table 4.20 LED Status Indication ....................................................................................................................... 48
Table 4.21 Polarity of Manchester-II Signal at LED1 .......................................................................................... 49
Table 4.22 Oscillator Pin Parameters ................................................................................................................. 49
Table 4.23 IC Initialization Times ........................................................................................................................ 50
Table 4.24 Power-On Reset Threshold Voltages ............................................................................................... 50
Table 4.25 Timing of External Reset .................................................................................................................. 51
Table 4.26 Status Register Content .................................................................................................................... 56
Table 4.27 Properties of Voltage Output Pins UOUT and U5R .......................................................................... 59
Table 4.28 AS-Interface Bus Load Properties .................................................................................................... 59
Table 4.29 CAP Pin Parameters ......................................................................................................................... 60
Table 4.30 Shutdown Temperature .................................................................................................................... 60
Table 6.1 ASI4U Package Pin List .................................................................................................................... 64
Table 6.2 SOP28 Package Dimensions (mm) .................................................................................................. 66
Table 6.3 SSOP28 Package Dimensions (mm) ............................................................................................... 67
Important Safety Notice: This IDT product is intended for use in commercial applications.
! Applications requiring extended temperature range, unusual environmental requirements, or
high-reliability applications, such as military, medical life-support, or life-sustaining equipment,
are specifically not recommended without additional mutually agreed upon processing by IDT
for such applications.
0.9
0.8
0.7
Ptot / W
0.6
0.3
0.2
-25 0 25 Ta / °C 50 75 100
The ASI4U/ASI4U-E/ASI4U-F supports an integrated clock watchdog. If no crystal or clock oscillation is recog-
nized for 150µs, the IC generates a RESET event until clock oscillation is available. More detailed oscillator pin
definitions can be found in section 4.10.
DATA- OUT
POWER- ON
SHUT- DOWN
RESET
U5RD
CLK
ASI4U/ASI4U-E/ASI4U-F
UOUT
INPUT DI(3:0)
STAGE
DATA-IN
P - PULSE
RECEIVE I/O
ASIP N - PULSE RESET STAGE DSR
DATA- STRB
REC- RESET DIGITAL
LOGIC PARAM OUTPUT
PST
STRB STAGE
SEND-D
ASIN
TRANSMIT
PARAM
SEND- SBY
IN
THERMAL / INPUT
PWR_FAIL
LOGIC
FAULT_IN
PARAM
OVERLOAD
OUT
PROTECTION OVER- HEAT
IRD_IN P(3:0)
CMOS AC OUTPUT DIG ANA OUTPUT
INPUT CURRENT STAGE STAGE
STAGE INPUT INPUT
STAGE
AGND LGND
Following device functions are associated with the different blocks of the IC:
RECEIVE The RECEIVE block converts the analog telegram waveform from the AS-i bus to a digital pulse-
coded signal that can be processed further by a digital UART circuit.
The RECEIVE block is directly connected to the ASIP and ASIN pins, which connect to the AS-i
line. It converts the differential AS-i telegram to a single-ended signal and removes the DC offset
by high-pass filtering. To adapt quickly to changing signal amplitudes in telegrams from different
network users, the amplitude of the first telegram pulse is measured by a 3-bit flash ADC and the
threshold of a positive and a negative comparator is set accordingly to about 50% of the mea-
sured level. The comparators generate the P-pulse and N-pulse signals.
TRANSMIT The TRANSMIT block transforms a digital response signal to a correctly shaped send current
signal that is applied to the AS-i bus. Due to the inductive network behavior of the network, the
changing send current induces voltage pulses on the network line that overlay the DC operating
voltage. The voltage pulses must have sin²-wave shapes; therefore the send current shape must
follow the integral of the sin²-wave function.
DIGITAL LOGIC The DIGITAL LOGIC block contains the UART, Main State Machine, EEPROM memory and
other control logic. EEPROM write access and other I/O operations of the Main State Machine
are supported in Slave Mode only (see description of general IC operational modes below). In
Master Mode, the IC is basically equivalent to a physical layer transceiver.
If Slave Mode is activated, the UART demodulates the received telegrams, verifies telegram
syntax and timing, and controls a register interface to the Main State Machine. After reception of
a correct telegram, the UART generates appropriate Receive Strobe signals that tell the Main
State Machine to start further processing. The Main State Machine decodes the telegram
information and starts respective I/O processes or EEPROM access. A second register interface
is used to send data back to the UART for construction of a telegram response. The UART
modulates the response data into a Manchester-II-coded bit stream that is used to control the
TRANSMIT unit.
ELECTRONIC INDUCTOR The ELECTRONIC INDUCTOR block is basically a gyrator circuit. It provides an
inductive behavior between the IC’s UIN and UOUT pins while the inductance is controlled by the
capacitor on the CAP pin. The inductor decouples the power regulator of the IC as well as the
external load circuit from the AS-i bus, and this prevents cross talk or switching noise from
disturbing the telegram communication on the bus.
The AS-Interface Complete Specification V3.0 describes the input impedance behavior of a slave
module by an equivalent circuit that consists of a resistance (R), an inductance (L), and a
capacitance (C) in parallel. For example, a slave module in Extended Address Mode must have
R > 13.5kΩ, L > 13.5mH and C < 50pF. The electronic inductor of the ASI4U/ASI4U-E/ASI4U-F
delivers values that are well within the required ranges for output currents up to 55mA. More
detailed parameters can be found in section 4.18.2.
The electronic inductor requires an external capacitor of at least 10µF at the UOUT pin for
stability.
POWER SUPPLY The POWER SUPPLY block consists of a bandgap-referenced 5V regulator and other
reverence voltage and bias current generators for internal use. The 5V regulator requires an
external capacitor at pin U5R of at least 1µF for stability. It can source up to 4mA for external use;
however, the power dissipation and the resulting device heating become a major concern if too
much current is drawn from the regulator.
OSCILLATOR The OSCILLATOR block supports direct connection to 8.000 MHz or 16.000 MHz crystals with a
dedicated load capacity of 12pF and parasitic pin capacities of up to 8pF. The IC automatically
detects the oscillation frequency of the connected crystal and controls the internal clock generator
circuit accordingly.
After power-on reset, the IC is set to 16.000 MHz operation by default. After approximately
200µs, it will either switch to 8.000 MHz operation or remain in the 16.000 MHz mode. The
frequency detection is active until the first AS-i telegram has been successfully received in order
to ensure that the IC has found the correct clock frequency setting. The detection result is locked
thereafter to increase resistance against burst or other interferences.
The oscillator unit also contains a clock watchdog circuit that can generate an unconditional IC
reset if there has been no clock oscillation for more than approximately 20µs. This is to prevent
the IC from unpredictable behavior if a clock signal is no longer available.
THERMAL/OVERLOAD PROTECTION The IC is self-protected against overheating and short-circuiting of
the UOUT pin toward IC ground.
If the silicon die temperature rises above approximately 140°C for more than 2 seconds, the IC
detects overheating, switches off the electronic inductor, performs an IC reset, and sets all analog
blocks to power down mode. Although the 5V regulator is turned off in this state, there will still
remain a voltage of approximately 3V to 3.5V available at U5R that is derived from the internal
start circuitry. The overheating protection state can only be de-activated by power-cycling the
AS-i voltage.
Short-circuiting the UOUT pin toward IC ground causes the same IC behavior as overheating.
IRD CMOS / AC CURRENT INPUT The IRD pin is the input for the additional addressing channel in Slave
Mode (see section 3.2 for a description of general IC operational modes) or the direct AS-i
transmitter input in Master Mode. In Slave Mode, the IRD pin can be operated either in CMOS
Mode or AC Current Input Mode. The latter is provided for direct connection of a photodiode.
More detailed information can be found in section 4.3.
FID DIGITAL / ANALOG STAGE The FID pin can be set to the Digital CMOS Mode or Analog Voltage Input
Mode. In Slave Mode, it is set to CMOS operation; in Master Mode, it works in Analog Mode and
functions as the input for the power fail comparator.
INPUT STAGE All digital inputs, except the oscillator pins, have high voltage capabilities and partial Schmitt
trigger and pull-up features. For more details, see section 4.4.
OUTPUT STAGE All digital output stages, except for the oscillator pins, have high voltage capabilities and are
implemented as NMOS open-drain buffers. Each pin can sink up to 10mA of current.
In Slave Mode, the IC operates as a full-feature AS-i slave IC according to the AS-Interface Complete
Specification V3.0.
In Master Mode, the IC translates a digital output signal from the master control logic (e.g., a programmable logic
controller or microcontroller) to a correctly shaped, analog AS-i pulse sequence and vice versa. Every AS-i
telegram received is checked for consistency with the AS-Interface communication protocol specifications, and if
no errors were found, an appropriate Receive Strobe signal is generated.
Master Mode and Monitor Mode differ in the kind of telegrams signaled. In Master Mode, a single Receive Strobe
signal is provided validating every correctly received Slave Response; in Monitor Mode, two different Receive
Strobe signals are available indicating every correctly received Master and Slave telegram separately. The
Monitor Mode is intended for use in intelligent slaves and bus monitors that provide their own telegram decoding
mechanisms but do not check for correct telegram timing or syntax.
The Repeater Mode is specifically provided for AS-i bus repeater applications.
Figure 3.2 Conventional Application for AS-i IC Figure 3.3 Application for AS-i IC with Two
with One External Coil External Coils
ASI+ ASI+
AS-i AS-i
Slave Slave
Z1 IC Load Z1 IC Load
GND GND
ASI- ASI-
Z2 Z2
Important note regarding full compliance with the AS-Interface Complete Specification: In order to achieve full
compliance to the AS-Interface Complete Specification, the Program_Mode_Disable flag must be set by the
manufacturer of AS-i slave modules during the final manufacturing and configuration process and before an
AS-i slave device is delivered to field application users.
Write Extented ID
WID1 0 1 0 0 0 0 0 0 ID3 ID2 ID1 ID0 PB 1 0 0 0 0 0 0 1
Code_1
0
Delete Address DELA 0 1 A4 A3 A2 A1 A0 0 0 0 0 PB 1 0 0 0 0 0 0 1
Sel
1
Reset Slave RES 0 1 A4 A3 A2 A1 A0 1 1 0 0 PB 1 0 0 1 1 0 0 1
~Sel
0
Read IO Configuration RDIO 0 1 A4 A3 A2 A1 A0 1 0 0 0 PB 1 0 IO3 IO2 IO1 IO0 PB 1
Sel
0
Read ID Code RDID 0 1 A4 A3 A2 A1 A0 1 0 0 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Sel
0
Read ID Code_1 RID1 0 1 A4 A3 A2 A1 A0 1 0 1 0 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Sel
0
Read ID Code_2 RID2 0 1 A4 A3 A2 A1 A0 1 0 1 1 PB 1 0 ID3 ID2 ID1 ID0 PB 1
Sel
1
Read Status RDST 0 1 A4 A3 A2 A1 A0 1 1 1 0 PB 1 0 S3 S2 S1 S0 PB 1
~Sel
Note: In Extended Address Mode, the "Select Bit" defines whether the A-Slave or B-Slave is being addressed. Depending on the type of master
call, bit I3 carries the select bit information (Sel = A-Slave) or the inverted select bit information (~Sel = B-Slave).
111 Sel=1 Rd_IO_Cfg <I3:I0> Read_ID <I3:I0> Read_ID_1<I3:I0> Read_ID_2 <I3:I0> Reset_Slave 0x6 Rd_Status <S3:S0>
Figure 3.4 Data Path in the Master, Repeater, and Monitor Modes
Master Mode Slave Mode, AS-i Channel Slave Mode, IRD Addressing Channel
LED1
ASI Transmitter LED Output (RX)
Master Mode, Repeater Mode, and Monitor Mode differ from each other in the kind of signals that are available at
the data I/O and parameter port pins of the IC. The signal assignments in Table 3.3 are provided:
Table 3.3 Signal Assignments for Data I/O and Parameter Port Pins
PIN MASTER MODE REPEATER MODE MONITOR MODE
P0 Receive Clock Hi-Z Receive Clock
P1 Power Fail Hi-Z Power Fail
P2 Receive Strobe – Slave Telegram Hi-Z Receive Strobe – Slave Telegram
P3 Hi-Z Hi-Z Receive Strobe – Master Telegram
DI0 Inverting of IRD input signal. If these two are on different levels, the IRD input signal is inverted before further
DI1 processing; otherwise it is directly forwarded to the UART.
DI2 Inverting of LED output signal. If these two inputs are on different levels, the LED output signal is inverted after
DI3 processing; otherwise it is directly forwarded to the LED1 output.
More detailed signal descriptions can be found in sections 4.6, 4.7, and 4.12.
3.5. EEPROM
The ASI4U provides an on-chip EEPROM with typical write times of 12.5ms and read times of 110ns. For security
reasons, the memory area is structured in two independent data blocks and a single bit Security flag.
The data blocks are named the “User Area” and “Firmware Area.” The Firmware Area block contains all
manufacturing-related configuration data (e.g., selection of operational modes, ID codes). It can be protected
against undesired data modification by setting the Program_Mode_Disable flag to 1.
The User Area contains only data that is relevant for changes in the final application (i.e., field installation of the
slave module). The environment, where modifications of the user data might become necessary, can sometimes
be rough and unpredictable. In order to ensure a write access cannot result in an undetected corruption of
EEPROM data, additional security is provided when programming the User Area.
Any write access to the User Area (by the calls Address_Assignment or Write_ID_Code1) is accompanied by two
write steps to the Security flag, one before and one after the actual modification of user data.
The following procedure is executed when writing to the User Area of the EEPROM:
1. The Security flag is programmed to 1.
2. The content of the Security flag is read back, verifying it was programmed to 1.
3. The user data is modified.
4. A read back of the written data is performed.
5. If the read back has proven successful programming of the user data, the Security flag is
programmed back to 0.
6. The content of the Security flag is read back, verifying it was programmed to 0.
In addition to a read out of the data areas, the Security flag of the EEPROM is also read and evaluated during IC
initialization. If the value of the Security flag equals 1 (e.g., due to an undesired interruption of a User Area write
access), the entire User Area data is treated as corrupted and the Slave Address is set to 0HEX in the
corresponding volatile shadow registers during initialization. Then the programming of the User Area data can be
repeated.
VLSIGon
The IC determines the
amplitude of the first VSIG / 2
negative pulse of the
AS-i telegram. This
amplitude is asserted First negative
to be VSIG / 2. pulse of the
AS-i telegram
To support high symmetry extended power applications as shown in Figure 5.2, the transmitter is designed to
allow input voltages different from IC ground at the ASIN pin. The limits given in Table 2.2 apply. When the
transmitter is turned on, the receiver is turned off to reduce the power consumption.
IRD
Input
Current
MAX
I IRD_Amplitude
MIN
MAX
IIRD_Amplitude I IRD_Offset
Time
Note: The complemented definition was chosen to retain backward compatibility to A²SI-based AS-i Master
designs.
Note: PST and LED2 are inputs for test purposes only.
tSetup tPST
PST
Data remains constant Hi-Z if Multiplex_Parameter
if Multiplex_Parameter flag is set
flag is not set
Keep stable
thold
min max
tPI-latch
If the P1_Filter_Activation flag is set in the EEPROM, the activation of the data input filters depends on the value
of the Parameter Port signal P1. The following coding applies:
INPUT VALUE AT P1 DATA INPUT FILTER FUNCTION
LOW level (=0) Activated
HIGH level (=1) Deactivated
Table 4.10 Parameter Port Output Signals in Master, Repeater, and Monitor Modes
PIN MASTER MODE REPEATER MODE MONITOR MODE
P0 Receive Clock Hi-Z Receive Clock
P1 Power Fail Hi-Z Power Fail
P2 Receive Strobe – Slave Telegram Hi-Z Receive Strobe – Slave Telegram
P3 Hi-Z Hi-Z Receive Strobe – Master Telegram
Receive Clock is provided to simplify external processing of Manchester-II-coded output data at the LED1 pin.
The availability of a new AS-i telegram bit at LED1 is signaled by a rising edge of the receive clock so that the
received data can simply be clocked into a shift register. The output signal is active HIGH.
Power Fail signals a breakdown of the AS-i supply voltage. The output signal is active HIGH. For further
information regarding the Power Fail function, refer to section 4.8.
Receive Strobe – Slave Telegram is generated after every correctly received AS-i slave telegram. The output
signal is active HIGH.
Receive Strobe – Master Telegram is generated after every correctly received AS-i master telegram. The output
signal is active HIGH.
The generated pulse width is 1.0µs for both Receive Strobe signals at the output drivers (Hi-Z time). The resulting
signal pulse width depends on the external pull-up resistor and the load circuit.
Figure 4.4 Timing Diagram Data Ports DO[3:0], DI[3:0] and DSR
tSetup tDSR
DSR
Data remains constant Hi-Z if Multiplex_Data
if Multiplex_Data flag is set
flag is not set
Keep stable
thold
min max
tDI-latch
Any IC reset or the reception of a Delete_Address call changes the Data Output Register to FHEX and forces the
data output drivers to a high impedance state. Simultaneously, a Data Strobe is generated, having the same tsetup
timing and tDSR pulse width as is used when new output data is driven. All Data Port operations as well as the
generation of a slave response to Data_Exchange (DEXG) requests depend on the value of the
Data_Exchange_Disable flag. It becomes set during IC reset or after a Delete_Address call prohibiting any data
port activity after IC initialization or address assignment, as long as the external circuitry was not pre-conditioned
by dedicated parameter output data. The Data_Exchange_Disable flag is cleared while processing a
Write_Parameter (WPAR) request. Consequently the AS-i master must send a WPAR call in advance of the first
Data_Exchange (DEXG) request in order to enable Data Port operation at the slave.
Input
Signal
Filter
Output
If AS-i Cycle Mode is selected, a new input value is returned to the master if equal input data has been sampled
for two consecutive Data_Exchange cycles. As long as the condition is not true, previous valid data is returned.
To suppress undesired input data validation in the case of immediately repeated Data_Exchange calls (e.g., AS-i
Masters immediately repeat one Data_Exchange request if no valid slave response was received on the first
request), input data sampling is blocked for 256µs (-6.25%) after every sampling event in AS-i Cycle Mode.
Figure 4.7 Principle of AS-i Cycle Input Filtering (Example for Slave with Address 1)
Input
Signal
Sampling Point
The DI_Filter_Configuration register provides channel-selective enabling of input filters; just as the
DI_Invert_Configuration register allows individual inverting of the four Data Port input channels. Again, the index
of the DI channel corresponds to the bit position within the register; e.g., data at input channel DI0 is filtered if
bit 0 of the DI_Filter_Configuration register is set and similarly input channel DI3 is filtered if bit 3 is set.
In general, the Data Input Filters become active if the corresponding bit in the DI_Filter_Configuration Register is
set.
• They are initialized with “0” and the filter timer is reset after the initialization phase of the IC. (The first is
because an AS-i Master interprets data inputs at “0” to be inactive.)
• If the P1_Filter_Activation flag is set to “1,” the filters will also start to run after the initialization phase;
however, the data to construct the slave response is taken from either the actual Data Input values or the
filtered values, depending on the state of Parameter Port P1.
If the IC is operated in Parameter Multiplex Mode (see descriptions in section 4.6.1 and subsequent sections)
while the P1_Filter_Activation flag is set, the Parameter Multiplex Mode remains disabled for parameter port pin
P1. This is to avoid erroneous deactivation of the input filters if no external driver is connected.
Input data inverting and input data filtering are independent features that can be combined as required by the
application. Programming the following EEPROM flags or registers activates them:
The Parameter Port signal P2 is sampled at the rising edge of the Data Strobe (LOW/HIGH transition) signal
to determine the Data I/O behavior at the next Data Output event.
If the IC is operated in Parameter Multiplex Mode (see section 4.6.1) while the Synchronous_Data_IO flag and
P2_Sync_Data_IO_Activation flag are set, the Parameter Multiplex Mode remains disabled for Parameter Port pin
P2. This is to avoid erroneous deactivation of the Synchronous Data IO Mode if no external driver is connected.
Once activated, input data sampling as well as output data driving events are moved to different times
synchronized to the polling cycle of the AS-i network. Nevertheless, the communication principles between
master and slave remain unchanged compared to regular operation. The following rules apply:
• Data I/O is triggered by the DEXG call to the slave with the lowest slave address in the network. Based on
the fact that a master is calling slaves successively with rising slave addresses, the ASI4U/
ASI4U-E/ASI4U-F considers the trigger condition to be true if the slave address of a received DEXG call is
less than the slave address of the previous (correctly received) DEXG call.
Data I/O is only triggered if the slave has (correctly) received data during the last cycle. If the slave did not
receive data (e.g., due to a communication error), the Data Outputs are not changed and no Data Strobe is
generated (“arm+fire” principle). The inputs, however, are always sampled at the trigger event.
• If the slave with the lowest address in the network is operated in the Synchronous Data I/O Mode, it
postpones the output event for the received data for a full AS-i cycle. This is to keep all output data of a
particular cycle image together.
Note: To make this feature useful, the master must generate a data output cycle image once before the
start of every AS-i cycle. The image is derived from the input data of the previous cycle(s) and other control
events. If an AS-i cycle has started, the image must not change. If A and B slaves are installed in parallel at
one address, the master must address all A Slaves in one cycle and all B Slaves in the other cycle.
The input data, sampled at the slave with the lowest slave address in the network, is sent back to the master
without any delay. Thus, the input data cycle image is fully captured at the end of an AS-i cycle, just as in
networks without any Synchronous Data I/O Mode slaves. In other words, the input data sampling point has
simply moved to the beginning of the AS-i cycle for all Synchronous Data I/O Mode slaves.
• The first DEXG call that is received by a particular slave after the activation of the Data Port
(Data_Exchange_Disable flag has been cleared by a WPAR call is processed as in regular operation. This
is to capture valid input data for the first slave response and to activate the outputs as fast as possible.
The Data I/O operation is repeated together with the I/O cycle of the other Synchronous Data I/O Mode
slaves in the network at the common trigger event. By that, the particular slave has fully reached the
Synchronous Data I/O Mode.
• If the P2_Sync_Data_IO_Activation flag is set to ‘1’ at the slave with the lowest address in the network,
one data output value is lost when the Synchronous Data I/O Mode is turned off (L/H transition at P2), while
the value that is received in the cycle when the IC detects a signal change at P2 (H/L transition) is
repeated. This particular behavior is caused by the fact that in Synchronous Data I/O Mode the data output
at the slave with the lowest address is postponed for a full AS-i cycle (see description above).
• To avoid a general suppression of Data I/O in the special case that a slave in Synchronous Data I/O mode
receives DEXG calls only to its own address (i.e. employment of a handheld programming device), the
Synchronous Data I/O Mode is turned off once the ASI4U receives three consecutive DEXG calls to its own
slave address. The IC resumes to Synchronous Data I/O Mode operation after it has observed a DEXG call
to a slave address different from its own. The reactivation of the Synchronous Data I/O mode is handled
likewise for the first DEXG call after activation of the Data Port (see description above).
The Data Strobe (DSR) signal is also generated in Synchronous Data I/O Mode. The timings of input sampling
and output buffering correspond to the regular operation (refer to Figure 4.4 and Table 4.11).
Input data is captured and returned to the master at every cycle, independent of the value of information bit I2. As
a consequence, the cycle time is different for input data and output data:
• Data input values become refreshed in the master image in less than 10 ms.
• Data output values become refreshed at the slave in less than 21 ms.
Table 4.16 Meaning of Master Call Bits I0, I1, I2, and I3 in Ext_Addr_4I/4O_Mode
BIT IN MASTER CALL OPERATION / MEANING
I0 If I2 = ‘1’ then I0/I1 are directed to temporary data output registers DO0_tmp/DO1_tmp
I1 If I2 = ‘0’ then I0/I1 are directed to the data output registers DO2/DO3 and
DO0_tmp/DO1_tmp are directed to the data output registers DO0/DO1
I2 I2: /Select-bit for transmission to Bank_1 (DO0/DO1) / Bank_2 (DO2/DO3)
I3 I3: /Select bit for A-Slave/B-Slave addressing
The following feature descriptions relate to the logical signals after the (optional) data input
inverters.
Important Note: As described above, the pin assignment of DI2 and DI3 is exchanged in Safety
Mode. However, the configuration register for selective input inverting is directly associated with
the physical IC ports and is not changed. Thus, in Safety Mode bit 3 of the
DI_Invert_Configuration register defines the inverting of the logical signal DI2 and bit 2 defines
the inverting the signal DI3.
Modification of code sequence: The transmitted value for D0 is calculated according to the following
equation:
D0 = D0 XOR (D1 AND D2 AND D3)
Thus, the ASI4U will generate ‘1110’ from the input value ‘1111’ and ‘1111’ from the input value
‘1110’. To comply with the coding rules of the safe AS-Interface communication, which prohibit
‘1111’ as a valid state in the data stream, the external code generator must store ‘1111’ instead of
‘1110’.
If the Safety Mode becomes accidentally deactivated by a hardware fault, the IC discontinues
performing the D0 combination. The Safety Monitor would detect this as an error by reception of
‘1111’ (see Figure 4.9).
Deactivation of the standard data path: Theoretically, the Safety Mode could become deactivated for a
single bit only if a (single) fault occurs at one of the multiplexers. This would lead to code
sequences where three bits are routed in the Safety Path and the fourth bit is routed in the
Standard Path. Therefore, an additional OR gate is added in the Standard Path that ties the
Standard Path to constant ‘1’ if the Safety Mode is activated.
A valid data transfer in Standard Mode or Safety Mode is only possible if all four multiplexers are
switched to the same direction. Any other state will be recognized by the Safety Monitor.
Activation of Data_Exchange_Disable: The Data_Exchange_Disable flag is set by the IC after a reset and
will be cleared after the first parameter call. If the flag is set, the IC does not respond to
Data_Exchange calls. If the Safety Mode is activated and the Synchronous_Data_IO flag or any
of the DI_Filter_Configuration flags are set in the firmware area of the EEPROM, the
Data_Exchange_Disable flag cannot be cleared. This prevents any data communication in this
case. See Figure 4.10.
The flow charts given in Figure 4.8 are valid in the Safety Mode of the ASI4U:
Note: The following symbols are used in Figure 4.8, Figure 4.9, and Figure 4.10.
>=1 represents a logical OR
=1 represents a logical XOR
& represents a logical AND
The IC contains only a single inverter that generates the inverted Safety Mode signal for all requirements. See
Figure 4.9.
Figure 4.8 Flowchart – Input DI3, DI2, and DI1 in Safety Mode
DI[n] DI[m]
Invert_DI[m]
n = 3,2,1
m = 2,3,1
Invert_DI[n]
=1 =1
Filter
1 0
Filter_Enable
Sync
1 0
Sync_Enable
Safety_Mode
>=1
1 0
/Safety_Mode
To UART
Invert_DI1
Invert_DI2
Invert_DI3
Invert_DI0
=1 =1 =1
=1
Filter
&
1 0
Filter_Enable
Sync =1
1 0
Sync _Enable
Safety_ Mode
>= 1
1 0
/Safety _Mode
Command
Send Mux
To UART
Filter_Enable
>=1
Sync_Enable
& Data_Exchange_Disable
Safety_Mode
Note: The complemented definition is designed to retain backward compatibility to A²SI-based AS-i Master
designs.
The Data Output Port is used exclusively in Monitor Mode to provide additional UART error signals. The signals
are defined to be active LOW and will be set immediately after a telegram error was detected. They become reset
at the beginning of the next telegram. The signals described in Table 4.18 are available:
Table 4.19 Power Failure Detection at FID (Master Mode and Monitor Mode)
PARAMETER SYMBOL CONDITIONS MIN MAX UNIT
FID reference voltage to detect a VFID-PF An external voltage divider is required for 1.94. 2.06 V
power failure the measurement of the AS-I-voltage.
Input resistance of FID input RIN-FID 2M Ω
Power supply break down time to tLoff 0.7 0.9 ms
generate a “Power Fail” signal
Note: For compatibility to A²SI board layouts, where pin number 23 (former U5RD) must be connected to
U5R, the LED2 function is turned OFF by default, keeping LED2 always at the high impedance state. This is
to protect LED2 against shorting the 5V supply (U5R) to ground. LED2 will be activated if the
Enhanced_Status_Indication flag and/or the Dual_LED_Mode flag are set in the EEPROM.
In order to comply with the signaling schemes defined in the AS-Interface Complete Specification V3.0, a red
LED must be connected to LED1 and a green LED must be connected to LED2. Direct operation of a dual LED
is also supported but requires the Dual_LED_Mode flag to be set. This is because LED1 and LED2 must be
controlled differently for AS-Interface compliant dual LED signaling.
Table 4.20 gives the definitions for the status indications that are supported by the IC.
The flashing frequency of any flashing status indication is approximately 2Hz.
As shown in Table 4.20, the LED2 pin is deactivated in Standard Status Indication Mode (i.e., when
Extended_Status_Indication = ‘0’ and Dual_LED_Mode = ‘0’) for downward compatibility. In this case, the green
LED must be connected directly to the UOUT pin or a different sensor supply.
No data
green red yellow Slave is waiting for address assignment.
exchange red
Data Port communication is not possible.
(Address=0)
red/
Peripheral
green red green
Periphery Fault signal generated at FID input.
Fault
red/
green red green Alternating Alternating
Serious
Alternating
Periphery green red red Data Strobe driven LOW for more than 44µs.
Fault with
Reset
Note: The complemented definition is designed to retain backward compatibility to A²SI-based AS-i Master
designs.
Every received AS-i telegram is checked for consistency with the protocol specifications and timing jitters are
removed if they remain within the specified limits. If a telegram error is detected, the output signal becomes
disrupted in such a way that subsequent logic can also recognize the Manchester-II-coded output signal as being
erroneous.
LED2 is always logic HIGH (high impedance) in the Master, Repeater, and Monitor Modes to reduce internal
power dissipation of the IC. In such applications, the green LED must be connected to the UOUT pin or different
supply levels.
4.11. IC Reset
Any IC reset turns the Data Output and Parameter Output registers to FHEX and forces the corresponding output
drivers to high impedance state. Except at power-on reset, Data Strobe and Parameter Strobe signals are
simultaneously generated to visualize possibly changed output data to external circuitry.
The Data_Exchange_Disable flag becomes set during IC reset, prohibiting any data port activity right after IC
initialization and as long as the external circuitry was not pre-conditioned by decent parameter output data.
Consequently the AS-i master has to send a Write_Parameter call in advance of the first Data_Exchange request
to an initialized slave. Following IC initialization times apply:
U5R VPOR1R
VPOR1F
tLOW
Reset
Note: The power-on reset circuit has a threshold voltage reference. This reference matches the process tolerance
of the logic levels and therefore is not accurate. All values depend slightly on the rise and fall time of the supply
voltage.
DSR
Serious
tINIT Peripheral Fault
Hi-Z
DO[3:0] Data port output data
Hi-Z
P[3:0] Parameter port output data
tnoRESET
tRESET
In contrast to the A²SI, the external reset is generated “edge sensitive” to the expiration of the tRESET timer. The
initialization procedure starts immediately after the event, independent of the state of the DSR pin. A Serious
Peripheral Fault is recognized in Slave Mode if DSR remains LOW after tRESET + tINIT. The corresponding error
state display is described in section 4.9.
4.12. UART
The UART performs a syntactical and timing analysis of the received telegrams at both telegram input channels
(AS-i input, Addressing Channel input), converts the pulse coded AS-i input signal into a Manchester-II-coded bit
stream, and provides the Receive Register with decoded telegram bits.
The UART also performs the Manchester-II-coding of a slave answer (Slave Mode only) and controls the telegram
data paths at the different operational modes of the IC (Slave Mode, Master Mode, Repeater Mode, and Monitor
Mode).
In Slave Mode, data communication takes place on the AS-i input and AS-i output ports (AS-i receiver + AS-i
transmitter) by default. The Addressing Channel (IRD input + LED1 output) can be activated by a Magic
Sequence sent to the IRD input (see section 4.3). If the Addressing Channel is activated, the AS-i channel is
turned inactive. Re-activation of the AS-i channel requires a reset of the IC.
In the Master, Repeater, and Monitor Modes, the output signal of the Manchester-II-coder (AS-i pulse to
Manchester-II signal conversion) is resynchronized and forwarded to the LED1 pin. Any pulse timing jitters of the
received AS-i signal are removed, if they are within the specified maximum limits. If the received AS-i telegram
does not pass one of the error checks (see detailed descriptions in section 4.12.1), the LED1 output is distorted
so that it no longer forms an AS-i telegram signal.
In the Master, Repeater, and Monitor Modes, the ASI4U provides a simple interface function between AS-i
channel and Addressing Channel. The channel receiving an input signal first while the UART is in idle state (no
active communication) is activated and locked until a communication pause is detected on that channel.
Timing_error Within any master request or slave response, the digital pulses that are generated by the
+1.500 µs
receiver are checked to start in periods of (n * 3 µs ) −0.875 µs after the start of the initial
negative pulse, where n = 1 to 26 for a master request and n = 1 to 12 for a slave
response. Violation of this rule is detected as a Timing_error.
Note: There is a specific pulse timing jitter associated with the receiver output signals
(compared to the analog signal waveform) due to sampling and offset effects at the
comparator stages.
In order to take the jitter effects into account, the timing tolerance specifications differ
slightly from the definitions of the AS-Interface Complete Specification V3.0.
No_information_error As derived from the Manchester-II-Coding rule, either a positive or negative pulse must
+1.500 µs
be detected in periods of (n * 6 µs ) −0.875 µs after the start of the initial negative pulse,
where n = 1 to 13 for a master request and n = 1 to 6 for a slave response. Violation of
this rule is detected as a No_information_error.
Note: The timing specification relates to the receiver comparator output signals. There is
a specific pulse timing jitter in the digital output signals (compared to the analog signal
waveform) due to sampling and offset effects at the comparator stages.
In order to take the jitter effects into account, the timing tolerance specifications differ
slightly from the definitions of the AS-Interface Complete Specification.
Parity_error The sum of all information bits in master requests or slave responses (excluding start and
end bits, including the parity bit) must be even. Violation of this rule is detected as a
Parity_error.
+1.500 µs
End_bit_error The pulse to be detected (n * 6 µs ) −0.875 µs after the start pulse must be of positive polarity,
where n = 13 (i.e., 78 µs) for a master request and n = 6 (i.e., 36 µs) for a slave
response. Violation of this rule is detected as an End_bit_error.
Note: This stop pulse must finish a master request or slave response.
Length_error Telegram length supervision is processed as follows. A Length_error is detected if a
signal different from a pause is detected under any of these three conditions: during the
th
first bit time after the end pulse of a master request (equivalent to the 15 bit time) for
synchronized slaves; during the first three bit times for non-synchronized slaves
(equivalent to the bit times 15 to 17); or during the first bit time after the end pulse of a
th
slave response (equivalent to the 8 bit time).
If at least one of these errors occurs, the received telegram is treated as invalid. In this case, the UART will not
generate a Receive Strobe signal, move to asynchronous state, and wait for a pause at the AS-i line input. After a
pause has been detected, the UART is ready to receive the next telegram.
Receive Strobe signals are generally used to validate the correctness of the received data. In the Master and
Monitor Modes, the signals are visible at the Parameter Ports for further processing by external circuitry.
Corresponding Parameter Port configurations can be found in Table 4.10.
In Slave Mode, a Master Receive Strobe starts the internal processing of a master request. If the UART was in
asynchronous state before the signal was generated, it changes to synchronous state thereafter. If the received
slave address matches the stored address of the IC, the transmitter is turned on by the Receive Strobe pulse,
letting the output driver settle smoothly at the operation point.
Information 0 0 1 0 1 Pause
Bit Stream
Transmitted
Manchester-II-
Coded Bit Stream
Equivalent to the AS-i input channel checks, the signals received at the Addressing Channel input (IRD pin) are
checked for telegram transmission errors. The checking, however, is only performed in Slave Mode. In the
Master, Repeater, and Monitor Modes, the IRD signal is checked only for logical correctness. It is directly
forwarded to the AS-i line transmitter avoiding any additional logic delays.
Note: Because the telegram checking is disabled on the Addressing Channel in the Master, Repeater, and
Monitor Modes, corresponding Receive Strobe signals are neither displayed at the Parameter Ports nor
generated for internal purposes.
The master control logic must care to deliver correctly timed Manchester-II signals, ensuring that the
resulting AS-i telegrams fulfill the specified timing limits.
Start_bit_error The initial signal transition (after a pause) must be of the falling edge. Violation of this rule
is detected as a Start_bit_error.
No_information_error Within a received telegram, signal transitions (of the rising or falling edge) must occur in
+2.000 µs
periods of (n * 6 µs ) −1.000 µs after the initial falling slope, where n = 1 to 13. Violation of this
rule is detected as a No_information_error.
Note: The Addressing Channel input (IRD) only accepts master requests in Slave Mode.
Parity_error The sum of all information bits in master requests (excluding start and end bits, including
the parity bit) must be even. Violation of this rule is detected as a Parity_error.
End_bit_error The signal transition to be detected 13 ∗ 6 µs (i.e., 78 µs) after the initial falling start
transition, must be of rising slope. Violation of this rule is detected as an End_bit_error.
Note: This stop transition must finish the master request.
Length_error A Length_error is detected if a signal different from a pause is detected during the first bit
th
time after the end pulse of a master request (equivalent to the 15 bit time) for
synchronized slaves or during the first three bit times for non-synchronized slaves
(equivalent to the bit times 15 to 17).
In total, the power dissipation must not exceed the specified values of section 2.1.
To cope with fast internal and external load changes (spikes) external capacitors at UOUT and U5R are required.
The 0V pin defines the ground reference voltage for both UOUT and U5R.
5 Application Circuits
The following figures show typical application cases for the ASI4U. Note that these schematics show only basic
circuit principles. For more detailed application information, see the ASI4U Application Note – Evaluation Board.
Figure 5.1 outlines a standard slave application circuit. Figure 5.2 shows an extended power application circuit
with an externally decoupled sensor supply. A Master/Repeater Mode application is shown in Figure 5.3.
UOUT +24V
FID
UIN
DI0
8/16MHz DI1
DI2
OSC1
DI3
DO0 DIO-0
OSC2 DO1 DIO-1
DO2 DIO-2
ASI4U
1N4001 DO3 DIO-3
ASI+ ASIP DSR DSR & Reset
ZMM 39
ASI- ASIN P0 P0
P1 P1
P2 P2
CAP P3 P3
PST PST
U5R LED1
47nF 100nF
LED2
0V IRD
GND
100nF 10µF
0V
UOUT +24V
FID FAULT_IN
8mH
DI0 DI-0
UIN DI1 DI-1
DI2 DI-2
8/16MHz
DI3 DI-3
OSC1
DO0 DO-0
2x
DO1 DO-1
ZMM 4.7
OSC2 DO2 DO-2
DO3 DO-3
ASI4U
1N4001 1N4148
DSR DSR & Reset
ASI+ ASIP
ZMM 39 P0 P0
ASI- ASIN P1 P1
P2 P2
P3 P3
CAP PST PST
2x
LED1
ZMM 4.7 U5R
LED2
1µF 100nF
IRD Addressing
0V option
8mH GND receiver
10µF 100nF
0V
U_EXT
UOUT
U5R +Ub
SEND
IRD VO
UIN
GND
8/16MHz
DI0
OSC1 DI1 +Ub REC_CLK
DI2 VO
(optional)
OSC2 DI3 GND
ASI4U
1N4001 DO0 +Ub REC_STRB
ASI+ ASIP DO1 VO
DO2 (optional)
ZMM 39 GND
DO3
ASI- ASIN
DSR +Ub
P0 VO RECEIVE
CAP GND
P1
P2
FID P3
47nF /POWER_FAIL
PST
0V LED1
LED2
GND
100nF 10µF
GND_EXT
6 Package Specifications
6.1. Package Pin Assignment
Table 6.1 ASI4U Package Pin List
Note: All open drain outputs are NMOS based. Pull-up properties at input stages are achieved by current sources referenced
to U5R.
ASIP UIN
ASIN UOUT
0V U5R
IRD CAP
FID LED1
OSC2 LED2
OSC1 DSR
DO3 PST
DO2 DI3
DO1 DI2
DO0 DI1
GND DI0
P3 P0
P2 P1
ASI4U ZMDI
R-YYWWLZZ LLLLLL
+ G1
PIN 1 PIN 1
Top Marking:
ASI4U or ASI4U-E or ASI4U-F Product name
IDT Manufacturer
R Revision code
YYWW Date code (year and week)
L Assembly location
ZZ Traceability code
G1 “Green” RoHS-compliant package
Bottom Marking:
LLLLLL IDT Lot Number
For ICs pre-programmed to Master Mode, the string “-M” follows the product name.
For ICs with an operation temperature up to 105°C, the string “-E” follows the product name.
For ICs with an operation temperature up to -40°C, the string “-F” follows the product name.
7 Ordering Information
RoHS Minimum Order
Ordering Code Type Package Ta [°C] Packaging
Conform Quantity
8 Related Documents
Document
ASI4U/ASI4U-E/ASI4U-F Feature Sheet
ASI4U/ASI4U-E/ASI4U-F Release Note RevE
ASI4U/ASI4U-E/ASI4U-F Errata Sheet
Production and Repair of AS-i Safety Slaves *
ASI4U Application Note – Evaluation Board *
9 Glossary
Term Description
DEXG Data Exchange
DSR Data Strobe and Reset
EMI Electromagnetic Interference
FID Fault Indication
IRD Integrated Receiver/Decoder
PST Parameter Strobe
UART Universal Asynchronous Receiver/Transmitter
WPAR Write Parameter
IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be
reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT.
Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property
of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. All contents of this document are copyright of Integrated Device
Technology, Inc. All rights reserved.
These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible
for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3)
ensuring your application meets applicable standards, and any other safety, security, or other requirements. These
resources are subject to change without notice. Renesas grants you permission to use these resources only for
development of an application that uses Renesas products. Other reproduction or use of these resources is strictly
prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property.
Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims,
damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject
to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources
expands or otherwise alters any applicable warranties or warranty disclaimers for these products.
Trademarks
Renesas and the Renesas logo are trademarks of Renesas
Electronics Corporation. All trademarks and registered
trademarks are the property of their respective owners.