This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 1

A Fast Voltage Clamp Circuit for the Accurate

Measurement of the Dynamic On-Resistance of
Power Transistors
Ratmir Gelagaev, Student Member, IEEE, Pieter Jacqmaer, Student Member, IEEE,
and Johan Driesen, Senior Member, IEEE

Abstract—For determining the dynamic on-resistance Rdyn,on speed switching operations and the static on-resistance calcu-
of a power transistor, the voltage and current waveforms have lated from direct-current (DC) measurements is not sufficient
to be measured during the switching operation. The novel as a guideline to predict the conduction losses. The reason
heterostructure wide-bandgap (eg. AlGaN/GaN) transistors in-
herently suffer from the current collapse phenomenon, caus- for this is that the on-resistance is determined by the junction
ing the dynamic on-resistance to be different from the static. temperature which is unknown. Also, heterostructure wide-
Measuring voltage waveforms using an oscilloscope distorts the bandgap semiconductor transistors [12] (e.g. AlGaN/GaN de-
characteristics of an amplifier inside the oscilloscope when the vices) are subject to a phenomenon known as current collapse,
range of the measurement channel is not set wide enough also called charge trapping [13]–[16] and this causes the on-
to measure both on-state and off-state voltage, resulting in
failure to accurately measure the voltage waveforms. A novel resistance to be dependent on the voltage the transistor has to
voltage clamp circuit improving the accuracy of the transistor’s withstand during its off-state.
on-state voltage measurement is presented. Unlike traditional The on-resistance of a transistor after applying high-voltage
clamping circuit, the presented voltage clamp circuit does not swings to the drain of the device under test in its off-state,
introduce delay caused by RC time constants keeping the voltage is further referred to as the dynamic on-resistance Rdyn,on . It
waveform clear, even during state transitions of the device under
test. The performance of the presented circuit is illustrated by can be obtained by dividing the voltage and current waveforms
measurements on a 2 MHz inverted buck converter. during the on-state.
When measuring the voltage waveform, the measurement
Index Terms—Measurements, accuracy improvement, voltage
clamping, dynamic on-resistance, heterostructure wide-bandgap range on the oscilloscope must be set wide enough in order
transistors, current collapse, charge trapping. to measure both on-state and off-state voltage levels. If this
is not the case, the characteristics of amplifiers inside the
oscilloscope are distorted, due to a phenomenon known as
I. I NTRODUCTION ”Oscilloscope Overdrive” and the lack of recovery thereof,
The reduction of losses in power converters is indisputably resulting in failure to accurately measure the on-state voltage
one of the most important issues in the field of power ( [17], chapter 24). An 8 bit Analog to Digital converter in an
electronics. Next to the optimization of the efficiency of a oscilloscope provides 28 = 256 quantization levels to discrete
power switching converter, also cost minimization is of great an analog signal. If the transistor switches between 0.1 V and
importance [1]–[4]. The losses in a power switching converter 400 V, this gives a resolution of about 400/256 = 1.56 V, re-
are present both in the passive as well as in the active elements. sulting in completely inaccurate values of the on-state voltage,
In [5], [6] the losses in a high power DC/DC converter are which may even be perceived as negative because of the large
reduced by an optimal design of the planar transformer. In quantization error. In recently developed GaN heterostructure
[7]–[9] the switching losses are reduced by a soft switching semiconductor devices, this problem is even more pronounced
strategy. Despite previous efficiency-enhancing techniques, the because these devices exhibit a much lower on-resistance for
conduction losses still represent a large part of the total losses. the same blocking voltage than silicon devices, and can there-
In particular, the on-resistance of the transistor, which is fore be downscaled with respect to traditional components,
directly linked to the conduction losses, needs to be as low as allowing them to switch faster [18]–[21]. This means that for
possible [10], [11]. Therefore, accurate measurement of the on- wide-bandgap devices an even higher measurement resolution
resistance is indispensable. Recently developed high voltage is required and that measurements should be performed with
semiconductor switching devices frequently perform high- faster circuitry.
Conventional circuits partially solve this problem by clam-
Manuscript received November 6, 2013; revised February 19, 2014, May ping the off-state voltage to a lower value [22]. However,
6, 2014 and June 10, 2014; accepted July 14, 2014. they introduce problems such as voltage peaks, measurement
Copyright c 2014 IEEE. Personal use of this material is permitted.
However, permission to use this material for any other purposes must be offset and delays due to RC time constants. These problems
obtained from the IEEE by sending a request to [email protected]. get worse with increasing switching frequency and decreasing
R. Gelagaev and P. Jacqmaer and J. Driesen are with the Depart- switching times, resulting in failure to accurately measure the
ment of Electrical Engineering (ESAT), KU Leuven, Kasteelpark Aren-
berg 10, 3001 Heverlee, Belgium (e-mail: [email protected], voltage waveform.
[email protected], [email protected]) To address these problems, a novel voltage clamp circuit is

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 2

proposed which improves the accuracy of the on-state voltage In literature, there are only a few references [16], [22], [24],
waveform measurements. Unlike traditional clamping circuits, [25] that have extracted the dynamic Rdyn,on of transistors.
the presented voltage clamp circuit does not introduce delay Moreover, clear illustrations of both the applied measurement
caused by RC time constants keeping the voltage waveform method and circuit, are rarely given. Therefore, the authors
clear, even during state transitions of the device under test conducted this work and deemed that a paper dedicated to
(DUT). The circuit is presented in [23] but in this paper this subject would be of value. The proposed circuit can be
the parameters influencing the performance and operation of built inside oscilloscopes or measurement units, meaning the
the circuit are thoroughly investigated. Recommendations are circuit has immediate industrial or scientific value.
given for the selection of high voltage diodes. A new power This paper is organized as follows: three conventional cir-
converter is built to test the circuit performance at higher cuits, also employing the voltage clamping principle, are first
switching frequency (2 MHz). A new state-of-the-art circuit explained and discussed to illustrate their disadvantages with
has been found in the literature and is investigated in this respect to the novel measurement circuit of this work. Then,
paper. The state-of-the-art circuits are built and measured to the novel circuit is presented and assessed using simulations
confirm their advantages and disadvantages. and measurements. The measurement accuracy is determined,
The circuit presented in this article is in the first place both analytically and through simulations. Next, the most
intended to measure the dynamic on-resistance of heterostruc- important factors for mitigating voltage peaks in the clamped
ture wide-bandgap semiconductor switches. Due to the charge- voltage are experimentally evaluated. Finally, the influence of
trapping effect, mentioned above, the on-resistance is depen- temperature on the measurement accuracy is evaluated.
dent on the off-state voltage, and therefore might differ a
lot from the static on-resistance. But, there is also a second II. S TATE - OF - THE - ART VOLTAGE CLAMP CIRCUITS
application in which the circuit of this work is useful. Fig.
A. State-of-the-art circuit I: based on a Zener diode
1 shows measurement results performed with the presented
voltage clamp circuit for different superjunction MOSFETs A first voltage clamp circuit is shown in Fig. 2. The circuit is
not suffering from the charge-trapping effect, in function of the connected to the drain and source terminals of the device under
switching frequency. The higher the switching frequency, the test (DUT). The measurement of the drain-to-source voltage
higher the switching losses and thus the temperature increase waveform is performed with an oscilloscope by placing a
of the measured device. This results in an increase of the on- voltage probe between output nodes A and B. During the
resistance. Because the junction temperature is unknown, the off-state, the drain voltage of the DUT is high (e.g. 400 V)
static on-resistance listed in the components’ datasheets cannot and the voltage between the output nodes A and B (Vout ) is
be used to determine the conduction losses. The presented clamped to a level equal to the sum of the voltage drop across
voltage clamp circuit is capable of measuring the on-resistance diode D1 and the Zener voltage across Zener diode D2 . The
of a device while switching at high frequencies, and therefore, sum of these voltage drops is called the clamping voltage. The
allowing one to determine its conduction loss. Furthermore, in main reason for using diode D1 is to reduce the total series
all applications where the voltage has a pulsation behaviour parasitic capacitance of diodes D1 and D2 .
and where only the low voltage level should be measured The value of the clamping voltage must be chosen greater
accurately, and it is of no importance that the high level is than the on-state voltage of the DUT. Hence, diodes D1 and
clipped to a lower value, the circuit of this work can be applied. D2 will not clamp the drain-to-source voltage during the on-
In all cases, the measured devices are treated as a black box state and the measured voltage Vout between points A and B
with the device parasitics accounted for in the measurements. will be equal to the on-state voltage of the DUT.

Vds=400V To drain
550 A
FCPF22N60NT of DUT
500 IPA60R190C6 R
STF23NM60ND
450
D1
400

350

D2
Rdyn [mΩ]

300

250
To source
200 B
of DUT
150
Fig. 2: State-of-the-art circuit I
100

50
Note that the highest measured voltage Vout is the clam-
0
100 150 200 250 300 350 400 ping voltage. Consequently, the measurement range of the
frequency [kHz] oscilloscope may be set to a value wide enough to measure
Fig. 1: Dynamic on-resistance of different superjunction MOSFETs vs swit- the clamping voltage instead of the high off-state drain-to-
ching frequency (VDS = 400 V, IDS = 4 A, VGS = 12 V) source voltage. This results in an increase of the measurement

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 3

resolution with respect to a direct measurement with a factor: for low frequencies, typically a few tens of kilohertz up till
100 kHz.
Vpp, off
Resolution improvement = (1)
Vpp, clamped
B. State-of-the-art circuit II: based on a transistor
A second voltage clamp circuit is described in the US
where Vpp, off is the peak-to-peak value of the drain-to-source patent application 2008/0309355 A1 and depicted in Fig. 4.
voltage during the off state, and Vpp, clamped is the peak-to-peak It is connected to the drain and source terminals of the DUT.
value of the clamped drain-to-source voltage. The output voltage (Vout ) of the circuit is measured between
However, this circuit has some disadvantages. Fig. 3 shows the nodes A and B using a voltage probe. Transistor M
that during the on-state there is a current flowing through the is a normally-on type field-effect transistor with a negative
resistor R resulting in a voltage drop across it. This current is threshold voltage (e.g. −2 V). In the patent, transistor M
the sum of the leakage currents through the clamping diode is a wide-bandgap normally-on type transistor. The gate of
and the measurement probe. Even though the leakage currents transistor M is connected to a positive DC voltage supply
are small, the high resistance value will lead to a significant Vcc .
voltage drop across R. Therefore, the measured voltage at
the output of the circuit, between the points A and B will M
be the on-state voltage minus a voltage drop across R. The To drain
measurements, performed under the same conditions as for the
A
of DUT
presented circuit, show a voltage drop across the resistor R of
a few hundred millivolts depending on the value of R.
There is also an RC time constant caused by the resistor +
VCC R
R and the parasitic capacitances of diodes D1 and D2 , and of
the measurement probe. Due to this time constant, the output
voltage of the clamping circuit will only gradually decrease To source
to the real on-state voltage, causing a measurement delay. B
of DUT
To counter this problem, the resistance value of R could be
reduced, or probes and diodes with a low capacitance could Fig. 4: State-of-the-art circuit II
be employed. However, to limit the power dissipation of R,
which shows a maximum during the off-state of the device, During the off-state of the DUT, a current flowing through
and is then equal to (Vds − Vclamped )2 /R, the resistance value the resistance R will cause a voltage increase at the source
should not be chosen too low. terminal of transistor M . When the gate-to-source voltage of
transistor M decreases below its threshold voltage (e.g. Vth =
to 300
[ V −2 V), transistor M is turned off. At this point, a voltage
equilibrium will be established and the output voltage Vout will
6
be clamped to the clamping voltage Vclamp = Vg −Vth = 4 V.
5.5 This allows the range of the oscilloscope to be zoomed in
Vds to a range wide enough to measure Vclamp , thus increasing
5 the measurement resolution. When the DUT is turned on, the
source voltage of transistor M decreases, causing the gate-
4.5
Clamped Vds
to-source voltage of transistor M to become higher than its
Vds [V]

4 threshold voltage, bringing the transistor into conduction. As

a result, the on-state voltage of the DUT is measured at the
3.5 output of the circuit. For a clamping voltage of e.g. 4 V, the
RC time constant
measurement accuracy is 4 V/28 = 0.0156 V, using an 8 bits
3
resolution oscilloscope. For an on-state voltage of 0.1 V, this
2.5 allows a sufficiently accurate measurement.
Measurement offset This circuit has a few disadvantages. Firstly, the simulations
2 in Fig. 5 show that when the DUT switches off, the output
0.6 0.8 1 1.2 1.4 1.6
Time [s] −5
x 10 voltage Vout is increased above Vclamp (Vout peaks) due
Fig. 3: Simulation results of circuit I (100 kHz), D1 = 1N 4148, D2 = to the parasitic drain-to-source capacitance of transistor M .
BZV 85C3V 6, R = 200 kΩ, switch = IRF 840, 2.97 A, 300 V These voltage peaks increase with the value of the resistance
R and can be several times the clamping voltage Vclamp .
Furthermore, the value of R also depends on the current Consequently, this will cause the oscilloscope overdrive phe-
which has to flow through D2 in order to achieve correct nomenon, resulting in failure to accurately measure the voltage
Zener operation. Typically for many Zener diodes, a current of waveforms. To prevent this, the range of the oscilloscope has
a couple of milli-amps is required. Due to these disadvantages to be set to a range wide enough to capture the voltage peaks
this circuit cannot be used to measure the on-resistance during which decreases the measurement resolution. Moreover, the
high-speed switching operation. The circuit can only serve voltage peaks at the source of transistor M (also equal to

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 4

in the clamped voltage are minimal. If the DUT is off, the

potential at node A is clamped according the same operating
principle as circuit II, to a voltage VG − Vth , because of the
presence of the zener diode D3 , with VG the potential at which
the gate of M is biased and Vth the threshold voltage of M . If
the DUT is on, M is also on, and the on-state voltage appears
across points A and B.
To drain
of DUT
M R1

D1 D3
+
C VCC

D2 R2

Fig. 5: Simulation results of circuit II (100 kHz), M = GaN [26], R = 50 Ω, To source

B
Vcc = 2.5 V, switch = IRF 840, 2.97 A, 300 V of DUT
Fig. 6: State-of-the-art circuit III, combination of I and II

Vout ) will cause its gate-to-source voltage Vgs to become more In Fig. 7 simulation results at 100 kHz switching frequency
negative than allowed (Vgs peaks) which might lead to its are shown. It can also be shown that the circuit performs well
destruction. However, this can be solved by putting a series of at 2 MHz.
fast switching diodes, between the source and gate of transistor However, this circuit has disadvantages. The large drain-
M , with a total forward voltage drop larger than the threshold to-source parasitic capacitance of transistor M leads to high
voltage. voltage peaks at the node A during the switching transitions
Secondly, to reduce the voltage peaks, the value of the of the DUT. The Schottky diodes D1 , D2 and the Zener
resistance R has to be taken as small as possible. However, D3 together with the resistor R2 are used to reduce these
during the on-state of the DUT, transistor M is turned on voltage peaks. However, these components introduce a leakage
and due to the resistance R a small current flows through M , current leading to a voltage drop across transistor M . The
causing a voltage drop across it. This will introduce an error measurements, performed under the same conditions as for
on the measurement. The error can be significant if the value the presented circuit, show a voltage drop across transistor M
of the resistance is taken too small. Additionally, there is a up to 160 mV.
power dissipation in the resistance R which can be up to 1 W.
Thirdly, during the transition to the off-state of the DUT to 300 V

there is a large dv/dt across its capacitance Cgd . Therefore, 18

a large current will be flowing through the voltage supply Vcc 16

which might lead to its destruction. 14
The transistor used in the patent 2008/0309355 A1 is a wide
12 V ds
gap normally-on type field-effect transistor (Fig.4). However,
the circuit can also operate if a regular normally-off type field- 10

effect transistor is used. This is achieved by increasing the 8 Clamped Vds spikes
Vds [V]

supply voltage Vcc by a few volts (e.g. Vcc = 8 V). For a 6 Clamped Vds
threshold voltage of Vth = 4 V, this gives a clamping voltage 4
of Vclamp = Vcc − Vth = 4 V.
2

0
C. State-of-the-art circuit III: combination of I and II
−2
In [22], another voltage clamp circuit is described, which
−4
can be seen as a combination of the first two circuits. It 0.6 0.8 1 1.2 1.4 1.6
Time [s] −5
x 10
is shown in Fig. 6. It is connected to the drain and source
terminals of the DUT and the output of the circuit is the Fig. 7: Simulation results of circuit III (100 kHz), D1 = D2 = 1N 4148,
D3 = 1N 4733, R1 = 20 Ω, R2 = 10 Ω, switch=IRF 840, 2.82 A, 200 V,
voltage between the nodes A and B. Basically, the circuit Vcc = 8 V, T = IRF 620, C = 10 nF
consists of a normally-off field-effect transistor M (IRF 620
in [22]) connected to a Zener diode D3 (5.1 V) in series with Transistor M should carry the high voltage that the DUT
a resistor R2 with a low resistance value (10 Ω). The transistor also carries, and thus has a large size, implicating that the
is biased at a constant voltage Vcc of between 6 and 8 V. The parasitic drain-to-source capacitance has a large value. In the
exact value of this voltage is chosen so that the voltage peaks circuit presented in this work, the novel voltage clamp circuit,

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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no MOSFETs are used in the clamping circuit, only diodes, clamping diodes, as indicated by the solid line in Fig. 8. The
having a lower parasitic capacitance. This is beneficial for output voltage is thus the clamping voltage Vclamp . In the
the voltage spikes in the clamped voltage. Therefore, there is design of the circuit, the clamping diodes or their number
no need to use extra components that lead to leakage current should be chosen so that the clamping voltage is higher than
and voltage offset. To give a numerical example, with data the on-state voltage of the DUT. Because the output voltage
available in the components’ datasheets: compare the parasitic Vout is limited to at most the clamping voltage Vclamp , the
diode capacitance of the BAS21J diode: Cparasitic ≈ 2 pF range of the oscilloscope may be set to one wide enough
at 0 V, with the drain-to-source capacitance of the IRF620 to measure Vclamp , therefore improving the measurement
MOSFET: Cds ≈ 70 pF at Vgs = 0 V and Vds = 25 V. resolution.
Circuit III does not suffer from an RC-delay, but introduces Note that reversely connected Zener diodes can also be
a voltage offset which is not the case for the proposed circuit used as clamping diodes. They usually have more internal
of this work. capacitance than forward conducting Schottky diodes or small
Moreover, during the transition to the off-state of the DUT signal diodes and hence are not preferred.
there is a large dv/dt across the gate-to-drain capacitance Cgd
of M . Consequently, if Cgd is large, a large current will be VCC

flowing through the voltage supply Vcc which might lead to

its destruction, as is the case in circuit II.
Nevertheless, circuit III has the advantage that no differ-
ential voltage probe should be used to measure the output Transistor on
voltage, unlike the novel proposed circuit of this paper.
Cascode
Current Mirror Transistor off

III. N OVEL VOLTAGE CLAMP CIRCUIT

In Fig. 8 the voltage clamping circuit of this work is pre-
sented. It consists of a current mirror circuit, two high voltage
diodes DA and DB having the same I-V characteristic and a R

series connection of one or more clamping diodes connected

between the points A and B. The circuit is connected via the A B
high voltage diodes to the drain and source terminals of the Clamping diodes

transistor of which the on-state voltage or the dynamic on- DA DB

resistance is to be evaluated. The mirror circuit provides two
equal currents, hereafter referred to as mirror currents. The
value of these currents is determined by the resistance R, the To drain of DUT To source of DUT
supply voltage Vcc and the forward voltage drops across the Fig. 8: Presented voltage clamp circuit with current flows during the on- and
current mirror transistors, as shown in Fig.8. The mirror circuit off-states of the transistor
can have any kind of topology, for instance a Wilson current
mirror, but in the figure, a cascode mirror is shown. Wilson The presented voltage clamp circuit has a high measurement
or cascode current mirrors have the advantage that the Early accuracy. Current mirrors typically exhibit a high current
effect of the two upper BJT transistors is avoided and that accuracy of ±0.5% (see for example the REF200 current
the output resistance has a very high value. The output of the mirror from Texas Instruments). When the mirror currents have
voltage clamp circuit is the voltage Vout between the points for example a nominal value of 60 mA, in the worst case
A and B. Therefore, the voltage should be measured with a situation, the real mirror currents are 60.3 mA and 59.7 mA.
differential probe and an oscilloscope. In case two high voltage diodes BAS21J are used, a PSpice
During the on-state of the DUT, the drain-to-source voltage simulation reveals that this will result in a difference between
is low and the mirror currents flow through the high-voltage the voltage drops across the high voltage diodes DA and DB
diodes, as shown in Fig. 8 with the dashed lines. They do not of about 0.983 mV. When the on-state voltage of the DUT is
flow through the clamping diodes. The potential at node A is for example 1 V, this means that the measurement error is at
then the sum of the voltage drops across DA and the drain- most 0.1 %.
to-source voltage of the DUT. The potential at node B is the Fig. 9 shows simulation results of the presented circuit. The
voltage drop across diode DB . Because the mirror currents simulation is done at a switching frequency of the DUT of
are equal and because the diodes DA and DB have equal I-V 100 kHz, with a cascode mirror circuit of BC557C BJTs, a
characteristics, the voltage drops across DA and DB are the VCC of 10 V, a series connection of 5 BAV 3004W clamping
same and the voltage between A and B is equal to the on-state diodes and the same high voltage diodes, and R = 100 Ω.
voltage of the DUT. There are in the simulation no voltage peaks at the output
During the off-state of the DUT, the left mirror current during the transition to the on-state. However, during the
cannot flow through diode DA anymore because the drain- transition to the off-state a voltage peak of about 6.53 V
to-source voltage of the DUT is high. The left mirror current can be observed which is still much less than the voltage
therefore is forced to flow through the series connection of peaks observed in the state-of-the-art circuit II. This voltage

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
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peak is caused by the parasitic capacitance of diode DA and with Vt,A = kT /q and Vt,B = k(T + ∆T )/q. Therefore, the
can be minimized by choosing a better diode. For the best error is:
performance a diode should be chosen with the lowest parasitic
 = Vpn,A − Vpn,B
capacitance and limited reverse recovery.    
nkT I nkT I + ∆I
= ln +1 − ln + 1 − ...
q I0 q I0
 
nk∆T I + ∆I
ln +1
q I0
I+I0
!  
nkT I0 nk∆T I + ∆I
= ln I+∆I+I0 − ln +1
q I
q I0
0

Neglecting I0 with respect to I, we find:

   
nkT ∆I nk∆T I + ∆I
 ≈ − ln 1 + − ln +1
q I q I0
Making use of the Maclaurin-series of the natural logarithm
ln(1 + x) ≈ x, x → 0, we have:
nkT ∆I nk∆T Vpn,B
 ≈ − −
q I q nkT /q
nkT ∆I ∆T
≈ − − Vpn,B (4)
q I T
At 300 K, with ∆I = 0.6 mA, I = 59.7 mA, and for two
Fig. 9: Simulation results of the presented circuit; 100 kHz, DA =
BAV 3004W = DB =clamping diodes, series connection of 5 clamping BAV21 diodes that are held at the same temperature, and have
diodes, Vcc = 10 V, R = 100 Ω, switch=IRF 840, 2.974 A, 300 V an emission coefficient of n = 2.8541 , we find an absolute
error of
The main advantage of the presented voltage clamp circuit 2.584 · 1.38065 · 10−23 · 300 0.6
is that it does not introduce delay caused by RC time ≈− = −0.671 mV
1.602 · 10−19 59.7
constants keeping the voltage waveform clear, even during approximating the value simulated by PSpice, stated above,
state transitions of the DUT. Also, there is no offset in the well.
output voltage Vout due to a voltage drop across a resistor or
MOSFET in the clamping circuit as was the case in state-of- V. M EASUREMENT RESULTS
the-art circuits I, II and III.
As mentioned above, the measurement of the on-state
voltage waveform is necessary to determine the dynamic on-
resistance Rdyn,on . The following measurements were per-
IV. Q UANTIFYING THE ACCURACY OF THE MEASURING
formed using a Tektronix TDS 5054 500 MHz oscilloscope, a
CIRCUIT
Tektronix P5100A 500MHz voltage probe, a Tektronix P6251
In a previous paragraph, a numerical example illustrated 1 GHz differential probe and a LEM PR50 Universal 50 MHz
the accuracy of the voltage clamp circuit. Making use of current probe.
the relationships between voltage and current of diodes, an The measurements are done on an inverted buck converter
expression for the absolute and relative errors can be derived. [27], [28] and the presented voltage clamp circuit (Fig. 10).
Referring to Fig. 8, it is assumed that diode DA is a pn- The circuit is built very compactly to reduce the parasitics
diode, conducting a current of I, and having a junction at in it. The voltage clamp circuit consists of a cascode current
temperature T . Diode DB is a pn-diode, conducting a current mirror built with two BCV 62B components in series. The
of I + ∆I, having a junction at temperature T + ∆T . Suppose provided current is adjusted through the supply voltage and the
the saturation currents I0 of both diodes are the same. The resistance R (Fig. 8). For the high voltage diodes BAS21J,
absolute error  of the on-state voltage is then the difference BY V 26C and ES1G are used. For the clamping diodes it
of the two p-to-n voltages of the diodes: is advised to use fast Schottky diodes. For the subsequent
measurements twenty 1P S76SB10 Schottky diodes in series
 = Vpn,A − Vpn,B are used. Fig. 11 shows the voltage waveform measurement
conducted on a Fairchild MOSFET F DP F 5N 60N Z with an
For pn-diodes, the relationship between p-to-n-voltage and off-state drain-to-source voltage of 300 V, average current of
diode current is: 1 A, frequency f = 2 MHz, VGS from −2 V to 12 V and
  duty cycle D = 0.5.
I = I0 eVpn,A /(nVt,A ) − 1 (2) The off-state drain-to-source voltage is clamped from 300 V
  to approximately 6.1 V.
I + ∆I = I0 eVpn,B /(nVt,B ) − 1 (3) 1 The emission coefficient is obtained from the Spice-model of the diode.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 7

12
To the load 10
Rdyn , measured with Vds
8

6
VDC
VCC 4

Rdyn [Ohm]
2
Buck converter Clamping circuit
0
Rdyn, measured with Vclamp
−2

−4

−6
Gate driver
−8
−0.5 0 0.5 1 1.5 2 2.5 3
Time [s] x 10
−7
Fig. 10: Test circuit
Fig. 12: Dynamic on-resistance with and without the proposed clamping
circuit (2 MHz)

As can be seen from the Fig. 11, the on-state drain-to-

source voltage waveform Vds , measured without the voltage GaN/GaN, the value of the dynamic on-resistance can change
clamp circuit, is completely unreliable as it contains a signi- during the on-state due to the current collapse phenomenon
ficant amount of noise. However, the presented voltage clamp [13], [14]. Therefore, to obtain a representative value of the
circuit provides an accurate and clear measurement of the dynamic on-resistance, its average value should be calculated.
on-state drain-to-source voltage waveform Vds that can be This can for example be done on an energy basis, using the
used to determine the dynamic on-resistance Rdyn,on . For the following equation:
voltage measurement with the clamping circuit the Tektronix
differential probe P6251 is used. The drain-to-source voltage Z τon
1
is measured with the Tektronix high voltage probe P5100A. Rdyn,on = Rdyn (t) · i2 (t)dt (5)
I 2 · τon 0
10
with
Vds Z τ
8 1
I = i(t)dt
6
τ 0

where i(t) is the current through the DUT, τ is the period of

4 Vclamp
the waveform and τon is the on time of the DUT.
Vds [V], Ids [A]

0
VI. I NFLUENCING FACTORS ON THE VOLTAGE PEAKS IN
THE CLAMPED VOLTAGE AT THE SWITCHING INSTANTS
−2
Ids As stated before, the voltage peaks in the clamped voltage
−4 can be observed during the switching transitions. The values of
these peaks depend on the high voltage diodes used, and on the
−6
switching times of the measured device. The peaks are higher
−8
0 1 2 3 4 5
if the parasitic capacitance of the high voltage diodes is larger
Time [s] x 10
−7 or when the dv/dt of the switching transitions of the DUT are
Fig. 11: Measurement with presented voltage clamp circuit with BAS21J larger. The first influencing factor, the parasitic capacitance,
diodes (2 MHz) is because capacitances tend to keep the voltage across them
constant. The larger the parasitic capacitance, the higher the
Fig. 12 shows the results for the dynamic on-resistance peaks in the clamped voltage. However, the capacitance of
Rdyn,on during the on-state with and without the use of the diodes is voltage-dependent, and the relationship between the
presented voltage clamp circuit. The dynamic on-resistance voltage peaks and the used high voltage diodes is therefore
determined without the voltage clamp circuit contain a signi- not obvious.
ficant amount of noise throughout the whole on-period of the From Fig. 13, it can be seen that for a mirror current of
DUT. The quantization levels can be clearly distinguished in 10 mA, for a transistor switching at 300 V, the BAS21J
the measurement due to the limited measurement resolution. diode performs best, both for the positive peak and for the
The result for the dynamic on-resistance obtained using the negative peak. A proper choice of the high voltage diodes is
presented voltage clamp circuit contains much less noise and thus of the utmost importance, because the voltage peaks in
gives a very accurate measurement. the clamped voltage decrease the measurement resolution. The
In HEMT devices based on heterostructures such as Al- BY V 26C and the ES1G diodes have a similar performance

0278-0046 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 8

350
with respect to the negative voltage peak, but of the two, the 300 V
ES1G performs slightly better when the transistor switches
300
off.
250 BAS21J
40
BYV26C
BYV26C
ES1G

Vpeak−to−peak
30 200 Direct

20
150
10 BAS21J
300 V
100
0
Vclamped [V]

−10 ES1G 20 V 300 V

50

−20
0
5 10 15 20
−30
Mirror current [mA]

−40 Fig. 14: Peak-to-peak value of the clamped voltage versus the mirror current,
for different high voltage diodes
−50
0 1 2 3 4 5 6 7
Time [s] −7
x 10
are not too high, so that the measurement accuracy is not
Fig. 13: Clamped voltage, for different high voltage diodes (300 V). Peaks
can be observed at the switching instants. They decrease the measurement
compromised.
accuracy
6

A second factor, the large dv/dt, is due to the limitation BAS21J

BYV26C
of the current needed to charge/discharge the parasitic capa- 5
ES1G
Direct
citance of the high voltage diode DA in a short time.
300 V
The resolution improvement calculated by (1) is different 4
for all measured diodes as can be seen from Fig. 14. The
Rdyn [Ω]

higher the peak-to-peak voltage the lower the resolution im- 3

provement. The scale of the oscilloscope should be set to
make the measured waveform fit in the screen. There are 20 V (all diodes and direct measurement) 300 V (BAS21J)
2
two measurements performed, for drain-to-source voltages
of 20 V and 300 V for different high voltage diodes and
mirror currents. For the drain-to-source voltage of 20 V, all 1
300 V
diodes have a very low peak-to-peak voltage resulting in a
high measurement resolution. However, for the drain-to-source 0
5 10 15 20
voltage of 300 V, only the BAS21J has a low enough peak- Mirror current [mA]
to-peak voltage (16.4 V ) to still accurately measure the on- Fig. 15: Dynamic on-resistance versus the mirror current, for different high
voltage. This can be seen in Fig. 15 where the measurements voltage diodes
of the BAS21J at 300 V coincide with the measurements at
low voltage (20 V). The latter suffer less from the decreased
accuracy due to the limited voltage peaks in the clamped
VII. F URTHER REMARKS ON ERROR ANALYSIS
voltage and therefore can be considered as approximating the
dynamic on-resistance well. In section IV, a calculation example was given to determine
In Fig. 14 the peak-to-peak voltage of the directly measured the magnitude of the error of the proposed measurement
drain-to-source voltage is 314.8 V . This results in a resolution circuit. Formula (4) shows that the error consists of two terms.
improvement of 314.8/16.4 = 19.2. Furthermore, from Fig. In the calculation example of section IV, it was assumed that
14, one can also see that the peak-to-peak values of the the two high-voltage diodes where at the same temperature.
clamped voltages are fairly independent of the mirror current Now, we would like to see how the error is influenced by
on the condition that the mirror current is large enough to temperature differences. Taking the same current mirror and
bring the high voltage diodes fully into conduction. high-voltage diodes as in section IV, the first term in the error
Furthermore in Fig. 15, the obtained resistance is more or is, at 25 degrees Celsius:
less the same for all diodes at 20 V, and for the BAS21J diode
at 300 V. It can also be seen that the dynamic on-resistance nkT ∆I
1 = − (6)
is not influenced by the choice of the mirror current. This q I
proves that the presented measurement circuit is robust with 2.584 · 1.38065 · 10−23 · 298.15 0.6
= − (7)
respect to the concrete choice of the mirror current. It is only 1.602 · 10−19 59.7
of importance that the voltage peaks in the clamped voltage = −6.6697 · 10−4 V (8)

0278-0046 (c) 2013 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See
http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 9

The second term is, for a temperature difference of 1 degree: constants keeping the voltage waveform clear, even during
∆T state transitions of the DUT. The performance of the presented
2 = − Vpn,B circuit is illustrated by measurements on a 2 MHz inverted
T
1 buck converter. The dynamic range can be increased by using
= − 0.44 a power converter that switches at higher frequencies and
298.15
= −0.0015 V integrating the measurement circuit on a chip.
Simulations and practical measurements show that the pre-
440 mV is the forward voltage drop at 60 mA; this value sented voltage clamp circuit drastically improves the measure-
can be found in the datasheet of the BAV21 diode. That ment resolution of the on-state voltage waveform. The accu-
means that per degree temperature difference, the second racy of the measurement circuit is assessed, both analytically
term has 0.0015/0.00066697 = 2.21 times more influence. and with simulations. Also, it is observed that the clamped vol-
Temperature difference have therefore the most significant tage exhibits sharp peaks at the switching transitions. Because
effect on the error. Let’s now quantify their influence. For these peaks decrease the accuracy of the measurement circuit,
the BAV21 diode, the thermal resistance between junction their influencing factors are investigated. The peaks occur due
and ambient can be found in the datasheet and is 300 K/W. to the parasitic capacitance of the high voltage diodes. They
A transient thermal impedance is not given so the results can be reduced by choosing diodes with a low capacitance.
discussed below will be worst case. Assume that the DUT The mirror current has little influence on the voltage peaks.
transistor switches with a duty cycle of 50 %. In this case, the
diode A (Fig. 8) is conducting a current of 59.7 mA half the
ACKNOWLEDGMENT
time. The temperature increase of diode A is
The authors would like to thank Kristof Engelen, Peter Tant
0.5 · 300 · 59.7 · 10−3 · 0.44 = 3.9402 K and Jeroen Zwysen from the Department of Electrical Engi-
The temperature increase of diode B, which alternately has to neering (ESAT), KU Leuven, for the valuable and interesting
conduct 60.3 mA and 60.3 + 59.7 = 120 mA, is discussions about this work.

0.5 · 300 · 60.3 · 10−3 · 0.44 + R EFERENCES

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http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI
10.1109/TIE.2014.2349876, IEEE Transactions on Industrial Electronics
IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS 10

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Ratmir Gelagaev (S’07) was born in 1983 in

Grozny. He received the MSc degree in Electrotech-
nical Engineer in 2007 from the Catholic University
of Leuven (KU Leuven), Belgium where he is cur-
rently working towards a PhD in Electrotechnical
Engineering at the Research Group ELECTA, KU
Leuven. His interests are high frequency power
electronics, measurement techniques, modeling of
active and passive components, design and multi-
objective optimization of power electronic convert-
ers. His research focuses on the development of high
frequency power converters, gate drivers and measurement circuits.

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