Lab 12
Lab 12
Lab 12
University of Engineering
&
Technology, Taxila
DSD
Lab Manual# 12
GROUP NO 3
6 SEMESTER
TH
OMEGA SECTION
SUBMITTED TO: ENGR.ASGHAR ISMAIL
Dated;
18/07/2023
LAB MANUAL NO 12
Objective:
Designing, Simulating and Implementing the Verilog Code for Stopwatch
Procedure:
Following is Procedure for Implementation on FPGA kit
Writing the Source Code of module and simulating it
Opening Elaborated Design
Setting Constraints
Running Synthesis
After Successful Synthesis Running Implementation
After Successful Implementation Generating Bit Stream
Downloading Bit Stream to FPGA kit using Hardware Manager
Apparatus List:
Verilog HDL
FPGA Development Board
Xilinx Vivado or any other Verilog simulation and synthesis tool
TASK
Verilog Code for Stopwatch.
Verilog Code:
Source code Code for sec2
Endmodule
case(state) reset_state:
Code for Toplevel if(start)
begin
state = start_state;
module Top(min2,min1,sec2,sec1,start,stop,rst,clk); end
output [2:0] min2,sec2; output [3:0] min1,sec1; else
input start,stop,rst,clk; begin
wire state = reset_state;
min2CF,min1CF,sec2CF,sec1CF,min2INC,min1INC, end
sec2INC,sec1ENB,min2RST,min1RST,sec2RST,sec1 start_state: if(stop)
RST; begin
state = stop_state;
DataPath end
D1(min2,min1,sec2,sec1,min2CF,min1CF,sec2CF,sec else
begin
1CF,min2INC,min1INC,sec2INC,sec1ENB,min2RST,
state = start_state;
min1RST,sec2RST,sec1RST,clk); end
stop_state: if(stop)
ControlUnit begin
C1(min2INC,min1INC,sec2INC,sec1ENB,min2RST, state = stop_state;
min1RST,sec2RST,sec1RST,start,stop,rst,clk,min2CF end
,min1CF,sec2CF,sec1CF); else
begin
endmodule state = start_state;
end
sec2CF_state: if(sec1CF)
begin
state = sec2CF_state;
end else
begin
state = start_state;
end
min1CF_state: if(sec2CF)
begin
state = min1CF_state;
end begin
state = start_state;
end
min2CF_state: if(min1CF)
begin
state = min2CF_state;
end
else if(min2CF)
begin
state=reset_state;
end
else
begin
state = start_state;
end
endcase
end end
endmodule
RESULTS:
Schematics:
FPGA Implementation:
CONCLUSION:
We can conclude
The stopwatch will continue to increment the number till 59 in sec1 and sec2 respectively and as it hits 59, the
min 1 bit will be set to 1, and will turn min2 bit to 1 as the min 1 bit reaches 9, and will continue to increment
till min1 and min2 bits become 59 respectively. Reset and Stop will work accordingly.