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Published in IET Power Electronics
Received on 20th June 2011
Revised on 28th September 2011
doi: 10.1049/iet-pel.2011.0229

ISSN 1755-4535

Quasi-two-level and three-level operation of a

diode-clamped multilevel inverter using space
vector modulation
G.P. Adam1 S.J. Finney1 O. Ojo2 B.W. Williams1
1
Electronic and Electrical Engineering, Strathclyde University, Scotland, UK
2
Department of Electrical Engineering, Tennessee Technology University, Cookeville, TN, USA
E-mail: [email protected]; [email protected]; [email protected]; [email protected]

Abstract: This study presents space vector-based quasi-two-level operation of a diode-clamped multilevel inverter which
improves dc link utilisation and output voltage quality, and avoids the dc link capacitor voltage balancing problem
experienced with standard multilevel operation. Beside a review of quasi-two-level operation and the capacitor voltage
balancing method, the study presents a detailed discussion on the implementation of space vector modulation and the
selection of switching sequence for a five-level inverter. Additionally, the condition for maximum theoretical modulation
index for space vector modulation is established. A prototype five-level diode-clamped inverter is to experimentally validate
the approach. Also this study extends the concept of quasi-two-level-to-three-level operation of the diode-clamped multilevel
inverter in order to address the shortcomings experienced with quasi-two-level operation, such as low waveform quality and
high switching losses. The validity of three-level inverter operation is confirmed experimentally on a prototype of a five-level
diode-clamped inverter. The study also highlights the limitations of three-level operation of a diode-clamped multilevel inverter.

1 Introduction addition cost; requires fewer capacitors (resulting in small

size) and the device voltage stress is limited to one
Two-level voltage source inverters are commonly used in capacitor voltage. In order to sustain these advantages, the
many applications, ranging from low voltage to high voltage voltage across each dc link capacitor of the diode-clamped
[1 – 5]. In medium- and high-voltage applications, two-level circuit must be maintained at Vdc/(N 2 1), where N is the
converters with series connected devices are preferred number of levels and Vdc is rail-to-rail dc voltage [1– 6].
because of its simple construction, simple to control and The structure has higher stray inductance than other
resilience to ac faults. However, they require large ac filters multilevel topologies.
and transformers with high insulation requirements owing As the number of inverter levels increases, dc link capacitor
to increased dv/dt (resulting from switching a large voltage balancing becomes challenging; being power factor-
voltage step) and have higher switching losses [4 – 9]. The and modulation index-dependent [1, 6]. This means the
alternative approach for generating high voltage is to use a amount of deliverable active power and extractable voltage
multilevel converter [8]. This approach reduces the filtering magnitudes are restricted depending on the inverter
requirements (requires small ac filters), generates high operating point [7– 16]. Since a diode-clamped multilevel
voltage without the need for series connection of the devices, inverter uses the same dc link capacitors as an energy tank
reduces insulation requirements on the interfacing for the all three phases, it requires capacitor voltage
transformer owing to low dv/dt (resulting from the switching balancing strategies that consider the interactive effect of
of small voltage step at reduced switching frequency) and the all three phases.
have lower switching losses [9 – 19]. However, the device There are three approaches commonly used to maintain
count and complexity of the control system increase capacitor voltage balance. The first approach utilises the
significantly; ability to ride through different types of faults addition of small dc offset to the modulating signals of
is in doubt and requires complex capacity voltage balancing the three phases in order to achieve voltage sharing between
methods, which increase with the number of levels. The the dc link capacitors of the diode-clamped inverter [12, 15].
common types of multilevel converters are diode-clamped, However, this approach is viable only in three-phase systems
flying capacitors, cascaded with an electrically isolated dc where the dc offset is cancelled in the line-to-line voltage and
source and a modular converter [20, 21]. no dc will appear in the three-phase load currents. This
Diode-clamped multilevel inverters have received more approach has been established only for three-level diode-
research and industrial attention than other multilevel clamped inverters [known as the neutral-point clamped (NPC)
topologies. This is because of its unique circuit structure inverter] and limits the maximum attainable modulation index
that allows regeneration (bi-directional power flow) at no to 1 2 d, where d is the per unit dc offset [3, 12, 15]. The

542 IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542 –551
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0229
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authors in [22–24] demonstrate the possibility of using dc offset This paper describes the principle of quasi-two-level
to balance the dc link capacitors of the active NPC converter operation of the diode-clamped multilevel inverter where
with more than three level. However, the main drawback of space vector modulation is used rather than SPWM. Space
the active NPC converter with more than three levels is that it vector modulation is adopted in order to extend the
requires a number of series-connected switching devices in modulation index linear range, where capacitor balancing is
the inner clamping paths and in the main converter arm. In based on the state dwelling time. The validity of the
practice, this may necessitate the use of voltage sharing presented results is confirmed using experimentation.
mechanism such as active or passive snubber circuits, which
is undesirable. Also it lacks modularity as the converter
switches are rated differently as they experience different 2 Quasi-two-level operation
voltage stresses. The authors in [25] propose an optimised
pulse pattern to achieve near uniform distribution of switching Fig. 1 shows one-phase of a five-level diode-clamped
losses between the converter switches, hence facilitating an inverter. This diode-clamped circuit version ensures the
approximately modular thermal circuit design. However, the voltages across the switching devices and clamping diodes
authors have not addressed the problems related with series are limited to one capacitor voltage and eliminates the need
device connection. This may limit the active NPC converter to for series connection of clamping diodes. When this diode-
medium-voltage applications. clamped circuit is operated in quasi-two-level mode, the dc
The second balancing approach uses the redundant state link nodes 1 – 3 are utilised to generate intermediate voltage
vectors of the multilevel space vector modulation that levels in order to achieve a stepped transition between
generate the same line-to-line voltage with opposite effect the voltage levels +1/2Vdc and 21/2Vdc , in which the
on the dc link capacitors of the diode-clamped inverter [6, intermediate voltage levels are held for minimum dwell
19]. As the number of inverter levels increases, the usable time compatible with the recovery of the clamping circuit
redundant states that guarantee voltage balance, with [16, 21, 22]. The use of the step waveform approach within
minimum number of switching transitions within one each switching cycle allows the inverter switching devices
switching cycle, tend to move towards the centre of the to operate based on the principle of minimum switching
space vector diagram (in the area corresponding to lower losses that guarantee the switching of one voltage level in
modulation index) [6, 16]. This limits the maximum each switching instant. As a result the overall dv/dt is
achievable modulation index and results in poor harmonic reduced [16]. However, the effective switching frequency
performance. Also with increased levels, the number of per switch is the same as the two-level inverter (this may
redundant states increases exponentially, making the use of increase the switching frequency considerably). This
space vector modulation impractical. approach also eliminates the need for series connection of
The third approach uses auxiliary balancing circuitry to the devices and capacitive snubber circuits.
maintain the correct voltage sharing between the dc link
capacitors [3, 12, 14, 15]. This approach has been proven
practically with three- and five-level inverters (single phase
and three phase), however, it adds cost, losses and
complexity to the control system. Since this paper is
concerned with the diode-clamped inverter, the other
topologies are not pursued here.
Quasi-two-level operation of a five-level diode-clamped
inverter has been proposed [16, 20] as a potential alternative
to standard multilevel operation which is hampered by the
capacitor voltage balancing problems. In these references,
the authors use sinusoidal pulse-width modulation (SPWM)
based on regular sampling. It is demonstrated that the
maximum attainable modulation index for quasi-two-level
operation with SPWM is 0.937 without pulse dropping for
unity power factor with a dwelling time of 5 ms [16]. The
key objectives of the quasi-two-level operation of a diode-
clamped multilevel inverter are [16, 20]:

† Improves the dc link voltage utilisation of the diode-

clamped inverter with more than three-levels in applications
involving large amounts of real power (operation with high
power factor and high modulation index).
† Avoids the dc link capacitor voltage imbalance associated
with standard multilevel operation.
† Instead of switching the output phase between 0 and Vdc as
in two-level inverter case, the intermediate nodes of the dc
link capacitors are utilised to generate intermediate voltage
levels; these voltage levels are used to achieve smooth
transition between voltage levels 0 to Vdc (this reduces dv/dt
as a result of small voltage steps). The capacitive clamps
perform a controllable soft clamping function.
† Reduces dc link capacitor size, which results in lower
clamping circuit stray inductance and small inverter footprint. Fig. 1 One-phase leg of a five-level diode-clamped inverter

IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542–551 543

doi: 10.1049/iet-pel.2011.0229 & The Institution of Engineering and Technology 2012
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Fig. 3 Five-level space vector diagram

sector. Thus, the switching sequence when the voltage

vector is located in the first sector will be

000  100  200  300  400  410  420 

430  440  441  442  443  444//444 
Fig. 2 Phase voltage referred to neutral point (node 2) and
443  442  441  440  430  420 
currents drawn from the dc link nodes
410  400  300  200  100  000

The average currents drawn from the intermediate dc link

nodes 1 –3 with the first method in the first sector can be
Since quasi-two-level operation does not utilise the full expressed as follows
potential of multilevel modulation, it produces lower-quality
output voltage compared to full multilevel operation for the ⎡ ⎤ ⎡ ⎤⎡ ⎤
i1 d100 d410 d420 ia
same number of levels and switching frequency. However,
⎣ i2 ⎦ = ⎣ d200 d420 d442 ⎦⎣ ib ⎦ (1)
it represents a practical compromise between a multilevel
inverter operation and two-level inverter operation. i3 d300 d430 d443 ic
During the switching transition of the output voltage from
0 to Vdc and vice versa, the dc link nodes 1 – 3 are loaded with Since the dwell time at nodes 1–3 are set the same, Td , within
a short pulse current of dwell duration of Td with an average each switching cycle, the average currents drawn from
magnitude of iaTd/Ts , where ia is the phase current and Ts is these nodes must be zero according to i1 = i2 = i3 =
the switching cycle. As a result, the current shape drawn d(ia + ib + ic ) = 0, where d ¼ (Td/Ts). Theoretically, this
from these nodes are a sampled version of the load currents means the dc link of a five-level inverter when operated in
as shown in Fig. 2. Since the intermediate dc link nodes quasi-two level will remain balanced, as with a standard three-
(1 – 3) are used only for short durations, the energy drawn level inverter (assumes perfect modular without errors in
from the dc link capacitors is much smaller than with full calculations of switching instants over full fundament period,
multilevel operation; as a result, capacitor voltage balancing ignoring non-linearity of the switching devices, and equal dc
issues are significantly reduced. link capacitors). Practically, a capacitor voltage-balancing
strategy is needed to ensure correct voltage sharing between
the dc link capacitors under all practical cases, such as
3 Space vector pulse-width modulation transient conditions, load imbalance and imperfect modulators.
implementation of quasi-two-level operation The second space vector modulation (SVM) method
considers each sector of the space vector diagram to be
Quasi-two-level operation of multilevel inverters can be comprised of many layers. For example, in a five-level
implemented using regular sampled SPWM, selective inverter case, Fig. 3, the first sector comprises four layers A,
harmonic elimination or space vector modulation. However, B, C and D. Therefore the switch sequence is determined
space vector pulse-width modulation is considered in this based on the location of the target voltage vector within the
paper for the reasons previously given. Quasi-two-level sector. For example, if the target voltage vector is located in
operation using space vector modulation can be realised by layer D, the resultant switching sequence is the same as the
two different methods. The first method ignores the internal first method. If the voltage vector is located in layer C, there
triangular regions within each sector of the space vector two possible switching sequences:
diagram in Fig. 3. Instead each sector of space vector
diagram is treated as one triangular region. The switch (i) 000  100  200  300  310  320  330 
states on the circumference of the main triangular region are 331  332  333//333  332  331  330  320 
used regardless of the voltage vector location within each 310  300  200  100  000.

544 IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542 –551
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0229
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(ii) 111  211  311  411  421  431  441  vector diagram in Fig. 3. In this sector, the maximum duty
442  443  444//444  443  442  441  431  cycle, based on two-level space vector modulation, is
321  411  311  211  111.

1 1 1 T1 T2
If the reference voltage vector is located in layer B, three D = [T1 + T2 + T0 ] = 1 + + (5)
Ts 2 2 Ts Ts
possible switching sequences can be formed, in similar way
as for layer B, but requires fewer switch states. Therefore
Substituting (4) into (5), the following expression for duty
the second method may produce lower switching losses at
cycle is obtained
medium and lower modulation indices as a result of a
1  p 
considerable reduction in the number of switching
transitions required per switching cycle. The average D= 1 + ma sin u + (6)
currents drawn from the dc link nodes 1 – 3, with the 2 3
sequence (i), can be expressed as
For fixed dwell times, the condition for maximum modulation
⎡ ⎤ ⎡ ⎤ index, before over-modulation, can be obtained, without
i1 d100 d310 d331 creating voltage imbalance at the dc link. This condition is
⎢ ⎥ ⎢ ⎥
⎣ i 2 ⎦ =⎣ d200 d320 d332 ⎦ developed when a restriction on maximum allowable pulse
i3 [d300 + d310 + d320 ] 0 −[d330 + d331 + d332 ] width is imposed to prevent pulse dropping and switching of
⎡ ⎤ ⎡ ⎤ more than one voltage levels at any instant (as a result of
ia 0 no time left from the switching cycle to implement the
⎢ ⎥ ⎢ ⎥ dwell times in order to achieve smooth transition during
× ⎣ ib ⎦ = ⎣ 0 ⎦ (2)
the switching)
ic 3d[ia − ic ]
1  p 
Since non-zero current is drawn from node 3 with this 1 + ma sin u + ≤ 1 − 3d (7)
2 3
switching sequence, capacitor i3 will be charged or
discharged depending on the relative direction of i3 . The maximum pulse width is attained when u + ( p/3) ¼ ( p/2),
Similarly, the average currents drawn from dc link nodes therefore the maximum attainable modulation index is
1 – 3 with sequence (ii), when the reference voltage vector is ma , ¼ 1 2 6d. This limit is the same as that achieved with
located in the third layer, can be expressed as SPWM, as demonstrated in [16]. However, the dc link
⎡ ⎤ ⎡ ⎤ utilisation with space vector modulation is better than with
i1 −[d211 + d311 + d411 ] 0 [d421 + d431 + d441 ] SPWM for the same modulation index, which resultsp in
⎢ ⎥ ⎢ ⎥ higher output voltage than SPWM, by a factor of (2/ 3)
⎣ i 2 ⎦ =⎣ d211 d421 d442 ⎦
(which is 15.5% extra).
i3 d311 d431 d443
⎡ ⎤ ⎡ ⎤
ia −3d[ia − ic ] 4 Review of dwell time balancing strategy
⎢ ⎥ ⎢ ⎥
× ⎣ ib ⎦ = ⎣ 0 ⎦ (3)
The balancing strategy maintains voltage sharing between the dc
ic 0 link capacitors by adjusting the voltage output dwell time at
nodes 1–3 [16, 21]. The node dwell times are decided based
When sequence (ii) is used, non-zero current is drawn on the direction of the currents at each node and the voltage
from node 1; as a result, the capacitor C1 will be charged or deviation direction of each dc link capacitor from its reference
discharged depending on direction of i1 . Equations (1) –(3) voltage (1/(N 2 1))Vdc [16]. The voltage deviation of each dc
show the first method always draws zero net currents from link capacitor is defined as DVci ¼ (1/(N 2 1))Vdc 2 Vci , and
dc link nodes 1 – 3. As a result, the first method is expected i ¼ {1, 2, . . . , N 2 1}, that is, DVci ¼ (1/4)Vdc 2 Vci for a
to perform better than the second method in terms of dc five-level inverter. Assuming the current directions in
link capacitor voltage balancing. Based on the balancing Fig. 1 as positive and the maximum and minimum dwell
grounds, the first method is favoured over the second ^ _
times at each node are T and T , the dwelling time capacitor
method in avoiding severe dc link capacitor voltage voltage balancing strategy is summarised as [16]:
imbalance problems.
Since the switch states on the circumference of each sector ^
1. DVci × Ii , 0, set Td = T .
are normally utilised, calculation of dwell times T1 , T2 and T0 _
corresponding to the main voltage vectors V1 , V2 and V0 based 2. DVci × Ii . 0, set Td = T .
on two-level space modulation. Therefore T1 , T2 and T0 are
given by For more details on the dwell time control-balancing
strategy, refer to [16, 21].
p
T1 = ma Ts sin −u
3 5 Performance evaluation of quasi-two-level
(4) operation
T2 = ma Ts sin u
T0 = Ts − T1 − T2 This section evaluates the performance of space vector
 √

 modulation-based quasi-two-level operation of a five-level

where ma = 2/ 3 (Vref /Vdc ) is the modulation index. diode-clamped inverter. The prototype five-level diode-
In order to establish the theoretical maximum modulation clamped inverter has 470 mF dc link capacitors, illustrating
index limit for space vector-based quasi-two-level operation the reduction achievable in dc capacitor size. Note that the
of a five-level inverter, consider the first sector of the space capacitors labelled Cx1 – Cx6 are 10 nF high-frequency

IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542–551 545

doi: 10.1049/iet-pel.2011.0229 & The Institution of Engineering and Technology 2012
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Fig. 4 Prototype and waveforms obtained when modulation index is 0.8 and load power factor is 0.95 lagging (static load with R ¼ 18 V and
L ¼ 12.5 mH), dc link voltage of 200 V and 2.1 kHz switching frequency
a Prototype of a five-level diode-clamped inverter. Scale (10 ms/div, 100 V/div)
b Phase currents. Scale (2.5 ms/div, 2A/div)
c Phase voltage referred to negative bus and node currents I1 , I2 and I3 (dc link voltage is 300 V)
d Phase voltage referred to negative bus and dc link node currents I4 and I0 within one switching cycle (dc link voltage is 300 V). Scale (10 ms/div, 100 V/div)
e Line-to-line voltage (dc link voltage is 200 V). Scale (2.5 ms/div, 100 V/div)
f Spectrum of line voltage. Scale (1.25 kHz/div, 10 dB/div)
g Voltage across dc link capacitors

546 IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542 –551
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0229
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metallised polypropylene capacitors to counter the effects of
stray and parasitic inductance. The switching frequency and
dwell time are 2.1 kHz (476 ms switching cycle) and 5 ms,
respectively. This switching frequency is selected to be a
multiple of six times the fundamental frequency
(7 × 6 × 50 Hz, i.e. seven switching cycles per sector) in
order to avoid switching of more than one leg at the same
time during a transition between sectors. The maximum and
minimum dwell times are 3 and 5 ms. Space vector pulse-
width modulation is implemented using a 32 bits
microcontroller, TC1796 tri-core, from Infineon, with a
2.5 ms dead time. Fig. 4 shows a prototype of a five-level
diode-clamped inverter and results when the modulation
index is 0.8 with 0.96 load power factor lagging. Fig. 4b
shows five-level diode-clamped inverter operated in quasi-
two-level mode produces good quality of the load current at
a 2.1 kHz switching frequency. Fig. 4c demonstrates that
the principle of minimum switching loss is ensured during
the output phase voltage transition from 0 to Vdc and vice
versa. This is important because it ensures switching of
small voltage steps as with standard multilevel modulation;
therefore the load may experience low dv/dt. Figs. 4c and d
show phase voltage within one switching period referred
to as negative bus and current waveforms at dc link nodes
0 – 4. It can be observed that the practical plots are inline
with theoretical plots in Fig. 2. Figs. 4e and f show the
line-to-line output voltage and its spectrum. The absence of
first switch component is observed while the sidebands
remain, as expected with space vector modulation. This
places most of the harmonic energy in the second switching
frequency harmonic component and its sidebands, which
are sufficiently separated from the power frequency range
and readily filtered using small ac filters or even phase
inductances in machine drives applications. The voltage
balance of the dc link capacitors of the five-level inverter is
maintained 1/4Vdc as demonstrated in Fig. 4g.
Figs. 5 and 6 show the voltage across the dc link capacitors
at different modulation indices and load power factors. These
results confirm the benefits of quasi-two-level operation in
terms of extending the modulation range where the five-
level inverter can operate independent of load power factor. Fig. 5 Waveforms demonstrating the limitation imposed by
Fig. 5 shows that despite quasi-two-level operation of modulation index on the capacitor voltage balancing of a five-
diode-clamped multilevel inverters the loading on the dc level diode-clamped inverter operated in quasi-two-level mode
link capacitors is not increased, and as with standard
a M ¼ 0.7, pf ¼ 0.96 lag and Ia ¼ 2.7 A (rms)
multilevel operation, dc link capacitor voltage balancing b M ¼ 0.9, pf ¼ 0.96 lag and Ia ¼ 3.49 A (rms)
remains modulation index-dependent. However, this c M ¼ 0.95, pf ¼ 0.96 lagging, dc link voltage is 200 V and load current
dependency is related to the dwell time employed in the Ia ¼ 2.45 A (rms)
implementation as demonstrated by (7). Figs. 5a and b Scale (x-axis: 2.5 ms, y-axis: 50 V/div)
show that the dc link capacitor voltages of the five-level
diode-clamped inverter operated in quasi-two-level
mode remains stable at 1/4Vdc when 0.7 and 0.9 modulation results obtained at a 0.9 modulation index and load power
indices are used, with a 0.96 load power factor lagging factors of 0.75, 0.9 and 0.96 lagging, respectively.
in both cases. Fig. 5c shows the dwell time control Also the quasi-two-level operation of a five diode-clamped
adopted fails to maintain dc link capacitor voltage inverter permits the use of small dc link capacitances
balancing at 1/4Vdc when the modulation index exceeds the (470 mF). This is a significant reduction, compared to that
theoretical limit previously established. Nonetheless, required for full multilevel operation, which may result in a
the achievable modulation index is much higher than smaller inverter footprint. Such a feature is invaluable in
that possible with standard modulation operation. It applications where space is expensive, such as in ships and
has been established that the maximum attainable the aerospace industry.
modulation for the five-level diode-clamped inverter with a
5 ms dwell time; this limit may be increased if smaller
dwell times are employed or relative lower switching 6 Three-level operation of a diode-clamped
frequency is used. multilevel inverter
Fig. 6 demonstrates that the dc link capacitor voltage
balancing of the diode-clamped multilevel inverter is In an attempt to improve output voltage waveform quality
independent of load power factor. Figs. 6a – c illustrate the and reduce switching losses, three-level operation of

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doi: 10.1049/iet-pel.2011.0229 & The Institution of Engineering and Technology 2012
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Fig. 7 Phase voltage and space vector diagram for three-level

operation of a five-level diode-clamped inverter
a Expanded version of phase voltage referred to node 2
b First sector of space vector diagram of a five-level inverter

21/2Vdc) to 2 (voltage level 0) through node 1 (voltage level

Fig. 6 Voltages across dc link capacitors at different modulation 21/4Vdc) and between nodes 2 –4 (voltage level +1/2Vdc)
indices and load power factors (dc link voltage of 200 V and through node 3 (voltage level + 1/4Vdc). The maximum
capacitance of 470 mF) dwell time at nodes 1 and 3 is Td , which can be adjusted in
order to maintain the voltage balance of dc link capacitors,
Scale (x-axis: 2.5 ms, y-axis: 50 V/div)
a M ¼ 0.9, pf ¼ 0.75 leading and Ia ¼ 2. 35A (rms). M ¼ 0.9, pf ¼ 0.9 taking into consideration the current direction at nodes 1 and
lagging, dc link voltage is 200 V and load current Ia ¼ 2.73A (rms) 3. Node 2 is maintained at 1/2Vdc with respect to both the
b M ¼ 0.9, pf ¼ 0.96 lagging, dc link voltage is 200 V and load current positive and negative dc rail using standard line-to-line
Ia ¼ 3.17 A(rms) voltage redundancy of the three-level diode-clamped
inverter. Fig. 7b shows the five-level inverter space vector
diagram used to achieve three-level operation of the diode-
diode-clamped multilevel inverter is investigated as a potential clamped inverter in Fig. 1. Labels A, B, C and D depicted the
alternative to quasi-two-level operation of diode-clamped regions in the first sector of the five-level space vector
inverters. In a three-level operation mode, the five-level diagram. The switching sequence is selected according to the
diode-clamped inverter in Fig. 1 is operated as a three-level target vector location to besynthesised. For example, if the
inverter, with the switching technique modified to prevent target vector is located in region B, the only possible switching
switching of more than one voltage level during the sequence using symmetrical modulation (three nearest vectors
transition between 21/2Vdc to 0 and 0 to +1/2Vdc through plus one redundant vector) is: 200  300  400  410 
21/4Vdc and +1/4Vdc , respectively (see Fig. 7a). The 420  421  422//422  421  420  410  400 
modification introduced in the switching technique permits 300  200. With this switching sequence, the average currents
smooth transition between the dc link nodes 0 (voltage level drawn from the dc link nodes 1–3 within each switching

548 IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542 –551
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0229
 www.ietdl.org
period are expressed by (9) and (10)
⎡ ⎤ ⎡ ⎤
⎡ ⎤ ⎡ ⎤⎡ ⎤ i1 0 d210 d421
i1 0 d410 d421 ia ⎢ ⎥ ⎢ ⎥
⎣ i2 ⎦ = ⎣ d200 − d422 ⎣ i2 ⎦ = ⎣ d220 + d210 − d422 d420 + d421 + dd320 −d220 ⎦
d420 + d421 0 ⎦⎣ ib ⎦ (8)
i3 i3 d320 0 0
d300 0 0 ic
⎡ ⎤
ia
⎢ ⎥
× ⎣ ib ⎦ (9)
where i1 , i2 and i3 are the average currents drawn
from the intermediate nodes of the dc link 1 – 3 ic
within one switching period, d410 ¼ d421 ¼ d300 ¼ d, and
d200 + d422 ¼ (T1/Ts). T1 represents the time shared ⎡ ⎤ ⎡ ⎤
between the two redundant switch states (200 and 422) i1 0 0 d421
⎢ ⎥ ⎢ ⎥
that represent voltage vector V1 so as to maintain the ⎣ i2 ⎦ = ⎣ −d422 d420 + d421 + d320 d442 − d220 + d432 ⎦
potential of the node 2 at 1/2Vdc with respect to the i3
positive and negative rails. When the target vector is d320 d432 0
located at region C, the two possible switching sequences ⎡ ⎤
ia
using symmetrical modulation are ⎢ ⎥
× ⎣ ib ⎦ (10)
ic
(a) 200  210  220  320  420  421  422//422 
421  420  320 220  210  200. Equation (8) shows that the dc link capacitor voltages can be
(b) 220  320  420  421  422  432  442//442  maintained at 1/4Vdc independent of load power factor only if
432  422  421  420  320  220. d ¼ 0, and the redundant switch states corresponding to
vector V1 (with duty cycles d200 and d422) are utilised to
maintain zero mean current from dc link nodes 1 –3. A
The average currents drawn from nodes 1 – 3 within each similar problem exists when the target located in region C,
switching period when the target vector is located in region with both switching sequences (a) and (b). For this
C and switching sequences (a) and (b) are applied, are reason, the dc link capacitor voltage balancing of the

Fig. 8 Voltage and current waveforms demonstrating the concept of three-level operation of a diode-clamped inverter (dc link voltage is
200 V, switching frequency 2.1 kHz, modulation index, M ¼ 0.9 and load power factor is 0.8 lagging)
a Line voltage (total harmonic distortion (THD) ¼ 29.78%). Scale (x-axis: 5 ms/div and y-axis: 100 V/div)
b Three-phase load currents. Scale (x-axis: 2.5 ms/div and y-axis: 2 A/div)
c Voltage across the four link capacitors. Scale (x-axis: 50 ms/div and y-axis: 20 V/div)

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Fig. 9 Voltage and current waveforms obtained when a three-phase five-level diode-clamped inverter is operated in three-level mode with
200 V dc link, modulation index ¼ 0.8 and power factor ¼ 0.67 lagging)
a Line voltage. Scale (x-axis: 5 ms/div and y-axis: 100 V/div)
b Three-phase load currents. Scale (x-axis: 2.5 ms/div and y-axis: 2 A/div)
c Voltage across the four dc link capacitors. Scale (x-axis: 100 ms/div and y-axis: 10 V/div)

diode-clamped inverter when operated in a three-level mode demonstrated by (8) – (10). This increases the voltage stress
remains power factor-dependent. The times T0 through T5 , across some of the circuit devices. This voltage imbalance
corresponding to voltage vectors V0 through V5 , are increases when the power factor approach unity. Fig. 9
calculated using standard three-level space vector shows the results obtained when a five-level inverter is
modulation, then the dwell time Td is introduced at states, operated in three-level mode with 0.8 modulation index and
such as (300, 411), 410 and (310, 421), to allow smooth 0.67 power factor lagging. These results show that the
transition between 200– 400, 400– 420 and 420– 422 quality of current waveforms is improved and distribution
without switching of two voltage levels. As a result, low of the dc voltage across the four dc link capacitors voltages
dv/dt and low switching losses are possible owing to a is better compared to that in Fig. 8c. This demonstrates that
significant reduction in a number of switch states required the capacitor voltage balancing of the diode-clamped
per switching period. In general, it can be noticed that inverter operated in three-level mode is power factor-
three-level operation of diode-clamped multilevel inverters dependent as in standard multilevel operation of diode-
is only possible when number of levels is odd. clamped inverter with more than three levels. The only
difference is that the mean currents drawn from the nodes 1
and 2 are smaller than that with full multilevel operation.
7 Performance evaluation of three-level The lower averages node currents result in relatively smaller
operation voltage drift from the desire set point. However, the voltage
drift from 1/4Vdc is worse at unity power factor. Also it can
Fig. 8 shows the results obtained when a five-level diode- be noticed that the dc link capacitors voltage ripple with
clamped inverter is operated in a three-level mode with a three-level operation is large despite the use of relatively
modulation index of 0.9, feeding a three-phase static load large capacitance compare to that use for quasi-two-level
with 0.8 power factor lagging. Three-level operation of the operation.
five-level diode-clamped inverter is implemented using
space vector modulation as explained above, with a
switching frequency of 2.1 kHz and dc link capacitance of 8 Conclusions
2.2 mF. Figs. 8a– c show the line voltage, load current and
dc link capacitor voltages. It is observed that three-level This paper investigates the use of space vector modulation-
operation of the diode-clamped inverter produces voltage based quasi-two-level operation of diode-clamped inverter
and current waveforms with limited distortion, and the dc to maximise dc link utilisation, reduce dc link capacitance,
link capacitor voltages are not equally distributed across the avoid dc link capacitor voltage imbalance and improve the
four dc link capacitors as shown in Fig. 8c. This is because quality of output voltage by placing the dominant harmonic
the mean currents from the dc link nodes 1 and 3 cannot be components beyond and around second switching frequency
forced to zero for non-zero values of dwell time as components. This approach produces an inverter viable for

550 IET Power Electron., 2012, Vol. 5, Iss. 5, pp. 542 –551
& The Institution of Engineering and Technology 2012 doi: 10.1049/iet-pel.2011.0229
 www.ietdl.org
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doi: 10.1049/iet-pel.2011.0229 & The Institution of Engineering and Technology 2012