Logic Circuits Design Experiment1 2023
Logic Circuits Design Experiment1 2023
Logic Circuits Design Experiment1 2023
Complementary
Transistor-tra Emitter-coupled Metal-oxide
metal-oxide
nsistor logic logic semiconductor
semiconductor
TTL and ECL are based upon bipolar transistors. TTL has
a well-established popularity among logic families. ECL is
used only in systems requiring high-speed operation. MOS
and CMOS, are based on field effect transistors. They are
widely used in large scale integrated circuits because of their
high component density and relatively low power
consumption. CMOS logic consumes far less power than MOS
logic.
There are various commercial integrated circuit chips
available. TTL ICs are usually distinguished by numerical
designation as the 5400 and 7400 series. The former has a wide
operating-temperature range, suitable for military use, and the
latter has a narrower temperature range, suitable for industrial
use. The power supply for TTL ICs usually is 5V. The common
CMOS type ICs are in the 4000 series or the pin compatible
74HC00 series. The power supply for CMOS ICs ranges from
3V to 15V. The common ECL type is designated as the 10,000
series.
2
This figure shows the TTL level specifications for logic High
and Low. Also shown are the normal values for V cc and ground.
3
Propagation delay is the time delay for a signal transition
to propagate from input to output when the binary input
signals change in value. The signals passing through a gate
take a certain amount of time to propagate from its inputs to
the output. This interval of time is defined as the propagation
delay of the gate. Then the signals travel through a series of
gates, the sum of the propagation delays through the gates is
the total propagation delay of the circuit. Both input and
output signals are not ideal signals, i.e. they have finite rise
and fall times. Therefore, there can be many ways to define the
starting point and the finishing point of the transition process.
Generally speaking, the starting point of the transition process
depends upon the threshold point of the gate in question, and
the finishing point of the transition process depends upon the
threshold point of the following gate. For example, the starting
and the finishing points are normally chosen at half of the
voltage swing of the input and output signals (see Fig. 2). It
should be noted that the transition period for the rising and
falling edges of the same gate may not necessarily be the same,
although it is normally desirable to have a symmetrical
transition.
Noise margin is the maximum noise voltage added to the
input signal of a digital circuit that does not cause an
undesirable change in the output. There are two types of noise
to be considered. DC noise is caused by a drift in the voltage
levels of a signal. AC noise is a random pulse that may be
created by other switching signals. Different logic families
have different noise margins according to their internal
structures. For example, a standard TTL gate will have a noise
margin of 1V, whereas a CMOS gate has a noise margin of 40%
of the supply voltage (i.e. if VDD = 5V, its noise margin is 2V).
4
Gates are electronic circuit that produces output signal
when one or more specified inputs conditions are met.
0 0 0
0 1 1
1 0 1
1 1 1
Source: Signetics 2007
Note: If any input is logic 1, then the output of an OR gate will be logic 1.
1 0 0
1 1 1
Note: The AND Gate requires all inputs to be logic 1 for an output of
logic 1.
5
Truth Table Logic Symbol Circuit Diagram
Input Output
A B X
0 0 1
0 1 0
1 0 0
1 1 0
Source: Signetics 2007
Note: When all inputs are logic 0, the output of a NOR Gate is logic 1.
0 0 1
0 1 1
1 0 1
1 1 0
Source: Signetics 2007
Note: The output of a NAND Gate is logic 0 if all inputs are logic 1.
6
Truth Table Logic Symbol Circuit Diagram
Input Output
A B X
0 0 0
0 1 1
1 0 1
1 1 0
Source: Signetics 2007
Safety Considerations
7
package. The digital integrated circuit below shows the typical
packaging of IC (integrated circuitry) used in digital electronics,
where multiple devices might have several inputs and outputs in
one package. The standard configuration allows for the supply of
power to operate the devices through pin 14 and the common
connection through pin 7. Other pin connections will vary
according to the type of device.
8
This figure shows the connections between the various rows and
columns of holes on a standard bread board.
9
Name: ______________________________ Rating: _________________
Instructor: _________________________ Schedule: _____________
Experiment No. 1
LOGIC INVERTER
I. OBJECTIVE:
II. MATERIALS:
III. PROCEDURES:
Switch Position VI VO
Up
Down
10
b. What are the two output voltage levels assuming
positive logic?
Input Output
1
0
11
input will come from logic SW1 and output will be
displayed on LED indicator L1. Apply the logic voltage to
the input as shown in Table 1-2 and measure the
corresponding output voltages. Record results in Table 1-2.
Does the circuit invert? _______
Table 1-2
Binary 0 ( ) volt/s
Binary 1 ( ) volt/s
10. Wire the circuit shown in Figure 1-5. How many inverters
are cascaded? ________________
VCC
+5V
vcc 1 K-ohms VO
+5v
4.7 K-ohms
VI
SW
Figure 1-1
12
VCC
+5V
vcc 1 K-ohms
+5v
VO
4.7 K-ohms
VI
SW
Figure 1-2
VCC
+5V
1 K-ohms
vcc L2
+5v 1 K-ohms
4.7 K-ohms
4.7 K-ohms
SW
L1
Figure 1-3
SW1
Figure 1-4
13
+5v
L2
SW
L1
Figure 1-5
V. OBSERVATION:
14
VI. CONCLUSION:
15