A Low Power Two Stages CMOS OpAmp

Heng Liu, Student Member, IEEE

Shanghai Jiao Tong University, Center of Analog/RF Integrated Circuit (CARFIC), Shanghai, China
E-mail: [email protected]

Abstract—This is the design report for a two-stage Miller A. Large Signal Analysis
compensated OpAmp, using the gm/Id method. The amplifier
is designed for 0.18µm technology, and is simulated and char-
First of all, the input common mode range (ICMR) should
acterized using Cadence Virtuoso and Spectre design tools. In be analyzed, because it is a key factor in low power supply
this design, high gain and low power consumption are priorities. circuit. The maximum CM voltage in Fig.1 is
The result shows that the DC gain of the OpAmp is 67 dB, the
bandwidth is 6.27 kHz, the GBW is 16.6 MHz, the phase margin VDD − VGS3 + VT H , (1)
is 69.57 degree, the slew rate 12.15 V /µs when driving a 1 pF
load capacitance. Furthermore, the input referred noise voltage while the minimum CM voltage is
√
is 45.9 nV / Hz, the CMRR is 55 dB, the PSRR is 83.6 dB, and
the total power consumption is 42 µW .
VGS1 + VGS5 − VT H , (2)
Keywords—OpAmp, Miller Compensation, CMOS, gm/Id. which means the ICMR is
VGS1 + VGS5 − VT H ≤ Vin,CM ≤ min{VDD − VGS3 + VT H }.
I. I NTRODUCTION (3)

The specified circuit is in Fig. 1. Generally, it is called B. Small Signal Analysis

Operational Amplifier (OpAmp), which is widely used in The small signal model is shown in Fig. 2, where
analog design. In this report the detailed analysis and design 1 1
procedure will be presented for the specs as follows: R1 = ro1 |ro3 | ≈ , (4)
gm3 gm3
• Differential voltage gain Av ≥ 1000;
R2 = ro2 |ro4 , (5)
• GBW ≥ 1 MHz;
• Load capacitance CL = 1 pF ; R3 = ro6 |ro7 , (6)
• Phase margin ≥ 60 degree;
and,
• Slew rate ≥ 10 V /µs;
C1 ≈ Cgg3 + Cgg4 , (7)
• Power supply VDD = 1.8V ;
• Power consumption as low as possible. C2 ≈ Cgg6 , (8)
C3 ≈ CL . (9)

Fig. 2. Complete small signal model

To simplify it, assume C1 = 0, then

Vin gm1 Vin
V1 = gm1 R1 = , (10)
2 gm3 2
Fig. 1. Operational Amplifier cell gm1 Vin Vin
gm4 V1 = gm4 = gm1 , (11)
gm3 2 2
because gm3 = gm4 .
As a consequence, Fig. 2 could be safely reduced to Fig. 3,
II. O PA MP A NALYSIS where
gmI = gm1 = gm2 , (12)
In this section, the OpAmp is analyzed both in large signal
and small signal. gmII = gm6 , (13)
 RI = ro2 |ro4 , (14) Considering the stability, if 60 degree of phase margin is
required, and the RHP zero is placed 10 times beyond GBW,
RII = ro6 |ro7 , (15)
then
CI ≈ Cgg6 , (16) GBW GBW GBW
arctan( ) + arctan( ) + arctan( ) ≤ 120o ,
z |p1 | |p2 |
CII ≈ CL . (17) (26)
which could be written as
GBW
arctan(0.1) + 90o + arctan( ≤ 120o , (27)
|p2 |
GBW
arctan( ≤ 30o − 5.7o = 24.3o , (28)
|p2 |
|p2 | ≥ 2.2GBW. (29)
Take the separation factor χ = 3, then it is not difficult to
obtain that
Fig. 3. Simplified small signal model z = 10GBW ⇒ gmII = 10gmI , (30)
gmI
|p2 | = 3GBW ⇒ Cc = CL = 0.3CL . (31)
gmII
C. Transfer Function
Notice that this circuit also has a mirror zero and a mirror
1) Without Nulling Resistor: The signal flow graph (SFG) pole
without nulling resistor as illustrated in Fig. 4 is analyzed first 2gm3
for convenience, then the equation will be modified to include ZM = − , (32)
Cgg3 + cgg4
the nulling resistor. gm3
ZM = − , (33)
Cgg3 + cgg4
but they are far beyond GBW, so their influence can be
ignored.
2) With Nulling Resistor: These results above coincides
with intuition. Now the nulling resistor is introduced to
eliminate the right half plane (RHP) zero, then the admittance
Fig. 4. Signal flow graph must be replaced with[1]
sCc
The transfer function is , (34)
1s Rz Cc
Vout Ao [1 − s(Cc /gmII )] so the new transfer function becomes
= (18)
Vin 1 + bs + cs2 Vout Ao [1 − sCc (1/gmII − RZ )]
where = , (35)
Vin 1 + bs + cs2 + ds3
Ao = gmI RI × gmII RII , (19)
As a result, the first two poles’ location are close to the
c = RI RII [CI CII + Cc (CI + CII )], (20) original, while the zero is moved depending on RZ :
b = RII (CII Cc ) + RI (CI + Cc ) + RI RII gmII Cc , (21) 1
z= . (36)
Cc (1/gmII − RZ )
the zero
gmII What’s more, the nulling resistor also introduces another
z=+ , (22)
Cc pole
−1
and the poles p3 = . (37)
RZ Cgg6
−1
p1 = Now there are two strategies to choose the value of RZ . On
RII (CII Cc ) + RI (CI + Cc ) + RI RII gmII Cc the one hand RZ = 1/gm6 , to push the zero to infinity, and
(23)
−1 on the other hand RZ ≥ 1/gm6 , to push the zero to LHP. The
≈ ,
RI · gmII RII Cc second method provides a opportunity to eliminate one pole
−gmII Cc −gmII with the zero, which means
p2 = ≈ , (24)
Cc (CI + CII ) + CI CII CII 1 −gmII
= (38)
and GBW Cc (1/gmII − RZ ) CII
1 gmI Cc + CII
ωT = × gmI RI gmII RII = . (25) RZ = . (39)
RI gmII RII Cc Cc gmII Cc
 III. C ALCULATION FOR PARAMETERS Cc is chosen more or less arbitrary to be 350f F , because
In this section, the calculation procedure using gm /ID it is optimal to be around 0.3CL . Then
lookup table are presented step by step for the parameter I5 = 5µA ≥ 3.5µA, (46)
determination.
I6 = 15µA ≥ (10 + 3.5)µA. (47)
A. Gain
D. Parameter Summary
Table. I summarizes the transistors’ sizes obtained from
(gm /ID )2 (gm /ID )6
Ao = gmI RI gmII RII = · ≥ 1000 Fig. 6.
λ2 + λ4 λ6 + λ7
(40)
TABLE I
The maximun value of gm /ID is 25, so (λ2 +λ4 )(λ6 +λ7 ) ≤ PARAMETER S UMMARY
0.625, based on Fig. 5, it’s evident that channel length should
be longer than 260nm. To achieve high transit frequency and Transistor gm /ID Current(µA) gm (Simulation) W/L
small layout area, the channel length should be set to be M1/M2 22 2 41µS 3u/0.26u
260nm. M3/M4 8 2 15µS 0.24u/0.26u
M5/M8 18 4 67.7µS 1.7u/0.26u
M6 18 15 282µS 17.74/0.26u
1.8e-07
2e-07
M7 18 15 283µS 6.4u/0.26u
0.6
2.2e-07
2.4e-07 RZ 4.7 KΩ
0.5
2.6e-07 Cc 350 fF
2.8e-07
3e-07 Rb 321 KΩ
3.2e-07
0.4 3.4e-07
3.6e-07
lambda [1]

3.8e-07
4e-07
0.3
4.2e-07 #10 -4
4.4e-07
1.8
4.6e-07
0.2 4.8e-07 1.6
5e-07
6e-07
1.4
7e-07
0.1
8e-07
9e-07 1.2
1e-06
0
Id/(W/L)

1
0 5 10 15 20 25 30
gm/Id [mS/mA]
0.8

0.6
Fig. 5. λ vs gm /ID
0.4

0.2
Furthermore, to achieve the gain requirement,
0
0 5 10 15 20 25 30
(gm /ID )1,2 = 22, (41) gm/Id [mS/mA]

(gm /ID )6 = 18, (42) Fig. 6. Id/(W/L) vs gm /ID

and consider the matching problem, (gm /ID )7 is set to be
equal to (gm /ID )6 . Also (gm /ID )5,8 is chosen to be 18 to From Table. I the gm6 is also easy to get to calculate nulling
get higher ICMR. resistor
Cc + CII
RZ = = 4.7KΩ. (48)
B. Noise gmII Cc
The input referred noise voltage spectral density is given by Finally, the third pole should be paid extra attention to
16 1 gm3,4 guarantee stability
Sn (f ) = kT (1 + ), (43)
3 gm1,2 gm1,2 1 gm2
Cgg6 / ≫ 10, (49)
RZ Cc
so (gm /ID )1,2 should be much smaller than (gm /ID )3,4 to
meet the noise requirement, namely (gm /ID )1,2 = 8. so the parameters meet the requirement.

C. Slew Rate IV. T ESTBENCH AND S IMULATION R ESULTS

A. Open Loop
I5 Fig. 7 shows the open loop test bench, where a LPF (R =
SRinternal = ≥ 10V /µs, (44)
Cc 1T Ω, C = 1F ) is employed to define the output common
I6 − I5 mode voltage, while the influence of high frequency is filtered.
SRexternal = ≥ 10V /µs. (45) Fig. 8 illustrates that the DC gain equals 69 dB (2818x), BW
CL
 Fig. 7. Open Loop Test bench

Fig. 10. Slew Rate Testbench

Fig. 8. Open Loop Results

is 6.27 kHz, GBW is 16.558 MHz, and the phase margin is

69.57 degree to guarantee stability.
Fig. 9 shows the static current, which accounts for the power
consumption of 42.26 µW . Fig. 11. Slew Rate

What’s more, Fig. 13 shows that the PSRR+ and PSRR- are
calculated individually when small signal is imposed at VDD
or GND.

Fig. 9. Power Consumption

B. Slew Rate
It’s shown in Fig. 10 that when measuring slew rate, a large
pulse should be imposed at the input, and Fig. 11 demonstrates
that the slew rate is 12.15 V /µs.

C. CMRR and PSRR

Fig. 12 provides a method to in one testbench without
simulating ADM and ACM −DM separately.

ACM vCM + Av [vCM − (vOU T − vCM )] = vOU T , (50)

vOU T ACM 1 Fig. 12. CMRR Test bench
≈ = . (51)
vCM Av CM RR
 D. Large Signal
Large signal performance of the OpAmp should be mea-
sured when it’s connected as a unity gain form as shown in
Fig. 16, and sweep the input common mode voltage between
0-1.8 V.

Fig. 16. Unity Gain

Fig. 13. PSRR Test bench Fig. 17 shows that the offset voltage is 3 mV. What’s more,
the ICMR could be measured by looking at the voltage of
M5’s drain, because once the M5 works properly, the OpAmp
Fig. 14 and Fig. 15 show that CMRR is 55 dB, PSRR+ is
works properly, as shown in Fig. 18.
83.6 dB, and PSRR- equals 54.1 dB.

Fig. 17. Offset Voltage

Fig. 14. CMRR Result

Fig. 15. PSRR Result Fig. 18. ICMR Result

E. Noise V. C ONCLUSION
√
Fig. 19 shows that the IRN is 45.9 nV / Hz@1M Hz. In this design, gm/Id method is employed to assist transistor
sizing, and the results demonstrate it a useful tool in analog
design.
And the performance of the Miller OpAmp is summarized
in Table. II.

TABLE II
P ERFORMANCE S UMMARY

DC Gain BW GBW PM
69 dB 6.27 kHz 16.56 MHz 69.57 degree

SR Power CMRR PSRR+

12.15 V /µs 42.26 µW 55 dB 83.6 dB

PSRR- ICMR Vos IRN

√
Fig. 19. IRN Result 54.1 dB 0.5-1.8 V 3 mV 45.9 nV / Hz@1MHz

F. Close Loop ACKNOWLEDGMENT

Fig. 20 and Fig. 21 illustrate the inverting amplifier test The authors would like to thank Prof. Atef and all the
bench and result separately. classmates in CARFIC.
R EFERENCES
[1] G. Palmisano, G. Palumbo, and S. Pennisi, “Design procedure for two-
stage cmos transconductance operational amplifiers: A tutorial,” Analog
Integrated Circuits and Signal Processing, vol. 27, no. 3, pp. 179–189,
2001.

Fig. 20. Inverting Amplifier

Fig. 21. Inverting Amplifier Result