Broatcom Acpl-798j

Data Sheet
ACPL-798J
Optically Isolated Sigma-Delta Modulator with
LVDS Interface
Description Features
The Broadcom® ACPL-798J is a 1-bit, second-order sigma-  Up to 25 MHz external clock input range
delta (Σ-Δ) modulator that oversamples an analog input signal  LVDS clock and data interface.
into a highspeed data stream with galvanic isolation based on
 1-bit, second-order sigma-delta modulator
optical coupling technology. The ACPL-798J operates from a
5 V power supply with dynamic range of 82 dB with an  16 bits resolution no missing codes (12 bits ENOB)
appropriate digital filter. The differential inputs of ±200 mV (full  75 dB Typical SNDR
scale ±320 mV) are ideal for direct connection to shunt  3.5 V/°C maximum offset drift
resistors or other low-level signal sources in applications such  ±1% maximum gain error
as motor phase current measurement.
 ±200 mV linear range with single 5 V supply
The analog input is continuously sampled by means of sigma-  –40°C to +105°C operating temperature range
delta oversampling using external clock, coupled across the  SO-16 package
isolation barrier, which allows synchronous operation with any  25 kV/μs common-mode transient immunity
digital controller. The signal information is contained in the
 Safety and regulatory approval (pending):
modulator data, as a density of ones with data rate up to
25 MHz, and the data are encoded and transmitted across – IEC/EN/DIN EN 60747-5-5: 1414 Vpeak working
the isolation boundary where they are recovered and insulation voltage
decoded into high-speed data stream of digital ones and – UL 1577: 5000 Vrms/1min double protection rating
zeros. The original signal information can be reconstructed – CSA: Component Acceptance Notice #5
with a digital filter. The ACPL-798J comes with an LVDS
interface on both clock inputs and data outputs for better Applications
signal integrity.  Motor phase and rail current sensing
Combined with superior optical coupling technology, the  Power inverter current and voltage sensing
modulator delivers high noise margins and excellent immunity  Industrial process control
against isolation-mode transients. With 0.5 mm minimum  Data acquisition systems
distance through insulation (DTI), the ACPL-798J provides
 General-purpose current and voltage sensing
reliable double protection and high working insulation voltage,
which is suitable for fail-safe designs. This outstanding  Traditional current transducer replacement
isolation performance is superior to alternatives including
devices based on capacitive or magnetic-coupling with DTI in
micro-meter range. Offered in an SO-16 package, the CAUTION! It is advised that normal static precautions be
isolated ADC delivers the reliability, small size, superior taken in handling and assembly of this
isolation and over-temperature performance motor drive
component to prevent damage and/or
designers need to accurately measure current at much lower
price compared to traditional current transducers. degradation which can be induced by ESD.
Broadcom AV02-4339EN
July 19, 2019
ACPL-798J Data Sheet Optically Isolated Sigma-Delta Modulator with LVDS Interface
Functional Block Diagram

V DD1 V DD2
Σ−Δ LED MDAT+

VIN + DECODER
MODULATOR/ DRIVER MDAT-
V IN – ENCODER
SHIELD
BUF
LED MCLKIN+
CLOCK
DETECTOR DRIVER MCLKIN-
V REF SHIELD ACPL-798J
GND1 GND2
Pin Configuration and Descriptions

VDD1 1 ACPL-798J 16 GND2
VIN+ 2 15 NC
VIN− 3 14 VDD2
GND1 4 13 MCLKIN+
NC 5 12 MCLKIN−
NC 6 11 MDAT+
VDD1 7 10 MDAT −
GND1 8 9 GND2
Table 1: Pin Descriptions
Pin No. Symbol Description

1, 7 VDD1 Supply voltage for input side relative to GND1.
2 VIN+ Positive analog input, recommended input range ±200 mV.
3 VIN– Negative analog input, recommended input range ±200 mV (normally connected to GND1).
4,8 GND1 Supply ground for signal input side.
5, 6, 15 NC No connection. Leave floating.
9, 16 GND2 Supply ground for data output side (digital side).
11 MDAT+ Positive LVDS modulator data output.
10 MDAT– Negative LVDS modulator data output.
13 MCLKIN+ Positive LVDS modulator clock input
12 MCLKIN– Negative LVDS modulator clock input
14 VDD2 Supply voltage for output side, referenced to GND2.
2
Table 2: Ordering Information
Option IEC/EN/DIN
Part Number (RoHS Compliant) Package Tape and Reel EN 60747-5-5 Quantity
ACPL-798J -000E SO-16 X 45 per tube
-500E X X 850 per reel
To order, choose a part number from the part number column and combine with the desired option from the option column
to form an order entry.
Example: ACPL-798J-500E to order product in Tape and Reel packaging.
Contact your Broadcom sales representative or authorized distributor for information.
Package Outline Drawings

16-Lead Surface Mount (SO-16)
LAND PATTERN RECOMMENDATION
0.457 1.270 0.64 (0.025)
(0.018) (0.050)
16 15 14 13 12 11 10 9
TYPE NUMBER
DATE CODE
A 798J
LEAD-FREE YYWW 7.493 ± 0.254 11.63 (0.458)
EEE (0.295 ± 0.010)
LOT ID
2.16 (0.085)
1 2 3 4 5 6 7 8
10.312 ± 0.254
(0.406 ± 0.10) ALL LEADS
8.986 ± 0.254
9° (0.345 ± 0.010) TO BE
COPLANAR
± 0.002
0.457 3.505 ± 0.127

(0.138 ± 0.005) 0-8° 0.203 ± 0.076
(0.018) 0.025 MIN. (0.008 ± 0.003)
10.160 ± 0.254 STANDOFF
(0.408 ± 0.010)
Notes:
Dimensions in millimeters and (inches).
Floating lead protrusion is 0.15 mm (6 mils) max.
Initial and continued variation in color of the white mold compound is normal and does not affect performance or reliability of the device.
3
Recommended Pb-Free IR Profile

Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
The ACPL-798J is pending for approvals by the following organizations:
EC/EN/DIN EN 60747-5-5 Approved with Maximum Working Insulation Voltage VIORM = 1414 Vpeak.
UL Approval under UL 1577, component recognition program up to VISO = 5000 Vrms/1 min.
File E55361.
CSA Approval under CSA Component Acceptance Notice #5, File CA 88324.
4
IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa

Descriptiona Symbol Value Unit
Installation classification per DIN VDE 0110/1.89, Table 1
For Rated Mains Voltage ≤ 150 Vrms I-IV
For Rated Mains Voltage ≤ 1000 Vrms I-III
Climatic Classification 55/105/21

Pollution Degree (DIN VDE 0110/1.89) 2
Maximum Working Insulation Voltage VIORM 1414 Vpeak
Input to Output Test Voltage, Method b VPR 2652 Vpeak
VIORM × 1.875 = VPR, 100% Production Test with tm = 1 sec,
Partial Discharge < 5 pC
Input to Output Test Voltage, Method a VPR 2262 Vpeak
VIORM × 1.6 = VPR, Type and Sample Test, tm = 10 sec,
Partial Discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage, tini = 60 sec) VIOTM 8000 Vpeak
Safety-Limiting Values (Maximum values allowed in the event of a failure)
Case Temperature TS 175 °C
Input Currentb IS,INPUT 400 mA
Output Powerb PS,OUTPUT 600 mW
Insulation Resistance at TS, VIO = 500V RS ≥109 Ω
a. Insulation characteristics are guaranteed only within the safety maximum ratings, which must be ensured by protective circuits within the
application.
b. Safety-limiting parameters are dependent on ambient temperature. Refer to Figure 1 for dependence of PS and IS on ambient temperature.
Figure 1: Case Temperature Chart
800
OUTPUT POWER - PS, INPUT CURRENT - IS
PS (mW)
700
IS (mA)
600
500
400
300
200
100
0
0 25 50 75 100 125 150 175 200
TS - CASE TEMPERATURE - oC
5
Insulation and Safety Related Specifications

Parameter Symbol Conditions Value Unit
Minimum External Air Gap L(101) Measured from input terminals to output terminals, 8.3 mm
(External Clearance) shortest distance through air.
Minimum External Tracking L(102) Measured from input terminals to output terminals, 8.3 mm
(External Creepage) shortest distance path along body.
Minimum Internal Plastic Gap Through insulation distance, conductor to conductor, 0.5 mm
(Internal Clearance) usually the direct distance between the photoemitter
and photodetector inside the optocoupler cavity.
Tracking Resistance CTI DIN IEC 112/VDE 0303 Part 1. >175 V
(Comparative Tracking Index)
Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1). IIIa
Absolute Maximum Ratings

Parameter Symbol Min. Max. Unit
Storage Temperature TS –55 +125 °C
Ambient Operating Temperature TA –40 +105 °C
Supply Voltage VDD1, VDD2 –0.5 6.0 V
Steady-State Input Voltage a, b VIN+, VIN– –2 VDD1 + 0.5 V
Two-Second Transient Input Voltagec VIN+, VIN– –6 VDD1 + 0.5 V

Digital Input/Output Voltages MCLKIN, MDAT –0.5 VDD2 + 0.5 V
Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane
a. DC voltage of up to –2V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
b. Absolute maximum DC current on the inputs = 100 mA, no latch-up or device damage occurs.
c. Transient voltage of 2 seconds up to –6V on the inputs does not cause latch-up or damage to the device; tested at typical operating conditions.
Recommended Operating Conditions

Parameter Symbol Min. Max. Unit
Ambient Operating Temperature TA –40 +105 °C
VDD1 Supply Voltage VDD1 4.5 5.5 V
VDD2 Supply Voltage VDD2 3.0 5.5 V
Analog Input Voltagea VIN+, VIN– –200 +200 mV

a. Full scale signal input range ±320 mV.
6
Electrical Specifications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 3.0V to 5.5V, VIN+ = –200 mV to +200 mV, and
VIN– = 0V (single-ended connection); tested with Sinc3 filter, 256 decimation ratio, fMCLKIN = 20 MHz.
Parameter Symbol Test Conditions Min. Typ.a Max. Unit Notes Fig.
Static Characteristics
Resolution Decimation filter output set to 16 bits. 16 — — Bits
Integral Nonlinearity INL TA = –40°C to +85°C; see Definitions. –15 3 15 LSB
TA = 85°C to +105°C. –25 3 25 LSB
Differential Nonlinearity DNL No missing codes, guaranteed by –0.9 — 0.9 LSB
design; see Definitions.
Input Offset Voltage VOS TA = –40°C to +105°C. –1.5 0.6 2.5 mV 6, 7
Input Offset Voltage vs. TCVOS TA = –40°C to +105°C. — 1 3.5 μV/°C 6
Temperature NOTE: Direct short across inputs.
Input Offset Drift vs. VDD1 — 110 μV/V
Gain Error GE TA = –40°C to +105°C, VIN+ = –200 to –2 — 2 % 8
+200 mV; see Definitions.
TA = 25°C, VIN+ = –200 to +200 mV. –1 — 1 % 8
Gain Error Drift vs. Temperature TCGE TA = –40°C to +105°C. — 60 — ppm/°C 8
Gain Drift vs. VDD1 TA = –40°C to +105°C. — 0.15% — %/V 9
Analog Inputs
Full-Scale Differential Voltage FSR Referenced to GND1. — ±320 — mV b
Input Range
Linear Input Range VIN+, Referenced to GND1. — ±200 — mV
VIN–
Average Input Bias Current IINA VDD1 = 5V, VDD2 = 5V, VIN+ = 0V. — –0.5 — μA c
Average Input Resistance RIN Across VIN+ or VIN– to GND1; — 12.5 — kΩ c

FCLKIN = 20 MHz.
Input Capacitance CINA Across VIN+ or VIN– to GND1. — 16 — pF
AC Characteristics
Signal-to-Noise Ratio SNR TA = –40°C to +105°C; see Definitions. 68 82 — dB d
Signal-to- (Noise + Distortion) SNDR TA = –40°C to +105°C; see Definitions. 65 75 — dB d 10,

Ratio 11, 12
Effective Number of Bits ENOB See Definitions. — 12 — Bits
Isolation Transient Immunity CMR VCM = 1 kV, TA = 25°C. — 25 — kV/μs
(CMTI)
Digital Inputs and Outputs
Output differential Voltage Vod Rload = 100Ω; MDAT+ – MDAT–, — 350 — mV e
(MDAT+, MDAT–) VDD1, VDD2 = 5V.
Output Common Mode Voltage Vocm VDD1, VDD2 = 5V. 1 1.25 1.5 V
Output Short Circuit Current IOSD Output shorted to GND. — 3.5 — mA
(MDAT+, MDAT–)
Input Threshold High VthH Referenced to Vocm. — — 100 mV
(MCLKin+, MCLKin–)
7
Parameter Symbol Test Conditions Min. Typ.a Max. Unit Notes Fig.
Input Threshold Low VthL Referenced to Vocm. –100 — — mV
(MCLKin+, MCLKin–)
Power Supply
Input Side Supply Current IDD1 VDD1 = 5.5V. — 15.5 20 mA 13,
14, 15
IDD2 VDD2 = 3.3V. — 14.5 18 mA
VDD2 = 5V. — 17 20 mA 16,
17, 18
a. All Typical values are under Typical Operating Conditions at TA = 25°C, VDD1 = 5 V, VDD2 = 5V.
b. Beyond the full-scale input range the data output is either all zeros or all ones.
c. Because of the switched-capacitor nature of the isolated modulator, time averaged values are shown.
d. Input signal frequency = 1 kHz.
e. Output differential voltage Vod = MDAT+ – MDAT–.
Timing Specifications
Unless otherwise noted, TA = –40°C to +105°C, VDD1 = 4.5V to 5.5V, VDD2 = 3.0V to 5.5V.
Parameter Symbol Test Conditions Min. Typ. Max. Unit Notes Fig.
Modulator Clock Input Frequency fMCLKIN Clock Duty Cycle 40% to 60%. 5 20 25 MHz a
Data Delay upon MCLKIN Input TCS VIN = 0V, VDD1 and VDD2 = 5V, — 150 — μs 2
Startup TA = 25°C.
Data Propagation Delay after TD VIN = 0V, VDD1 and VDD2 = 5V. — 15 — ns a 3
MCLKIN Edge
Data Delay Upon VDD1 Power Up TPS1 VIN = 0V, VDD1 > 3.8V VDD2 supplied, — 250 — μs b 4
MCLKIN active, TA = 25°C.
Data Delay Upon VDD2 Power Up TPS2 VIN = 0V, VDD1 supplied, TA = 25°C, — 165 — μs 5
MCLKIN active.
a. The ACPL-798J has an in-built clock conditioning scheme that makes it tolerant to variations on the input clock duty cycle.
b. When VDD1 is not supplied, MDAT+ is high and MDAT– is low, i.e., modulator output level is 1.
8
Figure 2: Data Delay upon Clock Input Startup Figure 4: Data Delay upon VDD1 Startup
MDAT+
MCLKIN+ MDAT-
MCLKIN-
TPS1
TCS
MDAT+ VDD1
MDAT-
Figure 3: Data Propagation Delay Figure 5: Data Delay upon VDD2 Startup
MCLKIN-
MDAT+
MDAT-
MCLKIN+ TPS2
TD
MDAT+ VDD2
MDAT-
Package Characteristics
Parameter Symbol Test Conditions Min. Typ. Max. Unit Note
Input-Output Momentary Withstand VISO RH ≤ 50%, t = 1 min; TA = 25°C. 5000 — — Vrms a, b
Voltage
Input-Output Resistance RI-O VI-O = 500 Vdc. 1012 1013 — Ω b
TA = 100°C. 1011 — — Ω b
Input-Output Capacitance CI-O f = 1 MHz. — 1.4 — pF b
Input IC Junction-to-Ambient θJAI 1 oz. trace, 2-layer PCB, still air, — 83 — °C/W c
Thermal Resistance TA = 25°C.
Output IC Junction-to- Ambient θJAO 1 oz. trace, 2-layer PCB, still air, — 85 — °C/W c
Thermal Resistance TA = 25°C.
a. In accordance with UL 1577, each optocoupler is proof tested by applying an insulation test voltage ≥6000 Vrms for 1 second. This test is
performed before the 100% production test for partial discharge (method b) shown in IEC/EN/DIN EN 60747-5-5 Insulation Characteristic
Table.
b. This is a two-terminal measurement: pins 1 to 8 are shorted together and pins 9 to 16 are shorted together.
c. Maximum power dissipation in analog side and digital side ICs needs to be limited to ensure that their respective junction temperature is less
than 125°C. The maximum permissible power dissipation is dependent on the thermal impedance and the ambient temperature.
9
Typical Performance Plots

Unless otherwise noted, TA = 25°C, VDD1 = 5V, VDD2 = 5V, VIN+ = –200 mV to +200 mV, and VIN– = 0V, fMCLKIN = 20 MHz,
with Sinc3 filter, 256 decimation ratio.
Figure 6: Offset vs. Temperature Figure 7: Offset vs. MCLKIN Clock
1 1
0.9 0.9
0.8 0.8
0.7 0.7
Offset (mV)
Offset (mV)
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
0.1 0.1
0 0
-40 -20 0 20 40 60 80 100 120 10 15 20 25
Temperature (˚C) Frequency (MHz)
Figure 8: Gain vs. Temperature Figure 9: Gain vs. VDD1
1.00% 0.20%
0.15%
0.50% 0.10%
0.05%
Gain Err (%)
Gain Err (%)
0.00% 0.00%
- 0.05%
-0.50% Vdd1 =5.0 - 0.10%
Vdd1 =5.5
Vdd1 =4.5 - 0.15%
-1.00% - 0.20%
-40 -20 0 20 40 60 80 100 120 4.5 5 5.5
Temperature (˚C) Vdd1 (V)
Figure 10: SNDR vs. Temperature Figure 11: SNDR vs. MCLKIN Frequency
80 85
75 80
75
70
SNDR (dB)
SNDR (dB)
70
65
65
60
Vdd1 = 4.5V 60
55 Vdd1 = 5.0V 55
Vdd1 = 5.5V
50 50
-40 -20 0 20 40 60 80 100 120 10 15 20 25
Temperature (˚C) Frequency (MHz)
10
Figure 12: SNDR vs. Input Voltage VIN Figure 13: IDD1 vs. MCLKIN Frequency
80 18
16
75
14
70 12
SNDR (dB)
Idd1 (mA)
10
65
8
60 6
Vin+ = -400mV
4
55 Vin+ = 400mV
2
50 0
100 200 300 400 500 10.00 15.00 20.00 25.00
Vin (Vpp) Frequency (MHz)
Figure 14: IDD1 vs. Input Voltage VIN Figure 15: IDD1 vs. Temperature
16 18
15 17
14 16
13
15
Idd1 (mA)
Idd1 (mA)
12
14
11
13
10
Vdd1 = 4.5V
9 12
Vdd1 = 5.0V
8 11 Vdd1 = 5.5V
7 10
-0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 -40 -20 0 20 40 60 80 100 120
Vin (V) Temperature (˚C)
Figure 16: IDD2 vs. MCLKIN Frequency Figure 17: IDD2 vs Input Voltage VIN
19 18
17 17
16
15
Idd2 (mA)
Idd2 (mA)
15
13
14
11
13
Vdd2 = 5.5V Vdd2 = 5.5
9 12
Vdd2 = 3.0V Vdd2 = 3.0
7 11
10 15 20 25 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4
Freq (MHz) Vin+ (V); Vin– = GND
11
Figure 18: IDD2 vs. Temperature Gain Error

20
18 Gain error is the difference between the ideal gain slope and
16 the actual gain slope, with offset error adjusted out. Gain
14 error includes reference error. Gain error can be corrected
12 by software or hardware.
Idd2 (mA)
10
8
6 Signal-to-Noise Ratio (SNR)
4 Vdd2 = 5.5V
2 Vdd2 = 3.0V The SNR is the measured ratio of AC signal power to noise
0
-40 -20 0 20 40 60 80 100 120 power below half of the sampling frequency. The noise
Temperature(˚C) power excludes harmonic signals and DC.
Definitions Signal-to-(Noise + Distortion) Ratio

(SNDR)
Integral Nonlinearity (INL) The SNDR is the measured ratio of AC signal power to
noise plus distortion power at the output of the ADC. The
INL is the maximum deviation of a transfer curve from a
signal power is the rms amplitude of the fundamental input
straight line passing through the endpoints of the ADC
signal. Noise plus distortion power is the rms sum of all non-
transfer function, with offset and gain errors adjusted out.
fundamental signals up to half the sampling frequency
(excluding DC).
Differential Nonlinearity (DNL)
DNL is the deviation of an actual code width from the ideal Effective Number of Bits (ENOB)
value of 1 LSB between any two adjacent codes in the ADC
The ENOB determines the effective resolution of an ADC,
transfer curve. DNL is a critical specification in closed-loop
expressed in bits, defined by ENOB = (SNDR – 1.76)/6.02.
applications. A DNL error of less than ±1 LSB guarantees no
missing codes and a monotonic transfer function.
Isolation Transient Immunity (CMR)
Offset Error The isolation transient immunity (also known as Common-
Mode Rejection or CMR) specifies the minimum rate-of-rise/
Offset error is the deviation of the actual input voltage
fall of a common-mode signal applied across the isolation
corresponding to the mid-scale code (32,768 for a 16-bit
boundary beyond which the modulator clock or data is
system with an unsigned decimation filter) from 0V. Offset
corrupted.
error can be corrected by software or hardware.
12
Product Overview input range of the modulator (±320 mV); an input range of
±200 mV is recommended to achieve optimal performance.
Users are able to use higher input range, for example ±250
Description mV, as long as within full-scale range, for purpose of over-
current or overload detection. Figure 19 shows the
The ACPL-798J isolated sigma-delta (Σ-Δ) modulator
simplified equivalent circuit of the analog input.
converts an analog input signal into a high-speed (up to
25 MHz) single-bit data stream by means of a sigma-delta Figure 19: Analog Input Equivalent Circuit
oversampling modulator. The time average of the modulator
data is directly proportional to the input signal voltage. The 200Ω (TYP)
VIN+
modulator uses external clock ranges from 5 MHz to
25 MHz that is coupled across the isolation barrier. This fSWITCH
= MCLKIN 3 pF (TYP)
arrangement allows synchronous operation of data 1.5 pF
acquisition to any digital controller, and adjustable clock for
speed requirements of the application. The modulator data COMMON MODE
are encoded and transmitted across the isolation boundary ANALOG VOLTAGE
where they are recovered and decoded into high-speed GROUND
data stream of digital ones and zeros. The original signal fSWITCH 1.5 pF
3 pF (TYP)
information is represented by the density of ones in the data = MCLKIN
200Ω (TYP)
output.
VIN–
The other main function of the modulator (optocoupler) is to
provide galvanic isolation between the analog signal input In the typical application circuit (Figure 22), the ACPL-798J
and the digital data output. It provides high noise margins is connected in a single-ended input mode. Given the fully
and excellent immunity against isolation-mode transients differential input structure, a differential input connection
that allows direct measurement of low-level signals in highly method (balanced input mode as shown in Figure 20) is
noisy environments, for example measurement of motor recommended to achieve better performance. The input
phase currents in power inverters. currents created by the switching actions on both of the pins
are balanced on the filter resistors and canceled out each
With 0.5-mm minimum DTI, the ACPL-798J provides
other. Any noise induced on one pin will be coupled to the
reliable double protection and high working insulation
other pin by the capacitor C and creates only common mode
voltage, which is suitable for fail-safe designs. This
noise which is rejected by the device. The resistors and the
outstanding isolation performance is superior to alternatives
capacitor also forms an anti-aliasing filter for the sigma-delta
including devices based on capacitive- or magnetic-
modulator. Typical value for RA and RB is 22Ω and 10 nF for
coupling with DTI in micro-meter range. Offered in an SO-16
C.
package, the isolated ADC delivers the reliability, compact
size, superior isolation and over-temperature performance Figure 20: Simplified Differential Input Connection Diagram
motor drive designers need to accurately measure current
at much lower price compared to traditional current 5V
transducers. VDD1
Ra
+Analog Input VIN+
Analog Input C
Rb ACPL-798J
The differential analog inputs of the ACPL-798J are –
–Analog Input VIN–
implemented with a fully-differential, switched-capacitor GND1
circuit. The ACPL-798J accepts signal of ±200 mV (full
scale ±320 mV), which is ideal for direct connection to shunt
based current sensing or other low-level signal sources
applications such as motor phase current measurement. An
internal voltage reference determines the full-scale analog
13
Latch-up Consideration corresponds to 18.75% density of ones, and a differential

input of +200 mV is represented by 81.25% density of ones
Latch-up risk of CMOS devices needs careful consideration, in the data stream. A differential input of +320 mV or higher
especially in applications with direct connection to signal results in ideally all ones in the data stream, while input of –
source that is subject to frequent transient noise. The well 320 mV or lower will result in all zeros ideally. Table 3 shows
designed analog input structure of the ACPL-798J is this relationship.
resilient to transients, which are often encountered in highly
noisy application environments such as motor drive and Digital Filter
other power inverter systems. Other situations could cause
transient voltages to the inputs include short circuit and The original analog signal that is converted to a digital bit
overload conditions. The ACPL-798J is tested to be able to stream by the oversampling sigma-delta modulator can be
reject DC voltage of –2V and 2-second transient voltage of recovered by means of filtering in the digital domain. A
–6V presented to the analog inputs without any latch-up or common and simple way is through implementation of a
damage to the device. cascaded integrated comb (CIC) filter or Sinc3 filter. The
digital filter averages or decimates the oversampled bit
Modulator Data Output stream and effectively converts it into a multibit digital
equivalent code of the original analog input signal. With a
Input signal information is contained in the modulator output 20-MHz external clock frequency, 256 decimation ratio and
data stream, represented by the density of ones and zeros. 16-bit word settings, the output data rate is 58 kHz (=
The density of ones is proportional to the input signal 20 MHz/256). This filter can be implemented in an ASIC, an
voltage, as shown in Figure 21. A differential input signal of FPGA or a DSP. Some of the equivalent digital codes with
0V ideally produces a data stream of ones 50% of the time corresponding input voltages are shown in Table 3.
and zeros 50% of the time. A differential input of –200 mV
Figure 21: Modulator Output vs. Analog Input
MODULATOR OUTPUT +FS (ANALOG INPUT)
0 V (ANALOG INPUT)
–FS (ANALOG INPUT)

ANALOG INPUT
TIME
14
Table 3: Input Voltage with Ideal Corresponding Density of 1s at Modulator Data Output, and ADC Codea,b
Analog Input Voltage Input Density of 1s ADC Code (16-bit Unsigned Decimation)
Full-Scale Range 640 mV — —
+Full-Scale +320 mV 100% 65,535
+Recommended Input Range +200 mV 81.25% 53,248
Zero 0 mV 50% 32,768
–Recommended Input Range –200 mV 18.75% 12,288
–Full-Scale –320 mV 0% 0
a. With bipolar offset binary coding scheme, the digital code begins with digital 0 at –FS input and increases proportionally to the analog input
until the full-scale code is reached at the +FS input. The zero crossing occurs at the mid-scale input.
b. Ideal density of 1s at modulator data output can be calculated with VIN/640 mV + 50%; similarly, the ADC code can be calculated with (VIN/
640 mV) × 65,536 + 32,768, assuming a 16-bit unsigned decimation filter
Figure 22: Typical Application Circuit with a Sinc3 Filter
ISOLATION Non-Isolated
5V BARRIER 5 V/3.3 V
V DD1 V
DD2
INPUT MCLKIN+ CLOCK+
CURRENT V IN + 100 Ω CLOCK-
MCLKIN-
Fs Fs/M
R SHUNT MDAT+ DATA+
V IN – CIC/SINC 3 Filter
MDAT- 100 Ω DATA-
GND1 GND2
Decimation ratio = M
ACPL-798J MCU/FPGA
NOTE: In applications, a 0.1 μF bypass capacitor must be connected between pins VDD1 and GND1, and between pins
VDD2 and GND2 of the ACPL-798J.
15
Application Information
Digital Current Sensing Circuit
Figure 23 shows a typical application circuit for motor control phase current sensing. By choosing the appropriate shunt
resistance, any range of current can be monitored, from less than 1A to more than 100A.
Power Supplies and Bypassing

As shown in Figure 23, a floating power supply (which in many applications could be the same supply that is used to drive
the high-side power transistor) is regulated to 5V using a low cost and common regulator like the LM78L05.
Figure 23: Typical Application Circuit for Motor Phase Current Sensing
Floating Positive
Supply
HV+
Gate Drive
Circuit
5V/3.3V
IN OUT
78L05 C5 C3
0.1μF 10μF
C1 C2
0.1μF V DD1VDD1 V DD2
10μF C4
0.1μF MCLKIN+
R2a 22Ω R3a 100Ω
V IN+ MCLKIN+
FPGA
Cin /MCU/
MOTOR R2b 22Ω 10nF DSP
V IN− MDAT+
MDAT− R3b 100Ω
+ -
R SENSE GND1 GND2 0.1μF 10μF
ACPL-798J
HV -
16
Alternatively a simple zener diode could also be used to in LVDS also helps to reduce the EMI emissions associated
place of the regulator to provide the required power supply. with high speed digital signaling. Being high speed in
The voltage from the current sensing resistor or shunt general, LVDS signals are treated as transmission lines and
(RSENSE) is applied to the input of the ACPL- 798J through must be resistively terminated properly (as shown in
an RC anti-aliasing filter (R2 and Cin). Although the Figure 23) to reduce or eliminate transmission line
application circuit is relatively simple, a few reflection. The same resistors (R3a and R3b) also perform
recommendations should be followed to ensure optimal the function of terminating the LVDS lines that are current
performance. The power supply for the isolated modulator is mode outputs, and should be place as close as possible to
most often obtained from the same supply used to power the end receiver. The value of the differential terminating
the power transistor gate drive circuit. If a dedicated supply resistor is typically 100Ω which should match the differential
is required, in many cases it is possible to add an additional impedance of the transmission line. The LVDS interface is
winding on an existing transformer. Otherwise, some sort of in accordance to the TIA/EIA-644-A standard.
simple isolated supply can be used, such as a line powered
transformer or a high-frequency DC-DC converter. To help PC Board Layout
attenuate high-frequency power supply noise or ripple, a
resistor or inductor can be used in series with the input of The design of the printed circuit board (PCB) should follow
the regulator to form a low-pass filter with the regulator’s good layout practices, such as keeping bypass capacitors
input bypass capacitor. A ferrite bead is also recommended close to the supply pins, keeping output signals away from
to be placed close to VDD1 pin to filter out any high- input signals, the use of ground and power planes, etc. The
frequency noise in the supply. As shown in Figure 23, input anti-aliasing filter network should be placed as close
bypass capacitors (C2 to C5) should be located as close as as possible to the input pin to minimize any stray
possible to the input and output power-supply pins of the inductance. The termination resistor for the LVDS interfaces
isolated modulator (U2). The bypass capacitors are required should be placed as close as possible at the receiver pins,
because of the high-speed digital nature of the signals and the differential traces should be of the same length and
inside the isolated modulator. Tantalum capacitors are also be running along side each other. In addition, the layout of
recommended over electrolytic capacitors due to their lower the PCB can also affect the isolation transient immunity
ESR which translates to faster response to support the (CMR) of the isolated modulator, due primarily to stray
switching currents required by the isolated modulator. A capacitive coupling between the input and the output
10-nF bypass capacitor (Cin) is also recommended at the circuits. To obtain optimal CMR performance, the layout of
input due to the switched-capacitor nature of the input the PC board should minimize any stray coupling by
circuit. The input bypass capacitor together with the maintaining the maximum possible distance between the
resistors R2a and R2b also forms part of the anti-aliasing input and output sides of the circuit and ensuring that any
filter, which is recommended to prevent high frequency ground or power plane on the PC board does not pass
noise from aliasing down to lower frequencies and directly below or extend much wider than the body of the
interfering with the input signal. isolated modulator.
LVDS Interface
One of the features on the ACPL-798J is that it uses a Low
Voltage Differential Signaling (LVDS) interface on both the
clock input and the modulator output. In a typical motor drive
application where the ACPL-798J is used, the surrounding
environment is usually noisy. Very often, the current sensor
or modulator can be partitioned on another separate board
and interfaced through connectors or cables to the
controller board. The benefits of using LVDS in this case
helps to make the interface between the modulator and the
controller more robust and less susceptible to
electromagnetic interference from the surroundings.
17
Shunt Resistors resistance of the shunt can be decreased below the

maximum value to decrease power dissipation. The
The current-sensing shunt resistor should have low minimum value of the shunt is limited by precision and
resistance (to minimize power dissipation), low inductance accuracy requirements of the design. As the shunt value is
(to minimize di/dt induced voltage spikes which could reduced, the output voltage across the shunt is also
adversely affect operation), and reasonable tolerance (to reduced, which means that the offset and noise, which are
maintain overall circuit accuracy). Choosing a particular fixed, become a larger percentage of the signal amplitude.
value for the shunt is usually a compromise between The selected value of the shunt will fall somewhere between
minimizing power dissipation and maximizing accuracy. the minimum and maximum values, depending on the
Smaller shunt resistances decrease power dissipation, particular requirements of a specific design. When sensing
while larger shunt resistances can improve circuit accuracy currents large enough to cause significant heating of the
by utilizing the full input range of the isolated modulator. The shunt, the temperature coefficient (tempco) of the shunt can
first step in selecting a shunt is determining how much introduce nonlinearity due to the signal dependent
current the shunt will be sensing. The graph in Figure 24 temperature rise of the shunt. The effect increases as the
shows the RMS current in each phase of a three-phase shunt-to-ambient thermal resistance increases. This effect
induction motor as a function of average motor output power can be minimized either by reducing the thermal resistance
(in horsepower, hp) and motor drive supply voltage. of the shunt or by using a shunt with a lower tempco.
Lowering the thermal resistance can be accomplished by
Figure 24: Motor Output Horsepower vs. Motor Phase Current repositioning the shunt on the PC board, by using larger PC
and Supply
board traces to carry away more heat, or by using a heat
40 sink.
MOTOR OUTPUT POWER - HORSEPOWER
440
35 380
220 For a two-terminal shunt, as the value of shunt resistance
30 120 decreases, the resistance of the leads becomes a
25 significant percentage of the total shunt resistance. This has
20 two primary effects on shunt accuracy. First, the effective
15 resistance of the shunt can become dependent on factors
10 such as how long the leads are, how they are bent, how far
they are inserted into the board, and how far solder wicks up
5
the lead during assembly (these issues will be discussed in
0
0 5 10 15 20 25 30 35 more detail shortly). Second, the leads are typically made
MOTOR PHASE CURRENT - A (rms) from a material such as copper, which has a much higher
tempco than the material from which the resistive element
The maximum value of the shunt is determined by the itself is made, resulting in a higher tempco for the shunt
current being measured and the maximum recommended overall.
input voltage of the isolated modulator. The maximum shunt
Both of these effects are eliminated when a four-terminal
resistance can be calculated by taking the maximum
shunt is used. A four-terminal shunt has two additional
recommended input voltage and dividing by the peak
terminals that are Kelvin-connected directly across the
current that the shunt should see during normal operation.
resistive element itself. These two terminals are used to
For example, if a motor will have a maximum RMS current
monitor the voltage across the resistive element while the
of 10A and can experience up to 50% overloads during
other two terminals are used to carry the load current.
normal operation, then the peak current is 21.1A
Because of the Kelvin connection, any voltage drops across
(= 10 x 1.414 x 1.5). Assuming a maximum input voltage of
the leads carrying the load current should have no impact on
200 mV, the maximum value of shunt resistance in this case
the measured voltage. Several four-terminal shunts from
would be about 10 mΩ. The maximum average power
Isotek (Isabellenhütte) suitable for sensing currents in motor
dissipation in the shunt can also be easily calculated by
drives up to 71 Arms (71 hp or 53 kW) are shown in Table 4.
multiplying the shunt resistance times the square of the
The maximum current and motor power range for each of
maximum RMS current, which is about 1W in the previous
the PBV series shunts are indicated.
example. If the power dissipation in the shunt is too high, the
18
For shunt resistances from 50 mΩ down to 10 μm, the This is important because the large load currents flowing
maximum current is limited by the input voltage range of the through the motor drive, along with the parasitic inductances
isolated modulator. For the 5 mΩ and 2 mΩ shunts, a heat inherent in the wiring of the circuit, can generate both noise
sink might be required due to the increased power spikes and offsets that are relatively large compared to the
dissipation at higher currents. small voltages that are being measured across the current
shunt. If the same power supply is used both for the gate
When laying out a PC board for the shunts, a couple of drive circuit and for the current sensing circuit, it is very
points should be kept in mind. The Kelvin connections to the important that the connection from GND1 of the isolated
shunt should be brought together under the body of the modulator to the sense resistor be the only return path for
shunt and then run very close to each other to the input of supply current to the gate drive power supply in order to
the isolated modulator. This minimizes the loop area of the eliminate potential ground loop problems. The only direct
connection and reduces the possibility of stray magnetic connection between the isolated modulator circuit and the
fields from interfering with the measured signal. If the shunt gate drive circuit should be the positive power supply line.
is not located on the same PC board as the isolated
modulator circuit, a tightly twisted pair of wires can In some applications, however, supply currents flowing
accomplish the same thing. Also, multiple layers of the PC through the power-supply return path can cause offset or
board can be used to increase current carrying capacity. noise problems. In this case, better performance can be
Numerous plated-through vias should surround each non- obtained by connecting VIN+ and VIN– directly across the
Kelvin terminal of the shunt to help distribute the current shunt resistor with two conductors, and connecting GND1 to
between the layers of the PC board. The PC board should the shunt resistor with a third conductor for the power-
use 2 or 4 oz. copper for the layers, resulting in a current supply return path, as shown in Figure 24. When connected
carrying capacity in excess of 20A. Making the current this way, both input pins should be bypassed. To minimize
carrying traces on the PC board fairly large can also electromagnetic interference of the sense signal, all of the
improve the shunt’s power dissipation capability by acting conductors (whether two or three are used) connecting the
as a heat sink. Liberal use of vias where the load current isolated modulator to the sense resistor should be either
enters and exits the PC board is also recommended. twisted pair wire or closely spaced traces on a PC board.
The 22Ω resistor in series with the input lead (R2) forms a
Shunt Connections lowpass anti-aliasing filter with the 20 nF input bypass
capacitor (Cin) with a 723 kHz bandwidth. The resistor
The recommended method for connecting the isolated performs another important function as well: it dampens any
modulator to the shunt resistor is shown in Figure 23. VIN+ ringing that might be present in the circuit formed by the
is connected to the positive terminal of the shunt resistor, shunt, the input bypass capacitor, and the inductance of
while VIN– is shorted to GND1, with the power-supply return wires or traces connecting the two. Undamped ringing of the
path functioning as the sense line to the negative terminal of input circuit near the input sampling frequency can alias into
the current shunt. This allows a single pair of wires or PC the baseband producing what might appear to be noise at
board traces to connect the isolated modulator circuit to the the output of the device.
shunt resistor. By referencing the input circuit to the
negative side of the sense resistor, any load current induced
noise transients on the shunt are seen as a common-mode
signal and will not interfere with the current-sense signal.
19
Table 4: Four-Terminal Shunts
Shunt Maximum Motor Power Range

Resistance Tol. RMS Current 120 VAC to 440 VAC
Shunt Resistor
Part Number mΩ % A hp kW
PBV-R050-0.5 50 0.5 3 0.8 to 3 0.6 to 2
PBV-R020-0.5 20 0.5 7 2 to 7 0.6 to 2
PBV-R010-0.5 10 0.5 14 4 to 14 3 to 10
PBV-R005-0.5 5 0.5 25 [28] 7 to 25 [8 to 28] 5 to 19 [6 to 21]
PBV-R002-0.5 2 0.5 39 [71] 11 to 39 [19 to 71] 8 to 29 [14 to 53]
Figure 25: Schematic for Three Conductor Shunt Connection

Floating Positive
Supply
HV+
Gate Drive
Circuit
5V/3.3V
IN OUT
78L05 C5 C3
0.1μF 10μF
C1 C2
0.1μF 10μF V DD1VDD1 V DD2
C4
0.1μF MCLKIN+
R2a 22Ω
MCLKIN− R3a 100 Ω
V IN +
FPGA
Cin /MCU/
MOTOR R2b 22 Ω 20 nF DSP
V IN - MDAT+
Cin R3b 100Ω
+ - MDAT−
20 nF
R SENSE GND1 GND2
ACPL-798J
HV -
Voltage Sensing
The ACPL-798J can also be used to isolate signals with amplitudes larger than its recommended input range with the use
of a resistive voltage divider at its input. The only restrictions are that the impedance of the divider be relatively small (less
than 1 kΩ) so that the input resistance (12.8 kΩ) and input bias current (0.5 μA) do not affect the accuracy of the
measurement. An input bypass capacitor is still required, although the 22Ω series damping resistor is not (the resistance of
the voltage divider provides the same function). The low-pass filter formed by the divider resistance and the input bypass
capacitor might limit the achievable bandwidth. To obtain higher bandwidth, the input bypass capacitor (C2) can be reduced,
but it should not be reduced much below 1000 pF to maintain adequate input bypassing of the isolated modulator.
20
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Copyright © 2005-2019 Broadcom. All Rights Reserved.
The term “Broadcom” refers to Broadcom Inc. and/or its subsidiaries. For more information, please visit www.broadcom.com.
Broadcom reserves the right to make changes without further notice to any products or data herein to improve reliability,
function, or design. Information furnished by Broadcom is believed to be accurate and reliable. However, Broadcom does
not assume any liability arising out of the application or use of this information, nor the application or use of any product or
circuit described herein, neither does it convey any license under its patent rights nor the rights of others.

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Data Sheet

Functional Block Diagram

Σ−Δ LED MDAT+

Pin Configuration and Descriptions

Table 1: Pin Descriptions

Pin No. Symbol Description

Table 2: Ordering Information

Example: ACPL-798J-500E to order product in Tape and Reel packaging.

Contact your Broadcom sales representative or authorized distributor for information.

Package Outline Drawings

0.457 3.505 ± 0.127

Recommended Pb-Free IR Profile

IEC/EN/DIN EN 60747-5-5 Insulation Characteristicsa

Climatic Classification 55/105/21

Figure 1: Case Temperature Chart

Insulation and Safety Related Specifications

Absolute Maximum Ratings

Steady-State Input Voltage a, b VIN+, VIN– –2 VDD1 + 0.5 V

Two-Second Transient Input Voltagec VIN+, VIN– –6 VDD1 + 0.5 V

Recommended Operating Conditions

Analog Input Voltagea VIN+, VIN– –200 +200 mV

Average Input Resistance RIN Across VIN+ or VIN– to GND1; — 12.5 — kΩ c

Signal-to- (Noise + Distortion) SNDR TA = –40°C to +105°C; see Definitions. 65 75 — dB d 10,

Input-Output Capacitance CI-O f = 1 MHz. — 1.4 — pF b

Typical Performance Plots

Figure 6: Offset vs. Temperature Figure 7: Offset vs. MCLKIN Clock

Figure 8: Gain vs. Temperature Figure 9: Gain vs. VDD1

Figure 18: IDD2 vs. Temperature Gain Error

Definitions Signal-to-(Noise + Distortion) Ratio

Latch-up Consideration corresponds to 18.75% density of ones, and a differential

Figure 21: Modulator Output vs. Analog Input

MODULATOR OUTPUT +FS (ANALOG INPUT)

–FS (ANALOG INPUT)

Figure 22: Typical Application Circuit with a Sinc3 Filter

Power Supplies and Bypassing

Shunt Resistors resistance of the shunt can be decreased below the

Table 4: Four-Terminal Shunts

Shunt Maximum Motor Power Range

Figure 25: Schematic for Three Conductor Shunt Connection

Copyright © 2005-2019 Broadcom. All Rights Reserved.

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