IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO.

2, FEBRUARY 2024 1481

Shared External Driver for VHF Converter With

a Synchronous Rectifier Based on Matching
Network Parameters Optimization
Tianwei Huang , Yanfeng Chen , Member, IEEE, Bo Zhang , Senior Member, IEEE,
and Dongyuan Qiu , Member, IEEE

Abstract—In order to reduce the conduction loss of and high power-density of the power converter and improve
diode, synchronous rectification is usually adopted in very- the performance of the system, which has become an inevitable
high-frequency (VHF) converters, in which the rectifier trend in the development of the future power converters [1], [2],
diode is replaced by a MOSFET with very low on-state resis-
tance. And to ensure normal operation of the synchronous [3].
rectifier switch, it is necessary to design a suitable driver The main circuit topology of high-frequency power converter
with accurate timing. The widely used self-oscillating reso- is generally divided into inverter stage, matching network, and
nant drive circuit has a limited range of duty cycle adjust- rectifier stage [4]. At present, diodes are usually used for recti-
ment, and the body diode of synchronous rectifier switch fication [5], [6], [7]. As a semicontrolled switch, the diode does
has long on-state time and a large conduction loss. There-
fore, based on the analysis and parameters optimization not require additional control circuit, but has a threshold voltage,
of matching network, a shared external drive circuit is put which will cause a large conduction loss, especially in the case
forward. That is, the drive signals of the inverter switch and of low-voltage and high-current output. This will not only lead
the synchronous rectifier switch come from the same exter- to a decrease in the efficiency of the power converter, but also
nal oscillation signal. On the premise of ensuring accurate the heat generated by the loss will increase the temperature of
drive timing, it can improve the drive signal’s duty cycle of
synchronous rectifier switch, reduce the conduction loss of the power electronic equipment, affecting its normal work.
body diode, and improve the efficiency of converter. Then, Unlike a diode with a threshold voltage, for the MOSFET, when
on the basis of the proposed drive circuit, a VHF converter it is ON, it can be regarded as resistance; its voltage drop is
prototype with operating frequency of 10 MHz, 13 V input, equal to the product of the current and on-state resistance. And
and 8 V/10 W output is designed, and the feasibility of the
the limitation of physical characteristics makes it difficult to
proposed drive circuit is verified by simulations together
with experiments. reduce the threshold voltage of the diode. On the contrary, the
on-resistance of MOSFET can be reduced by increasing the size of
Index Terms—Matching network, shared external drive the silicon chip or separating the devices in parallel. Therefore,
circuit, synchronous rectification, very-high-frequency
(VHF) converter.
in order to reduce the conduction loss of the rectifier stage,
the synchronous rectification scheme is proposed, in which
a fully controlled power MOSFET switch with extremely low
I. INTRODUCTION on-state resistance can be used to replace the rectifier diode
N ORDER to adapt to the development trend of miniatur- [8], [9]. However, in this case, the drive signal of this power
I ization of electronic equipment, the integration of power
converters into chips is a recognized solution. Therefore, the
MOSFET must be synchronized with the phase of the voltage
being rectified [10], [11]. That is, the timing of the drive circuit
volume of passive components is usually reduced by increasing of two MOSFETS in the converter needs to be well designed to
the operating frequency, so as to achieve the miniaturization achieve synchronous rectification.
If another external driver is added to the synchronous rectifier
switch, the delay of the driver chips will cause the timing
Manuscript received 25 November 2022; revised 20 February 2023; sequence of the drive signal inaccurate at very high frequency
accepted 22 March 2023. Date of publication 3 April 2023; date of (VHF), making it difficult for the two MOSFETS to coordinate
current version 16 August 2023. This work was supported by the
National Natural Science Foundation of China and Natural Science and the converter to work normally. Therefore, self-oscillating
Foundation of Guangdong Province under Grant 52077085 and Grant resonant driver [12], [13], [14], [15] is generally adopted to
2023A1515012273. (Corresponding author: Yanfeng Chen.) ensure accurate drive timing. But even for the self-oscillating
The authors are with the School of Electric Power, South China Uni-
versity of Technology, Guangzhou 510640, China (e-mail: eptwhuang@ resonant drive circuit with dc bias [16], [17], its drive signal’s
mail.scut.edu.cn; [email protected]; [email protected]; duty cycle DRD is still less than 0.5. When the synchronous
[email protected]). rectifier switch’s duty cycle DR is greater than 0.5, there is still
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TIE.2023.3262892. a long time for current to pass through the body diode of the
Digital Object Identifier 10.1109/TIE.2023.3262892 synchronous rectifier switch, resulting in large volume diode

0278-0046 © 2023 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 1482 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 2, FEBRUARY 2024

Fig. 2. Synchronous rectifier circuit.

Fig. 1. Topology of main circuit. TABLE I

PARAMETERS OF RECTIFIER

conduction losses and low efficiency of the converter. Therefore,

the purpose of this article is to improve the duty cycle of the
synchronous rectifier drive signal on the premise of keeping the
drive timing accurate, so as to further reduce the on-state time
and conduction loss of the body diode.
In this article, the working principle of the VHF dc–dc con-
verter with a synchronous rectifier is described first, and then
how to optimize the parameter design of matching network is
analyzed. Based on this, a scheme of shared external drive circuit
is proposed. That is, the drive signals of the inverter switch Fig. 3. Equivalent circuit of matching network.
and the synchronous rectifier switch are provided by the same
external oscillation circuit. Compared with the self-oscillating
resonant drive circuit, the proposed scheme has the advantages parallel capacitor CR , which includes the diode parasitic capaci-
of precise timing, high duty cycle of synchronous rectifier’s tance, are grounded, so that the inverter switch and synchronous
drive signal, low diode conduction loss, and high efficiency. rectifier are driven in common ground. Here, the inductance LR
Finally, a synchronous rectification-based dc–dc converter with and the capacitance CR form a resonant network to realize ZVS
operating frequency of 10 MHz, 13 V input, and 8 V/10 W output of S2 and reduce the switching loss of the rectifier stage. The
is designed, and the feasibility of the proposed drive circuit is input ac current source iIN of the rectifier circuit is equivalent to
verified by both simulations and experiments. the output of the inverter stage, whose frequency is the switching
frequency fs . CO is the output filter capacitor and RL is the
II. PARAMETERS DESIGN AND MODES ANALYSIS resistor load.
At present, the general method to design VHF resonant recti-
The main circuit topology of the VHF Class Φ2 dc–dc con- fier circuit is to use simulation software for parameters scanning
verter with a synchronous rectifier adopted in this article is [19], [20]. And this method can be extended to the design of
shown in Fig. 1. The circuit is divided into the following three MOSFET-based synchronous rectifier circuit, since it has similar
parts: the front stage is a Class Φ2 inverter, the middle stage is a characteristics to the diode-based rectifier. Thus, parameters of
matching network of an inductor and a capacitor in series, and the the rectifier stage can be obtained, as shown in Table I. Here,
rear stage is a Class E current source synchronous rectifier. The RREC is the equivalent input resistance of the rectifier stage.
parameters are designed in the order of rectifier stage, matching
network, and inverter stage. The design should make the circuit B. LC Series Matching Network
meet the following requirements.
1) The inverter switch and synchronous rectifier switch The matching network is the intermediate link between the
achieve zero-voltage switching (ZVS). inverter stage and the rectifier stage, which plays the role of
2) Parasitic parameters in the switches are absorbed. isolating the dc component and regulating the load capacity of
3) The parameters of the matching network make the drive the inverter stage. The equivalent circuit of the matching network
timing of the master switch and the synchronous rectifier is shown in Fig. 3, which is composed of inductance LS and ca-
switch to be the same. pacitor CS . When analyzing the matching network, the rectifier
stage is equivalent to the resistance RREC , and the inverter stage
is equivalent to the drain–source voltage vds1 of the switch S1 .
A. Synchronous Rectifier Stage According to Fig.1, the voltage across RREC is the voltage vds2 of
Replacing the diode in the Class E current source resonant the synchronous rectifier switch S2 . Therefore, the relationship
rectifier circuit [18] with a MOSFET (S2 ) forms a synchronous between the drain–source voltages of two switches is determined
rectifier circuit, as shown in Fig. 2. by the matching network.
In order to avoid the switch floating influence on the design The voltages vds1 and vds2 represent, respectively, the input
of the drive circuit, the synchronous rectifier MOSFET S2 and the and the output of the matching network with a transfer function

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 HUANG et al.: SHARED EXTERNAL DRIVER FOR VHF CONVERTER WITH A SYNCHRONOUS RECTIFIER 1483

Fig. 4. Bode diagram of H(s).

H(s) being shown in (1). Obviously, the power transmission Fig. 5. Influence of the parameters variation of matching network.
ability from the inverter stage to the rectifier stage and the (a) Before parameters optimization. (b) After parameters optimization.
soft-switching characteristics of the two switches are affected
by the transfer function
vds2 sRREC CS
H (s) = = 2 . (1)
vds1 s LS CS + sRREC CS + 1
When S1 can achieve ZVS operation, that is, during the switch
OFF, vds1 rises and changes according to the resonance law, and
when it reaches 0, the switch is turned-ON by the drive signal.
When S2 and S1 adopt the same external drive signal, the phase of
vds2 must be the same as that of vds1 to ensure that both switches
Fig. 6. Equivalent circuit of Class Φ2 inverter.
can achieve soft switching at the same time. Then, according to
(1), it is easy to know that the parameters LS and CS of the
matching network should meet the following (2). And the bode
diagram of H(s) is shown in Fig. 4 When the drive timing is correct, the waveforms of vds1 and
1 vds2 are shown in Fig. 5(a). In this case, the phase difference of
√ = fs . (2) the two drive signals should be 52.4°, so they cannot adopt the
2π LS CS
same external drive signal. If another external driver is added
to the synchronous rectifier switch, the delay of the driver chips
The relationship between the RMS Vds1,rms and Vds2,rms is
will cause the timing sequence of the drive signal inaccurate at
Vds2,rms VHF. If self-oscillating resonant driver [16] is used, there will
= 1. (3)
Vds1,rms be a limit that the duty cycle of the drive signal is less than 0.5.
Generally, the drain–source voltage vds1 of the inverter switch After parameters optimization, the waveforms of vds1 and vds2
is assumed to be a square wave with a duty cycle of 0.5, and its are shown in Fig. 5(b), so that two MOSFETS can adopt the same
effective value is as follows [19]: external drive signal. The parameters optimization of matching
√ network is the premise of using the shared external drive circuit
2 2 proposed in this article.
Vds1,rms = VIN . (4)
π
The power PT transferred from the inverter stage to the C. Class Φ2 Inverter Stage
rectifier stage must be greater than the output power PO.
The equivalent circuit of the Class Φ2 inverter stage [21] is
Vds2,rms
2
shown in Fig. 6. The duty cycle of the inverter switch DI is 0.5.
PT = > PO . (5) LF , CF , L2F , and C2F are resonant elements.
RREC
In order to ensure that the inverter switch can achieve ZVS, it
Then, to meet power transmission requirements, the following
is necessary to fine-tune the parameters so that the phase of the
inequality should be satisfied:
drain–source impedance Zds of the master switch is between 30°
√
2 2  and 60° at the switching frequency fs . The equivalent circuit of
Vds2,rms = VIN > PO RREC . (6) drain–source impedance Zds of the inverter switch is shown in
π
Fig. 7, which includes the resonant elements of the inverter stage
If the parameters of the matching network do not meet (2),
and the matching network. The relationship between LS and CS
for example, CS = 750 pF, LS = 180 nH, the phase difference
is determined by (2). Adjust the values of elements so that the
between vds1 and vds2 is
phase of Zds at 10 MHz is between 30° and 60°, as shown in
ϕ (vds2 ) − ϕ (vds1 ) = ∠H (jω) |ω = 2πfs ≈ 52.4◦ . (7) Fig. 8.

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 1484 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 2, FEBRUARY 2024

Fig. 7. Drain–source impedance equivalent circuit of inverter switch.

Fig. 8. Phase frequency characteristic curve of Zds .

D. Operating Mode Analysis of Main Circuit

There are two switches with the converter, the inverter switch
and synchronous rectifier switch. The former is assumed to Fig. 9. Operation modes of the converter when DRD = 0.5. (a) Mode
operate in an ideal situation, that is, it has a duty cycle of I [t0 –t1 ] with both S1 and S2 ON. (b) Mode II with S1 OFF and S2 body
0.5, the same as that of its drive signal. Then, there are two diode ON [t1 –t2 ] [t3 –t4 ]. (c) Mode III with both S1 and S2 OFF [t2 –t3 ].
cases with the inverter switch, i.e., “ON” and “OFF.” As for the
synchronous rectifier switch, there exists three cases, namely,
“ON” (not including body diode ON), “OFF,” and “body diode
ON.”
In general, the VHF converter shown in Fig. 1 will have six
operating modes. However, according to the parameters design
of the rectifier stage and matching network above, the two
switches adopt the same external drive signal, and the duty cycle
DR of the synchronous rectifier switch is greater than the duty
cycle DI of the inverter switch. Therefore, if the drive signal’s
duty cycle DRD of the synchronous rectifier is 0.5, there are
only three operating modes during a working cycle, as shown in
Fig. 9. And the typical waveforms are shown in Fig. 10.
The sequence of the operation modes is briefly described
below according to Fig. 10. Within the time interval of (t0 –t1 ),
the converter operates in mode I with both switches are turned ON
by the same external drive signal, as shown in Fig. 9(a). During
the interval of (t1 –t2 ), S1 is turned OFF, while the body diode of
S2 is ON. And the converter is in mode II, as shown in Fig. 9(b).
Thanks to the resonant tank formed by LF , CF , L2F , and C2F , the Fig. 10. Typical waveforms of the VHF Class Φ2 DC–DC converter
voltage vds1 start to rise. However, since the duty cycle of S2 is with a synchronous rectifier when DRD = 0.5.
greater than 0.5, current still flows through the body diode of S2 .
Then, within the duration of (t2 –t3 ), S1 is still OFF, S2 is turned
OFF with its body diode OFF too. And the converter operates in the body diode of S2 . The resonant operation of the converter
mode III, as shown in Fig. 9(c). The resonant tank formed by makes vds1 drop to 0 at the end of this stage, so that the ZVS
LR and CR makes vds2 increase to the maximum value and then action of S1 can be realized. The operation modes are cycled in
decrease to 0, to ensure that the soft ZVS action of S2 can be the manner of mode I-mode II-mode III-mode II-mode I.
achieved. In following time period of (t3 –t4 ), the converter enters The body diode’s duty cycle of the synchronous rectifier
mode II operation. This is because that vds2 drops to zero before switch is DR –DRD . The external drive signal can improve its
the conduction signal arrives, causing current to flow through duty cycle by increasing its dc bias voltage. When DRD >0.5,

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 HUANG et al.: SHARED EXTERNAL DRIVER FOR VHF CONVERTER WITH A SYNCHRONOUS RECTIFIER 1485

part of the time of mode II (S1 OFF and S2 body diode ON) will
be changed to S1 OFF and S2 ON, so that the on-state time of the
body diode will be further reduced.
From the discussion above, it can be seen that, the operating
modes of the VHF converter with a synchronous rectifier in
this article will be greatly simplified by selecting the parameters
of the matching network. In addition, the shared external drive
circuit can be designed to reduce the body diode on-state time
of the synchronous rectifier switch.

III. SHARED EXTERNAL DRIVER AND CONTROL STRATEGY

Because the loss of square wave drive circuit is proportional
to the switching frequency, VHF dc–dc converters generally
adopt resonant drive circuit, so that the drive voltage applied
across the gate–source of the MOSFET switch is a sine wave or
approximately sinusoidal signal. At present, external resonant
Fig. 11. Shared external drive circuit.
drive circuit [22], [23], [24] and self-oscillating resonant drive
circuit are used in VHF converters.
Different from dc–dc converters using diode rectification, for
the VHF dc–dc converter with synchronous rectification, an with auxiliary shut-off branches. The resonance of Lg and Cgs
additional drive circuit needs to be designed for the synchronous changes the square wave signal VT into a sinusoidal wave signal
rectifier switch besides the inverter switch, which will increase with dc bias VT /2, thus reducing the drive loss. For the inverter
the size of the PCB. Yet, if a self-oscillating resonant drive circuit switch, set VT1 = 2Vth1 , then the drive signal’s duty cycle DID
[16], [17] with dc bias is used to drive the synchronous rectifier of the inverter switch can be 0.5, the same as its duty cycle
tube, the duty cycle DRD of the drive signal is less than 0.5, DI . In order to reduce the diode on-state time of synchronous
resulting in a long on-state time of the body diode and a large rectifier switch, it is necessary to set VT2 >2Vth2 , so that the
conduction loss. drive signal’s duty cycle DRD of synchronous rectifier tube is
Based on parameters optimization of the matching network, greater than 0.5. The closer DRD is to DR , the shorter the on-state
a shared external drive circuit is designed in this article. The time of the body diode. However, consideration should also be
drive signals of the inverter switch and synchronous rectifier given to the problem of the sine wave drive voltage caused by
switch are based on the same external oscillating signal, that is, high VT2 exceeding the MOSFET limit. So VT2 needs to choose
only one drive chip is required, and no additional phase-shifting a compromise. In addition, a shut-off branch, which includes an
circuit is required. And the drive signal’s duty cycle DRD of auxiliary switch tube in series with a diode, is paralleled to the
synchronous rectifier switch can be greater than 0.5, so as to gate of the main switch. And the control signal Vctrl is connected
reduce the on-state time and conduction loss of the body diode. to the gate of the auxiliary tube via a CMOS inverter. When the
control signal is low level, the auxiliary switches are turned
A. Shared External Drive Circuit ON, so as to quickly clamp the drive voltage of two switches to
zero to prevent misdirection. The parallel branch composed of
Based on the analysis above, the shared external drive circuit LP and CP is to reduce the ON–OFF loss on CMOS totem pole
as shown in Fig. 11 is designed. [23].
In the first stage of the drive circuit, an external pulse signal
generated by the oscillation chip U1 , with a duty cycle of 0.5
and a frequency of 10 MHz. And Vctrl denotes the output signal B. ON–OFF Control Strategy
of the control module, as shown in Fig.11 below, which acts as At present, ON–OFF control is commonly used in VHF dc–dc
the input of drive circuit module. The oscillation signal together converters. Set the upper voltage VH and lower voltage VL and
with Vctrl will determine the operation of the drive circuit via sample the output voltage VO . When the output voltage reaches
the NAND gate. When the control signal is high, the oscillating the upper level VH , the converter stops working, and the output
signal can be output and the drive circuit works normally. And voltage begins to drop. When the output voltage drops to the
when the control signal is low level, the drive circuit stops lower level VL , the converter is restarted and the output voltage
working. The output signal of the NAND unit is split into two starts to rise again, and the abovementioned process is repeated.
channels and connected to the next drive network stage, which For the VHF dc–dc converter with synchronous rectification
consists of multiple CMOS buffers in parallel to enhance the discussed in this article, the proposed sharing external drive
drive current. It should be noticed that the two channels have circuit is applied to both switches. And a hysteresis comparator
different power supply voltages and their corresponding square composed of an operational amplifier U5 and resistors R1–R4,
wave drive signals have different amplitudes VT1 and VT2 . is used as an ON–OFF control block to provide the control signal
The third stage is composed of series resonant tanks together for the drive circuit module, as shown in Fig. 12.

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 1486 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 2, FEBRUARY 2024

TABLE III
MAJOR DEVICE MODELS

TABLE IV
PARAMETERS OF DRIVE CIRCUIT AND CONTROL CIRCUIT

Fig. 12. Equivalent circuit of ON–OFF control.

TABLE II
PARAMETERS OF MAIN CIRCUIT AND DESIGN INDICATORS

The MOSFET with small ON–OFF resistance, small parasitic

parameters, and fast switching speed should be selected. For
inductance and capacitance, devices with high Q value and low
ESR (Equivalent Series Resistance) should be selected, as shown
in Table III. The parameters of drive circuit and control circuit
are shown in Table IV.
The results of PSIM simulation are shown in Fig. 13.
The upper voltage and lower voltage of the hysteresis com- The drive signals of the two switches obtained from the shared
parator can be determined by the following formulas: external drive circuit are shown in Fig. 13(a). The average thresh-
⎧   old voltage of MOSFET is about 2 V, the drive signal of inverter
⎨ VH = R1 +R2 R3 Vref
+ R4 VCH
switch is a sine wave with 2 V dc bias, and the drive signal duty
R2
 R3 +R4 R3 +R4
 (8)
⎩ VL = R1 +R2 R3 Vref
+ R4 VCL cycle DID is about 0.5. The drive signal of synchronous rectifier
R2 R3 +R4 R3 +R4
is a sine wave with 3 V dc bias, and the duty cycle DRD is about
where VCH is the high level of the comparator output, which is 0.54, greater than 0.5, which conforms to the design. As shown
about its supply voltage, VCL is the low level of the comparator in Fig. 13(b) and (c), there is no overlap between drain–source
output, which is about 0, and Vref is the reference voltage. voltages and currents of two switches. It means that two switches
achieve ZVS. Synchronous rectifier switch’s duty cycle DR is
about 0.66. As its drive signal’s duty cycle DRD is 0.54. The
IV. SIMULATION AND COMPARISON STUDY on-state time of body diode is 0.12 Ts . As shown in Fig. 13(d),
A. Simulation Verification drain–source voltages of two switches are in the same phase.
The rationality of the matching network design is verified and
The design indicators and main circuit parameters of the VHF the drive timing of the shared external drive circuit is correct.
dc–dc converter with a synchronous rectifier designed in this
article are shown in Table II.
In the shared external driver for VHF converter with a syn- B. Analysis of Loss and Comparison Study
chronous rectifier in this article, based on the parameters design The main losses of the converter include the following:
of the matching network, when the ON–OFF sequence of the 1) the drive loss Pd1 and the conduction loss Pcon1 of the
inverter switch and the synchronous rectifier switch are the inverter switch;
same, the two switches can achieve ZVS at the same time. If 2) the drive loss Pd2 and conduction loss Pcon2 of syn-
the switching time of the MOSFET is too long, the switching time chronous rectifier switch;
of the two MOSFETS may have a large gap in the whole operation 3) The loss of parasitic inductor resistance PL .
of the circuit. At the operating frequency of 10 MHz, this gap Through PSIM simulation and calculation, the final loss dis-
will lead to a large phase difference in the ON–OFF sequence of tribution is shown in Table V and Fig. 14. The total loss is 1.974
the two MOSFETS, making the switches unable to achieve ZVS. W, and the efficiency of the converter is about 83.5%.
Therefore, in order to ensure the normal operation of the circuit, In order to further verify the advantages of the shared external
the MOSFET with fast switching speed must be selected. drive circuit, the self-oscillating resonant drive circuit [16] and

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 HUANG et al.: SHARED EXTERNAL DRIVER FOR VHF CONVERTER WITH A SYNCHRONOUS RECTIFIER 1487

Fig. 14. Losses distribution.

TABLE VI
PARAMETERS OF SELF-OSCILLATING RESONANT DRIVE CIRCUIT

Fig. 15. Drive signal of self-oscillating resonant circuit.

the diode rectification circuit are designed on the basis of the

same main circuit parameters for comparison. The parameters
design of the self-oscillating resonant drive circuit [16] is shown
in Table VI. To ensure that the synchronous rectifier switch does
not mislead, the value of dc bias voltage Vbias should be less than
Fig. 13. Simulation waveforms. (a) Drive signals. (b) Drain–source
the minimum value Vth(min) of switch threshold voltage.
voltage/current of inverter switch. (c) Drain–source voltage /current of The resulting drive signal is shown in Fig. 15. Through
synchronous rectifier switch. (d) Drain–source voltages of two switches. simulation, it can be seen that the duty cycle of drive signal
is about 0.44, and the on-state time of the body diode is 0.22 Ts.
For the diode rectification circuit, the PMEG3030EP diode
with low on-state voltage drop is taken as an example, and its
TABLE V on-state voltage drop is about 0.315 V when the forward current
LOSSES DISTRIBUTION is 3 A.
The power losses of the three circuits on the rectifier switch
are simulated and calculated as shown in Table VII.
The synchronous rectification with shared external drive cir-
cuit is 2.6% more efficient than the diode rectification and
1.2% more efficient than the synchronous rectification with
self-oscillating resonant drive circuit. It has been proved theoret-
ically that the synchronous rectification-based dc–dc converter
with shared external drive circuit improves the efficiency of the
converter.

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 1488 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 2, FEBRUARY 2024

TABLE VII
COMPARISON OF RECTIFIER SWITCH LOSSES

TABLE VIII
COMPARISON BETWEEN SIMULATIONS AND EXPERIMENTS WITH on–off
CONTROL AND LOAD OF 6.4 Ω
Fig. 17. Experimental platform of the proposed converter.

Fig. 18. Output and drain–source voltage of synchronous rectifier

switch without ON–OFF control strategy when the load is 6.4 Ω.

are shown in Fig. 19, and the comparison between simulations

and experiments is shown in Table VIII.
The drive signals of the shared external drive circuit are shown
in Fig. 19(a). The dc offset of the drive signal of the inverter
switch is about 2.24 V, and the dc offset of the drive signal
of the synchronous rectifier switch is about 3 V. The phase
of the two drive signals is the same, which meets the design
requirements. Drain–source voltages of two switches are shown
in Fig. 19(b), have the same phase, realize ZVS, and verify
the rationality of the matching network design. Comparing the
experimental waveforms of vds1 and vds2 with the theoretical
Fig. 16. Experimental prototype of the proposed converter. waveforms (see Fig. 10), it can be verified that the sequence of
the operation modes of the experimental prototype is consistent
with the theory. The peak value of both of them is smaller than the
simulation values. The partial error may be caused by the loss of
V. EXPERIMENTAL RESULTS parasitic and distributed parameters in PCB. The output voltage
According to the abovementioned design parameters, an ex- with ON–OFF control is shown in Fig. 19(c) and its average value
perimental prototype was designed to verify the rationality of is about 7.99 V. At the same time, the distributed and parasitic
the proposed synchronous rectification-based dc–dc converter parameters in PCB greatly affect the circuit operation, so that the
with shared external drive circuit. The experimental prototype output voltage ripple is larger than the hysteresis width, about
is shown in Fig. 16 and the experimental platform is shown in 840 mV. When the control signal is at high level, the circuit
Fig. 17. works and the output voltage rises. When the control signal is
Without ON–OFF control strategy, when the resistive load is at low level, the circuit stops and the output voltage drops. The
6.4 Ω, the output voltage VO , and the drain–source voltage vds2 frequency of the ON–OFF control is about 66.7 kHz.
of synchronous rectifier switch are shown in Fig. 18. The output Combined with the experimental results, a comparison for
voltage is about 9.1 V. recent VHF dc–dc converters is carried out as illustrated in
With ON–OFF control strategy, when the resistive load is 6.4 Table IX. It indicates that the proposed design can improve the
Ω, the efficiency is about 81.8%. The experimental waveforms circuit efficiency.

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 HUANG et al.: SHARED EXTERNAL DRIVER FOR VHF CONVERTER WITH A SYNCHRONOUS RECTIFIER 1489

TABLE IX
COMPARISON FOR RECENT VHF DC–DC CONVERTERS

Fig. 20. Experimental waveforms with changed load. (a) Load

changes from 6.4 Ω to 13 Ω. (b) Load is 13 Ω.

than 0.5, thereby reducing the conduction loss of the body

diode. Moreover, proper parameters of the matching network
make both switches achieve ZVS while sharing the same ex-
ternal drive circuit. And the design of ON–OFF control strat-
egy also enables the output voltage stable under different
Fig. 19. Experimental waveforms of the converter with ON–OFF con- loads.
trol and load of 6.4 Ω. (a) Drive signals. (b) Drain–source voltages.
(c) Output voltage and ON–OFF control signal.
VI. CONCLUSION
Based on the principle of zero phase difference transmission
To test the dynamic performance of the proposed converter, signal, parameters of the matching network between the inverter
the load is varied from 6.4 to 13 Ω. As shown in Fig. 20, it can be and the synchronous rectifier of the VHF dc–dc converter are
seen that when the load changes, the output voltage is regulated properly designed. And then a new drive scheme, that is, both
to around 8 V without overshoot. Although the ON–OFF control the inverter switch and the rectifier switch share the same exter-
frequency and duty cycle are different at different loads, the nal drive circuit, is proposed. The principal circuit and related
output voltage can still be stabilized at 8 V. parameters of the drive mode are given, and a VHF synchronous
Based on the experimental results above, the rationality rectification-based dc–dc converter with 10 MHz, 13 V input,
of the proposed sharing external driver scheme for the VHF and 8 V/10 W output is designed accordingly. The effectiveness
dc–dc converter with a synchronous rectifier is verified. It is of the proposed scheme is verified by simulation and exper-
noticed that the key to effectively implementing this solution iments and the drive signal’s duty cycle of the synchronous
is to ensure correct drive timing. And thus, the drive sig- rectifier switch is improved on the premise of ensuring the drive
nal’s duty cycle of the synchronous rectifier switch is greater timing.

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 1490 IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, VOL. 71, NO. 2, FEBRUARY 2024

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 HUANG et al.: SHARED EXTERNAL DRIVER FOR VHF CONVERTER WITH A SYNCHRONOUS RECTIFIER 1491

Bo Zhang (Senior Member, IEEE) was born Dongyuan Qiu (Member, IEEE) was born in
in Shanghai, China, in 1962. He received the China, in 1972. She received the B.Sc. and
B.S. degree in electrical engineering from Zhe- M.Sc. degrees in automation from the South
jiang University, Hangzhou, China, in 1982, the China University of Technology, Guangzhou,
M.Sc. degree in power electronics from South- China, in 1994 and 1997, respectively, and the
west Jiaotong University, Chengdu, China, in Ph.D. degree in electrical engineering from the
1988, and the Ph.D. degree in power electronics City University of Hong Kong, Kowloon, Hong
from the Nanjing University of Aeronautics and Kong, in 2002.
Astronautics, Nanjing, China, in 1994. She is currently a Professor with the School of
He is currently a Professor with the School of Electric Power, South China University of Tech-
Electric Power, South China University of Tech- nology. She has authored or coauthored three
nology, Guangzhou, China. He has authored or coauthored 10 books books, and more than 100 papers and holds more than 80 patents. Her
and more than 450 technical papers and holds more than 100 patents. main research interests include wireless power transfer, fault diagnosis,
His current research interests include nonlinear analysis, modeling and and sneak circuit analysis of power electronic systems.
control of power electronic converters, and wireless power transfer ap- Dr. Qiu is currently an Associate Editor for the IEEE TRANSACTIONS ON
plications. POWER ELECTRONICS.

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