Advanced Technologies For Next Generation Integrated Circuits
Advanced Technologies For Next Generation Integrated Circuits
Advanced Technologies For Next Generation Integrated Circuits
Advanced Technologies
for Next Generation
Integrated Circuits
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Index 299
Chapter 1
Graphene and other than graphene materials
technology and beyond
Ashok Srivastava1
1
Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA, USA
2 Advanced technologies for next generation integrated circuits
Graphene Graphite
(a) (b)
residue which is structurally a multilayer graphene. This remained the best obser-
vation of graphene for several decades. The theoretical groundwork of graphene
also goes back to Wallace [5], who in 1947 first described the zone structure,
number of free electrons and conductivity of a single hexagonal layer of graphite.
Between the late 1970s and early 1990s, major attention was focused on full-
erenes (buckyballs) and CNTs which were discovered in 1985 [6] and 1991 [7],
respectively. However, some key features of currently known graphene were
reported during that period. Semenoff [8] found in 1984 that the wave functions of
graphene are similar to the solutions of relativistic Dirac equation. Finally in 1987,
Mouras et al. [9] coined the term “graphene” for single crystalline 2D carbon
allotrope, before which graphene was commonly termed as “thin graphite lamel-
lae”. Surprisingly, even before the experimental observation of two different types
of edge states, zigzag and armchair in graphene nanoribbon (GNR), a nanometer
dimensional form of infinite graphene sheet, Nakada et al. [10] in 1996 extensively
and accurately predicted their edge states with corresponding energy band
structure.
From 2004 to 2008, research on graphene spurred tremendously considering
graphene as an exciting condensed matter physics problem. Novoselov et al. [11]
found that the electron transport in graphene is governed by relativistic Dirac
equation where the charge carriers resemble Dirac fermions, relativistic particles
with zero rest mass (massless particle) with an effective speed in the range of light.
Graphene and other than graphene materials technology and beyond 3
Bandgap
Electric field
Conduction band Conduction band Conduction band
which became known as GNRs. Experimentally feasibility of GNRs has also been
demonstrated for making transistors and interconnects. Some of the recently
reported devices are room-temperature ballistic transport field-effect transistors
(FETs), single-electron transistors, spin transistors, and solar batteries. Researchers
at MIT have already demonstrated a graphene chip which could reach 1,000 GHz
(MIT Technical Talk, April 1, 2009).
According to Prof. Novoselov, one of the inventors of graphene “Being able to
control the resistivity, optical transmittance and a material’s work function would
all be important for photonic devices like solar cells and liquid crystal displays, for
example, and altering mechanical properties and surface potential is at the heart of
designing composite materials. Chemical modification of graphene—with gra-
phene as its first example—uncovers a whole new dimension of research. The
capabilities are practically endless.”
The synthesis and growth are significantly different from traditional bulk
three-dimensional materials because graphene is a two-dimensional atomically thin
material. While the current process technology for complementary metal-oxide
semiconductor (CMOS)-integrated circuit is mature, graphene process technology is
still under development, and extensive research has been carried out in this direction.
Moreover, the challenges associated with obtaining large-area single crystal graphene
and bilayer graphene are also present. In this chapter, synthesis of graphene and its
growth mechanism are presented followed by electronic structure and properties.
Adhesive
Mechanical tape
exfoliation
AFM tips
Top down
Chemical
exfoliation Sonication
Chemical
synthesis Reduced
Graphene graphene
synthesis oxide
Pyrolysis
Epitaxial
growth
Bottom up Thermal
CVD
Plasma
Other
methods
Graphene floating on
Cu etchant solution
1,200
2D
1,000
800 SL-Graphene
Intensity (a.u.)
I2D/IG~2
(a) 600 G
400
Graphene 200
D
0
SiO2 1,100 1,600 2,100 2,600
(b) (c) Wave number (cm–1)
Figure 1.4 (a) CVD grown graphene floating on Cu etchant after Cu has been
fully etched, (b) transferred on SiO2, and (c) Raman spectroscopy of
single-layer graphene after transferred on SiO2
Graphene and other than graphene materials technology and beyond 7
(a) (b)
Purge gas
To pump
Purge
Flow rate valve
controllers 1,200
Process gases
Ar CH4 = 7 sccm
1,000
Pressure
Temperature (°C)
Co
ng u
600 Nucleation
Cu foil
olin
Reaction chamber
gd
400
ow
n
200
Pressure
gauge Heater stage 0
0 5 10 15 20 25
(c) (d) Time (min)
Figure 1.5 Cold wall resistive heater type CVD system by Moorefield
Nanotechnology, U.K. (a) CVD assembly, (b) heater and chamber
assembly, (c) schematic of gas flow process, and (d) standard growth
condition for single-layer graphene
8 Advanced technologies for next generation integrated circuits
Recently, Hao et al. [27] have demonstrated that by controlling the oxygen on
copper substrate centimeter scale graphene single crystal can be obtained repeat-
edly. Traditionally the size of single crystals in a polycrystalline graphene sheet is
few micrometers only. Using cold wall CVD system, Misekis et al. [28] have
grown millimeter scale graphene sheet on copper foil for 30–60 min compared to
traditional hot wall CVD system which requires 3–7 h of growth time. Nevertheless,
the growth of more than centimeter scale graphene single crystal is still challenging.
Many attempts to grow bilayer graphene on copper have been carried out, however,
majority of these studies have resulted in small domain of bilayer graphene with a
large variation in the domain size [29]. Since an electric field tunable bandgap can
be obtained in a bilayer graphene, it is essential to produce uniform and large
domain single crystal bilayer graphene sheet. Hao et al. [29] recently have shown
that an oxygen activated CVD process can produce as large as half-millimeter size
Bernal A-B stacked bilayer graphene singe crystal on copper. Mu et al. [30] have
shown that by controlling the partial pressure of hydrogen during the nucleation
stage, bilayer graphene can be grown on copper foil. As part of growth studies of
single-layer and bilayer graphene, control of chamber pressure during growth period
has been modified for obtaining bilayer graphene on copper foil. Detail of the pro-
cess variability effect is provided in the following section.
450
BL-Graphene
400 D
I2D/IG~1
350
Intensity (a.u.)
300
Monolayer
250
G 2D
200
Bilayer 150
100
Multilayer
50
0
20 μm 1,000 1,500 2,000 2,500
(a) (b) Wave number (cm–1)
4,500
4,000 G
Multilayer-Graphene
3,500 I2D/IG~0.25
Intensity (a.u.)
3,000
2,500 D
2,000
1,500
2D
1,000
500
0
1,000 1,500 2,000 2,500
(c) Wave number (cm–1)
feature of a graphene film with defects or halogen terminated edges. An I2D/IG ratio
near 1 also reveals that the area is bilayer [33].
Further, Raman analysis of the darker region confirms that the graphene is
multilayer as shown in Figure 1.6(c). With an I2D/IG ratio of nearly 0.25 confirms
that the graphene in the region is more than 10 layers and similar to graphitic carbon
[33]. The D peak for this region is low which informs comparatively less defects or
hydrogen-terminated edges compared to the Raman spectra of Figure 1.6(b).
In order to analyze the effect of growth or exposure time on the number of
graphene layers in a similar growth condition, the copper foil was exposed for 300 s
instead of only 120 s. Figure 1.7(a) shows a sample area of the grown graphene for
such growth condition. It has been found that compared to uniform planar graphene
sheet, graphene growth for such long period of time results in not only multilayer
graphene but also a graphitic carbon with an extensive level of hydrogen-terminated
edges. For this reason, the Raman peaks obtained for such region of hydrogenated
graphitic carbon reveal a strong D peak and poor I2D/IG ratio which are shown
in Figure 1.7(b). It is to be noted that compared to the 0.25 ratio of I2D/IG, the
sample exposed for 300 s provides only an I2D/IG ratio of 0.19. Therefore, based on
the results obtained through Figures 1.6 and 1.7, an optimized growth period is
required for the large-area bilayer graphene synthesis. Nevertheless, further process
10 Advanced technologies for next generation integrated circuits
7,000
D
6,000
I2D/IG~0.17
5,000 G
Intensity (a.u.)
Graphitic carbon
4,000
3,000
2,000
2D
1,000
20 μm 0
(a) 1,100 1,600 2,100 2,600
–1
(b) Wave number (cm )
Figure 1.7 (a) Optical image of graphitic carbon grown on copper after an
exposure time of 300 s at a chamber pressure of 20 Torr and
(b) Raman spectroscopy of the dark area marked with an arrow
ky
b1
A B
K
δ1
δ3
Г M kx
a1 δ2 K'
a1 b2
(a) (b)
Figure 1.8 (a) Hexagonal lattice structure of graphene consisting of two atoms A
and B in a unit cell. a1 and a2 show direction of the lattice vectors in
the primitive unit cell and (b) reciprocal lattice vectors b1 and b2 in
the first BZ
triangular lattice with a basis of two atoms per unit cell. The lattice can be written
as follows [34]:
a pffiffiffi a pffiffiffi
a1 ¼ 3; 3 ; a2 ¼ 3; 3 (1.1)
2 2
2p pffiffiffi 2p pffiffiffi
b1 ¼ 1; 3 ; b2 ¼ 1; 3 (1.2)
3a 3a
The two points K and K0 are at the corners of the Brillouin zone (BZ). They are
referred to as Dirac points. The positions of these two points in a momentum space
are defined as follows:
2p 2p 0 2p 2p
K¼ ; pffiffiffi ; K ¼ ; pffiffiffi (1.3)
3a 3 3a 3a 3 3a
*–band
10
Ek(eV)
0
M
K
K
–5
K' M
–1
1
( –band
kx (
a
0
0
(
1 –1 ky(
a
Bilayer graphene
Substrate-induced
Bandgap
engineering
Epitaxial growth on
ordered substrate
Forming nanoribbon
The most commonly known method for opening a bandgap in graphene is to con-
fine the infinite graphene sheet into a narrow ribbon where length is much greater
than width. Due to the quantum confinement of the electrons into a nanoribbon, a
measurable finite bandgap can be opened [39,40]. For using graphene in transistor-
level operation, it is necessary to have a finite bandgap of the material and GNR
helps in this regard significantly.
Z
Zigzag edge
2 4 6
Armchair edge
GNR length
1 3 5 p
Y
GNR width
Figure 1.11 GNR, where p is an integer denoting the pth atom along the width
expressed as (p, 0), where p is the number of carbon atoms on each ring of unrolled
nanotube. Generally, “p” is defined in terms of any of the configurations from 3N,
3N þ 1 or 3N þ 2 along the GNR width. It should be noted that p is the total
number of atoms considering both sides of the nanoribbons whereas N is an integer.
Therefore, in a (4,0) armchair GNR, p ¼ 4 with 3N þ 1 configuration considering
N ¼ 1. Whereas in a (5,0) armchair GNR, p ¼ 5 with a 3N þ 2 configuration
considering N ¼ 1. For (6,0) armchair GNR, p ¼ 6 with 3N configuration con-
sidering N ¼ 2 [44].
Energy bandgap of GNR, both armchair and zigzag, differs depending on the
method of calculation. Electronic structure of GNR is modeled traditionally by the
simple tight binding (TB) approximation based on p-bonded pz -orbital electrons
or usually studied by Dirac equation of massless particle considering the effective
speed of light (~106 m/s). Such assumptions lead to conclude armchair GNR to be
either metallic or semiconducting. Results obtained by TB approximation con-
sidering nearest-neighbor hopping integral of 2.7 eV show that armchair GNR is
metallic for p ¼ 3N þ 2 and semiconducting for both p ¼ 3N and p ¼ 3N þ 1
configurations [45]. Basically, the hierarchy of energy bandgap is maintained as
D3Nþ1 > D3N > D3Nþ2(¼ 0 eV), D being the energy gap, where N is an integer.
Figure 1.12 shows the width-dependent bandgap, calculated using nearest-
neighbor tight binding Hamiltonian considering pz orbital encoded in “CNT
bands”, available in the open-source simulation framework Nanohub [46]. In
Figure 1.12, both (4,0) and (6,0) are semiconducting. Zero bandgap is observed for
(5,0) GNR which is a 3N þ 2 configuration for N ¼ 1.
However, the first principle calculation using self-consistent pseudopotential
method by local (spin) density approximation (L(S)DA) shows that there are no
Graphene and other than graphene materials technology and beyond 15
L L
1 3 1 3 5 1 3 5
(a) W (b) W (c) W
–5
metallic GNR [45]. The energy gap as a function of width is now grouped in a
family of energy gaps and maintains the hierarchy of D3Nþ1> D3N > D3Nþ2
( 6¼ 0 eV). Such an energy gap originates from the quantum confinement and crucial
role of edge states and changes with a-GNR width. Moreover, first principle many
electrons Green’s function approach within the GW approximation provides quasi-
particle energy gap with additional self-energy correction for both armchair and
zigzag GNRs. It should be noted that GW refers to the single particle Green’s
function “G” and the screened coulomb interaction “W”.
Recently, Kim et al. [47] have shown that proper consideration of higher
energy levels in addition to pz-orbitals in TB scheme gives more accurate
description of the GNR band structure. It is shown that within the TB method
3N þ 2 GNRs are not really metallic if higher energy levels such as “d” orbitals are
included. This is in agreement with the electronic structure obtained from rigorous
first principle-based calculations.
16 Advanced technologies for next generation integrated circuits
0 EVD
S ECD
EC
OFF
–0.2 EVC EVC
–0.4
EVS ON EVD
–0.6 λ
0 10 20 0 10 20
(c) Position (nm) (d) Position (nm)
and drain extension making the total length of GNR 30 nm. Figure 1.13(b) shows
an n-type a-GNR TFET. Figure 1.13(c) shows energy band diagram of n-i-p GNR
TFET (p-type GNR TFET where both VGS and VDS are ‘’ ve). Figure 1.13(d)
shows the energy band diagram of p-i-n GNR TFET (n-type GNR TFET where
both VGS and VDS are ‘þ’ ve). It should be noted that in both Figure 1.13(c) and (d),
solid line is for OFF state whereas dashed line is for ON state. OFF state is defined
as |VDS| ¼ 0.1 V and |VGS| ¼ 0 V and ON state is defined as |VDS| ¼ 0.1 V and |
VGS| ¼ 0.1 V. Semiconducting a-GNR (20, 0) has a bandgap of 0.289 eV for its
corresponding 4.9 nm width. In CMOS technology, the interconnect material is
copper and aluminum, which are different from silicon semiconductor used.
Contrary to silicon CMOS technology, graphene-based integrated circuits can use
the same material for both complementary transistors and interconnects.
Kang et al. [51] proposed all-graphene circuits as shown in Figure 1.14(a)–(g),
where transistors and interconnects are fabricated from a single sheet of graphene.
The figure shows a series of two all-graphene inverters. Tunable bandgap of gra-
phene can be adjusted for GNR interconnects by pattering it with larger width and
different orientation. Metallic and semiconducting GNRs are formed by changing
GNR width and chirality, such that zigzag edge GNRs can be used as metallic
source and drain regions and GNR interconnects while armchair GNRs are used for
the semiconducting channel [52]. The fabrication process with atomic precision is
required to implement zigzag-edged and armchair-edged GNRs for interconnects and
transistors with smooth edges in order to maintain the metallic and semiconducting
behaviors of GNR and prevent the reduction in mean free path by edge scattering.
The 3D hybrid structure of CNTs connected perpendicularly to graphene layers
has been synthesized by CVD process [53,54] and theoretically investigated by ab
initio calculation [55] as shown in Figure 1.15. It can be seen that one-dimensional
carbon nanotube can be used as a via (vertical structure contacting two horizontal
graphene layers) in this structure.
E E
Eg = 0
kx
(ac-) ir
cha
(a) (b) Eg (c)
k-Plane
Arm
Zigzag (zz-)
Lithography
Monolayer N+-doping
graphene P-doping
sheet
Graphene
(d) interconnects N-doping
GNRs (e)
P+-doping
Legends
Graphene VDD
Metal Graphene interconnects
Dielectric
Via
N+ GNR
Inverter 1 GNR
i PTFET
VIN PTFET WGNR
VG1 Xint P
VG2 VOUT2
Yint Area=Aint
Pad
VOUT LD
N-Drain Inverter 2
Oxide i-Channel GNR Lch
GND NTFET
P+-Source LS z x
due to the presence of a large quantity of edges, higher doping effect is observed in
GNRs than that in pristine graphene sheets.
In the current CMOS technology, transistor channel lengths are down to from
45 nm to 10 nm. By 2020, CMOS technologies are projected to reach line density
of 1010 devices/cm2, switching speed of 12 THz, circuit speed of 61 GHz and
switching energy of 3 1018 J. These are the figures which any new replacement
Graphene and other than graphene materials technology and beyond 19
technology for silicon has to compete with. The main reason why graphene FETs
cannot replace silicon transistors is because of the fact that channels cannot be
switched-off. Transistors will leak current in the off-state. Typical current on/off
ratio in digital CMOS devices is 104 to 107 whereas reported on/off current ratio in
wide channel graphene FET is ~100 at room temperature (wide channel FET from
SiC epitaxial graphene, L ¼ 10 mm, W ¼ 1.5 mm) with maximum field effect
mobility of 7,600 cm2 /V-s.
However, in most of the analog applications strict off-switching is not very
crucial. When circuits are powered, the transistors are biased in linear region. It is
the dynamic power consumption that dominates over the static power dissipation.
THz frequencies are possible with 20 nm gate lengths in graphene RF transistors.
One of the most severe limitations, already a limiting factor today, is power con-
sumption—or in other words heat generated by the operation of the device. Here,
graphene holds promise.
Discovery of two-dimensional atomic layer graphene in 2004 was perceived as
a possible replacement of silicon but it lost promise as an integrated circuit material
due to being semi-metal in electronic conduction. On the other hand, graphene is a
very useful material for optical applications such as solar cells, LEDs, touch
screens, photodetectors, etc. Monolayer graphene is almost transparent and when
combined with its excellent electrical conductivity, the natural applications relate
to transparent conductive films (TCF). TCFs are used as electrodes in solar cells, in
displays and touch screens, etc.
In search of materials other than graphene, layered transition-metal dichalco-
genide (TMD) type of materials denoted by MX2, where M is a transition metal
20 Advanced technologies for next generation integrated circuits
from group IV–VII, and X is a chalcogen such as S, Se, Te have shown great
promise for electronics, photonics, energy harvesting, and biosensors. TMDs, one-
atom thick, are superior to graphene in many ways. These have bandgap which is
very important to design transistors as switches and good absorbers of circularly
polarized light so they can be used as detectors. The most widely researched
material is molybdenum disulfide (MoS2) and single-layer MoS2-based FETs are
reported [63]. Bulk MoS2 is semiconducting with an indirect bandgap of 1.2 eV.
The single-layer MoS2 is a direct bandgap semiconductor with a bandgap of 1.8 eV.
The reported mobility in TMDs is too low to be used for semiconductor electronics
and attempts are being made to improve carrier mobility of TMD-based devices for
electronic applications. MoS2-based transistors with hafnium oxide (HfO2) gate
dielectric have reported mobility ~200 cm2v1s1 and 108 on/off current ratio with
ultra-low power operation. Recently, Srivastava and Fahad [64] have reported a
novel transistor based on combining horizontal current flow between source and
drain with vertical interlayer tunneling. A schematic of MoS2 junctionless tunnel-
ing FET considering MoS2/hBN/MoS2 is shown in Figure 1.16. The dashed line
AA0 refers to the vertical direction of interlayer tunneling and BB0 refers to lateral
direction of source-drain ballistic carrier transport. Compared to recently reported
device structures in [65] and [66], the present device structure gives subthreshold
slope close to 60 mV/decade and demonstrates upper GHz operation with relatively
comparable on/off current ratio.
Other new class of emerging two-dimensional materials denoted by Xenes
(silicene, germanene, and stanene) [67] based transistors remained yet to catch up
Top gate
VG
hBN = 20 layer
Top MoS2 = 1 layer
W = 5 nm hBN = 1 layer
source Bottom MoS2 = 1 layer drain
B hBN = 20 layers B’
SiO2
Bottom gate
Si
A’
1.8 Conclusion
Graphene with its unique electronic properties is highly suitable for numerous
electronic applications. Among different growth techniques, CVD is most pro-
mising due to its low cost and large area. However, growth of large-area single
crystal graphene is still challenging. Owing to its zero bandgap property, graphene
is not yet suitable for digital applications. However, finite bandgap can be obtained
in the form of GNR which demonstrates width and edge-type dependent energy
bandgap. GNR TFET can be a viable option for low power high-performance
integrated circuit design. By utilizing the zero band properties of graphene, the
promise of graphene interlayer tunnel transistor can also be explored. Other than
graphene 2D materials such as layered transition-metal dichalcogenide (TMD) and
Xenes have emerged and shown great promise for electronics, photonics, energy
harvesting, and biosensors.
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Chapter 2
Emerging graphene-compatible biomaterials
Hindumathi R. Dhanasekaran1, Jagannatham Madiga2,
Chandra P. Sharma3 and Prathap Haridoss2
2.1 Introduction
Present-day challenges in modern healthcare systems include invasive procedures
for the diagnosis of diseases and treatment, time-consuming lab tests, centralized
medical facilities which are not easily accessible to all people, and requirement of
expertise in medical prognosis. All these make modern healthcare costlier. These
factors also make early detection of onset of diseases and monitoring chronic
conditions difficult. Advances in bio-electronic devices make future healthcare
easier. Integrated circuits play a major role in all the three areas of biomedical
applications – diagnostic, monitoring and therapeutic. Biosensors and imaging
techniques help in diagnostics by sensing the change in different vital body signals
and by scanning the internal organs, respectively. Continuous monitoring of these
vital signals, electrochemically analysing the gas and chemical levels (e.g. glucose
sensing) and monitoring controlled delivery of therapeutic molecules are possible
only because of the advances in functional materials and integrated circuits.
Biomedical materials have come a long way, from inert supportive materials to
bioactive and responsive implants. Biocompatible and bioabsorbable materials
have made life with implants better and manageable. Portable devices which could
continuously monitor the condition of the patients by measuring vital signals and
biosensing, wirelessly transmitting the data to medical practitioner who could give
timely feedback and initiate therapy from remote location are nearing commer-
cialization [1]. The advances in nano materials and nano characterization techni-
ques have made this feasible.
Sensor technologies are based on either electrochemical, optical or acoustic wave
sensing. In addition, magnetic nanoparticles could be introduced in vivo and used for
1
Department of Biotechnology, Indian Institute of Technology Madras, Chennai, India
2
Department of Metallurgical and Materials Engineering, Indian Institute of Technology Madras,
Chennai, India
3
Biomedical Technology Wing, Sree Chitra Tirunal Institute for Medical Sciences and Technology,
Thiruvananthapuram, India
28 Advanced technologies for next generation integrated circuits
magnetic resonance imaging and sensing the path of drug delivery vehicles [2]. The
building blocks for bioelectronic systems include sensors for sensing physiological
signals, amplifier for the amplification of received signals, data encoder for con-
verting the signal into data, power source to power the components, control unit and
data storage or wireless transmitter. Miniaturized energy storage devices with high
power, high energy density and optical transparency are critical for portable and
wearable sensors. Micro and nano electromechanical systems (MEMs and NEMs) are
miniaturized, lightweight and ultra-sensitive devices and these are recent addition to
the biomedical systems. But miniaturized implantable devices face challenges due to
limited battery capacity and few energy sources [3].
While organic materials are naturally stretchable, inorganic materials could be
physically stretched and reconfigured while retaining their intended properties [4].
Inorganic nanoparticles are also attractive over organic nanoparticles for imaging
and biomedical applications as they are highly inert and stable with good
mechanical, optical and magnetic properties. They could also be easily functiona-
lized and surface-modified, which improves their functionality and processability
for different fabrication methods [5]. As further miniaturization of modern silicon-
based microelectronic semiconductor devices is difficult, carbon-based nanoma-
terials have emerged as next generation electronic materials. These nanocarbons
have very high carrier mobility and mechanical flexibility. Graphene, which is two-
dimensional (2D) planar arrangement of carbon atoms, has particularly gained
interest and widely studied. The strong sigma bonds between sp2-hybridized carbon
atoms renders graphene very high Young’s modulus (in the range of 1 TPa) and
exceptionally high 2D failure strength. Combined with their piezo-resistive prop-
erties, graphene nanomechanical resonators can sense ultra-low forces, charges and
single atomic masses and hence they are promising candidates for nano sensors [6].
They can also be fabricated into highly efficient and cost-effective devices for
energy harvesting and real-time imaging.
prominent among them are arc-discharge, chemical vapour deposition, laser ablation
and pyrolysis. The number of walls in the produced CNTs differ based on the process
parameters and the catalyst used during their production.
Graphite has a layered structure, with each layer containing hexagonally
bonded carbon atoms. Each single layer is called graphene. The hybridization of
carbon atoms in a graphene sheet is sp2. The covalent bonds between the carbon
atoms in the sheet are planar with the C–C bond length 1.42 Å and bond angle 120 .
There is also p bonding between the carbon atoms in the sheet. This delocalized p
bonding is responsible for the electrical conductivity. In comparison, the hybridi-
zation of carbon atoms in diamond is sp3, and the bonds are arranged in a tetra-
hedral geometry, with a bond angle of 109.5 . The lack of free electrons makes the
diamond an insulator (band gap of 5.5 eV) while the network structure helps in fast
conduction of lattice vibrations (phonons) responsible for the extremely high
thermal conductivity. The C–C distance in diamond is 1.54 Å. As evidenced from
the C–C distance in these two allotropes of carbon, the bonding in graphene is
stronger than that in diamond. The strength of graphene is not evident from the
measurement of mechanical properties of graphite, since graphite has a layered
structure (Bernal Stacking). The bonding between the layers is weak because of van
der Waals forces and therefore enables the individual sheets of strongly bonded
carbon atoms to slide with respect to each other.
Two-dimensional graphene is one of the crystalline allotropes of carbon.
Carbon atoms in the graphene are densely packed in a hexagonal pattern with
regular sp2 bonds. Graphene is a basic structure for any sp2-bonded carbon mate-
rials including graphite and it can be described as a one-atom thick layer of graphite
hexagonal sheet. High purity graphene has several advantages such as its strength,
low density and nearly transparent. Graphene also has high thermal and electrical
conductivities due to the phonon scattering and free electrons availability, respec-
tively. Graphene with unique physical, mechanical and electrical properties [11], is
widely being used in several applications such as metal-nanoparticles support [12],
gas storage [13], electrochemical energy storage [14], capacitors [15], etc.
Various types of graphene are available which differ in their three-dimensional
structure and properties. Graphene nanoribbons, also called nanostrips in the zig-
zag orientation at low temperatures, show spin-polarized metallic edge currents,
which have potential applications in the field of spintronics. In the ‘armchair’
orientation, the edges of the nanostrips behave like semiconductors. Using paper-
making techniques on dispersed, oxidized and chemically processed graphite in
water, the monolayer flakes form a single sheet of graphene and create strong
bonds. These sheets, called graphene oxide paper, have a measured tensile modulus
of 32 GPa. Graphene oxide flakes in polymers display enhanced photo-conducting
properties. Graphene-based membranes are impermeable to all gases and liquids
(vacuum-tight). However, water evaporates through them as quickly as if the
membrane was not present. In 2013, a three-dimensional honeycomb of hex-
agonally arranged carbon was termed 3D graphene.
Bilayer graphene displays anomalous quantum Hall effect, tunable band gap
and potential for excitonic condensation – making them promising candidates for
30 Advanced technologies for next generation integrated circuits
200 nm 2 nm 2 nm 2 nm
Figure 2.1 (a) TEM image of multi-layered graphene sheets produced by DC arc-
discharge. (b-d) HRTEM images showing the edge of multi-layered
graphene sheets consisting of two (b), three (c) and four (d) layers.
[Reprinted from [33] with permission from Elsevier]
32 Advanced technologies for next generation integrated circuits
such as graphene oxide and partially reduced graphene oxide materials also exhibit
these advantages except electrical conductivity. The deposition of nanoparticles
can be performed on the synthesized graphene using various methods. The most
commonly used methods are electroless and electrolytic deposition to decorate the
carbon materials. Pre-coating methods such as sensitization and activation are
necessary before electroless plating to achieve better coatings. In addition, chemi-
cal methods are also used to perform the deposition of nanoparticles on graphene.
To achieve the uniform and fine coating of the metal nanoparticles on graphene,
several factors and parameters need to be considered such as temperature, time, pH
of the solution, concentration of the metal-reducing agent and concentration of the
metal source. Recently, silver nanoparticles were decorated onto as-prepared gra-
phene using silver nitrate (AgNO3) in aqueous solution. The high electron density
of graphene is enough to reduce AgNO3 to Ag (0.8 V vs. NHE). Uniform dispersion
of silver nanoparticles were obtained on the surface of graphene sheet with the
mean size of 6 2 nm. Graphene sheets obtained from CNHs show better electrical
properties due to strong electron density [26].
Quantum dots are nanostructures and they exhibit exciting optical and elec-
tronic properties. However, many challenges need to be overcome for their effec-
tive use. In solar cells, the utilization of quantum dots suffers from accumulation of
charge carriers in the device [44]. Graphene oxide nanoplatelets decorated with
quantum dots overcome these challenges by acting as nanowires which promote
direct and efficient charge transfer to quantum dots. Thus, the efficiency of the
solar cells is increased. Substitutional doping of graphene involves the replacement
of carbon atoms from the hexagonal honeycomb lattice of graphene by N2 or B
atoms. The doped graphene sheets show n- or p-type behaviour depending on the
electrophilic character of the atoms that substitute the carbon atoms. The doping can
be controlled by various parameters and by controlling the degree of doping, elec-
trical properties can be monitored, and hence the applications of the modified gra-
phene can be explored in nanoelectronics devices.
Wrinkled structures could be formed from graphene nanosheets on surface
modification, which could also reduce the aggregation tendency of graphene
nanosheets [45].
voltage difference between the gate and the body of the device. Based on the charge
to the gate to the body, FETs are classified as n-type (negative charge) and p-type
(positive charge) FETs. They are also categorized depending on the material used
and some examples are metal-oxide semiconductor (MOS) and metal-nitride-oxide
semiconductor (MNO) FETs. Recently, development in fabrication techniques led
to the fabrication of next-generation FETs used in bioelectronic devices. Graphene-
based field-effect transistors (G-FETs) are also developed for biosensor applica-
tions. A G-FET consists of a conductive graphene-based channel through two metal
contacts which act as the source and drain electrodes. Graphene-based FETs could
largely reduce the size of the device, and the transconductance is linearly dependent
on width/length ratio of graphene. Graphene is used as an active layer and also as
an electrode in FETs and is advantageous over conventional organic materials as
they are more compatible with flexible and stretchable materials [66]. Graphene-based
FETs have the advantages of high sensitivity, low cost and time for preparation, and
high throughput detection with low detection limits. The high specific surface area of
the graphene is an advantage for bio-sensing applications. The exceptionally high
electron mobility and transconductance property of graphene make it an ideal can-
didate for high sensitive field-effect signal transducers. The source-drain current can
be modulated using a change in an external field. Similarly, changes in biological
environments that need to be measured/detected could trigger or act as a switch for
effecting the performance of graphene-based electronic devices [67]. Electrically
responsive tissue such as brain, ear and skeletal muscle could be stimulated, and the
energy can be utilized in neural prostheses in the treatment of vagal nerve, cochlear
implants, retinal implants and spinal cord [68].
Single-layer graphene FET (single-layer graphene flakes on oxidized Si sub-
strate) could successfully record electrogenic signals and have the unique capability
of recording signals as both p- and n-type devices, simply by changing the water
gate potential. Signals recorded with larger graphene device could represent the
average of extracellular potential from different sources and give broader peak-to-
peak signal width [69]. Distinguishable action potentials could be recorded with
graphene FETs from ex vivo heart tissue, in vitro cardiac-like cell line and in vitro
cortical neurons [70]. For applications such as prosthetic skin and minimally
invasive surgery, sensors with multi-axial detection capabilities, high sensitivity
and reliability are required [71]. Monolithic graphene-graphite designed as nano
FET sensors have 3D sensing capabilities with superior sensitivity, structural
flexibility and nanoscopic sensing resolution. Electrical detection from nanoscale
electric filed modulation of the graphene channel, detection of localized chemical
changes with high sensitivity could be achieved with these sensors [72].
excreted in sweat and blood are biomarker for a variety of diseases such as heart
failure, liver diseases, drug toxicity, metabolic disorders and microbial con-
tamination. Flexible graphene biosensor could detect as low as 0.08 mM lactate in a
steady-state measuring time of 2 s [74].
Aptamers such as adenosine triphosphate, nicotinamide adenine dinucleotide,
acetylcholine, cholesterol, benzenediol isomers, epinephrine; gases and ions can be
detected using graphene nanopores [75]. Aptamers are peptide molecules that bind
to a specific target molecule. Graphene–gold nanoparticle composite could serve as
a stable substrate for aptamer mobilization in a microfluidic chip designed with an
aptamer tagged with ferrocene as redox probe for detection of norovirus in spiked
blood samples, and also helps in signal amplification [76].
N OH
N N O OH
C
C C =
Fe
C C HO OH
N C N
OH
N
H+
H–
pH6 pH4
Substrate in solution
20
40×60 μm2 G-FETs
Spreading: 1,5 μm Polyimide 9500*
Substrate layer patterning
Mask 15
Current (μA)
Graphene sensors revelation by
polyimide exposure 10
Graphene + PMMA sheet transfer
G
5
PMMA acetone lift-off Device released by AI etch VDS = 30 mV SiO2
G Glass
Ti/Au contact PID
0
–1 0 1 2
*or another flexible and insulating material (c) Front liquid gate (V)
This MEA probe can be used as motor cortex implant to detect the activity of motor
neurons in brain [87].
Graphene printed onto water-soluble silk film could permit the biotransfer of
graphene nanosensor transducer onto tooth enamel. A parallel inductor–resistor–
capacitor resonant circuit was simulated, designed using simulation tool. This cir-
cuit was fabricated as biosensor using planar coil antennae with gold inductive coil
for wireless transmittance and graphene as resistive electrode. Through self-
assembly of peptides on the graphene transducer, pathogenic bacteria in saliva are
detected [88]. The fabrication and transfer onto tooth enamel is shown in
Figure 2.6. This flexible biosensor could also be successfully transferred onto
muscle tissue.
MEAs
(a) (b) 30 μm
FETs
40 μm
(c)
most cells. Hence their path inside human body could be easily traced from outside
through bioimaging techniques. This property can be used for nanoparticle-mediated
drug delivery to infected cells and monitoring the path of drugs. Sulphur doping
could increase the emission of blue colour of graphene quantum dots, which is
effective material for live cell imaging [90].
2.7.1 Microfluidics
Microfluidics is a network of 10 to 100 mm-size small channels which can handle
liquids in nanolitre or picolitre scale. As fluids could be precisely manipulated
using a micro-scale device, small-scale interaction of cells such as interaction
with other cells, biomolecules, toxins, pharmaceutical compounds and nanoma-
terials could be studied easily, which was not possible by conventional methods
[91]. Thus microfluidics has a major role in future biomedical research and
analysis. Because of miniaturized devices and liquid handling, microfluidics has
made possible the ‘lab-on-a-disc’ concept, for a wide range of medical diag-
nostics applications.
Emerging graphene-compatible biomaterials 43
(a) (b)
Silk
Graphene
5 mm 5 mm
(c) (d)
5 mm 5 mm
Figure 2.6 Graphene biotransfer and characterization. (a) Graphene printed onto
bioresorbable silk film. (b) Passive wireless telemetry system
consisting of a planar meander line inductor and interdigitated
capacitive electrodes integrated onto the graphene/silk film. (c, d)
Graphene nanosensor biotransferred onto the surface of a human
molar (c) and onto muscle tissue (d). Reprinted by permission from
Springer Nature, [88] 2012
Integrated
activity monitor
GO try Hummers' method
90°C, Na2S2O4
Flexible conductive
E-Textile
MEMS are miniaturized mechanical and electromechanical devices. MEM device has
various micro-electronic structure components such as micro-sensor and micro actua-
tor. The component size in MEMS varies between 1 to 100 mm and the size of the MEM
device ranges from 0.02 to 1 mm. The micro sensors and micro actuators used in
MEMS are generally piezoelectric transducers, which converts measured mechanical
signals into electrical. MEMS incorporated with micro-transducers improve the cap-
abilities of micro devices used for controlled drug delivery systems [98]. Scanning
tunnelling-tip microscope (STM), which is used to detect individual atoms and mole-
cules in nanometre scale and atomic force microscope (AFM) which is used to
manipulate the position of individual atoms and molecules on the surface of a substrate,
are typical examples of electromechanical based devices. Surface stress biosensors
such as micro cantilever, and micro membrane which act as transducers are highly
sensitive, fast and economic methods for drug screening and monitoring therapeutic
effect [99]. Biochemical liquid samples such as metabolites, macromolecules, pro-
teins, nucleic acids, cells and viruses can also be analysed using bio-MEMS [100].
NEMS are the devices in which the electrical and mechanical behaviour is
integrated at the nanoscale. The major difference between MEMS and NEMS is the
size of the functional components of the devices. Compared to MEMS, NEMS have
the high surface area to volume ratio, lower mass and large quantum effects. NEMS
are generally integrated with transistors with mechanical actuators or motors. Based
on the application, carbon nanomaterials can be utilized in both MEMS and NEMS.
In MEMs, they can be used as molecular wires and sensors.
NEMS are fabricated in two different approaches – top-down and bottom-up
methods. Top-down approaches are generally from manufacturing of MEMS
structures using electron beam lithography. Bottom-up approaches are by assembly
of the atoms and molecules as building blocks. Nanoparticles form a bridge
between bulk materials and molecular structures. Intrinsic graphene has symmetric
properties and do not show piezoelectric nature. But the piezoelectricity can be
introduced in graphene by inducing defects or adding foreign atoms [101]. Also,
monolayer or few layers graphene sheets on a supporting material can oscillate at
its natural frequency and could serve as a nanomechanical resonator. Graphene
cantilever, graphene clamped-clamped resonator and graphene drum resonator are
few examples [102]. Graphene-based materials are of light weight, and as graphene
has large surface area, they can bind over the entire device with lower quantity of
the material with enhanced properties. Graphene-based NEMS are applicable in
bioinspired technologies such as biomimetics which means mimicking the biology
found in nature. These NEMS also can be used in biotechnology to enable new
discoveries, for the amplification and identification of DNA structures, nano-
machined STMs, biochips for the detection of hazardous biological agents and
nanosystems for bio-screening applications. Various research studies are still going
on in the field of biotechnological applications of NEMS devices.
46 Advanced technologies for next generation integrated circuits
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Chapter 3
Single electron devices: concept to realization
Boddepalli Santhibhushan1, Anurag Srivastava1,
Anu2, and Mohammad Shahid Khan2
Single electron transistors are widely perceived as the next generation devices, and
beyond Moore’s law devices due to their promising aspects of low power con-
sumption, high switching speed, compact size, and importantly the ability to shrink
to atomic scale. The single electron devices operation is based on the quantum
phenomenon called “tunneling”. Though the basic structure and operating principle
of these devices is quite simpler, their fabrication and real-time operation is equally
difficult, as it requires multiple conditions of Coulomb blockade to be satisfied for
incoherent transport. This chapter provides comprehensive information about the
single electron devices, starting from their benefit over other devices in the same
series, associated concepts, operating principle, and the notable advancements in
experimental as well as theoretical research on these devices. This chapter is
expected to work as an absolute guide for any researcher interested in single
electron devices.
3.1 Introduction
3.1.1 Importance of single electron devices
The advances in integrated circuit (IC) technology have revolutionized several
sectors such as consumer electronics, telecommunications, computing, and space.
These advancements are led by the prediction made in 1965 by Gordon Moore, the
co-founder of Intel co., popularly known as Moore’s law, which states that the
number of transistors on a chip will double every two years. The law worked as a
roadmap for IC developers and resulted in colossal enhancement in the computa-
tional capacity. The maximum transistor count in a processor has reached from few
tens to few billions over time. As of 2019, AMD’s Epyc Rome processor holds the
tag of having the highest number of transistors at 39.54 billion in a commercially
1
Advanced Materials Research Group, CNT Laboratory, ABV–Indian Institute of Information Technology
and Management, Gwalior, India
2
Department of Physics, Jamia Millia Islamia, Central University, New Delhi, India
56 Advanced technologies for next generation integrated circuits
available processor. However, the stagnation of Moore’s law started in the early
twenty-first century and led to the invention of a dual-core processor (Figure 3.1)
[1,2]. The present technology node being used by Apple and Samsung is 10 nm,
while Intel is expected to release the 10 nm processors by 2019. The technology
node that follows 10 nm is 7 nm, followed by 5 nm. The semiconductor experts
believe 5 nm node as the end of Moore’s law due to uncontrolled quantum tun-
neling of carriers into gate.
Thus, developing next generation nanoelectronic devices with the capability to
extend Moore’s law is the current research topic of interest. Single electron tran-
sistor (SET) is a nanoelectronic device that promises to extend Moore’s law due to
the absence of scaling limits. Researchers have developed a prototype of SET with
single phosphorous atom as a quantum dot [3].
Transistors*
10,000,000,000
1,000,000,000
Intel XeonTM processor
Pentium® 4 processor
Intel itanium® processor
Intel® Celeron® processor
Pentium® III processor
Pentium® II processor
100,000,000
Pentium® Pro processor
Pentium® processor
i486TM processor
10,000,000
i386TM processor
1,000,000
286
8086
8088
100,000
8080
4004
8008
10,000
1970 1975 1980 1985 1990 1995 2000 2005 2010
Year of Introduction
*Note: Vertical scale of chart not proportional to actual transistor count.
Figure 3.1 Evolution of Intel processors with time (y-axis shows the transistor
count). Adapted with permission from [2]. Copyright owned by
Intel Co
Single electron devices: concept to realization 57
mechanics “all the microscopic material particles in motion can have wave char-
acteristics whose wavelength is inversely related to the size of particle, thus an
electron in motion can penetrate through a potential barrier of sufficiently small
size due to the wave-particle duality”. The SET contains an island, which is the
heart of the device. Two electrodes—source and drain to provide the bias, and a
third terminal—gate to control the flow of carriers through the island (Figure 3.2
(a)). The source and drain electrodes are separated from the island by thin insu-
lating tunnel barriers, while a thick insulation layer separates gate from island so as
to avoid unwanted electron tunneling into gate. The schematic of SET, equivalent
circuit, typical transfer, and output characteristics are shown in Figure 3.2. The
island is also called “quantum dot” as everything (charge, energy of electrons,
energy levels, current) on the island is quantized. Here, the word “quantized” refers
to the sizing to certain amount.
The working principle of SET involves one at a time tunneling of electrons
from the source to quantum dot and thereby to drain, provided the mechanism is
controlled by gate. In general, SETs can be operated in two regimes, coherent
transport (CT) and Coulomb blockade (CB) or incoherent transport or sequential
tunneling regimes. In CT regime, the quantum dot is strongly coupled between the
electrodes such that the tunneled electron onto quantum dot cannot localize itself
TUNNEL
JUNCTIONS
e– e–
VDS C1, Rt1 C2, Rt2
Source Quantum Drain
dot
Source QD Drain
INSULATOR
CONTROL CG
(a) GATE VGS (b)
Gate
ID ID
Current due to
single electron VG ≠ 0V VG = 0V
Coulomb gap
VDS
0 VGS VGS = 0V VG ≠ 0V
e/2C 2*e/2C 3*e/2C
(c) (d)
Figure 3.2 (a) Schematic of SET, (b) equivalent circuit of SET (C and Rt indicate
capacitance and tunnel resistance, respectively), (c) typical transfer
characteristics drawn between gate voltage (VGS) and drain current
(ID), and (d) typical output characteristics drawn between source-
drain bias (VDS) and drain current (ID)
58 Advanced technologies for next generation integrated circuits
and stays only for a short time, thereby retaining its original quantum information
of source. In CB regime, the quantum dot is weakly coupled between the electro-
des, such that the electron stays for sufficiently long time on the quantum dot and
localizes itself so as to lose its original quantum information of source.
CB is responsible for the controlled one after another tunneling of electrons in
SET. Due to CB effect, SET does not follow the Ohm’s law and the resulting
current–voltage (output characteristics) relation looks like a staircase. CB can be
defined as the opposition offered by the existing charge of quantum dot towards the
incoming charge. The term “Coulomb” is used since the blockade is a result of
Coulomb interaction of charges. If CB is not maintained, the operation of SET
cannot be controlled and no more acts like a SET. The following three conditions
should always be satisfied to maintain the Coulomb blockade [4,5].
I. Thermal energy addition of source and Island should be less than the charging
energy.
II. The uncertainty energy should be less than the charging energy.
III. Bias voltage (VDS) should be less than the elementary charge (e) divided by
self-capacitance of the quantum dot (Cdot).
Condition I
Thermal energy addition of source and island should be less than the charging
energy. Charging energy (EC) is defined as the energy required for adding one
elementary charge to the quantum dot, and is expressed as a function of self-
capacitance of the quantum dot as given in (3.1). When the quantum dot accom-
modates an excess electron under the influence of applied potentials, then its
energy rises to a value equal to the charging energy.
e2
EC ¼ (3.1)
2Cdot
It is necessary to design the SET in such a way that the quantum dot has a
charging energy higher than the thermal energy of source and island combined, so as
to avoid unwanted electron tunneling due to the thermal energy supplied by external
and internal temperatures. The condition can be expressed mathematically as,
e2
KB T < (3.2)
2Cdot
Condition II
Since the Island is a quantum mechanical system there must be some uncertainty in
the energy. This uncertainty in energy should be less than the charging energy.
e2
Uncertainty energy ðDEÞ < (3.3)
2Cdot
As per the Heisenberg’s uncertainty relation of energy and time,
DE Dt h=2
DE h=2Dt (3.4)
Since the quantum dot stores charge, it acts like a capacitor. Thus, it discharges
with a rate,
Dt ¼ Rt Cdot (3.5)
Here, Rt is tunneling resistance.
Substituting (3.5) in (3.4),
h
DE (3.6)
2Rt Cdot
Substituting (3.6) in (3.3),
h e2
<
2Rt Cdot 2Cdot
h
< e2
Rt
h
Rt >
e2
4:135 1015 eV s
Rt >
1:6 1019 e C
Rt > 26 kW (3.7)
Equation (3.7) states that the tunneling resistance offered by the tunnel junc-
tions should be higher than 26 kW to prevent any unwanted tunneling.
Condition III
The bias voltage (VDS) must be less than the elementary charge divided by self-
capacitance of quantum dot.
e
VDS < (3.8)
Cdot
This condition ensures weak coupling between the source and drain electrodes,
so that the tunneled electron can have enough time to localize itself on the island
and lose the original quantum information of source.
60 Advanced technologies for next generation integrated circuits
If VDS > e/Cdot, the source and drain electrodes get strongly coupled, which
may result in unwanted tunneling of electrons without applying gate voltage due to
the broadening of energy levels of the quantum dot. Also, the electron may retain
its quantum information of source even after entering the drain electrode.
The three aforementioned conditions ensure one after another electron tunneling
through the quantum dot by maintaining Coulomb blockade.
ISLAND
SOURCE DRAIN
–
e
EFS EFD
e–
Quantized energy
levels of island
Figure 3.3 Energy band diagram of SET (EFS and EFD refer to the Fermi level of
source and drain, respectively)
Single electron devices: concept to realization 61
(i) + VDS applied, VGS = 0 (ii) + VDS applied, + VGS = VTH applied
e.VDS
(iv) + VDS applied, + VGS = VTH applied (iii) + VDS applied, + VGS = VTH applied
Figure 3.4 Operation of SET device explained through energy band diagrams
Step-i: The applied bias potential across the source-drain electrodes lowers the
energy of drain with respect to the source. The shift in energy is proportional
to e VDS. Though this shift produces a Fermi function difference between
source-drain electrodes, the electron cannot tunnel from source to drain due
to the absence of unoccupied energy levels within the bias window.
Step-ii: If a positive gate potential is applied to SET, then the discrete energy
levels of quantum dot shift downwards. At some gate potential equivalent to
the threshold voltage of SET, an unoccupied discrete energy level can be
seen within the bias window, offering a chance for a source electron to
tunnel onto the quantum dot by overcoming Coulomb blockade. Since, by
definition, charging energy is the energy required to add one elementary
particle to the quantum dot, the shift in quantum dot energy (e.VGS) must be
equal to the charging energy. Thus,
e2
e VGS ¼ (3.9)
2Cdot
e
VGS ¼ ¼ threshold voltage ðVTH Þ (3.10)
2Cdot
Though we explain the operation with positive gate potentials, SET can also
be operated with negative gate potentials. An applied negative gate potential
62 Advanced technologies for next generation integrated circuits
shifts the discrete energy levels of quantum dot upwards. At a gate potential
equivalent to the threshold voltage, an occupied discrete energy level can be
seen within the bias window creating an opportunity for the quantum dot
electron to tunnel onto drain.
Step-iii: As a source electron occupies a discrete energy level of the quantum
dot, the energy of quantum dot raises by an amount equivalent to e VGS.
This forces the electron from the highest occupied discrete energy level of
the quantum dot to tunnel onto drain.
Step-iv: As the electron tunnels from quantum dot to drain, the energy of
quantum dot is again lowered by an amount equal to e VGS due to the
applied electric field from gate. Thus, another electron from source tunnels
onto the unoccupied discrete energy level of quantum dot, repeating step-ii.
high capacitive junctions show ohmic characteristics. Thus, smaller junctions are
favorable for inducing single electron tunneling effects.
Figure 3.6(a) depicts the voltage behavior for the drive current pumped
through S and L junctions with superconducting electrodes. Here, both S and L
junctions show Coulomb-gap structure, with L showing the typical structure of a
high capacitive junction. Curves SM and SMN depict the behavior of junction-S
when a substrate voltage is applied at superconducting (1.1 K) and non-
superconducting (1.7 K) temperatures, respectively. The substrate voltage is a
~0.05 Hz sawtooth wave with 0.5 V amplitude. The substrate voltage has resulted
oscillations in the voltage of horizontal electrode at both the superconducting and
non-superconducting temperatures. The period of oscillations is similar for both
superconducting and non-superconducting temperatures. Figure 3.6(b) gives a clear
representation of I–V variation with the substrate voltage, where, the uniformly
varied substrate voltage in increments of 1/6 has resulted in an offset of 7.5 nA
between the curves. To summarize, this work verifies the single electron charging
effects proposed theoretically by Averin and Likharev in [6]. The first evidence of
Coulomb-gap structure and ability of substrate electric field to influence the I–V
characteristics were presented.
In the following years, the SETs were fabricated and extensively analyzed by
several researchers for various applications such as charge sensor [9,10], dis-
placement detector [11–15], electric field sensor [16], spin detector [17], gas sensor
35 50
25
25
15
SMN
5
I (na)
I (na)
0
–5
SM
V (mv)
–15
S –25 0.8
–25 L 0.4
VM (mv)
–35 –100 0 100 200
–50
–1.4 –0.7 0 0.7 1.4 –1 –0.5 0 0.5
V (mv) V (mv)
(a) (b)
Figure 3.6 (a) I–V curves of low capacitive junction (S) and high capacitive
junction (L) at superconducting temperature 1.1 K. SM and SMN
curves show the behavior of junction S when substrate voltage is
applied at superconducting (1.1 K) and non-superconducting (1.7 K)
temperatures, respectively. (b) I–V curves of a sample at five
uniformly spaced substrate voltages at superconducting temperature
(1.1 K). Reprinted with permission from [8]. Copyright (1987) by the
American Physical Society
Single electron devices: concept to realization 65
[18], memory [19–24], switch [25–27]. In this section, we further highlight some
key experimental developments in the SET device technology.
60 Vg = 5.9 V
Conductance (e2/h)
0.2 30 Vg = 6.4 V
Vg = 6.9 V
Vg = 7.4 V
4 Vg = 7.7 V
0.1 2
0
1.0 1.5 2.0 2.5
Bias (V)
I (nA)
–0.1
Source Drain
V
Gate
–0.2 Vg
Figure 3.7 I–V characteristics of single C60 SET for varied gate potential at a
temperature of 1.5 K. The figure also shows a schematic
representation of the SET device. Reprinted with permission from
[28]. Copyright (2000), Springer Nature
66 Advanced technologies for next generation integrated circuits
changes reversibly with the applied gate potential, as a higher positive gate
potential stabilizes an additional electron on the C60 quantum dot. Another inter-
esting aspect is the electron hopping induced nano-mechanical oscillations of C60
against the electrode surface. When an electron from the gold electrode hops on to
the C60 quantum dot, the attractive interaction between the added electron and its
image charge on the electrode pulls the fullerene closer to the electrode. Likewise,
a similar phenomenon pulls the fullerene towards the other gold electrode when the
electron from C60 hops onto the electrode. This process causes nano-mechanical
oscillations of C60 with a frequency measured as 1.2 THz.
D Ejected D
Si
G1
nm
nm
nm
54
9.6
54
nm
9.2
[01
G2
0
S
]
S
(b)
(a) [100]
PH2 H PH3
P
P-Si
PH3 PH
(c) RT T = 350 °C
Figure 3.8 (a) STM image of the device, (b) close shot of the dotted region in (a),
(c) chemical reaction depicting the incorporation of single
phosphorous dopant into silicon (RT indicates Room Temperature).
Reprinted with permission from [3]. Copyright (2012),
Springer Nature
gate voltage of 0.45 V and the second transition D0!D occurs at a gate voltage
of 0.82 V. Figure 3.10(b) shows an experimentally observed charging energy
of 47 3 meV. Figure 3.10(c–g) shows the tight-binding simulation results of
potential profiles and orbital probability density between source-drain electrodes.
Figure 3.10(c) depicts the variation of D0 and D ground states position w.r.t the
gate voltage, where the charge transition occurs when the state touches the elec-
trode Fermi level. The difference in the energies of the two ground states gives the
charging energy 46.5 meV, which is very close to the experimental value. In
comparison to the equilibrium case depicted in Figure 3.9(c), Figure 3.10(d) and (f)
shows the relative reduction in potential barrier by silicon due to the applied
positive gate voltage. To summarize this work, the authors have successfully
positioned a single atom dopant into a single crystal of silicon with an accuracy of
one lattice point and utilized the dopant as a quantum dot for single electron tun-
neling. More studies of single atom transistors have followed in the subsequent
years from various other researchers aiming at quantum computation application
[29,30].
68 Advanced technologies for next generation integrated circuits
0
[110]
40 (nm)
m)
(n 20
10] 80
[1 D 120
40
G1
0.2
Potential (eV)
0
–0.2
G2
S –0.4
–0.6
(a) Donor potential, U
0.5 0.5
20
0 0
D0
–0.5 –0.5 0
–1 D S –1 G1 G2
–20
–1.5 –1.5
–2 –2 –40
Bulk
D0
–2.5 –2.5
–60
–3 –3
–80
–3.5 –3.5
–4 –4 –100
10 20 30 40 0 40 80 120 20 25 30 35
(b) [110] nm [110] nm (c) [110] nm
Though the experimental realization of single electron devices took shape in 1987,
the first principle device modeling of the same started only in 2008 when Kaasbjerg
et al. [31] introduced a semiempirical method to simulate an OPV5 molecule-based
SET. Later, in 2010, Kurt Stokbro [32] has extended that framework to model
molecular SETs using density functional theory (DFT). The framework by Stokbro
[32] has become so popular that it prompted enormous interest in the research
community in subsequent years to explore the SETs of various materials for
switching [33–42] and sensing [43–53] applications using DFT.
Experiment
400 50
300
200 25
100 EC =
VSD (mV)
VSD (mV)
ISD (A) 47 ± 3 meV
G (μS)
0 D0 D– 0
D+ 10–6 2
D+ D0 D–
–100 10–7
1
VG = 0.45 V
VG = 0.82 V
–200 10–8 –25
D+ ↔ D0
D0 ↔ D–
–300 10–9
0
–400 10–10 –50
–0.4 –0.2 0 0.2 0.4 0.6 0.8 1 0.2 0.4 0.6 0.8 1
(a) VG (V) (b) VG (V)
Theory
Energy w.r.t silicon Ecb (meV)
[110] (nm)
[110] (nm)
–50 –50
–20 D0 64 D– 64
GS
GS
EF EF
D
–40
0
–100 –100
–
46.5 mV
58 58
–60 22 28 34 22 28 34
–150 –150
[110] (nm) [110] (nm)
–80 EF
–200 Probability density –200 Probability density
0 0.2 0.4 0.6 0.8 22 25 28 31 34 22 25 28 31 34
(c) (d) (e) Min Max (f) [110] (nm) (g) Min Max
VG (V) [110] (nm)
Figure 3.10 (a) Stability diagram showing the drive current variation (log scale) w.r.t the VSD and VG, (b) differential conductance
variation (linear scale) in the dotted region of (a), (c–g) tight-binding simulation results of potential profiles and orbital
probability density between source and drain electrodes. Reprinted with permission from [3]. Copyright (2012),
Springer Nature
70 Advanced technologies for next generation integrated circuits
ΔVII (eV)
–2
Source Drain
–1
Dielectric ε = 10 ε0 0
Gate
Figure 3.11 The SET model designed by Stokbro. The figure also shows the
electrostatic potential induced in the device at a gate voltage of 2 V
and zero source-drain bias. Reprinted with permission from [32].
Copyright (2010), American Chemical Society
ð ðX
1 1X
E½n ¼ T ½n þ EXC ½n þ dV H ðrÞdnðrÞdr þ ViNA ðrÞdnðrÞdr þ Uij
2 2 ij
(3.11)
The energy contribution of external electric field from the metallic and dielectric
regions is estimated as,
ð X
DE ¼ V ext ðrÞnðrÞdr V ext ðRi ÞZi (3.12)
i
Here, V ðrÞ is the external electrostatic potential, Ri and Zi are the position of
ext
–2 C6H6 –2 C60
–9,440
–1,020
2 2
Total energy (eV)
–9,445 –1
–1,030 –1
1
1
–9,450
0
–1,040 0
–9,455
–10 –5 0 5 10 –10 –5 0 5 10
(a) Gate voltage (Volt) (b) Gate voltage (Volt)
15 15
C6H6 C60
10 10
Source-drain bias (Volt)
5 5
0 0
–5 –5
–10 –10
–15 –15
–10 –5 0 5 10 –10 –5 0 5 10
(c) Gate voltage (Volt) (d) Gate voltage (Volt)
Figure 3.12 Total energy plotted as a function of gate potential for various
charge states (0,1,2,-1,-2) of (a) benzene and (b) C60 quantum dot.
Charge Stability diagram as a function of gate and source/drain
potentials for (c) benzene and (d) C60 SET. The color code shows the
number of energy levels available for conduction within the bias
window (Dark blue: 0, light blue: 1, Green: 2, Yellow: 3, red: 4).
Reprinted with permission from [32]. Copyright (2010), American
Chemical Society
72 Advanced technologies for next generation integrated circuits
the least total energy in their neutral charge state at zero gate potential. For positive
gate potentials the negative charge states are more stable and vice versa. This beha-
vior is in agreement with the HOMO and LUMO levels following eVG, thus for
positive gate potentials the LUMO level moves below the electrode Fermi level and
accepts an electron, and for negative gate potentials the HOMO level moves above the
Fermi level of electrode and loses an electron. The non-linear variation of total energy
w.r.t gate potential in C60 SET is a result of charge polarization on C60 molecule due
to the screening of gate potential by the lower atoms for the rest of the molecule.
The charge stability diagram depicted in Figure 3.12(c) and (d) is plotted from
the total energies using (3.13) that represents the constraint for the current to flow
in the SET device.
e jV j ejV j
DEisland ðN Þ þ W (3.13)
2 2
Here, V is the source-drain bias potential, DEisland ðN Þ is the charging energy
(DE ðN Þ ¼ Eisland ðN þ 1Þ Eisland ðN Þ), and W is the work function of metal
island
electrodes. The figure shows less excitation energy requirement for C60 SET than the
benzene, meaning the C60 SET can be switched from OFF state (dark blue region) to
ON state (light blue region) by applying relatively low gate and source-drain potentials.
Next, the various DFT-based reports based on the Stokbro’s model exploring
SET device for switching and sensing applications are discussed.
Quantum dot
1.1 Å (C-H) Source Drain
1.1 Å (C-H)
1.39 Å (C-C) 1.53 Å (C-C)
Gate dielectric
Gate
Figure 3.13 Benzene (C6H6) and hexahydrobenzene (C6H12) molecules, and the
schematic of SET device. [2016] IEEE. Reprinted with permission,
from [37]
DOS (eV–1)
Molecular energy spectrum 0 2 4 6 8 10 12
LUMO+1 5.40 S, P
LUMO 2.62 P
0 Fermi level
5.23 eV
E (eV)
HOMO –2.62 P
HOMO–1 –4.48 S, P
–5.34 P
(a) 0 2 4 6 8 10 12
0 Fermi level
7.43 eV E (eV)
HOMO –3.72 S, P
HOMO–1 –4.80
–5.28 S, P
(b) 0 2 4 6 8 10 12
Figure 3.14 Molecular energy spectrum and the corresponding density of states
(DOS) profiles for (a) benzene and (b) hexahydrobenzene. [2016]
IEEE. Reprinted with permission, from [37]
74 Advanced technologies for next generation integrated circuits
15
4
3
10
Source-drain bias (Volt) 2
5 1
0
–5
–10
–15
–10 –5 0 5 10
VG = –6.37 V –3.88 V 6V 8.47 V
(a) Gate voltage (Volt)
15
4
2 3
10
1
Source-drain bias (Volt)
0
5
–5
–10
–15
–10 –5 0 5 10
VG = –6.04 V –3.07 V 9.17 V
(b) Gate voltage (Volt)
Figure 3.15 Charge stability diagram of (a) benzene and (b) hexahydrobenzene.
[2016] IEEE. Reprinted with permission, from [37]
point) for benzene than hexahydrobenzene when operated with positive gate poten-
tials, whereas the contrary is true for negative gate potentials. In this study, the
authors have further decoded the charge stability diagram by identifying and
indicating the charge state of molecular quantum dot in each Coulomb blockade
diamond (denoted as D0, Dþ1, Dþ2, D1, D2, etc. in the dark-blue diamonds) using
the total energy variation plot w.r.t gate potential for the first time.
Single electron devices: concept to realization 75
(a)
(b) (c)
(d)
2 2
Source-drain bias (Volt)
0 0
–1 –1
–2 –2
–3 –3
–2 –1 0 1 2 3 –2 –1 0 1 2 3
(a) Gate voltage (Volt) (b) Gate voltage (Volt)
4.0
2 3.5
Source-drain bias (Volt)
1 3.0
2.5
0
2.0
–1
1.5
–2 1.0
–3 0.5
–2 –1 0 1 2 3 0.0
(c) Gate voltage (Volt)
Figure 3.17 Charge stability diagrams for (a) thiol-ended dibenzothiophene, (b)
Cr-complex of thiol-ended dibenzothiophene, (c) W-complex of thiol-
ended dibenzothiophene. Reprinted with permission from [41].
Copyright (2018), Elsevier
like asthma, lung cancer, and heart diseases. Since, nicotine can stay significantly
strong in the environment for about 2 h before metabolizing to cotine. Thus,
nicotine detection is extremely important. The nanopore method proposed by the
author does not require any chemical preparations as the conventional methods
of nicotine detection like gas chromatography, radioimmunoassay, liquid chro-
matography require. Figure 3.21 shows the modeled nanopore device and the
electronic fingerprint. Here also the charge stability diagram has been used as
electronic fingerprint for the detection of nicotine with various possible
orientations.
In another study, S. J. Ray has proposed an effective double-gated SET
environment for the detection of single-atom impurities aimed at assisting the
nanoscale semiconductor device fabricators with controlled impurity addition into
the semiconductors [45]. Figure 3.22 shows the double-gated SET device structure
and the respective electronic fingerprint. Later in 2015, S. J. Ray has proposed a
very effective gate all-around structure of SET (see Figure 3.23) for humidity and
toxic gas detection [46,47].
78 Advanced technologies for next generation integrated circuits
Thiol-ended thiophene
Thiol-ended dibenzothiophene
Cr-complex
W-complex
4
Charge state
2
0
–3.5
–3.0
–2.5
–2.0
–1.5
–1.0
–0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
(a) Source-drain bias (Volt)
Charge state
0.5 0.5
0.0 0.0
–1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5 –1.5 –1.0 –0.5 0.0 0.5 1.0 1.5 2.0 2.5
(b) Gate voltage (Volt) (c) Gate voltage (Volt)
Figure 3.18 Tracings of CSDs (a) along source-drain bias for all the four
molecules, (b) along the gate voltage axis for thiol-ended thiophene
and thiol-ended dibenzothiophene, (c) along the gate voltage for Cr-
complex of thiol-ended dibenzothiophene and W-complex of thiol-
ended dibenzothiophene. Reprinted with permission from [41].
Copyright (2018), Elsevier
15
Source-drain bias (V)
10
Source
Drain
0
5
A C 1
0
ssDNA 2
–5 3
Dielectric –10
Gate –15
G T –15 –10 –5 0 5 10 15
Gate voltage (V)
Figure 3.19 Schematic of SET nanopore device used for DNA detection, and a
sample charge stability diagram as an electronic fingerprint.
Reprinted with permission from [43]. Copyright (2012), American
Chemical Society
A C G T A in SET
15
A0 C0 G0 T0
10
JA JC JT1 y
5
0 z
–5 JT2
–10
–15
15
AX90 CX90 GX90 TX90
10
5
0
0
Source-drain bias (V)
–5
–10
–15 1
15
AY90 CY90 GY90 TY90
10
5 2
0
–5
3
–10
–15
15
AZ90 CZ90 GZ90 TZ90
10
5
0
–5
–10
–15
–15
–10
–15
–10
–15
–10
–15
–10
–5
10
15
–5
10
15
–5
10
15
–5
10
15
0
5
0
5
0
5
0
5
Gate voltage (V)
Figure 3.20 The charge stability diagram electronic fingerprints of various DNA nucleobases adenine (A), cytosine (C), guanine
(G) and thymine (T) for four different orientations of each nucleobase in the nanopore. Reprinted with permission
from [43]. Copyright (2012), American Chemical Society
80 Advanced technologies for next generation integrated circuits
10 4
y90
S D 5 3
y A
Dielectric layer –5 1
z Vg –10 0
20 30 40 50 60 70
x (b) Vg(V)
(a)
Figure 3.21 (a) SET nanopore device modeled for nicotine detection and (b) the
charge stability diagram as electronic fingerprint. Reprinted from
[44], with the permission of AIP Publishing
Vtg
40
C 6
30
20 5
S D 10 4
0 D
3
–10
2
z6 –20
–30 1
–40 0
–40 –20 0 20 40
(a) Vbg (b)
Figure 3.22 (a) Double-gated SET with 1,3-cyclobutadiene island for the
detection of silicon atom impurity and (b) the respective charge
stability diagram electronic fingerprint. Reprinted from [45], with
the permission of AIP Publishing
Jain et al. have successfully utilized a tetracene quantum dot as a sensing host
to detect chlorine gas [48]. In this work, the tetracene quantum dot in SET envir-
onment is exposed to an approaching chlorine molecule and the resulting variations
in the electronic fingerprints are noted.
From Figure 3.24, the tetracene quantum dot is in the ionized state at zero
applied external potentials. When chlorine molecule is at a distance of 4 Å, only a
few degeneracy points show minute variations. At a distance of 3 Å, a definitive
right shift in the degeneracy points by a voltage of 0.05 V is noted. When chlorine
is close to the quantum dot (1.7 Å), a steep reduction in the excitation energy and
charge state transition of zero potential Coulomb blockade diamond from Dþ1 !
D0 is observed, representing the ultimate sensing ability of tetracene SET for
Single electron devices: concept to realization 81
Drain
Dielectric
layer Gate Source
H2O
Figure 3.23 Side view and the cross-section view of the gate all-around
architecture of SET designed for humidity and toxic gas detection.
Reprinted from [46], with the permission of AIP Publishing
15
–3,005 4
3
–2 2
–3,010
7.5
0
0
0
–3,025
–7.5
1
–3,030 2
–15
–3,035
(a) –8 –6 –4 –2 0 2 4 6 8 –10 –5 –1.8 0.2 4.45 6.2 10
Gate voltage (volt) Gate voltage (V)
15
–3,920
–2 4
–3,925 3
7.5
Total energy (eV)
–3,930 1
4Å –1 0
–3,935 2 1 0 –1 –2
D D D D
0
0 D
–3,940 1
–7.5
–3,945 2
–3,950
–15
–8 –6 –4 –2 0 2 4 6 8
(b) Gate voltage (volt) –10 –5 –1.75 0.2 4.45 6.25 10
Gate voltage (V)
15
–3,920
–2 4
–3,925 3
Source-drain voltage (V)
2
Total energy (eV)
7.5
–3,930 1
3Å –1 0
–3,935 2 1 0 –1 –2
D D D
0
D D
0
–3,940
1
–7.5
–3,945 2
–3,950
–15
(c) –8 –6 –4 –2 0 2 4 6 8
–10 –5 –1.7 0.25 4.5 6.3 10
Gate voltage (volt)
Gate voltage (V)
–3,910
15
4
3
2
Source-drain voltage (V)
–3,920
Total energy (eV)
1
7.5
–2 0
1.7 Å –3,930 –1 2 1 0 –1 –2
D D D D D
0
0
–3,940
–7.5
1
2
–3,950
–15
and theoretical [53] reports have successfully demonstrated the ability of SET for
charge detection.
To summarize the whole discussion, the research of single electron devices
has seen rapid advancements, since its first fabrication in 1987. Computational
simulations are always regarded as a way to cut the experimental expenses as
performing the simulation trials for various experimental possibilities not only save
money but also time. The DFT-based computational research has taken thrust since
Single electron devices: concept to realization 83
S D
(b)
Dielectric
G
Vg Vsd
(c)
(a)
Figure 3.25 (a) Schematic of SET with Cu-doped MoS2 quantum dot as host
material. Top and side views of (b) CO adsorbed Cu-MoS2 and
(c) NO adsorbed Cu-MoS2. [2018] IEEE. Reprinted with
permission, from [50]
the first successful modeling of SET device in 2010. So far, the device is been
widely explored for various applications such as switching, sensing, electrometry,
spectroscopy, and memory, both experimentally and theoretically. It is expected
that this novel device will take over the conventional FET devices in near future as
a switching element of ICs. Although there are few issues associated with the mass
fabrication and integration of these devices in large scale at this point of time, the
ever-increasing advancements in the fabrication technology may resolve such
issues and pave the way for a new generation of atomic scale single electron
devices with unprecedented computational capabilities.
References
[1] Kang, Sung-Mo and Yusuf, Leblebici; “CMOS Digital Integrated Circuits:
Analysis and Design” 3rd Ed., McGraw Hill Pub., New York, 2003, pp. 1–4.
[2] Web reference: http://download.intel.com/pressroom/images/events/moores_
law_40th/Microprocessor_Chart.jpg dated 19th Sep. 2018.
[3] Fuechsle, Martin, Jill A. Miwa, Suddhasatta Mahapatra et al. “A single-atom
transistor.” Nature Nanotechnology 7, no. 4 (2012): 242.
[4] Datta, Supriyo (2004) “ECE 453 Lecture 39: Coulomb Blockade,” http://
nanohub.org/resources/756
[5] Srivastava, Anurag, B. Santhibhushan, and Pankaj Dobwal “Performance
analysis of impurity added benzene based single-electron transistor.”
Applied Nanoscience 4, no. 3 (2014): 263–69.
[6] Averin, D. V., and K. K. Likharev “Coulomb blockade of single-electron
tunneling, and coherent oscillations in small tunnel junctions.” Journal of
Low Temperature Physics 62, no. 3–4 (1986): 345–73.
[7] Josephson, Brian David “Possible new effects in superconductive tunnel-
ling.” Physics Letters 1, no. 7 (1962): 251–53.
84 Advanced technologies for next generation integrated circuits
[51] Wang, Lin-Jun, Gang Cao, Tao Tu et al. “A graphene quantum dot with a
single electron transistor as an integrated charge sensor.” Applied Physics
Letters 97, no. 26 (2010): 262113.
[52] Schoelkopf, R. J., P. Wahlgren, A. A. Kozhevnikov, P. Delsing, and D. E.
Prober. “The radio-frequency single-electron transistor (RF-SET): A fast and
ultrasensitive electrometer.” Science 280, no. 5367 (1998): 1238–42.
[53] Ray, S. J., and R. Chowdhury. “Double gated single molecular transistor for
charge detection.” Journal of Applied Physics 116, no. 3 (2014): 034307.
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Chapter 4
Application of density functional theory (DFT)
for emerging materials and interconnects
Kazi Muhammad Mohsin1 and Ashok Srivastava1
4.1 Introduction
Scaling down of the critical dimensions of MOS transistors has been enabling
semiconductor industry to improve the performance of electronic devices. The idea
of scaling down goes back to 1965 when the founder of Intel’s Gordon Moore
forecasted the increase in functionality of integrated circuits (ICs), commonly
known as ‘Moore’s Law’. Moore’s law states that the number of transistors in an IC
would double in every 18 months. For nearly five decades, semiconductor industry
has fulfilled the prediction of this rule by constantly pushing the VLSI chip tech-
nology and maintained a tremendous effort spanning from material selection, fab-
rication process and novel architectures to keep the progress uncompromised.
However, Moore’s law may be reaching its end and a new paradigm shift with a lot
more interesting things are on the way [1]. One of the most interesting trends is the
exploration of novel wonder materials among the researchers. Not only experi-
mentalists are participating in this search but also theoreticians actively partici-
pating in predicting new exotic properties of newly discovered materials. Just to
name a few of these materials, carbon nanotube (CNT) [2], graphene, phosphorene,
etc. For VLSI applications CNT and graphene have been studied exhaustively
[3–13]. Among the various theoretical approaches, density functional theory (DFT)
[14,15] is one of the widely accepted approaches in studying new materials prop-
erties for electronic applications. In this chapter, DFT will be introduced briefly and
will be applied to simulate the electronic properties of a material.
DFT has been widely used by physicists, material scientists and chemists as a
method to understand new materials’ properties utilizing first principle approach. By
principle, DFT is an exact method. However, to speeding up the calculations,
1
Division of Electrical and Computer Engineering, Louisiana State University, Baton Rouge, LA, USA
90 Advanced technologies for next generation integrated circuits
b yi ¼ E i yi
H (4.1)
Application of DFT for emerging materials and interconnects 91
b is the Hamiltonian for a system consisting of M nuclei and N electrons. To
H
avoid the complexity of the development of DFT theory, we will not cover the
description of Hamiltonian of the system in this chapter. Rather we will present the
computationally demanding equation which will make more sense for explaining
the DFT theory. By Born–Oppenheimer approximation (BOA) [18], (4.1) reduces
to the following form,
Hd
elec yelec ¼ Eelec yelec (4.2)
Here Eelec is the Eigenvalue of (4.3) and Enu is the nuclear repulsive energy.
XM XM ZA ZB
Enu ¼ (4.4)
A¼1 B>A RAB
In (4.4), Z stands for the atomic number and R counts the inter-distance of each
pair. For example, RAB is the distance between the atomic centres of atom A and B.
If an electronic system is in the state y, its expectation value of the energy is,
hyHb yi
EðyÞ ¼ : (4.5)
hyyi
Here,
ð ! !
!
hyH by r dr
b yi ¼ y r H (4.6)
If a material system has N electrons and given nuclear potential is Vext, the
variational principle formulates a procedure to obtain the ground-state wave
92 Advanced technologies for next generation integrated circuits
function. In other words, the ground state energy is a function of the number of
electrons N and the nuclear potential Vext as described by the following (4.8).
Once ground state wave functions are obtained, ground state energy can be
calculated from the expected value of energy. From ground state wave functions,
electron density of ground state and other related properties of the material can be
calculated.
So far, we have seen how to calculate ground state of a material system using
(4.7). We re-write (4.7) for the minimum energy in terms of electron density as
follows,
ð ! !
!
E0 ¼ min F ½r þ r r Vnue r d r : (4.9)
r!N
In (4.9), the first term accounts for various electronic energy and the second
one electronic interaction energy with nucleus. Here, r is electrons density as a
function of space. Using KS theory and all necessary energy terms, the total energy
can be explicitly expressed in the following equation:
ð ð ! ! ð ! !
1X N
1 r r1 r r2 ! ! !
E ½ r ¼ hy r2 yi i þ d r1 d r2 þ r r Vnue r d r þ EXC ½r
2 i¼1 i 2 r12
(4.10)
The first term in (4.10) is electronic energy, the second term is the classical
Columbic interaction between electrons. The third term is the energy interaction
between electron and nucleus. The very last term in (4.10) corresponds to the
electronic exchange correlation. All terms in (4.10) are explicit except the last term
which accounts for exchange correlation. To obtain wave function dependency, all
density terms can be replaced by wave functions as follows,
ð ð 2
1X N
1XN X
N ! 1
y r1
! ! !
y r2 d r1 d r2
E ½ r ¼ hyi r2 yi i þ r
2 i¼1 2 i j 12
N ðX
X M
ZA !2 !
y r d r þ EXC ½r (4.11)
i
r
A 1A
Using the variational principle, now the problem is to minimize (4.11) under the con-
straint of wave function property hyi yj i ¼ dij . From this minimization, resulting
equation is the KS equation. KS equation looks like Schrödinger equation but is an
approximate to the true Schrödinger equation. KS equation is described by (4.12) as
follows,
Application of DFT for emerging materials and interconnects 93
"ð ! #!
1 r r2 ! ! XM
ZA 1 2 !
r2 þ d r þ VXC r1 yi ¼ r þ VS r1 yi ¼ i yi :
2 r12 r
A 1A
2
(4.12)
MATLAB,
avogadro/Xcrysden Wannier90
Molecular Atomic coordinates and Wannierization of
visualization crystal information electronic states in super computer
(INPUT)
Standard
Quantum conductance Post process programming
in MATLAB
Figure 4.1 Implementation of DFT using various software and programming tools
across various computational platforms
94 Advanced technologies for next generation integrated circuits
and selection of tools are shown in Figure 4.1. QUANTUAM ESPRESSO and
Wannier90 have been implemented using supercomputers. Code development,
testing and input/output generation were done in desktop computer.
The implementation of DFT starts with defining the crystal structure and
atomic coordinates. Any programming language can be used to obtain atomic
coordinates of a certain crystal structure. For example, we can take graphene’s
crystal structure. The first step is to define the unit cell of the graphene crystal. In
the following code, Quantum Espresso input code is presented for explaining gra-
phene crystal structure.
In Figure 4.2, the first section is to define what kind of calculation we are doing
using the DFT engine which is Quantum Espresso in this example. Calculation type
is used as ‘SCF’ which stands for ‘self-consistent field’ calculation. Beside calcu-
lation type, the first section also includes the computer work directory to save
necessary files. The second section is to define the crystal system. The first para-
meter ‘ibrav’ is to define what kind of Bravais lattice we are working with. In this
case, we are defining crystal structure of our own so it is not a predefined one.
Hence the value for ‘ibrav’ is set to ‘0’. We are using only carbon atoms in this
structure. So type of atom, ‘ntyp’ is set to ‘1’. Again, in a graphene crystal structure
there is to lattice points, populated by two carbon atoms. So, the number of atoms
‘nat’ is set to ‘2’. Lattice constant, ‘celldim (1)’ of graphene structure is 2.45 Å,
which is in atomic unit 4.830. After defining the crystal structure, we describe the
&CONTROL
calculation = 'scf'
restart_mode='from_scratch',
prefix='bulk',
pseudo_dir = '/work/',
outdir= '/work/output/',
/
&SYSTEM
ibrav= 0,
celldm(1) =4.830366967101510,
nat= 2, ntyp= 1,
/
&ELECTRONS
diagonalization='david',
electron_maxstep = 100,
mixing_beta = 0.2,
conv_thr = 1.0d-3,
/
ATOMIC_SPECIES
C 12.0107 C.pz-n-kjpaw_psl.0.1.UPF
CELL_PARAMETERS alat
1.000000000000000 0 0
0.500000000000000 0.866025403784439 0
0 0 10.732721359260136
ATOMIC_POSITIONS alat
C 0 0 0
C 0 0.577350269189626 0
K_POINTS automatic
4 4 1 0 0 0
Figure 4.2 Quantum Espresso input code for 2D graphene unit cell
Application of DFT for emerging materials and interconnects 95
electronic step calculation. For linear algebra package, we used the ‘Davidson’
diagonalization algorithm. In SCF calculation, maximum electronic calculation
iteration is set to ‘100’ as in ‘electron_maxstep’. Mixing beta is another optimization
parameter. Convergence threshold is the term to define the tolerance of the iterative
SCF calculation. Atomic species is to set the atom with its atomic mass in atomic
unit along with the pseudopotential file where the electronic energies of a single
isolated atom are pre-calculated. ‘Cell parameters’ are the crystal vectors of gra-
phene expressed in the unit of lattice constant which we previously defined in
‘System’ section. After defining all these sections, we need to define the atomic
positions of the two carbon atoms sitting at two lattice points of graphene crystal. At
the end the Brillouin Zone (BZ) or ‘K’ points sampling scheme is to be defined. In
this example, we are sampling with 4 4 1 points. The increase of ‘K’ points will
increase the accuracy of the calculation at the price of computational speed. The
output, electronic energy at different ‘K’ points will be generated in predefined
output directory. Next step will be post-processing these energy levels to generate
energy band diagram of the considered crystal system. The input code for Quantum
Espresso for band diagram calculation is as shown in Figure. 4.3.
In Figure 4.4, calculated energy band diagram of 2D graphene crystal is shown
along with the calculation from tight-binding method. Here, DFT accuracy has
been increased by considering the van der Waals correction (vdw) along with using
the plane-augmented wave (PAW) implementation [21].
&dos
prefix='bulk',
outdir = '/output/',
Emin = –5 , Emax = 5
DeltaE = 0.01,
fildos = '/work/kmohsi1/QE_g/dos.dat'
/
Figure 4.3 Quantum Espresso input code for band diagram calculation
0.8
DOS (states/eV/unitcell)
0.6
0.4
0.2
Tight binding
DFT+vdw+PAW
0
–5 0 5
Energy (eV)
→ →
ˆ a = dzˆ
a1 = a0x, 3
→ 1 ˆ 3 ˆ
a2 = a0 – x+ y
2 2
Y a0 = 2.56 Å, dCu-C = 2.24 Å
dCu-C = 2.08 Å
X
XY plane aligned with Cu {111} plane
Y
dCu-C
X
Z dCu-Cu
X
XZ plane, Cu {100} Graphene, C: sp2–sp2
minimum energy position for the whole system in equilibrium. Bottom two Cu
layers were fixed in their Cu crystal bulk position. Due to relaxation, one will find
that C-Cu interlayer distance increases slightly. Relaxation calculation optimizes
coordinates for all atoms in the system for finding the minimum energy state. Using
these optimized atomic positions, we then performed SCF calculation.
Each SCF cycle calculates electron density field which is a minimization
technique for electron density function. It tries to minimize the overall system
energy for an electron density distribution. When the difference of total energies of
two consecutive SCF cycles is reached as small as 109 eV, we stop the SCF
calculation. In SCF calculation, we sampled BZ uniformly with 32 32 1 K-grids
using Monkhorst–Pack (MP) method [23] for 2D bulk system. For one-dimensional
nanoribbon, we used 128 1 1 K-grids. MP method ensures generation of special
points in the BZ for facilitating efficient integration of periodic functions of the wave
vector over entire BZ.
Electron density obtained from SCF calculation was used for another round of
calculations for finding energy levels for each point of a densely sampled BZ.
We used 64 64 1 k-grids for BZ sampling using the MP method for 2D bulk
and 256 1 1 for nanoribbon. From this calculation, we obtained the electronic
band structure and electrons occupations in those energy states. We performed the
band structure calculation for 80 energy levels and obtained 0.7179 eV Fermi energy
for the bulk case and 3.9858 eV for the hybrid nanoribbon. Later on, for all other
calculations, we adjusted these Fermi energies to 0 eV when necessary for compar-
ison or for transport calculations. From SCF calculation, we constructed band struc-
tures and calculated density of states (DOS) of this hybrid system within QE code. For
DOS calculation, energy levels are adjusted in such a way that the Fermi energy
becomes 0 eV. Energy spectrum is sampled with a resolution of 10 meV.
Electronic band structure of G/Cu hybrid system for bulk (2D) and nanoribbon
(1D) are shown in Figures 4.6 and 4.7, respectively. From the band structure of
5
Band energy (eV)
0
Energy (eV)
Fermi energy
–5 0
–10 Band # 20
Band # 21
Band # 22 K
Band # 23
Fermi energy M
–15
Γ
–5
K Γ M K 0 10 20
Figure 4.6 (a) Band structure of G/Cu bulk system and (b) DOS from 5 eV to
5 eV are shown
98 Advanced technologies for next generation integrated circuits
8 8
6 6
6.0
4 4
5.0
4.0 2 2
Energy (eV)
Energy (eV)
3.0
Band energy (eV)
Figure 4.7 (a) Electronic band structure of G/Cu nanoribbon. Fermi level at
4.08 eV and (b) DOS of graphene interconnect are compared with
graphene/copper interconnect
bulk 2D system, it is apparent that four bands are crossing Fermi level (0.7179 eV).
Those Fermi level crossing bands are highlighted with red, green, blue and orange
colour in Figure 4.6(a) in the order of their energy from low to high energy. We
counted band index from the lowest energy one as first (near 15 eV). With this
counting, bands with indices 20 to 23 are contributing in constructing the Fermi
surface. For a metallic system, this multiple band crossing is expected. DOS of
G/Cu bulk system is shown in Figure 4.6(b). Being an infinite two-dimensional
system, DOS is continuous. Most importantly DOS is continuous and non-zero near
the Fermi energy. Just below 0 eV, there is a dense crowd of bands that is consistent
in DOS also.
For G/Cu nanoribbon, band structure and DOS are shown in Figure 4.7(a)
and (b), respectively. Unlike GNR, there is a non-zero DOS at Fermi level for G/Cu
nanoribbon. In case of nanoribbon, DOS is discrete due to one-dimensional con-
finement of the electron. In this hybrid system because of Cu, more states are
available in an energy window near the Fermi energy. Figure 4.7(b) shows the DOS
comparison of graphene and G/Cu material system. This difference of DOS in these
two material systems causes their difference in current transport.
We used Wannier90 code [24] for the transport study based on the Bloch states
obtained from SCF calculations. First step is to transform Bloch waves into
Wannier Function and then finding maximally localized Wannier wave function
(MLWF). Rest of the transport properties depend on MLWF. From MLWF, we
have computed current–voltage relation (I–V). Typical electronic MFP of copper is
40 nm and few microns for graphene. We assumed for this hybrid system electrons
MFP to be greater than 40 nm and smaller than 1000 nm. If this is the case for the
MFP, then this hybrid interconnect transport should be ballistic in nature for any
given interconnect length less than 40 nm. Hence, to compute current–voltage
Application of DFT for emerging materials and interconnects 99
2e2 m1 m2
I¼ M (4.13)
h e
Here, he is the magnitude of electronic charge and h is Planck constant. M
counts the number of transport modes for a conductor, m1 and m2 are the electro-
chemical potentials of left and right contacts, respectively. Wannier90 code uses
Bloch States obtained from QE code to obtain MLWF and construct system
Hamiltonian. After obtaining Hamiltonian, Wannier90 uses non-equilibrium Green
function (NEGF) for the transport calculation and transmission coefficient. In
Landauer–Buttiker (LB) formalism, by definition, the transmission coefficient is
quantum conductance. Due to high computational cost for first principle study, we
have limited our study to a 10 nm long wire, which represents a short local inter-
connect and is a good example of ballistic transport. For ballistic transport, one
should not use Fuchs–Sondheimer (FS) and Mayadas–Shatzkes (MS) models [25]
for resistivity estimation. Therefore, in ballistic transport regime, instead of FS and
MS theories we have used LB formalism.
In Figure 4.8, for graphene, no current is observed between 1.34 V and
1.34 V because of not having available states in that energy window. However, for
200
Graphene 30
Graphene
Graphene/copper 20 Graphene/copper
Current (µA)
150 10
0
–10
100
–20
–30
–1 –0.5 0 0.5 1
50 Voltage (V)
Current (µA)
–50
2e2 m1 – m2
–100 I= M e
h
–150
–200
–5 –4 –3 –2 –1 0 1 2 3 4 5
Voltage (V)
200
Graphene (2D)
G/Cu 2D
175 5 nm G/Cu
4 nm G/Cu
150 3 nm G/Cu
2 nm G/Cu
1 nm G/Cu
CQ (µF/cm2)
75
50
25
0
–1 –0.75 –0.5 –0.25 0 0.25 0.5 0.75 1
Voltage (V)
graphene on copper is still conductive in this window. Once, the I–V characteristics
of a material are known, resistance and resistivity can be calculated from this result.
DFT can be further used for the capacitive property calculation of hybrid
materials. Quantum capacitance can be calculated from the following equation,
ð þ1
CQ ¼ e 2 DðEÞFT ðE efG ÞdE (4.14)
1
Here, DOS is D(E) and FT ðEÞ is thermal broadening function defined as in (4.15).
df 1 E
FT ðE Þ ¼ ¼ sech2 (4.15)
dE 4KB T 2KB T
Equation (4.15) will be used for estimating thermal broadening at a finite tem-
perature for the calculation of quantum capacitance. However, for low temperatures,
the calculation becomes far easier. At absolute zero temperature, FT can be assumed
as a delta function and then CQ will be simply e2D(E). Calculated quantum capaci-
tance is a function of applied voltage. In Figure 4.9, voltage-dependent capacitance is
shown for various width of graphene–copper hybrid nanowires.
4.6 Conclusion
In this chapter, we have shown how to use DFT for modelling material and finding
their electronic structure. We have shown how to calculate the band diagram and
expanded it to the calculation of transport. Hybrid material modelling has been
Application of DFT for emerging materials and interconnects 101
References
[1] M. M. Waldrop, “The chips are down for Moore’s law,” Nature, vol. 530,
no. 7589, pp. 144–47, 2016.
[2] S. Iijima, “ Helical microtubules of graphitic carbon,” Nature, vol. 354,
no. 6348, pp. 56–58, 1991.
[3] N. Srivastava, and K. Banerjee, “Performance analysis of carbon nanotube
interconnects for VLSI applications,” Proceedings of the IEEE/ACM
International Conference on Computer-Aided Design (ICCAD), pp. 383–90,
2005.
[4] L. Hong, X. Chuan, and K. Banerjee, “Carbon nanomaterials: the ideal
interconnect technology for next-generation ICs,” IEEE Design & Test of
Computers, vol. 27, no. 4, pp. 20–31, 2010.
[5] A. Srivastava, Y. Xu, and A. K. Sharma, “Carbon nanotubes for next gen-
eration very large scale integration interconnects,” Journal of
Nanophotonics, vol. 4, no. 1, pp. 041690, 1–26, 2010.
[6] S. Berber, Y.-K. Kwon, and D. Tománek, “Unusually high thermal con-
ductivity of carbon nanotubes,” Physical Review Letters, vol. 84, no. 20,
pp. 4613–16, 2000.
[7] A. Naeemi, and J. D. Meindl, “Carbon nanotube interconnects,” Annual
Review of Materials Research, vol. 39, no. 1, pp. 255–75, 2009.
[8] M. Nihei, A. Kawabata, D. Kondo, M. Horibe, S. Sato, and Y. Awano,
“Electrical properties of carbon nanotube bundles for future via inter-
connects,” Japanese Journal of Applied Physics, vol. 44, no. 4A, pp. 1626,
2005.
[9] K. M. Mohsin, A. Srivastava, A. K. Sharma, and C. Mayberry, “A thermal
model for carbon nanotube interconnects,” Nanomaterials, vol. 3, no. 2,
pp. 229–41, April 26, 2013.
[10] K. M. Mohsin, A. Srivastava, A. K. Sharma, and C. Mayberry,
“Characterization of MWCNT VLSI interconnect with self-heating induced
scatterings,” Proceedings of the IEEE Computer Society Annual Symposium
on VLSI, pp. 368–73, 2014.
[11] K. M. Mohsin, and A. Srivastava, “Characterization of SWCNT bundle
based VLSI interconnect with self-heating induced scatterings,” Proceedings
of the GLSVLSI’15, pp. 265–70, 2015.
102 Advanced technologies for next generation integrated circuits
There are four fundamental circuit variables: voltage, current, charge, and magnetic
flux. Until the year 1971, there were only three fundamental components: resistor,
capacitor, and inductor. In that year 1971, Leon O. Chua proposed a new device
named “memristor” which relates charge and flux. At the time, due to lack of
sophisticated fabrication facilities, the new device did not receive much attention
until HP Labs successfully fabricated one in 2007. This fabrication of the new
device has provided device research with a new perspective as the memristor
exhibits a new hysteresis phenomenon named as “Pinched Hysteresis”. The mem-
ristor can remember the voltage that passed through it even when the supply is
turned off. Hence, the name memory þ resistor, memristor. After the device was
fabricated successfully, research has been done extensively implementing the
memristor in various applications which require reconfigurability. The memristor
has been used from oscillators to neural networks and logic gates to security
applications giving it a wide range of applications. This chapter presents the device
description, characteristics, and various applications of the memristor in analog and
digital applications.
This chapter is organized as follows: different types of memristors are
presented in Section 5.2. Fabrication principles of the memristor and how it
works are presented in Section 5.3. For simulation purposes, various models
for memristors have been proposed. Such models are presented in Section 5.4.
The electrical characteristics of the memristor are presented in Section 5.5.
Applications of memristors in analog and digital nanoelectronics are presented in
Sections 5.6 and 5.7, respectively. Summary and future directions are presented
in Section 5.8. Table 5.1 summarizes the notations and symbols used in the
current chapter.
1
School of Engineering & Technology, Central Michigan University, MI, USA
2
Computer Science and Engineering, University of North Texas, Denton, TX, USA
3
Electrical Engineering, University of North Texas, Denton, TX, USA
4
Electronics and Communication Engineering, Oriental University Indore, INDIA
104 Advanced technologies for next generation integrated circuits
5.1 Introduction
Non-volatile
memory
Programmable Low-power
logic applications
Memristor
Security Crossbar
latches
Analog and
digital
computations
crossbar latch which can be used for various purposes including memory [25],
neural networks [26], and security [27].
Memristor
Spin transfer
Titanium dioxide Polymeric Spintronic
torque
memristors memristor memristor
magnetoresistance
Resonant
Manganite
tunneling diode
memristors
memristors
the device and the direction of the voltage will determine the memristance offered
by the device. A polymeric memristor is another type of thin-film memristor [41]. It
also works on the principle of using a conducting layer of polymer in the device. A
polyaniline (PANI) layer is responsible for the variation of memristance according
to the redox state. A single passive layer between an electrode and an active thin
film attempts to exaggerate the extraction of ions from the electrode.
The existing literature presents memristors with different device structure and
materials used for design and fabrication [29–35,42–44].
Silicon substrate
Electron-gun evaporation
RF magnetron sputtering
TiO2/TiO2+xactive layer
Electron-gun evaporation
the atoms are concentrated in a single layer, the memristance offered by the device
will be high and when the atoms are distributed across the device, the memristance
offered will be low.
The titanium dioxide thin-film memristor has the following layers: [(1)] Layer-1:
the bottom titanium/platinum (Ti/Pt) bilayer electrode. Layer-2: active titanium
dioxide (TiO2) layer. Layer-3: active titanium dioxide with excess oxygen (TiO2þx)
layer. Layer-4: the top titanium/platinum (Ti/Pt) bilayer electrode. The process of
fabricating the memristor is shown in Figure 5.5. On the silicon substrate, electron
gun evaporation is performed to deposit the titanium or platinum electrodes. Then
the titanium dioxide layer is deposited with radio frequency magnetron sputtering
at room temperature and the titanium dioxide layer with excess atoms. The TiO2þx
layer is made non-stoichiometric with the addition of excess oxygen atoms by
passing oxygen gas during the deposition, making it the active layer of the
110 Advanced technologies for next generation integrated circuits
memristor. An additional layer of Ti/Pt bilayer is deposited for the top electrode to
make it a complete memristor.
Figure 5.6 shows an example of a magnetoresistance memristor [48,49]. There
are two different layers in the device. One is the fixed magnetic layer and the other
is the free layer. The fixed layer is considered as the reference and the free layer is
divided into two different sections each with opposite polarities. The change in the
resistance occurs when the movement of the domain wall dividing the two sections
is induced by the application of current.
Memristors are also manufactured based on the motion of silver dopants [29].
A cross-section of the memristor based on silver dopant motion is shown in
Figure 5.6. As in the usual memristor, there are two metal electrodes on the top and
bottom of the device. In between the metal layers, there is an amorphous silicon
layer and amorphous silver þ amorphous silicon layers. The silver ions are freely
moving in this case into the silicon layer based on the voltage applied. When the
top electrode is supplied with a positive voltage, the silver ions will move into
the silicon layer which will decrease the memristance offered by the device. When
the applied voltage direction is reversed, all the ions will move into the
silver þ silicon layer which will increase the memristance.
The silver dopant-based memristor structure is shown in Fig. 5.7(a) and the
silicon-based memristor cross-section design is shown in Figure 5.7(b) [30]. As
shown, there is a metal electrode in the top of the device which is followed by the
amorphous silicon layer which is co-sputtered by silver. This layer is an active
layer. The silver ratio in the layer is gradually varied toward the other end of the
device itself. At the bottom of the device, there is another electrode made from a
heavily doped p-type crystalline material. When a voltage is applied at the top of
the device, a conduction channel will form through the active layer of amorphous
silicon. This conduction layer will reduce the memristance offered by the device.
When the direction of the voltage applied reverses, the memristance offered by the
device will increase obstructing the flow of electrons.
The memristor structure based on silver chalcogenide is shown in Figure 5.7(c)
[34,50]. In this type of memristor, tungsten electrodes are used on the top and
Position (X)
Free layer
Ref. layer
Electrode Metalelectrode
Metal Electrode
Silver + Silicon
(Ag+Si) Amorphous - Silicon
Contact
bottom of the device. Between the top and bottom electrodes, there are three
Ge2Se3 layers. As shown in the figure, between the Ge2Se3 layers, there are Ag and
Ag2Se layers. Agþ ions will be able to freely move to the chalcogenide layer based
on the voltage applied. If a positive voltage is applied at the top electrode, all the
ions will migrate to the Ge2Se3 layers which will reduce the memristance offered
by the device. When the polarity is reversed, the memristance of the device will
increase.
Finally, the cross-section of a flexible memristor is shown in Figure 5.7(d)
[42]. Laser jet transparency is used to design the flexible memristor. The electrodes
used in this design are made of Al. Between the two Al electrodes, a TiO2 layer is
sandwiched. The properties exhibited by the device allow the scaling of the device
in the nanometer regime.
V A
Doped Undoped
RDoped RUndoped
significantly. The memristance for the dual-sided doped memristor is given by:
1
M ½q ¼ Roff 1 2 qðtÞ mv1 Ron1 þ mv2 Ron2 Ron ; (5.3)
D
where Ron1 and Ron2 are the on resistances of each layer.
The resistance of the memristor can be generalized as a time function [52]
given by:
All memristors that were initially introduced considered a periodic input for
the device. A mathematical model for the memristance is provided in [53] for a DC
input and symmetric periodic inputs. Based on the polarity of the input voltage, the
boundary of the dopants will move in the appropriate direction, increasing or
decreasing the memristance of the device. After evaluating the flux in (5.4), the
resistance can be written as:
where VDC is the DC voltage applied to the device and t is the time required to
reach saturation.
XSV
Top
electrode
iGm(t) iGx(t)
X(t)
Gm Gx Cx
Bottom
electrode
(a) Memristor (b) Determining the state variable.
SPICE equivalent
for determining
I−V characteristics
are modeled by a current source, Gm as shown in Figure 5.9(a). For determining the
state variable, the current source is connected in parallel to a capacitor.
For determining the IV characteristics, the current is given as [59]:
end
equations
let
az = mu * Ron / D^2;
in
if(X0 <= 0 && v <= 0)||(X0 >= 1 && v >=
0)
X0.der == 0;
else
X0.der == az & i;
end
end
Rm == Ron & X0 + Roff * (1 - X0);
v == i * Rm;
end
end
a1 xðtÞsinh ðbV ðtÞÞ; V ðtÞ 0;
iGm ðtÞ ¼ (5.6)
a2 xðtÞsinh ðbV ðtÞÞ; V ðtÞ < 0:
For determining the state variable from Figure 5.8 [59]:
iGx ðtÞ ¼ gðV ðtÞÞf ðV ðtÞ; xðtÞÞ (5.7)
ðt
xðtÞ ¼ iðtÞdt (5.8)
0
To plot the state variable during simulations, the port XSV was created in the
circuit. Algorithm 2 presents a SPICE subcircuit model of the memristor [59].
+
V
Rg
f(h,L,Af)
If Ib
f(Ad,d)
Rf
f(h,Af)
fz = uv * ron / (d**2);
fp = uv * vp / (d**2);
fn = uv * vn / (d**2);
xa = x0;
end
@(cross(V(mem), 0) or cross(V(mem)-vp, 0) or cross(V(mem)-
vn, 0));
if (V(mem) >= vp)
dxdt = fp * limexp(I(mem) * ron / vp);
else if (V(mem) <= vn)
dxdt = fn * limexp(I(mem) * ron / vn);
else dxdt = fz * I(mem);
if ((integ == -1 && V(mem) > 0) || (integ ==
1 && V(mem) < 0)) integ = 0;
@(cross(x,-1)) begin
integ = -1;
xa = 0;
end
@(cross(x-1,1)) begin
integ = 1;
xa = 1;
end
x = idt(dxdt, xa, integ, 1e-12);
rm = ron * x + roff * (1 - x);
I(mem) <+ V(mem) / rm;
end
endmodule
ADC
Vin B1
Digital potentiometer
GND
Vref B8
Sign
Analog to digital
converter ENB
Microcontroller
Even before Chua posited the memristor, its characteristics were observed by many
researchers [2–4]. Pinched hysteresis is the main fingerprint of the memristor.
Pinched hysteresis was observed throughout history in various forms, such as
the imperfect metal-to-metal contacts while fabricating an IC. But these effects
were not significant until we reached the nanometer scale [68,69]. Resistance vs.
voltage ðRV Þ and current vs. voltage ðIV Þ characteristics of a typical memristor
are shown in Figure 5.12. As shown in Figure 5.13, the memristor provides the
missing relationship between charge and flux.
Figure 5.8 shows the memristor device structure and the equivalent circuit
considered to observe the current-voltage characteristics [33]. As shown in the
figure, the device is divided into two regions, doped and undoped, due to the drift
of dopants throughout the device based on the voltage polarity supplied. When the
doped region is small, the memristance provided by the device will be high and
when the doped region is large, the memristance provided will be low.
For analysis purposes, the following parameters are considered for the mem-
ristor: [(1)] Lactive —total active length of the memristor. This is fixed once a
memristor is manufactured. ldoped ðtÞ—the doped active length of the memristor.
This changes with the voltage applied across the two terminals. Rdoped —resistance
of the doped layer of length Lactive . This is equivalent to the ON state resistance of
the memristor RON . Rundoped —resistance of the undoped layer of length Lactive .
This is equivalent to the OFF state resistance of the memristor ROFF . vðtÞ—the
applied biasing voltage across the memristor. qðtÞ—the resulting charge in
the memristor. iðtÞ—the resulting current through the memristor. m—the average
carrier mobility.
120 Advanced technologies for next generation integrated circuits
12,000
10,000
8,000
Resistance
6,000
4,000
2,000
0
–1.5 –1 –0.5 0 0.5 1 1.5
Voltage
(a) Resistance versus voltage (R−V ) characteristic.
×10–4
3
1
Current
–1
–2
–3
–1.5 –1 –0.5 0 0.5 1 1.5
Voltage
(b) Current versus voltage (I−V ) characteristic.
When we apply Kirchhoff’s voltage law (KVL) to the circuit equivalent of the
device shown in Figure 5.8, we obtain the following equation:
ldoped ðtÞ ldoped ðtÞ
vðtÞ ¼ Rdoped þ Rundoped 1 iðtÞ: (5.11)
Lactive Lactive
For linear drifting with uniform field, the doped active length ldoped ðtÞ is
obtained as the product of carrier velocity and carrier drifting time. The carrier
velocity is the product of the carrier mobility ðmÞ and the electric field, which is
given by the ratio vðtÞ=Lactive . The drifting time is calculated as the ratio of charge
Memristor devices and memristor-based circuits 121
R = dv/di
Voltage Current
v i
i i
C = dq/dv
L = dØ/di
v v
Charge q Ø Magnetic
M = dØ/dq flux
Figure 5.13 Memristor relates magnetic flux and charge; the missing connection
among the four variables, v, i, q, and f [33]
From (5.12) and (5.13), the memristance ðMÞ can be derived as:
vðtÞ mRdoped
MðqÞ ¼ ¼ 1 qðtÞ Rundoped : (5.14)
iðtÞ L2active
The memristance offered by the memristor can be changed on the fly by supplying
current to the device in the required direction. Hence, with memristive components
at the core of these designs, reconfigurability and reprogrammability can be added
to the system.
C2 R 1 R 3
þ ¼ ; (5.15)
C1 R 2 R 4
and the frequency of any Wien oscillator is calculated by the following:
1
f ¼ pffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi : (5.16)
2p R1 R2 C1 C2
In the Wien oscillator, when the resistors are replaced with memristors, the
memristance will drive the oscillations and based on the resistance offered by the
memristance, the oscillations can be controlled [33,70] according to (5.16). It is
assumed that the memristance of the memristor is not changed intentionally during
the operation of the oscillator. In such case, the initial memristance of the device
will determine the oscillation frequency.
Five different configurations can be attained by replacing the resistors with
memristors. R1 is replaced with the memristor M1 in configuration 1 and the
memristance is labeled R1;mem . R2 is replaced with memristor M2 in configuration 2
and the memristance is labeled R2;mem . R3 is replaced with memristor M3 in
C1 R1
+ Vout
R2 C2
–
R4
OPAMP
R3
C1 R1
+ Vout
R2 C2 –
M4 OPAMP
M3
C1 R1
+ Vout
R2 C2 –
M4 OPAMP
M3
Vdd
PMOS1 PMOS2
C1 C2
Vtune VoutN
L L
VoutP M C1 C2
NMOS1 NMOS2
Ip
Reset Set
RM
R set reset
Out Out
C C
Neurons
Digital nanoelectronics have come a very long way and Moore’s law has been the
driving force of IC technology development till now. Transistors have scaled down
and reached almost their limit. Memristors are predicted to replace transistors in the
near future as they are being introduced into the digital nanoelectronic domain.
Digital components are a part of almost every SoC or every IC in the market. With
the need for high-performance and low-power-consuming devices, research in
memristors has grown exponentially. With the advantage of reconfigurability on
the fly, memristors find their way into many major applications of digital electro-
nics starting at the fundamental logic gates, through security, and FPGA imple-
mentations. This section presents memristor-based applications in digital
nanoelectronics.
Memristor devices and memristor-based circuits 127
In1
Out
In1 In2 Out
In2
V0
V0
Input Working
memristors memristors
Extra 2 Carry in
Input A Input B Sum Y bits
… … …
… … …
Besides the design shown in Figure 5.21, there are many other designs of
memristor-based full adders proposed. A memristor-based XOR is used to build a
full adder in [90]. In this design, four memristors will be controlling the input and
four memristors will be controlling and storing the output sum and carry. An n-bit
design can be constructed by cascading the 1-bit design [90].
NEG Vwr
0 0
0 1
1
1
1
Response
bit
Challenge
bit
….
….
VI
…. ….
….
….
….
….
….
….
….
VO
horizontal and vertical wires [26]. This is much easier for the implementation of a
connection matrix in neural networks.
Acknowledgments
This chapter is based on previous papers from the authors, such as the following:
[33,55,61]. The authors would like to acknowledge their graduate students (Geng
Zheng and Mahesh Gautam) at the University of North Texas (UNT), who helped
with preliminary versions of this research.
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Chapter 6
Organic–inorganic heterojunctions for
optoelectronic applications
Chandra Shakher Pathak1,2, Jitendra Pratap Singh2 and
Rajendra Singh2
6.1 Introduction
Conducting polymers have been attracting attention after their discovery by
Shirakawa, MacDiarmid, and Heeger in 1977, who were awarded the Nobel Prize
in Chemistry in 2000 for the discovery of conductive polymers [1,2]. They used
organic polymer polyacetylenes, which is a conjugated polymer and insulator. They
increased the conductivity of polyacetylene films by several orders of magnitude by
chemical doping [1]. In recent years, there has been a lot of research activity in the
field of polymer electronics. It has attracted a lot of attention because of its light-
weight, high flexibility, and solution process ability [3]. Applications of conducting
polymers include organic light-emitting diodes, organic thin-film transistors, solar
cells, actuators and sensors, etc. [4–8]. Until the 1970s, organic polymers were
considered to be nonconducting and used as insulators. After the discovery of
conducting polymer, vast improvements in synthetic polymers have resulted in
polymers being used for conductive applications.
Poly (3,4-ethylenedioxythiophene)-poly(styrenesulfonate) (PEDOT:PSS) is
widely used conducting polymer because of its high conductivity, excellent thermal
stability, transparency, structural stability, and processability [9–11]. PEDOT:PSS
polymer is a promising candidate as a transparent electrode for optoelectronic devices.
PEDOT is made from ethylenedioxythiophene (EDOT) monomers. PEDOT is inso-
luble in many common solvents, and it is unstable in its neutral state. To improve its
processability, water-soluble polystyrene sulfonate (PSS), can be added and the
addition of PSS causes it to become soluble. During the polymerization, PSS acts as
charge-balancing dopant to yield PEDOT:PSS. PEDOT:PSS is synthesized from the
EDOT monomer, and PSS acts as the counter ion. The degree of polymerization of
1
Ben-Gurion National Solar Energy Center, Department of Solar Energy and Environmental Physics,
Jacob Blaustein Institute for Desert Research, Ben-Gurion University of the Negev, Midreshet Ben-
Gurion, Israel
2
Department of Physics, Indian Institute of Technology Delhi, New Delhi, India
140 Advanced technologies for next generation integrated circuits
PEDOT is limited and the chain length of PEDOT has been estimated up to 5 ~ 10
repeating units [12]. PEDOT chains are attached to the PSS chains through the
Columbic interaction and they are stabilized by the excess PSS.
The actual conductivity of PEDOT:PSS is a major limiting factor for device
applications. There have been several efforts to enhance the properties of PEDOT:
PSS through solvent treatments [4–6]. The solvent treatment of PEDOT:PSS films
may affect the conformation of the polymer. The structure of PEDOT chain
changes from benzoid to quinoid structure after solvent treatment [9]. The role of
organic solvent like dimethyl sulfoxide (DMSO) is a secondary dopant, which
improves the morphology of PEDOT:PSS films and improves the conductivity of
the films, which depends on its concentration [9]. When DMSO is added, the
interactions between the PEDOT chains and DMSO additive induce the con-
formational changes from coil structures to linear and expanded coil structures. The
interactions are initiated by the hydrogen bond formation between the sulfonic acid
groups and the polar groups of DMSO. Apart from the change in conductivity of
PEDOT:PSS films, solvent treatment may also affect other properties of the films
such as morphological and optical properties [13–15]. Pathak et al. [14] demon-
strated the effect of co-solvent on the electrical, vibrational, and morphological
properties of PEDOT:PSS films. They enhanced the conductivity of PEDOT:PSS
films by three orders of magnitude. Graphene oxide (GO) has recently emerged as a
new carbon-based material because of its low cost, large-scale production cap-
ability. The solubility of GO in water and other solvents allows it to be uniformly
deposited onto wide-ranging substrates in the form of thin films.
PSS PSS
PEDOT
GO
PEDOT
GO has emerged as a new carbon-based material due to its low cost and
large-scale production capability. Researchers have also used GO to enhance the
properties of PEDOT:PSS films [20,21]. Raj et al. have used GO blended with
PEDOT:PSS as hole-transporting layer for PTB7:PCBM bulk heterojunction solar
cells [20]. GO is used as a separating agent between the conducting PEDOT and the
insulating PSS to increase the conductivity of the electrode. In PEDOT:PSS,
PEDOT chains are attached to insulating PSS chains through columbic attraction.
The functional groups of GO separate the PEDOT and PSS chains. The columbic
attraction between PEDOT and PSS chains gets weaker and improves the linear
conformation of PEDOT and PSS chains. The separated PEDOT chains link up
with functional groups of GO, which enhance the conductivity of PEDOT:PSS
film. Figure 6.1 shows the schematic representation of conductivity enhancement
mechanism of PEDOT:PSS films with GO.
microscopy (KPFM) in the tapping mode and current image obtained using con-
ducting atomic force microscopy (CAFM) in the contact mode.
sulfoxide (DMSO), ethylene glycol (EG) and methanol (MeOH), GO and zonyl
were spin coated on Si wafers at 2,000 rpm for 60 s. The prepared PEDOT:PSS
films were then annealed at 150 C for 10 min on a hotplate. Finally, top contacts
were made with gold by thermal evaporation at a vacuum of 105 Torr. Ohmic
contacts using eutectic In–Ga were made on the backside of Si.
2 2
Height (nm)
Height (nm)
0 0
–2 –2
500 nm –4 –4
500 nm
–10 nm 0 200 400 600 800 1000 0 200 400 600 800 1000
–10 nm
10 nm Distance (nm) 10 nm Distance (nm)
8 10
(c) NMP NMP (d) DMSO DMSO
6 8
4 6
Height (nm)
Height (nm)
4
2
2
0
0
–2 –2
–4 –4
500 nm –6 500 nm –6
–8 –8
–10 nm 0 200 400 600 800 1000 –10 nm 0 200 400 600 800 1000
Distance (nm) 10 nm Distance (nm)
10 nm (f)
(e) EG 8 MeOH 8
EG MeOH
6 6
4 4
Height (nm)
Height (nm)
2 2
0 0
–2 –2
–4 –4
500 nm 500 nm
–6 –6
–10 nm
–10 nm 0 200 400 600 800 1000 0 200 400 600 800 1000
Distance (nm) Distance (nm)
Figure 6.2 Height and respective line scan of (a) bare, (b) DMF, (c) NMP, (d) DMSO, (e) EG, and (f) MeOH organic solvents doped
PEDOT:PSS films
Organic–inorganic heterojunctions for optoelectronic applications 145
0.0 Height Sensor 25.0 μm 0.0 Height Sensor 25.0 μm 0.0 Height Sensor 25.0 μm
(d) (e)
32.2 nm 37.1 nm
–26.1 nm –32.3 nm
Figure 6.3 AFM images of PEDOT:PSS films with (a) 0.01, (b) 0.03, (c) 0.05,
(d) 0.08, and (e) 0.10 vol.% doping concentration of GO
6.3.3 Conductivity
Conductivity enhancement of PEDOT:PSS films strongly depends on the chemical
structure of used organic solvents for doping. The bare PEDOT:PSS film exhibited
a low electrical conductivity of 0.16 S/cm, which is due to the disconnected
PEDOT chain. MeOH has a low boiling point, and it has only one polar group, the
electrical conductivity is not enhanced remarkably, despite having high dielectric
constant. Conductivity did not change remarkably with solvents having one polar
group and low boiling point [25]. However, by using polar solvents having high
boiling points such as DMSO, DMF, NMP, and EG, conductivity is enhanced
significantly. The high boiling point should allow more time to the PEDOT:PSS
film for structural refinements during the drying process. We obtained conductivity
of 40.0, 8.0, 19.0, 30.0, and 1.6 S/cm for NMP, DMF, DMSO, EG, and MeOH,
respectively. MeOH has only one polar group and there is not much enhancement
(a) Bare (b) DMF –320
–540 Bare DMF
–580 –340
–600 –350
–620 –360
500 nm 500 nm
–640
0 200 400 600 800 1,000 –370
0 200 400 600 800 1,000
Distance (nm) Distance (nm)
(c) –380 (d)
NMP NMP
DMSO –400 DMSO
Figure 6.4 Potential and respective line scan of (a) bare, (b) DMF, (c) NMP, (d) DMSO, (e) EG, and (f) MeOH organic solvents
doped PEDOT:PSS films
Organic–inorganic heterojunctions for optoelectronic applications 147
(d) (e)
220.3 mV 269.2 mV
117.8 mV 169.4 mV
Figure 6.5 Surface potential images of PEDOT:PSS films with (a) 0.01, (b) 0.03,
(c) 0.05, (d) 0.08, and (e) 0.10 vol.% doping concentration of GO
in conductivity. DMSO has only one polar group and it has strong dipole moment
close to PEDOT chain so that the dipole–dipole interaction can take place after the
formation of hydrogen bond with PSS [20]. From our results, we showed that the
conductivity obtained with NMP doping is much higher and it has the best com-
promise between high boiling point and high dielectric constant [26]. Similar
enhancement in the conductivity of solvent-modified PEDOT:PSS films was also
observed by Kim and Jonsson [16,17]. The reduction of PSS is confirmed by the
CAFM technique. CAFM current images of organic solvents-doped PEDOT:PSS
films are shown in Figure 6.6. From the current image, we observed the current in
nA range for bare-, DMF-, NMP-, DMSO-, EG-, and MeOH-doped PEDOT:PSS
films, respectively. Bare PEDOT:PSS has the minimum current and maximum
current was observed for NMP-modified PEDOT:PSS film. This shows the
reduction of more PSS from the surface for NMP-doped PEDOT:PSS film. The
current values obtained for all films are well correlated with the conductivity value
of PEDOT:PSS films.
The conductivity of PEDOT:PSS film increases with GO addition and after the
optimal value of GO conductivity starts to decrease. The average enhanced con-
ductivity of GO-PEDOT:PSS film with 0.05 vol.% GO was found to be 118 S/cm
compared to 0.16 S/cm for pristine PEDOT:PSS film. The conductivity of PEDOT:
PSS films then decreases with further increase in GO vol. The decrease in con-
ductivity after optimal doping of GO is mainly due to the reduction in structure
orientation of PEDOT due to the presence of more GO on the surface. Figure 6.7
shows the variation in the conductivity of PEDOT:PSS films with GO vol.%
deposited on glass substrate. In PEDOT:PSS, conductive PEDOT chains are
attached to insulating PSS chains through columbic attraction.
148 Advanced technologies for next generation integrated circuits
0.0 C-AFM Current 1.0 μm 0.0 C-AFM Current 1.0 μm 0.0 C-AFM Current 1.0 μm
0.0 C-AFM Current 1.0 μm 0.0 C-AFM Current 1.0 μm 0.0 C-AFM Current 1.0 μm
Figure 6.6 CAFM images of (a) bare, (b) DMF, (c) NMP, (d) DMSO, (e) EG, and
(f) MeOH organic solvents doped PEDOT:PSS films
120
100
Conductivity (S/cm)
80
60
40
20
0.00 0.02 0.04 0.06 0.08 0.10
Graphene oxide (vol.%)
PEDOT and PSS chains are separated by the functional groups of GO such as
–OH and –COOH. As a result of GO addition to PEDOT:PSS solution, the
columbic attraction between PEDOT and PSS chains becomes weaker which
improves the linear confirmation of PEDOT and PSS chains. The separated
PEDOT chains link up with functional groups of GO that enhance the conductivity
Organic–inorganic heterojunctions for optoelectronic applications 149
2,100
NMP
DMF
1,800
DMSO
1,500 EG
Intensity (a.u.)
MeOH
1,200
900
600
300
0
1,300 1,400 1,500 1,600
Raman shift (cm–1)
35
GO
800 30
Intensity (a.u.)
25
20
15
Intensity (a.u.) 600 10
5
0
400 1,200 1,400 1,600 1,800 2,000
Raman shif (cm–1)
0.01 vol.%
200 0.03 vol.%
0.05 vol.%
0.08 vol.%
0.10 vol.%
0
1,350 1,500 1,650 1,800
–1)
Raman shift (cm
10–4
10–5
10–6
Current (A)
10–7
10–8
NMP
10–9
DMF
10–10 DMSO
EG
10–11 MeOH
–1.0 –0.5 0.0 0.5 1.0
Voltage (V)
Figure 6.10 Semi-log forward and reverse I–V characteristics for Au/PEDOT:
PSS/n-Si/In-Ga heterojunction diodes doped with organic solvents
10–3
10–4
Current (A)
10–5
0.01 vol.%
0.03 vol.%
0.05 vol.%
10–6 0.08 vol.%
0.10 vol.%
–2 –1 0 1 2
Voltage (V)
vol.%. This is due to the presence of less amount of PSS chain network on the
surface and rearrangement of PEDOT, which enhances the charge transfer across
the device and improves the diode parameters and the reduction of PSS is also
confirmed by highest conductivity value obtained for 0.05 vol.% GO. Low ideality
factor, low reverse leakage current and higher barrier height are needed for good
quality diodes, and the heterojunction diodes fabricated with 0.05 vol.% GO have
all these requirements, which confirms the formation of good quality junction.
After the optimal value of GO, the ideality factor starts to increase and it might
be due to the decreased conductivity. The larger value of ideality factor may be
attributed to secondary mechanism like generation-recombination at the interface.
In this case, the charge transport across the interface is no longer due to the ther-
mionic emission but the other mechanism like generation and recombination of
charge carriers in depletion region might be the dominant current transport
mechanism. The electronic conduction through the diodes affected by the charge
Organic–inorganic heterojunctions for optoelectronic applications 153
traps in the conductive polymer and traps are locations arising from the defects,
impurities, disorders, etc. The interface states between the GO-PEDOT:PSS and Si
play an important role in the current transport process. Interface defects may also
lead to a lateral inhomogeneous distribution of barrier heights at the interface
[30–32]. The larger value of the ideality factor indicates that the forward current is
governed by the recombination current.
10–2
Current density (A/cm2)
10–3
Bare
NMP
DMF
DMSO
EG
10–4 MeOH
–0.1 0.0 0.1 0.2 0.3 0.4 0.5
Voltage (V)
18.91%. The low values of FF indicate extra current-limiting effects which are not
essentially related to PEDOT:PSS properties but arise from recombination sites
present at either Si surface or Au/PEDOT:PSS interface which causes larger ide-
ality factors and lower FF values [33]. The bare PEDOT:PSS sample shows the
short-circuit current density (Jsc) of 1.11 mA/cm2 and after doping with organic
solvents Jsc increases up to 5.46 mA/cm2 and well correlates with the increased
conductivity of PEDOT:PSS films. The removal of PSS and enhanced conductivity
has a positive effect on the value of Jsc. For bare PEDOT:PSS, power conversion
efficiency (PCE) value is 0.068% which was found to be increased up to a max-
imum of 0.526% after the addition of organic solvents.
The maximum PCE is obtained for EG-doped PEDOT:PSS film. PCE has
increased around 8 times by the addition of EG compared to the bare PEDOT:PSS
film. Due to the low value of FF and Jsc, we obtained a low value of PCE which is
attributed to the fact that the PEDOT:PSS films were deposited in air, resulting in
the polymer particles being oxidized during the deposition process. The presence of
oxygen has an adverse effect on the performance of polymer especially on FF [14].
The low value of PCE is because of higher leakage current, low value of Jsc and FF
of fabricated cells. We observed maximum PCE for EG-modified PEDOT:PSS due
to the low leakage current. The value of VOC is in good agreement with the reported
value, while the Jsc and FF values are not high. PEDOT:PSS is hygroscopic in
nature and it can absorb moisture during the fabrication process. This might be one
reason for low Jsc and FF. PEDOT:PSS cells without solvent have a PCE of
0.068% due to the low conductivity and organic solvents-modified PEDOT:PSS
solar cells have higher PCE in comparison to bare due to better conductivity.
Evac
KPFMΦp = 4.90 eV
Ec
EF
Ec
The band bending creates a space charge region resulting in a barrier to the
charge flow at the interface of PEDOT:PSS/n-Si. When the two materials are
brought in contact with each other, they will interact so as to achieve thermal
equilibrium resulting in the constancy of the EF.
6.4 Summary
Acknowledgments
C.S. Pathak is grateful to the Department of Physics and Nanoscale research facility
(NRF), Indian Institute of Technology Delhi, India, for providing characterization
facilities.
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Chapter 7
Emerging high-k dielectrics for nanometer
CMOS technologies and memory devices
Durgamadhab (Durga) Misra1, Md Nasir Uddin Bhuyian2,
Yi Ming Ding3, Kolla Lakshmi Ganapathi 4, and
Navakanta Bhat5
7.1 Introduction
The gate length of complementary metal-oxide semiconductor (CMOS) devices has
been scaled to below 10 nm with a three-year delay from the predicted year from
ITRS 2007 report [1]. The aggressive scaling has slowed down due to the transistor
reaching its physical limits. Three approaches are being followed to continue
scaling of chips [2]: (i) gate stack material, (ii) channel material, and (iii) device
architecture. The dielectric layer of gate stack is one of the leading candidates for
devices below 10 nm [3]. Metal gate high-k (MGHK) has been implemented to
boost the chip performance while keeping the physical thickness thick enough to
prevent large direct tunneling current. Secondly, different channel materials with
higher carrier mobility, other than Si, have been considered [4]. While only strained
silicon has been implemented thus far materials such as Ge or III-Vs are still in
their research stage. 3D structures like FinFET have been successfully imple-
mented to improve the drain-induced barrier lowering (DIBL) related to short
channel effect [5].
While CMOS technology is scaling down, the deposition process of high-k
gate dielectric and annealing has significantly improved. Atomic layer deposition
(ALD) method for high-k deposition provided several advantages over alternative
deposition methods, such as chemical vapor deposition and various physical vapor
deposition (PVD) techniques, due to its conformity, control over materials thick-
ness, step coverage, and composition. These desirable characteristics originate
from self-saturating nature of ALD processes [6].
1
ECE Department, New Jersey Institute of Technology, Newark, NJ, USA
2
Globalfoundries, Malta, NY, USA
3
Western Digital Corporation, Shanghai, China
4
Physics Department, Indian Institute of Technology Madras, Chennai, India
5
Centre for Nano Science and Engineering (CeNSE), Indian Institute of Science, Bangalore, India
160 Advanced technologies for next generation integrated circuits
During or after the ALD deposition or post deposition, the quality of dielectric
in terms of equivalent oxide thickness (EOT) and interface state density between
the substrate and dielectric can be improved by exposing them to a slot-plane-
antenna (SPA) plasma with various gases such as O2 or inert gases [7]. The SPA
plasma provides a high-density plasma at low electron temperature, where the
radicals diffuse from the plasma generation region to the wafer surface. SPA
plasma is also a very low-damage plasma process compared to conventional
inductively coupled plasma (ICP) or electron cyclotron resonance (ECR) plasma
[7]. It was observed that the SPA plasma helps better film densification as well as
improved interfacial layer (IL) growth. The dielectric is prevented from crystal-
lization at low annealing temperatures.
Several electrical characterization methods are used to evaluate the interface
quality or oxide quality to investigate the defects. These methods are categorized
into two major groups, i.e. evaluation of capacitance of the gate stack and leakage
current through the dielectric. Because of preexisting defects, experimental results
can deviate from theoretical calculations. On the other hand, these deviations are
utilized to evaluate the defects in the device. Characterization methods such as
conductance method [8], capacitance–voltage (CV) at various low temperatures,
flicker noise, capacitance transient spectroscopy, deep-level transient spectroscopy
(DLTS) [9], CV hysteresis, and time-dependent dielectric breakdown (TDDB) [10]
are utilized for the dielectric quality and interface evaluations.
This chapter describes the next-generation high-k gate dielectric for high-
mobility substrates like germanium (high-k/Ge) and for memory devices. One of
the critical issues in MGHK is the high interface state density (Dit 1012
cm2eV1) [11] compared to the traditional SiO2/Si system (1010 cm2eV1)
[12]. Conventional SiO2/Si system prevailed over decades due to its perfect inter-
face quality due to thermally grown SiO2 on Si substrate [12]. Introducing high-k
with metal gate (HKMG) brings additional reliability issues such as threshold
voltage degradation (DVth) after the bias temperature instability (BTI) stress in both
nMOS and pMOS transistors [13]. This is due to the degradation of both interface
and high-k gate dielectrics. If silicon substrate is replaced by other materials such
as Ge, it is necessary to address the interface defects density before expected
mobility can be achieved [14]. Therefore, it is imperative to evaluate the high-k
dielectric layer and the interface quality for next-generation devices.
The objective of this chapter is to use various electrical characterization
techniques to study the interface quality and high-k dielectrics deposited by various
process conditions. This provides comprehensive information on the defects, such
as density, energy level, time constant and how they interact with other parameters
(like flat band voltage, VFB, and dielectric lifetime). Both theoretical model and
experimental work are described. Different evaluation methods can provide a good
analytical approach to study the dielectrics in the gate stacks. The correlation of
experimental data from different methods can enhance the understanding of the
defects behavior. Since the next-generation gate dielectrics on high-mobility sub-
strates involve nanoscale devices, it requires a detailed understanding to integrate
the technology into standard CMOS technology. Furthermore, this study discusses
High-k dielectrics for nanometer CMOS technologies 161
the advantages and disadvantages of various techniques, since each method has its
own limitations such as like sensitivity, range, different extracted parameters, and
the difficulty of implementation.
The organization of this chapter is as follows. Section 7.2 reviews the state-of-
the-art MOS-capacitor. New interface control technique is introduced. The current
status of high-k/Ge was discussed, and its subsequent interface challenge is
addressed before it can be fully considered for commercial use. Section 7.3 dis-
cusses the dry and wet-processed interface layer properties for three different p type
Ge/ALD 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN gate. Several parameters such
as EOT, flat band voltage, bulk doping, and surface potential as a function of gate
voltage are reported. It is also discussed that the high-frequency capacitance of
TiN/ZrO2/Al2O3/p-Ge gate stacks measured in the accumulation region depends on
the device area after substrate resistance correction. Section 7.4 deals with the TiN/
ZrO2/Al2O3/p-Ge gate stacks subjected to the different slot-plane antenna plasma
oxidation (SPAO) annealing conditions, namely, (i) before high-k ALD, (ii)
between high-k ALD, and (iii) after high-k ALD. After XPS (X-ray photoelectron
spectroscopy) and EOT (estimated by capacitance voltage) measurement, the
carrier transport mechanisms on these samples were extracted at high field range to
reveal how SPAO can effectively remove traps in high-k layer. The reliability of IL
(GeOx/GeO2) is evaluated by TDDB performance under substrate electron injection
condition. Section 7.5 describes the impact of SPAO on the dielectrics when
HfZrO2 is used as the gate dielectric and Zr percentage is varied. Section 7.6
describes the use of the various dielectrics in next-generation resistive random-
access memory (RRAM) devices. Section 7.7 summarizes the overall research of
this chapter and outlines a few future challenges.
The first point-contact transistor was invented was in fact a germanium transistor
[15]. When MOS transistors were introduced it required an excellent dielectric for
field effect. SiO2 on silicon provided that solution because Ge does not form this
oxide layer on its surface so easily and GeO2 is hydroscopic and not thermally
stable [16]. In 2004, EOT (oxide thickness calculated by using dielectric constant
of SiO2) was scaled down to 1.2 nm [1]. However, ultrathin SiO2 suffers from
direct-tunneling current which increases exponentially as thickness decreases [17].
To overcome gate leakage problems, initially the addition of N into SiO2 has been
used either by post-deposition annealing in nitrogen ambient or forming a nitride/
oxide stack structure. As incorporating nitrogen into SiO2, it not only increases the
dielectric constant but also acts as a better barrier preventing boron penetration
from polysilicon gate. SiON served as a transition stage between high-k and SiO2,
which has maxim dielectric constant less than 8 [18].
High-k materials were first studied in memory devices. Before it can be
implemented in CMOS Technology, the following issues has to be considered first:
(a) permittivity, bandgap, and band alignment to silicon, (b) thermodynamical
162 Advanced technologies for next generation integrated circuits
stability, (c) film morphology and deposition method, (d) interface quality and bulk
defects, and (e) gate compatibility and process compatibility [3]. The detailed
properties of various high-k dielectrics are listed in [3]. In order to have a good
insulating property, it is suggested that conduction band offset (CBO) between
high-k and substrate should be larger than 1 eV to inhibit Schottky emission, and it
is same for valence band offset as well. Considering different work function
between substrate and the high-k dielectric, specifically a bandgap of 4 eV is
necessary to avoid serious leakage current and breakdown. Finally, it was sug-
gested that ZrO2 and HfO2 are good candidates since they have bandgap larger than
4 eV and its dielectric constant is still large enough for further EOT scaling.
In gate first CMOS processes, the gate stacks must undergo rapid thermal
annealing (RTA) at temperature as high as 1,000 C [19]. This requires that the gate
oxides must be thermally and chemically stable with the contacting materials [20].
From this point of view, HfO2 has better thermal stability than ZrO2 [21].
Additionally, as ZrO2 and HfO2 thin films were grown by ALD, the structural and
electrical behavior of the films were somewhat precursor-dependent, revealing
better insulating properties in the films grown from oxygen-containing precursors,
therefore the HfO2 films showed lower leakage compared to ZrO2 [22]. It is desirable
to have an amorphous high-k layer after necessary processing treatments due to
several benefits of the amorphous structure. Polycrystalline gate dielectrics are not
favored as gate oxide layer since grain boundaries serve as high-leakage paths. HfO2
or ZrO2, crystallize at much lower temperatures at 400 C and 300 C. [23]. The
crystalline temperature of dielectrics can be increased by incorporating other impu-
rities, which was first studied by van Dover [24].
Interface between high-k and substrate must have excellent electrical property
and low interface state density, Dit. Fixed charges present at the interface can cause
flat band voltage shift. Large Dit degrades mobility by surface scattering mechan-
ism. Most of the high-k materials reported Dit range from 1011 to 1012 cm2eV1
[25,26], which is much higher than conventional thermal grown SiO2 [27,28] on
silicon. Interface treatment, therefore, is necessary before depositing high-k layer
to obtain a low Dit interface. Also, the overall EOT value strongly depends on the
thickness of IL. Similar to interface defects, bulk defects formed in high-k oxides
during deposition also cause degraded transistor performance and it is reported that
high-k materials are intrinsically defective because of the bonding structure and
cannot relax easily [29]. The bonding in high-k oxides is ionic. The nature of
intrinsic defects in ionic oxides differs from those in SiO2. The oxygen vacancies,
oxygen interstitials, or oxygen deficiency defects are due to possible multiple
valences of the transition metal [29]. Moreover, high-k oxides achieve their high-k
value because of the low-lying soft polar modes. These modes could be a limit on
scattering, which does not exist in SiO2 [30]. Conventional polysilicon as gate
material is not suitable for high-k dielectrics due to Fermi level pinning problem
[31]. The solution came with the introduction of the metal gate such as TiN, a mid-
gap metal that allows a more threshold voltage control. The state of art of EOT of
HF-base dielectrics is reduced to as low as 0.42 nm [32]. IL plays a key role in EOT
scaling and carrier mobility in channel [33]. For future high-speed devices high-k
High-k dielectrics for nanometer CMOS technologies 163
Vacuum level
0
3 Y
Energy level from vacuum level (eV) Er
Yb
La,Sc
Hf CB
CB
4 Zr
Al
Ti EG(Ge)
EG(Si)
VB
5 Au
VB Ni
Pt
6
Metal/Si Metal Metal/Ge
Figure 7.1 Schottky barrier heights obtained experimentally for various metals
with different vacuum work-functions. In case of Ge, the Fermi level is
strongly pinned near the valence band edge [38]
as the last two assumptions are appropriate. This process is typically followed to
extract the information from silicon devices.
Ge devices, however, are not yet ready for this simple evaluation process.
There are two main reasons: (i) large interface density (larger than 1012 cm2/eV)
[47] that causes Fermi level more or less pined and (ii) small bandgap (0.67 eV)
that allows fast minority carrier generation and large leakage current. The first flaw
of high-k/Ge devices is a paradox when we study the interface state density of these
devices. In other words, larger interface defect density changes device attributes.
Both low density and high density of defects are difficult to be measured correctly.
It is, therefore, important to make sure that there exist three distinctive regions
(accumulation, depletion, and inversion) that can be observed in the CV measure-
ment. The second flaw is quite significant for Ge devices, which is not as relevant
in silicon. The data, as shown later, is easy to obtain in inversion region for Ge
devices at moderate frequencies due to the small bandgap and low bulk defects in
Ge substrate. It is, therefore, imperative to study the Ge devices at lower tem-
peratures such that the second flaw can be more or less addressed. More impor-
tantly, a temperature scan means one additional dimension to the measurement that
definitely benefits the data analysis.
In this section, we describe the measured CV and GV characteristics of Ge/
ALD 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN MOS capacitors on 300 mm wafers
with three different interface treatments. HP4284 LCR meter was used for the
measurement at ten different frequencies (1 MHz, 500 kHz, 100 kHz, 25 kHz,
10 kHz, 5 kHz, 2 kHz, 1 kHz, 500 Hz, and 100 Hz) and at five different tempera-
tures (100 K, 150 K, 200 K, 250 K, and 300 K). The interface treatments are
(i) simple chemical oxidation (Chemox); (ii) chemical oxide removal (COR) fol-
lowed by 1 nm oxide by slot-plane-antenna (SPA) plasma (COR & SPAOx); and
(iii) COR followed by vapor O3 treatment (COR & O3). The Chemox is a wet
process. The other two types of samples are dry processed. The EOT, VFB, bulk
doping, surface potential, and interface quality are calculated, and the results were
discussed with reference to the processing conditions after correcting the CV and GV
data. Additionally, Dit was estimated by conductance method, capacitance spectro-
scopy, and DLTS to study the interface treatment and its impact on the defects.
In CV plots, a frequency dispersion in the negative region (accumulation
region) is observed due to the substrate resistance, Rs. After a simple Rs correction
the dispersion is reduced but is still present unlike silicon devices [48]. This dis-
persion is not acceptable for further analysis since it did not give a robust value in
the accumulation region. Furthermore, the dispersion is mainly due to the interface
states and large interface defects density causes Fermi level pinning before entering
the accumulation region. The interface can, therefore, respond to the frequency
below or equal to 10 kHz and gives a pseudo accumulation region. But can we use
the value here for calculating Cox or EOT? The answer is yes, since there is no
major difference between interface capacitance (Cit) or bulk capacitance (CB), and
both of them are added to the substrate capacitance (Cs). Moreover, the measured
capacitance in the accumulation region should never be above oxide capacitance
(Cox) unless affected by the DC leakage current. The low-frequency data, therefore,
High-k dielectrics for nanometer CMOS technologies 167
dV
measurement from their devices in the accumulation region has minimum disper-
sion due to Rs effects. The only possible reason for dispersion is that Fermi level
can be pinned at flatband voltage. This may explain why the mobility in the p
substrate of Ge is lower than expected. The calculated CFB of Chemox sample
using (7.2) is about 0.005 pF/mm2. At 100 K, the capacitance measured at 1 MHz
shows a constant value of around 0.0043 pF/mm2 when the gate voltage is
decreasing below around 0.5 V (VFB of the Chemox sample). So, this proves that
our sample is pinned at flatband due to the interface states.
Another important observation is that the capacitance value cannot reach the level
0.03 pF/mm2 at 100 K whereas at 300 K it can. There are two possible reasons: Fermi-
level statistics are changing when temperature is changing, and lower temperature
causes Fermi level to be steeper instead of flat. Alternatively, as Kuzum et al. explained
[52], this change is due to the change of emission rate of defects as stated in (7.4),
1 E V ET Ei ET
ep ¼ ¼ sp vp Nv exp ¼ sp vp ni exp (7.4)
tp kT kT
where sp is the defect cross section, vp is hole thermal velocity, ni is intrinsic carrier
concentration, EV is effective density of states of hole at valence band, ET is
valence band energy level, Ei and ET are intrinsic energy level and defects energy
level, respectively. It assumes that interface states only respond to the valence
band. Also, it is further assumed that keeping all the parameters same, the time
constant, tp will increase when temperature decreases. In other words, for a specific
frequency window like 100 Hz to 1 MHz, by varying temperature, interface state
information in the bandgap can be obtained if Fermi level is not pinned.
However, the second explanation is not reliable if Fermi level is not moving
effectively as a function of temperature when the gate voltage is varying, especially
when one considers Dit as a function of bandgap. One could easily observe that
Fermi level in the bandgap near the flat band rarely moved under different tem-
peratures. Because of this, no horizontal shift was observed due to capacitance
interference [48]. The gate voltage was at slow rate (2 s), therefore most interface
states can follow the change in DC voltage. Presence of large interface states pin-
ned the Fermi level in the device before it entered the accumulation region. The
above discussion suggests that the region of bandgap that was observed remained
the same under different temperatures. However, the time constant of those mea-
sured interface states is decreased when temperature is increased, therefore they
can follow the AC signal after a specific temperature. It is further observed that
there is temperature dispersion at a specific frequency. It is important that the Dit
data are plotted as function of bandgap since it is necessary to relate the gate
voltage to surface potential. Software CVC.2.0 (North Carolina State University)
was used to generate the surface potential [53] where Cox, VFB, and bulk con-
centration were the input. Dit was calculated by conductance method [8] and further
verified by capacitance spectroscopy method.
As discussed earlier, we have Ge/1 nm-Al2O3/3.5 nm-ZrO2/TiN gate stacks
(MOSCAPs) with three different interface treatments. The COR þ SPAOx and
COR þ O3 are dry treatments whereas Chemox is a wet-processed interface.
High-k dielectrics for nanometer CMOS technologies 169
45
40
35
30
Capacitance (pF)
25
20
Chemox/Ge
15
COR&SPAOx/Ge
10
COR&SO3/Ge
5
0
–1.5 –1 –0.5 0 0.5 1 1.5
Gate voltage (V)
Figure 7.2 Corrected 1 MHz capacitances of three samples are plotted as a function
of gate voltage at room temperature. Device area is 40 mm 40 mm
Figure 7.2 shows corrected 1 MHz capacitances of three samples are plotted as a
function of gate voltage at room temperature (device area is 40 mm 40 mm).
Considering Vth, the dry treated interfaces exhibit more negative Vth shift compared to
wet treated samples since there existing positive border traps near for dry-processed
samples (see DLTS section). The EOT, on the other hand, for the dry-processed
interface (COR þ O3), shows a clear increase, as reported earlier (Table 7.2),
COR þ SPAOx shows the highest EOT because of 1 nm additional SPAO. When we
plot the dry (COR þ SPAOx) and dry (COR þ O3) processed CV at 100 K as a
function of frequency stark difference was observed between them. This indicates
there exist certain bulk defects in the upper half bandgap that can follow low fre-
quency at 100 K for dry (COR þ O3) processed sample. Even though the dry process
interface exhibited excellent room temperature frequency-dependent CV, in the
depletion it indicates the existence of interface states near valence band for both wet
and dry-processed COR þ O3 samples. For COR þ SPAOx samples, on the other
hand, a reduced interface state was observed (Figure 7.2).
Dit was estimated by the conductance method. In Figure 7.3(a), it was clearly
observed that COR & SPAOx processed interface had relatively lower interface state
at room temperature than the other two different processed samples. This further
suggests that SPAO samples have improved IL quality in terms of interface defects
density. At low temperature (100 K), SPAO samples also show a low mid-gap Dit.
Figure 7.3(b) compares the Dit values as a function of gate voltage measured by
capacitance spectroscopy method and conductance method. Similar results were also
observed by capacitance spectroscopy. Moreover, the difference of Dit estimated at
100 K and 300 K (Figure 7.3(b)) is due to their time constant variation as temperature
changes. It is, therefore, imperative to understand the defect energy levels.
170 Advanced technologies for next generation integrated circuits
1014
1013
Dit (cm–2/eV)
1.0×1014
Chemox/Ge Capacitance method
Chemox/Ge Conductance method
COR&SPAOx/Ge Capacitance method
COR&SPAOx/Ge Conductance method
COR&O3/Ge Capacitance method
COR&O3/Ge Conductance method
Dit (cm–2/eV)
5.0×1013
0.0
0.0 0.5 1.0 1.5
(b) Gate voltage (V)
Figure 7.3 (a) Dit is plotted as function of bandgap for three samples at two
temperatures (100 K and 300 K), other Dit as a function of
temperature are within this range; (b) Calculated Dit of three samples
as a function of gate voltage by capacitance spectroscopy method and
conductance method
The low interface state density in COR þ SPAOx samples indicates formation of
an IL constituting GeOx with a possible unit cell of GeO2 layer [41]. As mentioned by
Zhang et al., dielectric constant decreases once IL changes from GeOx to GeO2 layer
because of plasma oxidation. That was clearly evident in CV measurement and EOT
estimation (Table 7.2) for COR þ SPAOx samples. In addition, an increase in GeOx
during SPAO treatment may be possible, enhancing the EOT. In either way, interface
treatment by SPAO plasma tends to passivate the interface further [41] by reducing
the Dit (Figure 7.3) for COR þ SPAOx samples at the cost of an increase in EOT. We
believe the former mechanism is more responsible for Dit reduction. The chemical
processes (both wet and dry) Chemox and COR þ O3 failed to passivate the interface
with the formation of GeOx only even though the EOT was decreased.
High-k dielectrics for nanometer CMOS technologies 171
Nt ¼ DVCox =q (7.5)
where DV is obtained from CV plot using measured DC. The results suggest that it
is around 1013 cm2/eV for all the three samples. This further confirms that the
origins of interface state density, Dit, observed earlier for these samples (Figure 7.3)
are mainly due to these traps. The time constants of these defects are in the order of
50 100 150 200 250 300 350 50 100 150 200 250 300 350
0
∆C = Ct1–Ct2 (pF)
0
∆C = Ct1–Ct2 (pF)
–1 τ = 0.325 ms
–1
τ = 0.361 ms
–2 τ = 0.325 ms
τ = 0.433 ms
–2 τ = 0.361 ms
τ = 0.505 ms H2
–3 τ = 0.433 ms
τ = 0.577 ms
τ = 0.505 ms H3
τ = 0.649 ms
–4 H1 –3 τ = 0.577 ms
COR/SPAOx/Ge (Dry) - H3
4.5 COR&O3/Ge (Dry) - H4
COR&O3/Ge (Dry) - H5
Ln (τT2)
–1 τ = 1.3 ms
τ = 1.44 ms
4.0
τ = 1.73 ms 3.5
–2 τ = 2.02 ms 3.0
τ = 2.31 ms
H4 τ = 2.6 ms 2.5
–3 2.0
100 150 200 250 300 4 6 8
(c) (d)
Temperature (K) 1,000/T (K–1)
H1 H2 H3 H4 H5
ETEV (eV) 0.16 0.1 0.18 0.04 0.45
s (cm2) 6.3 1017 1.3 1019 3.6 1019 5.8 1021 8.6 1013
milliseconds that were observed earlier. This can further explain the observed
fluctuations in frequency dispersion curves at low temperatures. The relatively
negative Vth shift in dry-processed samples compared to wet process samples can
also be explained because of the presence of additional hole traps at the interface.
Table 7.3 summarizes the energy levels and cross-sections [9] of these traps. The
observed energy levels indicate the presence of a shallow level (H3) for
COR þ SPAOx sample as compared to a deep level (H5) for COR þ O3 samples.
The impact of these levels on Dit is clearly obvious as deep levels contribute sig-
nificantly to the interface state density.
When the gate leakage current densities for different types of samples were
compared, the SPAO-processed interface shows lower current density [48]. The
gate leakage current density increases when the EOT goes down. This is because
the thinner ILs help tunneling because of the reduced tunneling barrier. The sam-
ples with SPA plasma-enhanced IL showed the lowest tunneling leakage current. It
was previously reported that SPA plasma helps better oxide growth with reduced
impurities [7]. In addition, the SPA plasma makes atomically flat surface and
interface, which helps the reduction in leakage current density [54,55]. This further
confirms that dry-processed, especially, COR þ SPAOx interface is superior.
In summary, it has been demonstrated that an accurate parameter estimation
method for Ge/ALD 1 nm-Al2O3/ALD 3.5 nm-ZrO2/ALD TiN MOS capacitors
with three different interface treatments. COR & SPAOx samples show excellent
CV characteristics at room temperature. After evaluating several parameters like
EOT, flatband voltage, bulk doping, and interface defects density, COR & SPAOx
(dry) has better interface quality than Chemox (wet) and COR & O3 (dry)-processed
sample; however they all have larger Dit values in the order of 1013 cm2/eV that
causes Fermi level more or less pinned, which is confirmed by low temperature
measurements. Dry-processed sample (COR & SPAOx and COR & O3) has more
negative Vth shift due to the existing border trap discovered by DLTS. The levels of
leakage current of three samples follow the sequence of their EOT values. Therefore,
COR & SPAOx (dry) has the lowest trap-assisted tunneling effect, resulting in lowest
leakage current.
transistor (MOSFET) speed without any physical scaling. Before the development
of high-k oxide, the hygroscopic property of GeO2 impeded the implementation of
Ge MOSFET since SiO2 has a better stability as native oxide layer, grown on Si
[37]. Nevertheless, after metal/high-k gate stack was introduced, the formation of
appropriate thickness of GeOx or GeO2 between high-k and Ge substrate was
reported to have low interface state density (Dit) [56]. Growing a few Ångström
GeO2/GeOx intentionally is, therefore, necessary to obtain good interface quality
for high-k/Ge gate stacks [57]. The thickness of GeO2/GeOx layer will impact the
overall EOT because of its low dielectric constant compared to high-k layer [58].
Therefore, the tradeoff between EOT and Dit is an inevitable issue. Besides,
interface layer treatment of Ge and controlling its thickness are also critical to
further the scaling EOT below 1 nm [59]. High-k dielectrics like HfO2 and ZrO2
have already been integrated into CMOS technology. It is reported that HfO2/Ge
gate stack shows a larger CV hysteresis than Al2O3 [8], and Al2O3 can block
electron injection from substrate effectively by large conduction band offset related
to Ge substrate [43]. Moreover, ZrO2 showed lower leakage current than HfO2 with
similar dielectric constant [60]. Therefore, a bilayer high-k stack (ZrO2/Al2O3) was
used in this study. The IL quality (interface state density, Dit), and EOT of these
stacks were reported in a previous work [61] and it is summarized in Table 7.4. In
addition, the crystalline properties of the IL need to be evaluated along with XPS
analysis of IL atomic composition [62].
The reliability of high-k layer depends on the gate leakage current density
level (Jg) and charge to breakdown (QBD). The current density not only determines
the performance of memory and logic circuits but also affects how fast the oxide
layer degrades. After certain amount of the injection of the carriers through oxide
layer, it can be irreversibly broken down. Moreover, these two parameters are
somehow correlated if both of them are only dependent on the oxide layer quality.
The TDDB measurement is now showing polarity dependence on thin devices since
I–V depends on the barrier condition at the interface (gate/oxide and oxide/sub-
strate) [63,64] and it is expected that bilayer structure will further enhance this
phenomenon since different electric field across the layers and variance in dielec-
tric quality [65]. Moreover, as EOT is scaling down to below 1 nm, IL will have
more impact on the final TDDB performance [66] if a soft breakdown time is
measured instead of hard breakdown. If the degradation is due to the IL, a lower
current density cannot predict a longer lifetime of a dielectric layer in terms of
Table 7.4. EOT, VFB, Dit, and IL type for three samples
device stability. In the first half of this section, the carrier transport mechanisms
were evaluated for three different samples, namely, SPAO exposure before high-k
deposition by ALD, in between two different ALD high-k layers, and after ALD
high-k, to understand the effect SPAO on the gate leakage current and carrier
transport mechanism in dielectrics [67]. The trap distributions observed in this
experiment can significantly impact the reliability of the dielectric. Therefore,
samples were subjected to TDDB measurement to further understand the reliability
of p-Ge/Al2O3/ZrO2/TiN gate stacks under different SPAO exposure. Charge to
breakdown (QBD) was estimated from the TDDB measurements which were carried
out at different voltage stress conditions. Subsequently, voltage acceleration factor
(AF) was extracted. TDDB and I–V characteristics of three samples were studied by
using both gate electron injection (GEI) and substrate electron injection (SEI)
modes. This gives an overall evaluation of the high-k oxide and IL quality under
different SPAO conditions. To evaluate the performance 1 nm Al2O3 and 3.5 nm
ZrO2 were deposited as gate oxide, and the samples were subjected to three SPAO
annealing sequences: (i) Ge/SPAO/Al2O3/ZrO2 (SPAO before high-k), (ii) Ge/
Al2O3/SPAO/ZrO2 (SPAO in between two high-k layers), and (iii) Ge/Al2O3/ZrO2/
SPAO (SPAO after high-k).
Figure 7.5 shows the XRD spectra of SPAO-treated Ge MOS capacitors (TiN/
ZrO2/AlOx/Ge) at three different stages of high-k deposition process. XRD patterns
are composed of peaks corresponds to the metal electrode (TiN) and substrate (Ge/Si)
reflections [68,69]. No peaks correspond to the dielectric stack (ZrO2/Al2O3) have
been observed, which indicates that the dielectric stack is in amorphous phase only.
No structural changes have occurred after SPAO treatment in all three cases, this
reveals that the SPAO treatment is not causing any damage to the dielectric stack.
X-ray photoelectron spectroscopy was employed to examine the IL (GeOx)
formation and its oxidation states. Figure 7.6 shows the high resolution (HR) XPS
Si (220)
Ge (400)
Intensity (a.u.)
TiN (111)
Si (311)
TiN (220)
TiN (220)
20 40 60 80 100
2θ (degrees)
Intensity (a.u.)
Ge-3d
Ge-Ge
Ge+2
24 28 32 36 40 24 28 32 36 40
(a) B.E (eV) (b) B.E (eV)
Intensity (a.u.)
3d3/2
3d3/2 Ge-O
Ge+1 +2
Ge
GeO2 Ge+3
Ge+1 Ge+4
Ge+4
24 28 32 36 40 24 28 32 36 40
(c) B.E (eV) (d) B.E (eV)
Figure 7.6 High-resolution XPS spectra of Ge-3d all three cases: (a) and
deconvolution results of the Ge-3d spectra for SPAO after high-k (b),
in between high-k layers and (c) and prior to high-k (d)
spectra of Ge-3d in all three cases. The Ge-3d spectrum is entirely different in all
three cases as shown in Figure 7.6(a). A peak is observed in Ge-3d spectra at a
binding energy centered around 32.6 eV along with the Ge substrate peak
( 29.5 eV), attributed to the formation of GeOx in all three cases which confirms
the oxidation of the high-k stack and Ge interface [42,70,71]. The intensity of GeOx
component is more in SPAO after high-k and is less in SPAO in between ZrO2 and
Al2O3 indicates the thicker IL formation in sample with SPAO after high-k
deposition and the thinner IL formation in case of SPAO in between ZrO2 and
Al2O3. The thicker IL in SPAO after high-k might be due to longer duration (300 s)
exposure of gate stack (ZrO2/AlOx/Ge) to SPAO treatment compared to other two
cases, 30 s in between ZrO2 and Al2O3 and 15 sec in sample with SPAO prior to
high-k deposition, which causes down diffusion of more oxygen towards the
interface through the gate stack. The stability of the IL (GeOx) depends on the
176 Advanced technologies for next generation integrated circuits
oxidation state of Ge. The þ4 oxidation state of Ge is more stable than the lower
oxidation states, þ3, þ2, and þ1.
The various oxidation states of GeOx can be evaluated by the deconvolution of
GeOx peak to the corresponding to each oxidation state shown in Figure 7.6(b)–(d).
The difference in binding energy of oxide (Ge–O) and substrate (Ge–Ge) peaks in
SPAO after high-k (shown in Figure 7.6(b)) is around 3.1 eV, indicates the Geþ4
oxidation state. The intensity of GeO2 peak is significantly higher than the substrate
peak indicates the thicker IL formation. Also, a significant component of lower
oxidation state, þ2 of Ge at a binding energy of 30.8 eV is detected, indicates the
suboxide formation at the interface. The difference in binding energy of oxide
(Ge–O) and substrate (Ge–Ge) peaks in sample with SPAO in between ZrO2 and
Al2O3 (shown in Figure 7.6(c)) is around 3.2 eV, indicating a Geþ4 oxidation state.
The intensity of GeO2 peak is significantly lower than the substrate peak which
indicates the stable thinner IL (GeO2) formation in SPAO in between ZrO2 and
Al2O3 compared to samples with SPAO after high-k. However, a very weak signal
related to Geþ1 is detected at a binding energy of 30 eV in SPAO in between
ZrO2 and Al2O3, which may influence the electrical properties of the devices. The
difference in binding energy of oxide (Ge–O) and substrate (Ge–Ge) peaks in
sample with SPAO prior to high-k (shown in Figure 7.6(d)) is less than 3 eV,
indicates the suboxide formation at the interface. Multi oxidation states of Ge (þ1,
þ2, þ3 and þ4) are detected indicating an unstable IL formation [72,73]. This
demonstrates that the direct exposure of SPAO causes damage to the Ge interface
before high-k deposition. Hence the direct exposure of SPAO to Ge is not a good
choice to create superior and stable interface.
To understand the carrier transport mechanisms and/or prior to applying the phy-
sical carrier transport models, it is important to observe I–V characteristics at different
temperatures. At negative voltage range (gate electron injection) Figure 7.7(a) and (b)
shows the I–V dispersion at different temperatures for sample Ge/SPAO/Al2O3/ZrO2
and sample Ge/Al2O3/SPAO/ZrO2, respectively. On the other hand, the temperature
dependence of I–V is greatly reduced for sample Ge/Al2O3/ZrO2/SPAO (Figure 7.7
(c)). It is reported that SPAO can effectively reduce oxide traps [74]. Therefore, it is
believed that reduced temperature dependence is mainly due to reduced traps density in
ZrO2 and Al2O3 layers. Figure 7.7(d) compares temperature dependence of gate leak-
age current at fix bias condition. It shows that sample Ge/Al2O3/ZrO2/SPAO has the
lowest leakage current, followed by sample Ge/Al2O3/SPAO/ZrO2. Since I–V is not
significantly dependent on temperature (Figure 7.7(d)) at high electric field, FN tun-
neling is believed to be the dominant mechanism [75] for both GEI and SEI as FN is
strongly dependent on the biased voltage at high gate bias condition, which is of interest
in this study. On the other hand, DT is not dependent on the applied gate bias and only
dominant at low gate bias, which is beyond the scope of this study. For FN tunneling,
consider the following field in the oxide layer [76] and current expressions [67]:
10–3
(i) COR/SPAO/AI2O3/ZrO2 (ii) COR/AI2O3/SPAO/ZrO2
10–3
10–5
Jg (A/cm2)
Jg (A/cm2)
10–5
25 °C
25 °C
10–7 50 °C
10–7 50 °C
80 °C
80 °C
110 °C
110 °C
10–9 10–9
–1.5 –1.0 –0.5 0.0 0.5 1.0 –1.5 –1.0 –0.5 0.0 0.5 1.0
(a) Vg (V) (b) Vg (V)
10–5
(iii) COR/AI2O3/ZrO2/SPAO 10–3
Jg (A/cm2)
Jg (A/cm2)
10–4
10–7
AI2O3/ZrO2/SPAO GEI mode
25 °C AI2O3/SPAO/ZrO2 GEI mode
50 °C 10–5 SPAO/AI2O3/ZrO2 GEI mode
AI2O3/ZrO2/SPAO/ SEI mode
80 °C
AI2O3/SPAO/ZrO2/ SEI mode
110 °C SPAO/AI2O3/ZrO2 SEI mode
10–9 10–6
–1.5 –1.0 –0.5 0.0 0.5 1.0 20 30 40
(c) Vg (V) (d) 1/KT (1/eV)
Figure 7.7 Current density (Jg) is plotted as a function of gate voltage (Vg) at four
different temperatures (25 C, 50 C, 80 C, 110 C) for three different
samples: (a) Ge/SPAO/Al2O3/ZrO2, (b) Ge/Al2O3/SPAO/ZrO2, (c) Ge/
Al2O3/ZrO2/SPAO, and (d) Jg as a function of Vg-VFB is plotted for the
above three samples at 25 C, where VFB is the flat band voltage
!
q3 m0 4ð2mox Þ1=2 3=2 1
JFN ¼ E 2
exp ∅b E (7.7)
16p2 ℏmox ∅b 3qℏ
where e the dielectric constant, E is the electric field in oxide, and t is oxide
thickness. The electric field is calculated by (7.6a) assuming the dielectric con-
stants of ZrO2 and Al2O3 as 25 and 9, respectively. The barrier heights were then
extracted by fitting ln(JgE2) to 1/E as (2) indicates, where E is the electric field, q
is the electronic charge, mo, mox, are the electron mass in free space and in the
oxide, respectively; ℏ is the Planck’s constant, and fb is the barrier height. The
electron mass used in this calculation for ZrO2 and Al2O3 are 0.5mo and 0.3mo,
respectively [77,78]. In Figure 7.8, ln(JgE2) is plotted as a function of 1/E and
different barrier heights were obtained from the slopes in both GEI and SEI modes,
respectively. Metal (TiN) to dielectric barrier height, fb(ZrO2) at high field during
gate injection (barrier height of ZrO2) is calculated as 1.3 eV. The estimated fb
(ZrO2) is lower than the theoretical calculation (1.6 eV) due to the breakdown of
high-k before a sufficiently high electric field was applied. Substrate to dielectric
barrier height fb(Al2O3) at high field was estimated during substrate (Ge) injection
178 Advanced technologies for next generation integrated circuits
–36.0
Medium E field
–36.4 GEI mode
–37.2
–37.6
–38.0
–37
High E field
–38 SEI mode
In(Jg E –2) (AV2)
–39
–40
–41
–42
0.08 0.09 0.10 0.11 0.12 0.13
(b) 1/E (cm/MV)
2
Figure 7.8 ln(JgE ) is plotted as a function of 1/E as FN tunneling for sample
Ge/Al2O3/ZrO2/SPAO, Jg is the current density and E is the electric
field: (a) gate electron injection mode (GEI) and (b) substrate electron
injection mode (SEI)
(barrier height of Al2O3) is 2.2 eV assuming electrons tunnel through thin GeOx.
On the other hand, fb(AlO2) is very close to the expected theoretical value [43].
Note that the current–voltage characteristics in SEI mode at low field, in the
range from 0.5 V to 0.5 V, low to medium E field range for sample Ge/Al2O3/
ZrO2/SPAO (Figure 7.7(c)) I–V is clearly a function of temperature. Therefore,
Poole–Frenkel (PF) and hopping conduction (HC) mechanism is possibly the
dominant mechanism in this range and fits well I–V characteristics. The current
expression for HC is given by [67]:
qaE Ea
JHC ¼ qanvexp (7.8)
kT kT
In (7.8), a is the mean hopping distance (i.e., the mean spacing between trap sites),
n is the electron concentration in the conduction band of the dielectric, v is the fre-
quency of thermal vibration of electrons at trap sites, and Ea is the activation energy,
namely, the energy level from the trap states to the bottom of conduction band.
High-k dielectrics for nanometer CMOS technologies 179
As shown in Figure 7.9(a), HC model fits Jg-T (current temperature function) char-
acteristic well in medium E field range. Subsequently, the slope, S, (S ¼ qaE Ea)
obtained from Figure 7.9(a), can be plotted as a function of E field. In Figure 7.9(b), the
fitted slope is the product of mean hopping distance (a) and electronic charge (q), and
intercept of slope is the activation energy. The calculated values a and Ea are 0.3 nm
and 0.16 eV, respectively, in the sample Ge/Al2O3/ZrO2/SPAO.
As discussed above, sample Ge/Al2O3/ZrO2/SPAO shows FN tunneling in the
high E-field range since both ZrO2 and Al2O3 were exposed to SPAO. On the other
hand, ZrO2 layers were not subjected to SPAO for both the samples Ge/SPAO/
Al2O3/ZrO2 and Ge/Al2O3/SPAO/ZrO2. Therefore, both HC and PF mechanisms
seem to be dominated for the entire range of measured I–V characteristics (high and
low electric field range). The PF current expression is given by [67]:
1=2
!
ðq3 =per eo EÞ q∅t
JPF ¼ qNC mEexp (7.9)
kT
where m is the electronic drift mobility, Nc is the density of states in the conduction
band, qft is the trap energy level, and the other notations are the same as defined in
(7.9). ft has the physical meaning similar to that of Ea in the HC model. The
symbol difference is just to differentiate the values that are obtained using different
current models. The conduction mechanism, PF is different from that of HC. In PF,
electrons in trap centers are thermally excited to conductance band of oxide, and
subsequently relaxed to another trap center. In case of HC, electrons transit
between trap sites by trap assisted tunneling.
In Figure 7.10, both HC and PF models were applied to the sample Ge/SPAO/
Al2O3/ZrO2 and sample Ge/Al2O3/SPAO/ZrO2. The slope value S is the fitting
value from ln(Jg) versus 1/kT (not shown here). HC model (Figure 7.10(a)) gives
same trap energy level Ea1 as 0.09 eV for both GEI mode (black open symbol) and
–6.4
Medium E field
–0.08 SEI mode
–6.6
S = qaE – Ea (eV)
In(Jg) (A/m2)
–6.8 –0.12
Slope ∝ qa
2.7 MV/cm
–7.0 2.9 MV/cm –0.16
3.2 MV/cm Ea* ≈ 0.16 eV
–7.2 –0.20
30 31 32 33 34 35 36 0 1 2 3 4
(a) 1kT (1/eV) (b) E(MV/cm)
Figure 7.9 (a) Current density ln(Jg) is plotted as function of 1/kT for sample Ge/
Al2O3/ZrO2/SPAO, in SEI mode. (b) Slope value (S ¼ qaE Ea),
which is obtained from (a) is then plotted as function electric field E
(SEI mode)
180 Advanced technologies for next generation integrated circuits
0.00
–0.05
–0.05 Φt1 ≈ 0.13 eV
–0.10
Ea1 ≈ 0.09 eV –0.10
HC model
–0.15
–0.15 Φt2 ≈ 0.27 eV PF model
Ea2 ≈ 0.22 eV
–0.20 SPAO/AI2O3/ZrO2 at GEI Mode –0.20 SPAO/AI2O3/ZrO2 at GEI Mode
SPAO/AI2O3/ZrO2 at SEI Mode SPAO/AI2O3/ZrO2 at SEI Mode
–0.25 AI2O3/SPAO/ZrO2 at GEI Mode –0.25 AI2O3/SPAO/ZrO2 at GEI Mode
AI2O3/SPAO/ZrO2 at SEI Mode AI2O3/SPAO/ZrO2 at SEI Mode
–0.30 –0.30
0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0
(a) E (MV/cm) (b) E1\2 (MV/cm)1\2
Figure 7.10 HC and Poole–Frenkel emission (PF) were used to fit the I–V
characteristics for sample Ge/SPAO/Al2O3/ZrO2 (solid symbol) and
sample Ge/Al2O3/SPAO/ZrO2 (open symbol) at both GEI mode
(black symbol, squares) and SEI mode (red symbol, circles).
(a) Slope value (S ¼ qaE Ea) is plotted as function electric field E.
(b) Slope value (S ¼ bE1/2 qft) is plotted as function E1/2, where
b ¼ q3 =per eo . The slope value S is the fitting value from ln(Jg)
versus 1/kT
SEI mode (red open symbol) in sample Ge/Al2O3/SPAO/ZrO2. On the other hand,
HC model gives Ea1 as 0.09 eV for GEI mode (black solid symbol) and Ea2 as
0.22 eV for SEI mode (red solid symbol) in sample Ge/SPAO/Al2O3/ZrO2. In brief,
for GEI mode, electrons tunnel through ZrO2 layer assisted by the same trap centers
(Ea1 ), since ZrO2 layer of both samples was not subjected to SPAO. For SEI mode,
electrons tunnel via two different trap centers, Ea1 and Ea2 , for sample Ge/Al2O3/
SPAO/ZrO2 and sample Ge/SPAO/Al2O3/ZrO2, respectively. As mentioned earlier,
SPAO can significantly remove the trap center Ea2 (0.22 eV) in GeOx/Al2O3 layer
for the Ge/Al2O3/SPAO/ZrO2 device, when SPAO is processed after Al2O3
deposition. Both trap energy levels Ea2 and Ea1 were observed in Ge/SPAO/Al2O3/
ZrO2 sample.
When PF model (Figure 7.10(b)) was used, similar behavior was observed as
that of HC model. The trap energy level, ft1 of 0.13 eV calculated by PF model,
was observed for GEI mode (black solid and open symbols) in both the samples
Ge/SPAO/Al2O3/ZrO2 and Ge/Al2O3/SPAO/ZrO2. In SEI mode, one trap energy
level ft1 was observed with identical value of 0.13 eV. On the other hand, for SEI
mode (red and black solid symbols) in Ge/SPAO/Al2O3/ZrO2 a second trap
energy level, ft2 (0.27 eV), was observed in addition to ft1 (0.13 eV). Different
symbols were used as they are calculated by different models. Both HC model
and PF model are similar in trap-rich oxide layers with the difference in carrier
transit process between the trap sites. HC gives one more parameter, the hopping
distance, a, of about 0.3 nm from the slope in Figure 7.10(a). Carrier transport
mechanisms for GEI and SEI mode are marked in band diagram as Figure 7.11(a)
and (b), respectively, and mechanisms and trap energy levels are summarized in
Table 7.5. It is, therefore, clear that SPAO contributes to reduction of trap sites in
High-k dielectrics for nanometer CMOS technologies 181
Φt(A/ZrO3) = 2.2 eV
FN(iii)
Φ(ZrO2) = 1.3 eV FN(iii)
PF/HC(ii) PF/HC(i)
TiN PF/HC(i/ii) Φt1 = 0. 09 eV Ge
Φt1 = 0. 09 eV Ge TiN
Φt2 = 0. 27 eV
ZrO2
GeOx
GeOx
AI2O3 AI2O3
(a) Gate electron injection (GEI) (b) Substrate electron injection (SEI)
Figure 7.11 Carrier transport mechanisms are explained in band diagram for
both GEI mode and SEI mode: (a) GEI mode, band diagram is
simulated under Vg ¼ 1.5 V and (b) SEI mode, band diagram is
simulated under Vg ¼ 1 V
Table 7.5 Transport mechanisms at high field region are summarized. Trap
energy level ft, charge to breakdown at |1V| QBD, and AF were
calculated for both GEI and SEI mode
the GeOx/Al2O3 layer when SPAO is processed after Al2O3 deposition. This
reduction process was not observed if SPAO is processed prior to Al2O3
deposition (Ge/SPAO/Al2O3/ZrO2 sample). It is further observed that sample Ge/
Al2O3/ZrO2/SPAO has the best performance for GEI mode, since most of the
oxide trap centers were removed from the dielectric by SPAO [74]. The trap
distribution in the dielectric and the IL will have significant impact on dielectric
degradation. We have also observed difference in XPS data shown in Figure 7.6.
Therefore, the performance of SEI mode is dependent on IL as will be more
critical. The TDDB study was, therefore, employed to further understand the
contribution of the trap distribution observed above to the degradation process,
discussed in the following section.
The TDDB characteristics of all three samples were studied. The charge to
breakdown, QBD, and voltage AF were the two main parameters used in both GEI
and SEI modes to evaluate the dielectric quality and any contribution of the IL.
182 Advanced technologies for next generation integrated circuits
The oxide breakdown in this work is defined as the abrupt change of sampling gate
current (Ig). Although secondary abrupt changes of Ig exist (not shown here) that
were not considered. QBD was used instead of time to breakdown (TBD) to further
understand the trap distribution observed in the I–V characteristics. Weibull dis-
tribution was used to explain TDDB statistic shown in (7.10) [79], where b and h
are shape parameters and they are constant:
QBD b
F ðQBD Þ ¼ 1 exp (7.10a)
h
@logðQBD Þ
AF ¼ (7.10c)
@V
b in (7.10a) is about 0.7 for all samples and it is stress voltage-independent
(not shown here). But it depends on the oxide thickness and trap sphere size (ao)
theoretically as (7.11a) indicates [80], where tINT is thickness of IL [81], tox is the
dielectric thickness and a is a parameter describing the correlation between tox
and b:
tox
b¼a (7.11a)
ao
Figure 7.12 shows the values of all samples for both GEI and SEI mode. The
same value of 0.7 for all samples indicates that ao is similar in all samples.
0
In(-In(1-F))
–1
SPAO/AI2O3/ZrO2 at –3.0V
AI2O3/SPAO/ZrO2 at –3.0V
–2
AI2O3/ZrO2/SPAO at –3.0V
SPAO/AI2O3/ZrO2 at 4.1V
–3
AI2O3/SPAO/ZrO2 at 5.5V
AI2O3/ZrO2/SPAO at 5.5V
–4
Figure 7.12 b values are around 0.7 and similar for all samples and stress
conditions, which were obtained by Weibull plot
High-k dielectrics for nanometer CMOS technologies 183
102
SPAO/Al2O3/ZrO2 GEI mode
Al2O3SPAO/ZrO2 GEI mode
100
Al2O3/ZrO2 SPAO GEI mode
SPAO/Al2O3/ZrO2 SEI mode
10–2
Al2O3/SPAO/ZrO2 SEI mode
QBD (C/μm)
10–6
10–8
10–10
10–12
1 2 3 4 5 6
(a) Vg (V)
1011
107
103
10–1
1 2 3 4 5 6
(b) Vg (V)
Figure 7.13 (a) Charge to breakdown value (QBD) and (b) Time to breakdown
value (tBD) are plotted as function of gate voltage (Vg) for both GEI
mode (solid symbol) and SEI mode (open symbol)
184 Advanced technologies for next generation integrated circuits
The stress voltages were selected based on voltage ramping breakdown measurement
in previous work [61]. QBD and AF parameters are summarized in Table 7.5, where AF
values were obtained based on (7.10 (c)). At the GEI mode (Figure 7.11(a)), the
amount of tunneling electrons is dependent on the quality of ZrO2, which is the first
layer that electron has to tunnel through. The AF value of 6.1 is the largest for sample
Ge/SPAO/Al2O3/ZrO2, followed by an AF value of 10.7 for sample Ge/Al2O3/
SPAO/ZrO2, and sample Ge/Al2O3/ZrO2/SPAO has the lowest AF value of 17.9.
Also, it was observed that Ge/Al2O3/ZrO2/SPAO has the largest QBD. Therefore, it can
be concluded that the SPAO can affect the TDDB characteristics GEI mode by sig-
nificantly removing the traps from the dielectric layers [74] ZrO2 and Al2O3. The
dielectric quality was enhanced by SPAO in terms of AF and QBD. If traps are removed
from only the Al2O3 layer the AF value increased and QBD was decreased:
QBD ¼ Qo expðAF V Þ (7.12)
The same conclusion cannot be applied to the SEI mode, since TDDB degra-
dation is also affected by the degradation of IL (GeO2 or GeOx). XPS measurement
from earlier work on these devices concluded that sample Ge/Al2O3/ZrO2/SPAO
formed GeO2 IL, while the other two samples formed GeOx IL [61]. Some studies
reported that ALD process will decompose GeO2 into GeOx [84] since GeO2 is not
thermally stable [85]. This explained why only sample Ge/Al2O3/ZrO2/SPAO has
GeO2 as IL since subsequent ALD process decomposed the GeO2 to GeOx for other
two samples. As open symbols show in Figure 7.13, sample Ge/Al2O3/ZrO2/SPAO
has the largest AF and lowest QBD among three samples due to the formation of
GeO2. On the other hand, samples Ge/SPAO/Al2O3/ZrO2 and Ge/Al2O3/SPAO/
ZrO2 show better QBD. The formation of unstable fragmented IL causes an increase
in AF values (Table 7.5), and only sample Ge/SPAO/Al2O3/ZrO2 has similar AF
values at both GEI and SEI mode, which indicates a similar breakdown process.
Note that GeO2 shows the worst TDDB result among three different SPAO treat-
ments. This suggests that GeO2 has the worst resistance to stress in terms of device
stability compared to GeOx. Electrons transit through thinner GeOx IL, and TDDB
measured the quality of Al2O3 rather than IL. After taking into account of Dit and
EOT (Table 7.5), it can be concluded that formation of GeOx or GeO2 is helpful for
improvement of Dit values at the cost of increased EOT values and formation of
GeOx is better for device reliability rather than GeO2 because of rapid degradation
of GeO2 can cause gate stack instability, although sample Ge/Al2O3/ZrO2/SPAO
has the best performance of I–V.
Gate leakage current (Ig) is plotted as function sampling time for all samples.
Figure 7.14 shows that typical stress-induced leakage current (SILC) in TDDB
measurement, which was not observed in GEI mode. This SILC is a process of
increasing gate tunneling current via trap-assisted-tunneling. As oxide is degraded,
traps are created, and enhanced trap-assisted-tunneling increases the leakage cur-
rent. Another phenomenon, observed at SEI mode, was that leakage current was
decreased initially before SILC process for Ge/Al2O3/ZrO2/SPAO. This is possibly
due to GeO2 instability, and initially GeO2 transformed to GeOx, which has larger
conduction band offset to block electron from substrate [86,87]. An initial decrease
High-k dielectrics for nanometer CMOS technologies 185
50
SPAO/AI2O3/ZrO2 at 3.6 V
AI2O3/SPAO/ZrO2 at 4.0 V
40
AI2O3/ZrO2/SPAO at 3.7 V
Ig (μΑ)
30 Interfacial layer instable
SILC
20
10
1 10 100 1,000
Sampling time (s)
Figure 7.14 Gate leakage current (Ig) is plotted as function sampling time for all
the samples
in IG could also simply be due to electron trapping in the existing traps, followed by
hole trapping and subsequently increasing SILC by trap-assisted-tunneling. It was
also observed that there exists secondary breakdown in sample Ge/Al2O3/ZrO2/
SPAO, which is another evidence of IL degradation (not shown here). Therefore,
TDDB measurements at SEI mode were representing the quality of IL rather than
overall oxide breakdown (Figure 7.13).
In summary, the TiN/ZrO2/Al2O3/p-Ge gate stacks were studied for their
temperature-dependent carrier transport mechanisms and reliability in terms of
oxide breakdown. Different SPAO annealing conditions reveal that although SPAO
can effectively remove the traps in high-k dielectrics and subsequently reduce the
leakage current, the formation of GeO2/GeOx inevitably impacts the reliability.
Trap energy levels in ZrO2 and Al2O3 are found to be 0.13 eV and 0.27 eV
respectively by fitting Poole-Frenkel emission model. TDDB characteristics sug-
gest that GeO2 can be degraded faster than GeOx since in GeOx electron can transit
through IL even though both of the layers can give similar Dit values of around
5 1011 cm2/eV. If the ALD process decomposes GeO2 into a stable GeOx, the
overall performance of the gate stack is more stable as shown in case of sample Ge/
Al2O3/SPAO/ZrO2.
This section investigates the dielectric quality and interface properties of TiN/Hf1-
xZrxO2/Al2O3/Ge gate stacks with six different Zr content (0%, 25%, 33%, 50%,
75%, and 100%). The dielectrics were subjected to SPAO after the ALD deposition
process prior to metal deposition.
186 Advanced technologies for next generation integrated circuits
0.20
1.35
Jg@–1V+VFB (A/cm2)
0.15
1.20 10–4
0.10
EOT (nm)
VFB (V)
1.05
0.05
–0.05 1.75
Figure 7.15 EOT (filled squares to the right scale), and flat-band voltage shift
(open triangles to the left scale) (a), gate leakage current density at
1 V þ VFB (b) as a function of zirconium percentage for TiN/
Hf1xZrxO2/Al2O3 gate stacks on germanium substrate
High-k dielectrics for nanometer CMOS technologies 187
This can be attributed to the reduced direct tunneling because of thicker dielectric
barrier. This observation further supports the observed CV characteristics [88] and
corresponding EOT shown in Figure 7.15(a).
Group - I
R1 R3 R4
6 nm ALD TiN+50 nm PVD 6 nm ALD TiN+50 nm PVD 6 nm ALD TiN+50 nm PVD
TiN TiN TiN
8 nm Ti 8 nm Ti 8 nm Ti
7 nm HfAIO2 7 nm HfO2 7 nm HfZrO2
1 nm AI2O3 1 nm AI2O3 1 nm AI2O3
50 nm TiN 50 nm TiN 50 nm TiN
10 nm Ti 10 nm Ti 10 nm Ti
Group - II R5
R4 R2 6 nm ALD TiN+50 nm PVD
6 nm ALD TiN+50 nm PVD 6 nm ALD TiN+50 nm PVD TiN
TiN TiN 8 nm Ti
8 nm Ti 8 nm Ti ALD 2 nm TiN
PDA 7 nm HfZrO2
7 nm HfZrO2 7 nm HfZrO2
700C
1 nm AI2O3 1 nm AI2O3 60s 1 nm AI2O3
1
R3
R4
0.8
R1
Frequency (%)
0.6
0.4
0.2
0
1 10 100 1,000 10,000
ROFF/RON
Figure 7.16 Device configurations showing the switching layer variation and
process condition variations (a); Cumulative distribution of Roff/Ron
ratios of all the Group-I devices (b)
(R4) for identical compliance current. It is known that in stoichiometric HfO2 the
forming voltage is usually rather high (5). The initial filament formation starts with
a trigger location with either a defect site, grain boundary or oxygen vacancy
location. On the other hand, HfAlO2 and HfZrO2 show more suitability because of
the lower forming voltage. But when samples with HfZrO2 were subjected to a
post-deposition annealing (R2) the forming voltage increases. Whereas modifying
the top electrode (TE) metal (R5) has a little effect on the forming voltage values.
Table 7.6 shows the different devices, compliance currents and forming voltages.
Furthermore, by comparing the different parameters of the RRAM devices of
Group-I, where dielectric variation of the switching layer is listed, it was observed
High-k dielectrics for nanometer CMOS technologies 189
that the average set and reset power requirements for the R1 devices with HfAlO2
as switching layer are the lowest. Whereas HfO2 (R3) shows the worst perfor-
mance. Figure 7.16(b) outlines the cumulative variation of the Roff/Ron ratios of all
the Group-I devices. For reliability and endurance Roff/Ron ratios are significant.
Comparing the variation of switching layer it was observed that the device 10 nm
Ti/50 nm TiN/1 nm Al2O3/7 nm HfAlO2/8 nm Ti/6 nm ALDTiNþ50 nm PVD TiN
(R1) provided the superior average Roff/Ron values and both set and reset power com-
pared to HfO2 (R3), and HfZrO2 (R4) devices. When the HfZrO2 (R4) devices were
compared with the identical device with PDA (R2) Ron increased and Roff decreased for
the PDA device, reducing the Roff/Ron value. While the reset power increases the set
power for PDA devices moderately decreased. The impact of top electrode config-
uration shows that with a variation of cap layer to TiN instead of Ti decreases set power
but increases reset power. When all the RRAM devices for the set power and reset
power were compared it was observed that devices R3 and R2 behaved irregularly for
set and reset powers respectively. While reset power is the lowest for the R1 devices
with HfAlO2 as switching layer, the set power decreased for HfZrO2 when the top
electrode configuration was modified. RRAM operation and power requirement,
therefore, depends on the switching layer and electrode configuration.
In this section, several dielectric stacks for enhancing RRAM operation and
power requirements for a low-power operation were discussed. It was observed that
that HfAlO2 as the switching layer has superior characteristics while HfZrO2
showed comparable characteristics. When HfZrO2 as the switching layer was
subjected to a PDA, the characteristics degraded because of reduced trigger points.
With the top electrode metal configuration, the characteristics improved.
7.7 Summary
Since high mobility substrates such as Ge have attracted increasing attention to
enhance the devices, performance for the next-generation CMOS devices, the
chapter investigated the high-k dielectrics on germanium substrates for EOT scal-
ing and interface performance. In addition, we have looked at some of the appli-
cations of high-k dielectrics for next-generation resistive random-access memory
devices. In this study, several MOS structures, prepared by advanced ALD process
190 Advanced technologies for next generation integrated circuits
and with pre and post treatment by plasma generated by slot plane antenna (SPA)
were investigated. The chapter reviewed the oxide/substrate interface quality and
the dielectric quality of metal-oxide semiconductor (MOS) gate stack structures as
they are critical to future CMOS technology. Different electrical characterization
methods such as CV, GV, DLTS, IV and reliability issues like TDDB were used
throughout this chapter. Even though DLTS measurements were more difficult to
implement it complements the conductance and low-frequency CV methods for
device characterization. CV and GV are not able to provide true energy levels of
the trap/defects and it is usually fulfilled by simulation software like CVC 7.0. The
detection of trap energy level is usually limited in the depletion region and can be
extended to inversion region if substrate is not doped (no minority carrier
response). To extract the energy level, direct DLTS measurements are required.
The impact of different interface treatments on Ge/high-k gate stacks was
outlined. Simple interfacial treatment leads to higher Dit values in the order of
1013 cm2/eV that causes Fermi level more or less pinned. This was confirmed by
low temperature measurements. More negative Vth shift due to existing border trap
was characterized using DLTS method. The IL quality (Dit), and quality of high-k
layer in terms of leakage current density and TDDB under different SPAO
annealing were also discussed. Controlling SPAO decomposed the unstable GeO2
into GeOx, which turned out to be more reliable than GeO2 as observed in TDDB
results. SPAO removes high-k layer defects and different SPAO strategy also
formed different IL thickness. Improvement and understanding of post annealing
and ALD process is very critical to the future implementation of sub-nm EOT on
high-k layers regarding that they impact the IL quality.
References
[1] H. Iwai, “Roadmap for 22 nm and Beyond,” Microelectron. Eng., vol. 86,
p. 1520, 2009.
[2] maltiel-consulting.com, “International Technology Roadmap for
Semiconductors: 2012 Update,” 2012, [Online]. Available: http://www.maltiel-
consulting.com/ITRS-2012-Update-Overview.pdf. [Accessed: 28-Jun-2016].
[3] G. D. Wilk, R. M. Wallace, and J. M. Anthony, “High-K Gate Dielectrics:
Current Status and Materials Properties Considerations,” J. Appl. Phys.,
vol. 89, p. 5243, 2001.
[4] A. Lubow, S. Ismail-Beigi, and T. P. Ma, “Comparison of Drive Currents in
Metal-Oxide-Semiconductor Field-Effect Transistors Made of Si, Ge, GaAs,
InGaAs, and InAs Channels,” Appl. Phys. Lett., vol. 96, p. 122105, 2010.
[5] D. Hisamoto, W.-C. Lee, J. Kedzierski, et al., “FinFET—A Self-Aligned
Double-Gate MOSFET Scalable to 20 nm,” IEEE T. Electron. Dev., vol. 47,
2000.
[6] R. W. Johnson, A. Hultqvist, and S. F. Bent, “A Brief Review of Atomic
Layer Deposition: from Fundamentals to Applications,” Mater. Today.,
vol. 17, p. 236, 2014.
High-k dielectrics for nanometer CMOS technologies 191
8.1 Introduction
Dinaphtho[2,3-b:20 ,30 -f]thieno[3,2-b]thiophene (DNTT) is a popular material for
the fabrication of organic field-effect transistors (OTFTs), better stability in air,
with higher mobility, and better reproducibility. DNTT-based devices exhibit very
less degradation and hysteresis loss in the transfer characteristics of device over a
long period of time. These DNTT OTFT features are even better than pentacene,
which is also used in organic electronics fabrication field in the last decade. Due to
its high performance and stability, DNTT would be the next generation of the new
standard organic semiconductor (OSC). The air stability, good performance very
small molecule of DNTT can be used for the implementation of a flexible amplifier
circuit. Low-temperature polymers as a gate dielectric and air-stable DNTT as a
semiconductor active matrix (AM) backplanes can be successfully fabricated on
any flexible substrates.
From the past decade, efforts have been increased significantly to implement
and develop the electronic circuit on stretchable and flexible substrates. With the
advent of different soluble OSCs and conductors, printed electronic components
have become feasible. Printed electronic products are usually connected to organic
electronic products. They are characterized by the use of organic materials to
implement devices and circuits. Devices containing organic materials are on the
verge of commercialization. In recent years, the research in organic thin-film
transistors (OTFTs) has increased dramatically and has been proven for various
applications such as display with low cost [1], memory using OSC [2], components
used in RFID tags [3], low-end electronics products, circuits, electronic compo-
nents, and sensors using polymer [4]. Flexible electronics is a new era technology
that establishes electronic circuits with storing electronic products on flexible,
stretchable substrates such as paper, plastic and even on cloth. Compared with
inorganic electronic products, organic or flexible electronic products have the
1
Department of Electronics and Communication, Malaviya National Institute of Technology (MNIT),
Jaipur, India
2
Department of Electrical and Electronics, Poornima University, Jaipur, India
198 Advanced technologies for next generation integrated circuits
following distinct advantages: (i) it can be manufactured at low cost; (ii) it is light-
weight, thin, bendable, foldable and has strong absorbance and will not be crushed.
It has mechanical flexibility, low energy consumption, high emission efficiency;
and (iii) it has cheaper materials and lower cost deposition processes, the cost is
lower [5], therefore it is also used for large-area applications. In fact, the stacking
and rapid annealing of OSC and low-temperature polymer gate dielectrics are
suitable for high-throughput, low-cost printing manufacturing [6]. The researchers
used (DNTT) [7], poly(3-hexylthiophene) P3HT, poly(3-alkylthiophene), poly(3-
octylthiophene) P3OT and as organic materials instead of semiconductors, and used
dielectric layers to create complete flexibility.
8.2 Motivation
First field-effect transistor based on organic material (OFET) was reported by
Koezukaand in 1987 and it opened a new door for researchers all over the world in
this field. Since then, great progress has been made in the synthesis of organic
materials, manufacturing techniques, processing methods, and equipment. Organic
electronics refers to new era electronics that use polymers or carbon-based small
molecules as functional materials for conductors, semiconductors, and dielectrics.
Main reasons for this choice are as follows [5,6]:
1. Low process temperature
2. Low-cost manufacturing
3. Roll-to-roll manufacturing
4. Large-area electronics
5. Large material choice
6. Solution processable
Despite these advantages, organic electronics have some drawbacks which do
not allow them to compete with inorganic material (silicon)-based electronic
devices. The disadvantages are as follows:
1. Low carrier mobility
2. Mono-type circuits
3. Large variability
4. Limited controllability
However, the mentioned distinct properties of DNTT have been made it one of
the potential candidates for various applications.
From Figure 8.1, it can be seen that organic electronics have great potential in
the future by introducing products to the market in new forms.
The research community for integrating smart systems would explore oppor-
tunities to develop circuits and systems with OTFT. Figure 8.2 shows the com-
parison of organic and inorganic semiconductors because organic technology has
various advantages over inorganic technology [8].
High performance
High temperature
Silicon High performance
Low power
Cost
Large area
Organic Low cost
Low temperature
flexible
Performance
Dielectric
Aluminum Gate
VGS
Substrate
(a)
1 × 10–5
1 × 10–6
1 × 10–7
1 × 10–8
1 × 10–9
ID (A)
1 × 10–10
1 × 10–11
1 × 10–12
1 × 10–13
1 × 10–14
–3.0 –2.5 –2.0 –1.5 –1.0 –0.5 0.0
(b) Gate voltage (V)
Aluminum Aluminum
Dielectric
Au(S) Dielectric Au(D) DNTT (Organic semiconductor)
Substrate Substrate
(a) (b)
Figure 8.4 Structure of top gate configuration: (a) top gate top contact (TGTC)
and (b) top gate bottom contact (TGBC)
(c) (d)
Figure 8.5 Structure of bottom gate configuration (c) Bottom gate bottom contact
(BGBC) and (d) bottom gate top contact (BGTC)
Technology and modeling of DNTT organic thin-film transistors 203
Vacuum level
qφs
qφA1
S
S
LUMO
EF EF
HOMO
Metal gate DNTT
semiconductor
Insulator
(a) (b)
Figure 8.6 (a) Structure of DNTT OSC and (b) energy diagram of MIS
structure [14]
similar to OSC HOMO and LUMO energy gap. Especially for DNTT, HOMO
energy level is approximately 5.19 eV and energy level of LUMO is almost
1.81 eV [13,14]. This introduces a large enough 3.38 eV HOMO–LUMO energy
gap, which is sufficient for transistor operation. Numerical simulation of the bottom
gate and top gate configuration is completed using the parameter given in
Table 8.1.
rðx; yÞ
r:E ¼ (8.1)
2
204 Advanced technologies for next generation integrated circuits
where 2 is the permittivity of the region, and r(x, y) is the charge density given as
@n 1
¼ r:Jn þ Gn Rn (8.4)
@t q
@p 1
¼ r:Jp þ Gp Rp (8.5)
@t q
For OTFTs, there is no optical absorption, so the term is simplified and the
properties of the material are described by the minority carrier recombination
lifetime. Since MOSFETs are majority carrier devices, the behavior of carrier
recombination and generation are relatively unimportant. Physical properties of the
layer of OSCs depend on the movement and generation of polarons [16].
Third important set of equations for explaining device physics for charge
carrier is given by
It contains drift and diffusion parts. These equations determine the current
density based on carrier mobility (m), electric field (E), the carrier density (n, p) and
the diffusion coefficient of the carrier (D). Diffusion coefficient operators are
related to Einstein’s mobility relationship:
kT
Dn ¼ m (8.8)
q n
kT
Dp ¼ m (8.9)
q p
Technology and modeling of DNTT organic thin-film transistors 205
gðEÞ ¼ gTA ðEÞ þ gTD ðEÞ þ gGA ðEÞ þ gGD ðEÞ (8.10)
Trap energy is given by E, conduction energy is EC, valence energy EV and the
subscripts (G,A,D,T) stand for, Gaussian (deep level), acceptor, donor, tail states,
respectively:
E EC
gTA ðEÞ ¼ NTAexp (8.11)
WTA
E EV
gTD ðEÞ ¼ NTDexp (8.12)
WTD
" #
EGA E 2
gGA ðEÞ ¼ NGAexp (8.13)
WGA
" #
E EGD 2
gGD ðEÞ ¼ NGDexp (8.14)
WGD
DOS for the exponential tail is defined by its conduction and valence band edge
intercept density (NTA and NTD) and its attenuation energy (WTD and WTA).
DOS for Gaussian distributions is given by the total state density (NGD and NGA),
its attenuation energy (WGD and WGA) and peak distribution (EGD and EGA).
ð EC
nTD ¼ gTD ðEÞ:ftTD ðE; n; pÞdE (8.19)
EV
ð EC
nGD ¼ gGD ðEÞ:ftGD ðE; n; pÞdE (8.20)
EV
ftGA(E,n,p) and ftTA(E,n,p) are the ionization probabilities for the Gaussian acceptor
and tail DOS, and ftTD(E,n,p) and ftGD(E,n,p) are defined as the probability of occu-
pation of a trap level at energy E for the Gaussian and tail acceptor and donor states
in steady state are given by following (8.21)–(8.24):
i E
vn SIGTAE:n þ vp SIGTAH:ni exp EkT
ftTA ðE; n; pÞ ¼ i E i E
vn SIGTAE n þ ni exp EkT þ vp SIGTAH p þ ni exp EkT
(8.21)
i E
vn SIGGAE:n þ vp SIGGAH:ni exp EkT
ftGA ðE; n; pÞ ¼ i E i E
vn SIGGAE n þ ni exp EkT þ vp SIGGAH p þ ni exp EkT
(8.22)
i
vp SIGTDH:p þ vn SIGTDE:ni exp EE
ftTD ðE; n; pÞ ¼ i kT
i E
vn SIGTDE n þ ni exp EE
kT þ v p SIGTDH p þ ni exp EkT
(8.23)
i
vp SIGGDH:p þ vn SIGGDE:ni exp EE
ftGD ðE; n; pÞ ¼ i kT
i E
vn SIGGDE n þ ni exp EE
kT þ v p SIGGDH p þ ni exp EkT
(8.24)
where mpPF ðEÞ and mnPF ðEÞ are the Poole–Frenkel mobility’s for holes and elec-
trons, respectively, mn0 and mp0 are defined as the zero-field motilities and E is the
electric field. The activation energies at zero electric field for holes and electrons
are presented by DELTAEP.PFMOB and DELTAEN.PFMOB, respectively.
BETAN.PFMOB, BETAP.PFMOB is the Poole–Frenkel factor. Tneff , Tpeff are the
effective temperature.
–6.00E–010
VDS = 10 V
–5.00E–010 VDS = 15 V
Drain current (A)
–4.00E–010
–3.00E–010
–2.00E–010
–1.00E–010
0.00E+000
5.00E–011
0.00E+000
–5.00E–011
–1.00E–010
–1.50E–010
Drain current (A)
–2.00E–010
–2.50E–010
–3.00E–010
–3.50E–010
–4.00E–010 VGS = –5 V
–4.50E–010 VGS = –10 V
–5.00E–010 VGS = –15 V
VGS = –20 V
–5.50E–010
VGS = –25 V
–6.00E–010
–30 –25 –20 –15 –10 –5 0
(b) VDS (V)
Organic semiconductor
SS DNA molecules
Dielectric
Gate
for electronic paper or LCDs. OLEDs [21–23] are used in televisions, mobile
phones, and various display systems.
8.6 Conclusion
In this chapter, novel technology and modeling of DNTT-based OTFT is presented
by considering field-dependent mobility model and density of states model. Finite
element method (FEM)-based device simulation model is able to produce output
characteristics in linear and saturation region and transfer characteristics below and
above the threshold region of a DNTT-based OTFT. Some important applications,
advantages, and disadvantages of OTFTs are also discussed briefly.
Acknowledgments
The authors are thankful to the SERB, DST Government of India, for the financial
support of Project no. ECR/2017/000179.
210 Advanced technologies for next generation integrated circuits
References
[1] M. Mizukami, N. Hirohata, T. Iseki, et al. “Flexible AM OLED panel driven
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[2] M. Takamiya, T. Sekitani, Y. Kato, H. Kawaguchi, T. Someya, and
T. Sakurai “An organic FET SRAM with back gate to increase static noise
margin and its application to Braille sheet display” IEEE Journal of Solid
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[3] E. Cantatore, T.C.T. Geuns, G.H. Gelinck, et al. “A 13.56 MHz RFID sys-
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[5] A. Lodha, and R. Singh “Prospects of manufacturing organic semiconductor-
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and their application to field-effect transistors.” Journal of the American
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Transistor Applications, Materials to Circuits,” Boca Raton: Taylor &
Francis, CRC Press, 2017.
[9] P. G. LeComber, W. E. Spear, and A. Ghaith “Amorphous-silicon field-effect
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[10] A. Tsumura, H. Koezuka, and T. Ando “Macromolecular electronic device:
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[11] K. Kudo, M. Yamashina, and T. Moriizumi “Field effect measurement of
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[13] T. Yamamoto, and K. Takimiya, “Facile synthesis of highly p-extended
heteroarenes, dinaphtho[2,3-b:20 ,30 f]chalcogenopheno[3,2-b]chalcogenophenes,
and their application to field-effect transistors.” Journal of the American
Chemical Society 129, 22242225, 2007
[14] T. Zaki, S. Scheinert, I. Hörselmann, et al. “Accurate capacitance modeling
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[15] A. Buonomo, and C. di Bello “On solving Poisson’s equation in two-
dimensional semiconductor devices” Electronics Letters 20, 4 1984
Technology and modeling of DNTT organic thin-film transistors 211
9.1 Introduction
As we are moving towards sub-20 nm regime, the tunnel field-effect transistors
(TFETs) are captivating tremendous attention as the semiconductor switches. To
know why TFETs can be used as the semiconductor switch, it is essential to
comprehend what are the problems with conventional metal-oxide-semiconductor
field-effect transistors (MOSFETs). In order to understand that, we will begin with
the scaling of conventional MOSFETs and its merits and demerits.
According to Dennard’s scaling rules, the doping of source (S) and drain (D)
regions should increase by a factor of S, while keeping the electric filed inside the
1
Department of Electronics and Communication Engineering, Malaviya National Institute of
Technology, Jaipur, India
2
Department of Electrical Engineering, Indian Institute of Technology Delhi, Delhi, India
214 Advanced technologies for next generation integrated circuits
6
Supply voltage (VDD)
5 Threshold voltage (VTH)
4
Voltage (V)
3
Gate overdrive
voltage
2
VDD - VTH
0
1.4 1.0 0.8 0.6 .35 .25 .18 .13 .09 .065
Technology generation
Figure 9.1 The trend of supply voltage and threshold voltage scaling vs.
technology generations [1]
device unchanged [1]. In addition, all the device dimensions and applied voltages
should be scaled by 1/S. These rules have been roughly followed ever since, until
rather recently. The reason why Dennard’s scaling rules are no longer to be fol-
lowed for the conventional MOSFETs scaling as they were followed in the past
because of the threshold voltage (VTH) did not follow the natural rule of Dennard
scaling. One can observe from Figure 9.1, as we are scaling the technology node
from the 1.4 um to 65 nm node, the supply voltage (VDD) decreased to about 78% of
its original value, while the VTH only went down to approximately half of its
starting value, consequently, gate overdrive voltage is also cut down [2].
The most serious consequence of gate overdrive voltage reduction causes
decrement in ON-state current (ION). In addition, decrement in ION directly affects
the conventional MOSFET performance, the ION/IOFF ratio, and dynamic speed
(CG*VDD/ION). So, in order to acquire high gate overdrive voltage for keeping the
conventional MOSFET performance good, there are two possible solutions, which
are as follows:
● Scaling of threshold voltage, and.
● Need of slow supply voltage (VDD) scaling.
Thermionic emmision
CB
Energy level
n+ p n+
VB
Conventional MOSFET
Drain Channel Source
Figure 9.2 Energy band diagram of a MOSFET in which current takes place by
thermionic emission of carriers
dVg mkT
SS ¼ ¼ 2:33 (9.1)
dlogId q
where m is the body-effect coefficient, whose value is close to 1 for a well opti-
mized device. To be more precise, m ¼ 1 þ CDM/COX [4], where CDM is the bulk
depletion capacitance at threshold, when fs ¼ 2fF. A MOSFET with very good
gate control leads to COX/CDM 1, then m can be approximated to 1. Then (9.1)
becomes S ¼ ln(10) 26 mV, or about 60 mV/decade. Then this limit in SS has
impeded the scaling of the threshold voltage as can be seen in Figure 9.1.
The only way to scale the threshold voltage further is to reposition the IDS–VGS
characteristic of the conventional MOSFET horizontally left on the x-axis, as
shown in Figure 9.3(a). We can infer that if we want to shift VTH by 60 mV, then we
have to compensate an increase of one decade of OFF-state current (IOFF), and in
turn of passive power dissipation.
10–2
10–3
10–6
Ioff multiplied by 10x
10–7
for each curve shift
10–8
1E+03
Active power density
1E+02
1E+01
Power density (W/cm2)
1E+00
1E–01
1E–02
1E–03
Passsive power density
1E–04
1E–05
0.01 0.1 1
Gate length (µm)
Figure 9.3 (a) IDS–VGS characteristics of the conventional MOSFET [4], and
(b) active and passive power densities plotted against gate lengths [5]
where Ileak is the sum of leakage currents in the device when the conventional
MOSFET is in OFF-state. One can observe from Figure 9.3(b), the active as well as
the passive power densities are increasing continuously with scaling of gate length.
This is becoming a major concern in semiconductor devices.
Why power consumption is such a problem? There are some fundamental
problems, some of which will be mentioned here. The first reason is increasing cost of
powering and cooling the servers. On a more personal level, mobile devices suffer from
shorter battery life due to increased power dissipation. In addition, Figure 9.4 illustrates
the power dissipation and heatsink size (volume) of various Intel processors [6]. One
can depict that, as we are moving from Intel 386 to Core 2 Duo, the power and heatsink
volume have increased by approximately 92.34%. Since, we would like our appliances,
computers and gadgets to stay the same size or shrink, not get larger in order to
accommodate a large heatsink required by the power-hungry chip inside.
Doping-free tunnelling transistors – technology and modelling 217
70 25
Power
60 Heatsink volume
20
Power (W) 40 15
30 10
20
5
10
0 0
Intel Intel Pent. Pent. Pent. Pent. Core
386 486 II III IV 2 Duo
Microprocessor
Figure 9.4 Computer chip power trends, along with the accompanying increase in
heatsink volume [6]
Vg
Gate
Drain Dielectric Source
Vd Vs
+
N I-Si P+
CB
P+
Energy level
VB
I
N+
n-type TFET
CB
P+
Energy level
Tunneling path VB
N+
N+
Figure 9.6 Energy band diagram of (a) OFF-state and (b) ON-state for n-type
TFET in which current carries by BTBT
is extremely low and is equivalent to the reverse leakage current of the P-I-N diode.
By modulating the channel potential, the gate (i) opens the tunnelling window by
aligning the minimum of conduction band of the channel with the maximum of
valance band of the source, as shown in Figure 9.6(b) and (ii) modulates the effective
Doping-free tunnelling transistors – technology and modelling 219
tunnel barrier width at the source-channel junction, which determines the probability
of tunnelling and thus the level of injection. This role of the gate in controlling the
tunnelling current enables the TFET to operate as an effective switch.
Figure 9.7 Cross-sectional view of (a) conventional TFET [8] and (b) proposed
DF-TFET
Parameters Values
ND 5 1018 cm3
NA 1 1020 cm3
Channel doping 1 1017 cm3
Lightly doped Si 1 1015 cm3
W.F. of CG, PG-1, and PG-2 4.5 eV
TSI 10 nm
TOX 0.8 nm
LCG, LPG-1 and LPG-2 50 nm
SGAP;S 5 nm
SGAP;D 20 nm
Doping-free tunnelling transistors – technology and modelling 221
shown in Figure 9.7, is simulated using 2D ATLAS TCAD tool [15]. The working
mechanism of the proposed device is illustrated by the electrical characteristics and
functionalities supported by TCAD simulator after incorporating different models.
In addition, the potential benefits of polarity control concepts are as follow:
● It allows the degree of freedom to dynamically switch between n- and p-type
DFTFETs. In other words, we can change polarity during operation by setting
the PGs bias and obtained a different functionality from the same circuit.
● It is easy to fabricate and could be less sensitive for SCE than the conventional
TFETs, since the device does not require any exotic materials or advanced
techniques, such as strain technology, etc.
● It does not require thermal annealing and ion implantation process, and using
polarity control concept we can approach large-scale integration.
Moreover, the conventional TFET and proposed DF TFET are analysed using
2-D ATLAS Silvaco simulator. To consider the BTBT, the non-local BTBT model
is incorporated in the device simulation. Along with this trap-assisted tunnelling
(TAT) by Schenk is also incorporated in device simulation.
The dynamic configurable TFET can be achieved by applying the appropriate
biasing on PGs. To show the dynamic configurable TFET initially, the energy band
diagrams for different configurations is shown in Figure 9.8(a) and (b). The bias
condition for n-type TFET are VCG ¼ 0 V, VPG-1 ¼ 1.2 V, VPG-2 ¼ 1.2 V, and
VDS ¼ 50 mV and for p-type TFET are VCG ¼ 0 V, VPG-1 ¼ 1.2 V, VPG-1 ¼ 1.2 V,
and VDS ¼ 50 mV TFETs in the OFF-state can be seen in Figure 9.8(a). One can
observe that both devices (TFETs) in OFF-state offer sufficient barrier and obstruct
the flow of carriers. Similarly, on the application of control signal (i.e. ON-state),
there is an occurrence of appropriate band-bending for n- and p-type TFET, as
shown in Figure 9.8(b).
To validate the dynamic configurability of the proposed device, Figure 9.9
shows the carrier concentration contour plots for the proposed device. These plots
help us in understanding how the electron and hole carrier concentrations vary
across the device under OFF-state and ON-state conditions. On the application of
suitable bias over PGs, the configurable FET shows perfectly doped S/D regions
under different configurations. For example, an n-TFET in OFF-state (VCG ¼ 0 V,
VPG-1 ¼ 1.2 V, VPG-2 ¼ 1.2 V, and VDS ¼ 50 mV) perfectly exhibits the Nþ-I-Pþ
structure, however, on the application of control signal (i.e. ON-state), the structure
becomes Nþ-Nþ-Pþ. Hence, carrier concentration in the ON and OFF-states of
configurable TFET under different configurations perfectly matches with static
conventionally doped TFET.
2.0
CB
1.5 CB
1.0
VB
Energy level (eV)
0.5 n-TFET VB
0.0
p-TFET
–0.5
–1.0
–1.5 PG-1 CG PG-2
–2.0
Figure 9.8 Band diagrams of a configurable n- and p-TFET under (a) OFF-state
and (b) ON-state condition
SOI substrate is used and a vertical stack of four nano channels/wires of 350 nm
lengths on a p-type lightly doped (nearly 1015 atoms/cm3) silicon on insulator
substrate. In order to form HSQ patterns of 60 nm wide and 350 nm long patterns,
e-beam lithography is done to obtain nano channels/wires through single Bosch
DRIE process [16]. Then self-limiting oxidation followed by poly-Si deposition is
required to form gate oxide. To form PG all around the nano channels/wires, PG
material with mid-gap work function need to be deposited and then it can be pat-
terned through e-beam lithography [17]. To form the CG, another oxidation and
poly-Si deposition need to be performed and then patterning is required. Two PGs
and CG is isolated by deposition and patterning by forming spacer of Si3N4. Then,
to form the source and drain contacts, Ni is deposited through e-beam evaporation
and need to anneal around 200 C–400 C to form silicide (NiSi). Further wet
etching through hot Piranha is required to strip /remove/wipe out the Nickel which
is unreacted.
PG-1 CG PG-2
20
5 SGAP,S
SGAP,D
1.5
PG-1 CG PG-2
1.0 OFF-state n-type
ON-state DF-TFET
0.5
Energy level (eV)
0.0
CB
–0.5
–1.0
N+ P+
I
–1.5
VB
–2.0
Figure 9.10 (a) Electron/hole concentration, and (b) energy band diagram of
n-type DF-TFET (VDS ¼ 1.0 V, VPG-1 ¼ 1.2 V, and VPG-2 ¼ 1.2 V)
in OFF- (VCG ¼ 0 V) and ON-state (VCG ¼ 1.2 V)
not have any p-n junctions in thermal equilibrium. Further, to guarantee the
dynamic configurability and symmetric ID–VG characteristics of the proposed
device, we reversed the bias across PGs that represents p-type DF dynamically
configurable TEFT and observed ID–VG characteristics, as shown in Figure 9.11(b).
However, the ON-state current of the proposed device is smaller than the
conventional TFET as shown in Figure 9.11(a). It is because the resistance offered
by the proposed device in the ON-state is higher than the conventional TFET,
which is similar to the past reported results [14]. Furthermore, for conventional
TFET, the ON-state resistive components are channel resistance (Rch) and
Doping-free tunnelling transistors – technology and modelling 225
10–4
10–6
VDS = 1 V
10–8 VPG-1 = 1.2 V
10–10 VPG-2 = –1.2 V
10–12
101
p-type DF-TFET
10–1
Drain current, IDS (µA/µm)
10–3
10–5
VDS = 1.0 V
10–7 VPG–1 = –1.2 V
VPG–2 = +1.2 V
10–9
tunnelling width resistance (Rtunnel) whereas, for DF-TFET there are two more
additional resistive components, i.e. due to source side spacer (RSGAP;S) and drain
side spacer (RSGAP;S), as shown in Figure 9.12(a) and (b).
D CG S PG-1 CG PG-2
D S
Rch Rtunnel N RSGAP,D Reh RSGAP,S Rtunnel N
I
I
S S
N+ N P+ I I
CG PG-1 CG PG-2
0.5
Conventional n-type TFET
0.4
Drain current, IDS (µA/µm)
VCG = 0.8 V
0.1
0.0
0.0 0.2 0.4 0.6 0.8 1.0
(a)
VDS (V)
0.15
n-type DF-TFET
Drain current, IDS (µA/µm)
0.12
0.03
0.00
Figure 9.13 Output characteristics of (a) conventional TFET and (b) n-type
DF-TFET for different control-gate (CG) voltages
Doping-free tunnelling transistors – technology and modelling 227
The triode region in output characteristic can be defined as VDS < VGS VTH.
Further, in the triode region, ID and VDS follow a linear relationship, and saturation
region in output characteristic is due to the pinched off the channel. Further, in the
saturation region the drain current (ID) is free from the effect of drain to source
voltage (VDS). The saturation region in the output characteristic can be defined as
VDS VGS VTH.
10–4
VDS = 0.3 V
10–6
VDS = 0.4 V
10–8
VDS = 0.5 V
10–10
10–12
10–5
10–7
10–9
VPG–1 = 1.2 V & VPG–2 = –1.2 V
10–11 VPG–1 = 1.0 V & VPG–2 = –1.0 V
VPG–1 = 0.8 V & VPG–2 = –0.8 V
10–13
1.50
PG-1 CG PG-2
Decreasing
0.00 PG Bias
VB
–0.75
Figure 9.15 Impact of PG bias on (a) transfer characteristics and (b) OFF-state
band diagrams
35 25
n-type DF-TFET VDS = 1 V
20 15
Figure 9.16 Effect of VCG over energy barrier width and electron tunnelling
rate for n-type DF-TFET
Since energy barrier width is directly related to the electron tunnelling rate, in
other words, lower the energy barrier width higher the electron tunnelling rate and
consequently higher will be ION. One can justify the same with the (9.4), which is
based on the WKB approximation:
0 qffiffiffiffiffiffiffiffipffiffiffiffiffiffiffiffiffi1
4l Eg 3 2m
T WKB ¼ exp@ A (9.4)
2qh Eg þ Df
where m* is the effective carrier mass, Eg is the bandgap, Df is the energy range
over which tunnelling can take place, and l can be given as:
rffiffiffiffiffiffiffiffiffi
2SI
l¼ T OX T SI (9.5)
2OX
where TOX , TSI , 2SI and 2OX are the silicon and oxide film thickness and dielectric
constant, respectively.
4 18
ION n-type DF-TFET
SS 17
3
ION (µA/µm) 16
SS (mV/dec)
ION
2 15
VDS = 1 V
VPG-1 = 1.2 V 14
1 VPG-2 = –1.2 V
13
0 12
6 9 12 15
SGAP,S (nm)
Figure 9.17 ON-state current (ION) and SS of n-type DF-TFET for different
source side spacer thickness (SGAP;S)
10–5 LCG = 20 nm
LCG scales
10–7 LCG = 30 nm
LCG = 40 nm
10–9
vCG = 50 nm
10–11
0.0 0.3 0.6 0.9 1.2
(a) Control gate voltage, VCG (V)
VDS = +1.0 V
10–3 VPG-1 = +1.2 V
VPG-2 = –1.2 V
10–7 LCG = 20 nm
LCG = 30 nm
10–11 LCG = 40 nm
LCG = 50 nm
1013
DF-TFET
Conventional TFET
1012
1011
ION/IOFF
1010
109
108
107
20 nm 30 nm 40 nm 50 nm
(c)
LCG (nm)
ION (µA/µm)
VTH (mV)
500
21
VTH (mV)
200 400
450
14 n-type DF-TFET
100 375
400 7
Conventional n-type TFET
0 350 0 350
100 200 300 400 500 100 200 300 400 500
(a) Temperature (K) (b) Temperature (K)
580
300 580 n-type DF-TFET
12
560
250 560
Conventional n-type TFET 9 540
200 540
ION (µA/µm)
ION (µA/µm)
VTH (mV)
VTH (mV)
520
520
150 6 TOX = 0.5 nm
500
500 TOX = 1.5 nm
100
3 480
TOX = 0.5 nm 480
50
TOX = 1.5 nm 460 460
0 0
100 200 300 400 500 100 200 300 400 500
(c) Temperature (K) (d) Temperature (K)
Figure 9.19 ION and VTH fluctuation with variation in temperature for different
silicon thickness (a) conventional TFET, (b) DF-TFET and for
different oxide thickness, (c) conventional TFET and (d) DF-TFET
TOX ¼ 0.5 nm and same temperature change, yields approximately 0.1949 mV/K
change in VTH and 0.3174 mA/K change in ION, while in the case of the proposed
device, these changes remain 0.0981 mA/K and 0.0248 mA/K, respectively, that are
very small (about 1/10) in comparison to conventional TFET. These results are also
summarized in Table 9.2.
is specifically dependent on BTBT and also on the gate oxide capacitance [8]. For
different TOX Figure 9.20 depicts the sensitivity of both conventional and proposed
device in context of ION and SS. Due to enhancement in the gate electric field, it is
observed that reduction in TOX enhances ION and SS in both devices and even
reduces SCEs [21]. Furthermore, when comparing conventional TFET and the
proposed DF-TFET, conventional TFET shows a large variation in SS and ION. To
improve the short-channel characteristics in DF-TFET, there is no necessity to
aggressively scale TOX as in conventional TFETs, hence DF-TFET device exhibits
better control over channel. The SS and ION change by 11.2805 mV/dec and
34.867 mA/mm, respectively, for per nm change in TOX (scaling from 2.5 to 0.5 nm) of
conventional TFET, while SS and ION remain only 4.0963 mV/dec and 2.59 mA/mm,
respectively, for DF-TFET. From the results mentioned in Table 9.3, we can infer that
conventional TFET exhibits very high sensitivity (about 10) towards the device
parameters. The RDF in the devices is induced due to the presence of doped S/D and
channel regions under the influence of vertical electrical field, it even results in sig-
nificant differences in device electrical characteristics [12].
80 45
n-type DF-TFET
n-type Conv. TFET 40
60
35
ION (µA/µm)
SS (mV/dec)
40 30
SS 25
20
20
15
0
ION
10
0.5 1.0 1.5 2.0 2.5
TOX (nm)
n-type DF-TFET 24
500
n-type Conv. TFET
21
400
SS (mV/dec)
ION (µA/µm) 18
300
15
200
12
SS
100 9
ION
0 6
5 6 7 8 9 10
TSI (nm)
9.5 Summary
References
1
Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge,
LA, USA
238 Advanced technologies for next generation integrated circuits
understanding of the transistor operation but also enable their potential for circuit-
level synthesis.
In this chapter, an analytical current transport model of a p-i-n n-type armchair
GNR TFET is developed which is compared with numerical simulation. Two
separate current transport models are derived analytically from semi-classical and
semi-quantum modeling approaches. Non-equilibrium Green function (NEGF)-
based numerical simulation study is also carried out. Results obtained from these
two methods are compared with the numerical simulation to establish analytical
models. The analytical model in the work of Zhang et al. [2] is revisited and results
are also compared with the analytical and numerically simulated results in this
work. Furthermore, GNR TFET’s performance is studied for varying GNR width
using semi-classical, semi-quantum and NEGF simulation-based current transport
models. Finally, complementary GNR TFET inverter for digital circuit design is
demonstrated through the computation of voltage transfer characteristic from all
three modeling approaches.
0 D
S EC
EC OFF
C
–0.2 C EV
EV
–0.4
D
S ON EV
EV λ
–0.6
0 10 20 0 10 20
(c) Position (nm) (d) Position (nm)
Figure 10.1 Schematic of GNR TFET. (a) Vertical cross-section of p-type GNR
TFET with 1 nm SiO2 top gate dielectric. Channel length is 20 nm
with 5 nm of source and drain extension making the total length of
GNR 30 nm, (b) n-type GNR TFET, (c) energy band diagram of n-i-p
GNR TFET (p-type GNR TFET where both VGS and VDS are “” ve)
and (d) energy band diagram of p-i-n GNR TFET (n-type GNR TFET
where both VGS and VDS are “þ” ve). Note: In both (c) and (d), solid
line is for off-state whereas dashed line is for on-state. The off-state
is defined as |VDS| ¼ 0.1 V and |VGS| ¼ 0 V and on-state is defined as
|VDS| ¼ 0.1 V and |VGS| ¼ 0.1 V. Semiconducting GNR (20,0) has a
bandgap of 0.52 eV for its corresponding 2.3 nm width. Inset:
Enlarged view of potential variation
occurs through source-channel tunnel junction. Further, for VGS > 0 (in n-type
TFET) and VGS < 0 (in p-type TFET), a tunneling window opens and initiates band-
to-band tunneling. Direction of arrows shows flow of carriers due to tunneling
between source and channel. GNR TFET is less sensitive to channel mobility since
band-to-band tunneling dominates over the scattering in channel. Both source and
240 Advanced technologies for next generation integrated circuits
where jG and jS are contact potentials due to gate and source contacts. The built-in
potential jBI is defined as follows [12]:
EG N
jBI ¼ VT ln (10.2)
2 ni
where EG is the GNR bandgap (0.289 eV), VT is the thermal voltage (0.0259 V at
300 K), N is the doping density (5 1011/cm2), and ni is the intrinsic carrier
density (9 1010/cm2) [13]. jOX is the potential drop due to gate oxide over the
channel. Corresponding change in GNR bandgap due to additional intermediate
energy states from edge roughness can be considered through (10.2). Potential drop
through the gate oxide is defined as follows:
Qo
jox ¼ (10.3)
Cox
In (10.3), Q0 ¼ nsq is the total charge, where ns is the induced surface charge
density through gate oxide and is calculated as follows [14]:
eo eox ðVGS VTH Þ
ns ¼ (10.4)
qtox
Here, VGS is input gate-source voltage. For 1 nm SiO2 gate oxide (relative per-
mittivity 3.9) and 0.1 V gate-source input voltage, calculated ns is 2.16 1012 cm2
[15]. Oxide capacitance is defined as, Cox ¼ eoeox/tox. Substituting values of COX in
(10.3) and replacing jOX in (10.4), VTH can be calculated as a function of both
dielectric permittivity and oxide thickness.
Integrating product of charge flux and tunneling probability from 0 to energy
window of Dj, 1D Zener tunneling current is calculated as follows [12]:
ð Dj
IT ¼ qVg rGNR ðk Þ ½fS ðEÞ fD ðEÞTWKB dk (10.5)
0
In (10.5), ID is the tunneling drain current, Vg is the group velocity (1/ℏ (dE/dk));
rGNR(k) is the 1D density of states of graphene in k-plane (1/p) [2] and fD(E) is the
Fermi level position at drain (qVDS) and fS(E) is the Fermi level position at source (0).
TWKB is the tunneling probability in a semiconducting p-n junction GNR and is
expressed as follows [16]:
pEG2
TWKB ¼ exp (10.6)
4qℏvF x
Here, vF108 cm/s is the Fermi velocity, EG is GNR bandgap, ℏ is the reduced
Plank’s constant and x is the electric field at the source-channel tunnel junction.
Based on the universal analytic model for TFET proposed by Lu et al. [17], electric
field at the tunnel junction is linearly dependent on the junction built-in electric
field, VGS and VDS. This is expressed as follows:
x ¼ x0 ð1 þ g1 VGS þ g2 VDS Þ (10.7)
242 Advanced technologies for next generation integrated circuits
where x0 is the built-in electric field at the source-channel tunnel junction when
VGS ¼ VDS ¼ 0 V. Parameters g1 and g2 are the linear coefficients in unit of inverse
of volt (V1). An increase in gate bias enhances the electric field at the tunnel
junction by narrowing the tunneling barrier whereas an increase in drain bias also
does the same with a lesser degree as the drain field is screened by the gate elec-
trode. The limit considered in this work for g1 ranges from 1 to 5 whereas for g2
from 5 to 10, which is higher than that proposed in [17]. The model derived in [17]
describes the parameters with respect to bulk three-dimensional heterojunction
material. It is to be noted that the electrical properties and energy band structure of
GNR are significantly different from such materials. Built-in electric field is
dependent on both the built-in potential and the length of potential screening at the
source-channel tunnel junction as follows:
x0 ¼ jBI =l (10.8)
The Fermi levels at the drain and source are expressed as follows:
1
f D ðE Þ ¼ (10.9)
EEfD =kT
1þe
1
f S ðE Þ ¼ (10.10)
EEfS =kT
1þe
Here, E is the energy of electron with a unit in electron-volt (eV) during the
operation of band-to-band tunneling occurs. During the off-state, source Fermi
level is at 0 V and drain Fermi level is at VDS with reference to source. Considering
proper limits of integration from 0 to Dj ¼ VGS VTH, (10.5) can be expressed as
follows:
ð Dj " #
1 dE 1 1 1
IT ¼ q TWKB dk (10.11)
ℏ dk p EEfD =kT EEfS =kT
0 1þe 1þe
ð Dj
1 1 eðEqVDS Þ=qVT eðEÞ=qVT
IT ¼ q TWKB 1 1 dE
ℏ p 0 1 þ eðEqVDS Þ=qVT 1 þ eðEÞ=qVT
(10.12)
We obtain:
2 3
VGS VTH VDS VGS VTH
1 4q2 6 ln 1þexp VT
þ ln 1þexp
VT 7
6 7
IT ¼ VT TWKB 6 7
2 ℏp 4 VDS 5
þln 1þexp lnð2Þ
VT
(10.13)
Tunnel junctions to tunnel field-effect transistors 243
Considering built-in potential and thermal voltage, leakage current for GNR
TFET can be defined as follows [2]:
q2 j
IL ¼ VT exp BI (10.16)
pℏ VT
Combining (10.15) and (10.16), drain current for GNR TFET can be expressed
as follows:
ID ¼ IT þ IL (10.17)
m e0 eox ðVGS VTH Þ VGS VTH VDS
ID ¼ n VT TWKB ln 1 þ exp
tox VT
VGS VTH VDS
þ ln 1 þ exp þ ln 1 þ exp lnð2Þ
VT VT
q2 j
þ VT expð BI Þ (10.18)
pℏ VT
Equation (10.18) has been derived for semi-classical current transport model
for the n-type GNR TFET. Since the minimum conductivity of graphene of 4q2/
2pℏ is maintained at a charge density corresponding to (10.3), mobility in (10.18)
is estimated as 223.6 cm2/V-s. Such a small value of mobility has little or no effect
on tunneling phenomena as tunneling dominates over the scattering in TFETs [8].
The current transport model as described in [2] does not account for any leakage
current effect on drain current which may lead to an erroneous result.
to conduct charge carriers from source to drain, conductance of the channel defined
according to Landauer expression is as follows [18]:
2q2
GðEÞ ¼ MðEÞTWKB ðEÞ (10.19)
ℏ
where:
2jETM j
MðEÞ ¼ W (10.20)
pðℏvF Þ
W is the width of GNR and |ETM| is the energy of electron in transverse mode.
In this work, ETM is described in terms of gate-source voltage and is applied to
control energy window through which number of modes are calculated. The num-
ber of conducting channels at energy ETM is proportional to the width of the con-
ductor in two-dimensional and to the cross-sectional area in three-dimensional
geometry. Band structure of the conducting channel also affects the total number of
modes. Expression of M(E) in (10.20) is specific to graphene which is different
from the expression of mode usually adopted for a parabolic band structure [19]. In
ballistic transport, transmission coefficient TWKB(E) is assumed as 1. However, in
order to apply the similar concept for a tunneling transistor, transmission coeffi-
cient is assumed to be equal to tunneling probability as described by (10.6) in [20].
Considering source and drain Fermi-Dirac statistics and channel conductance
expressed in Landauer formalism, current can be calculated as follows:
ð
I ¼ dEGðEÞðfS ðEÞ fD ðEÞÞ (10.21)
where drain Fermi function fD (E) and source Fermi function fS(E) are described in
(10.9) and (10.10), respectively, and can be rewritten for |ETM| instead of E.
Combining (10.9), (10.10), (10.19) and (10.21), drain current is expressed as follows:
ð
2q2
ID ¼ dE MðEÞTWKB ðEÞðfS ðEÞ fD ðEÞÞ (10.22)
ℏ
Substituting expression of TWKB(E) from (3.6) and M(E) from (10.20), (10.22)
becomes:
ð !
2q2 2jETM j pEG2 1 1
ID ¼ dE W exp
ℏ pðℏvF Þ 4qℏvF x 1 þ eðETM EF Þ=kT 1 þ eðETM EF Þ=kT
S D
(10.23)
ð !
2q2 pEG2 2W jETM j jETM j
ID ¼ exp dE
ℏ 4qℏvF x pðℏvF Þ 1þe ð ETM EFS Þ=kT
1 þ e ETM EF Þ=kT
ð D
(10.24)
Tunnel junctions to tunnel field-effect transistors 245
4q3 W pEG2
ID ¼ exp
pðℏ2 vF Þ 4qℏvF x
"
VGS VTH
VT ðVGS VTH Þ ln 1 þ exp
VT
#
VGS VTH VDS ðpVT Þ2
ln 1 þ exp (10.25)
VT 12
10–4 10–5
Ref [2] S-Q Model
S-Q Model NEGF Simulation
NEGF Simulation S-C Model
10–5 S-C Model
Drain current, ID (μA/μm)
S-Q:
10–6
69mV/dec
I60
NEGF:
10–6 27.4mV/dec
10–7
S-C:
10–7 VDS = 0.1 V 26mV/dec
GNR (20,0) 60 mV/dec GNR (20,0)
VDS = 0.1V
W = 4.9 nm W = 4.9 nm
L = 20 nm L = 20 nm
10–8 10–8
–0.1 0 0.1 0 0.02 0.04
Gate source voltage, VGS (V) Gate source voltage, VGS (V)
Model VDD VGS Channel tox Drive current, OFF-state leakage Leakage Dynamic ION/IOFF Subthreshold I60
(V) (V) (nm) (nm) ID (mA/mm) current, IOFF power, power ½ Slope (mA/mm)
(mA/mm) VDDIOFF IDVDD (mV/dec)
(mW/mm) (mW/mm)
Analytical 0.1 0.1 L ¼ 20 1 1.51 105 1.2 1011 1.2 1012 7.55 107 1.25 106 14.15 3.8 106
model [101] W¼5
Semi-classical 0.1 0.1 L ¼ 20 1 6.2 106 5.05 108 5.05 109 3.1 107 122 26 4.2 106
analytical W ¼ 4.9
model
Semi-quantum 0.1 0.1 L ¼ 20 1 1.6 105 9.8 107 9.8 108 8 107 16.3 69 Does not
analytical W ¼ 4.9 provide
model
NEGF-based 0.1 0.1 L ¼ 20 1 5.95 106 5.145 108 5.145 109 2.9 107 116 27.4 4.4 106
simulation W ¼ 4.9
248 Advanced technologies for next generation integrated circuits
comparison of these three current transport models. Note that the drain current has been
normalized along the GNR width.
Though the semi-classical analytical model and numerical simulation for the
current transport matches closely, the semi-quantum analytical model differs from
both. Before further studies into GNR TFET transfer characteristics; it is to be
mentioned that the tunneling probability used in calculating the drain current in
semi-quantum model is taken from the semi-classical model which is semi-classical
in nature. The transmission coefficient (TWKB) of the Landauer’s conductance
expression has been considered as the equivalent tunneling probability (TWKB) from
semi-classical model following (10.6). A more rigorous calculation considering
source and drain contacts and their corresponding self-energy, and Fermi–Dirac
distribution between the source and drain and effect from the gate is required to
describe “TWKB” properly. Moreover, a self-consistent calculation of the number of
“modes” is essential to describe the semi-quantum analytical model completely
since the number of modes in on- and off-states differs based on the bias conditions.
For these reasons, the semi-quantum analytical model differs in describing the
current transport in GNR TFET when compared with semi-classical analytical
model and NEGF simulation.
where ITH is the current at threshold voltage (VTH) and IOFF is the off current
determined at VGS ¼ 0 V. In [23], VTH is considered as the half of the supply
voltage (VTH ¼ VDD/2) which returns ITH as ID at VDD/2. Following this notation
and after extracting the corresponding value of VDD/2 as 0.05 V, SS for all three
models is also evaluated from Figure 10.2(b) using (10.26). Here, SS is calculated
to be 28 mV/decade for the semi-classical model and 27 mV/decade for the NEGF
simulation. Both of these values closely match with previously mentioned values of
SS. SS of 68 mV/decade is obtained from this method for semi-quantum model.
Tunnel junctions to tunnel field-effect transistors 249
Figure 10.3 shows the output characteristics (ID–VDS) of n-type a-GNR TFET
using the three current transport models studied in this work for different VGS.
250 Advanced technologies for next generation integrated circuits
×10–5
4
The semi-classical analytical model shows good agreement with the results
obtained from the numerical simulation, however, the semi-quantum model dif-
fers largely.
For a fixed VGS, a constant amount of carriers tunnel through the source-
channel tunnel junction. For VDS ¼ 0 V and VGS > 0 V, a small tunneling window is
opened at the source-channel tunnel junction which works as the origin of leakage
current. From (10.7), maximum electric field at the source-channel tunnel junction
has linear dependence on VDS which is used to determine TWKB. It is obvious from
(10.7), for a fixed VGS, junction maximum electric field will solely depend on VDS.
As a result, tunneling probability depends exponentially on VDS. For a fixed VGS
with varying VDS, semi-quantum model is now strongly governed by the difference
in source-drain Fermi level. Therefore, any change in drain current calculated by
semi-quantum model is also strongly controlled by VDS as opposed to VGS depen-
dence of semi-classical and NEGF simulated current transport models. For this
reason a large deviation of semi-quantum model is observed in Figure 10.3 com-
pared to semi-classical analytical model and numerical simulation. Compared to
output characteristics of conventional MOSFETs where VDS governs channel
electric field and affects pinch-off and velocity saturation, output characteristics in
TFET not only depends on VGS but also on VDS. Especially in reduced dimensional
materials as in graphene such behavior is often observed. Current transport equa-
tions of (10.18) and (10.25) derived from semi-classical and semi-quantum con-
siderations, respectively, can be used also for p-type GNR TFET n-i-p structure
shown in Figure 10.1(a) with opposite voltage polarities.
Tunnel junctions to tunnel field-effect transistors 251
Figure 10.4(a) shows the schematic of a complementary GNR TFET inverter for
operation at different supply voltages and is similar to CMOS inverter in design and
operation. Characteristics of GNR TFET inverter is plotted from all three current
transport models. At input logic level “1” (either 0.1 V or 0.2 V), n-type GNR
TFET turns ON, p-type GNR TFET is OFF and output gives logic “0”. Similarly,
when input is at logic “0” (0 V), p-type GNR TFET turns ON and n-type GNR
TFET is OFF, output is at logic “1” (either 0.1 V or 0.2 V for the case in Figure 10.4
(b)). Figure 10.4(b) shows the plot of voltage transfer characteristics (VTC) of the
complementary GNR TFET-based inverter of Figure 10.4(a) for GNR for (20,0)
chirality and VDD ¼ 0.1 V and 0.2 V supply voltages. Following the transfer char-
acteristics obtained for all three current transport models, VTC of GNR TFET inverter
also shows good agreement between semi-classical analytical model and NEGF
simulation. However, semi-quantum analytical model differs from both of these
models in this case as well. A decrease in the logic “1” is observed due to inherent
leakage current at off-state for both transistors. However, sharp transition between on
to off-state is observed at reduced supply voltage. The VTC shown in Figure 10.4(b)
confirms the reliable use of semi-classical analytical model for digital circuit simu-
lation with a good agreement with numerical simulation.
0.2
VDD S-Q Model
NEGF Sim
S-C Model
0.15
p-type
GNR TFET GNR (20,0)
Length = 20 nm
VOUT (V)
VSS
0
0 0.1 0.2
VIN (V)
(a) (b)
Figure 10.4 (a) A complementary GNR TFET inverter circuit and (b) voltage
transfer characteristics of GNR TFET inverter for different
supply voltages
254 Advanced technologies for next generation integrated circuits
10.10 Conclusion
The semi-classical analytical model closely agrees with numerical simulation
whereas significant difference between semi-quantum model and NEGF simula-
tion is observed [28]. Performance of n-type GNR TFET is also studied for GNR
width variation. The semi-classical analytical current transport model of n-type
GNR TFET can be applied to p-type GNR TFETs (n-i-p structure) with opposite
voltage polarities. Promise of GNR TFET for digital logic application as a TFET
inverter is studied by all three current transport models. Characteristics sharp
transition from “on” to “off” condition is observed for lower supply voltage. By
comparing the semi-classical analytical model with the numerical simulation, it is
evident that the semi-classical analytical model derived can predict near similar
performance of GNR TFET for different figure of merits. Readers are suggested to
read [15].
However, semi-quantum analytical model differs from simulation due to
inherent limitation in calculation and hence it is not yet reliable in its current form.
Therefore, we conclude the semi-classical analytical current transport model as a
powerful tool for circuit simulation for digital IC design.
References
[1] X. Wang, Y. Ouyang, X. Li, H. Wang, J. Guo, and H. Dai, “Room-
temperature all-semiconducting sub-10-nm graphene nanoribbon field-effect
transistors,” Phys. Rev. Lett., vol. 100, pp. 206803-01–206803-04, 2008.
[2] Q. Zhang, T. Fang, H. Xing, A. Seabaugh, and D. Jena, “Graphene nano-
ribbon tunnel transistors,” IEEE Elect. Dev. Lett., vol. 29, pp. 1344–46, 2008.
[3] P. Zhao, J. Chauhan, and J. Guo, “Computational study of tunneling transistor
based on graphene nanoribbon,” Nano Letters, vol. 9, pp. 684–88, 2009.
[4] G. Fiori, A. Betti, S. Bruzzone, and G. Iannaccone, “Lateral graphene–
hBCN heterostructures as a platform for fully two-dimensional transistors,”
ACS Nano, vol. 6, pp. 2642–48, 2012.
[5] R. K. Ghosh and S. Mahapatra, “Proposal for graphene boron nitride
heterobilayer-based tunnel FET,” IEEE Trans. Nanotech., vol. 12, pp. 665–67,
2013.
[6] G. Fiori and G. Iannaccone, “Ultralow-voltage bilayer graphene tunnel
FET,” IEEE Elect. Dev. Lett., vol. 30, pp. 1096–98, 2009.
[7] Y. Yoon and S. Salahuddin, “Dissipative transport in rough edge graphene
nanoribbon tunnel transistors,” Appl. Phys. Lett., vol. 101, p. 263501, 2012.
[8] J. Knoch and J. Appenzeller, “Tunneling phenomena in carbon nanotube
field-effect transistors,” Physica Status Solidi (A), vol. 205, pp. 679–94,
2008.
[9] K. Boucart and A. M. Ionescu, “A new definition of threshold voltage in
Tunnel FETs,” Solid State Elect., vol. 52, pp. 1318–23, 2008.
Tunnel junctions to tunnel field-effect transistors 255
11.1 Introduction
Atomically thin two-dimensional graphene has emerged as a potential candidate for
the next generation electronics due to its unique electronic properties. However,
single-layer graphene is a zero-bandgap semiconductor. Scientifically it is well
known that bandgap engineering is required for obtaining a bandgap in graphene.
Undoubtedly, this makes the fabrication process complicated. In the absence of a
bandgap, graphene field-effect transistor suffers from poor on/off current ratio with
high off-state leakage current. Following the ITRS requirement [1] of energy-
efficient circuit design, a minimum on/off current ratio of 104 is required for a
supply voltage below 0.7 V for digital applications. Performance of the existing
graphene-based MOS-type transistors is still lagging behind unless graphene is
lithographically patterned to GNR or chemically synthesized.
In order to resolve the issue of on/off current ratio, vertical heterostructure
consisting of multilayer stacks of graphene and other atomically thin two-dimensional
materials such as boron nitride and the transition metal dichalcogenides have been
proposed for different transistor structures [2–11]. Basically, interlayer tunneling
technique is employed in these types of transistors. Majority of these transistors
contain two graphene conducting layers separated by a thin tunneling barrier. These
transistors are commonly known as interlayer tunnel field-effect transistors (iTFETs).
Schematic of a conventional n-channel MOSFET, a p-i-n band-to-band tunnel field-
effect transistor (TFET) and an iTFET are shown in Figure 11.1(a), (b), and (c),
respectively, for distinction. High on/off current ratio, sharp resonant tunneling
characteristic, and suitability for flexible and transparent electronics are some of the
reported key features of this graphene iTFET. However, these transistors lag the
potential for digital integrated circuit design considering the requirements of
steep subthreshold slope and high drive current. Due to fundamental physical
1
Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge,
LA, USA
258 Advanced technologies for next generation integrated circuits
Gate
Gate
Source Drain Source Drain
Oxide Oxide
n-type Si ID n-type Si p n
ID
p-type Si intrinsic
Source GT +
Drain GB Top gate – VG
Ohmic hBN Ohmic
Top graphene –
Top graphene
contact hBN e Tunneling contact
hBN Tunnel barrier Bottom graphene
ID hBN
Bottom graphene drain
ID Bottom gate
hBN Substrate 50nm
SiO2 SiO2
Si Si
L = 1 µm
GND W = 50 nm
(c) Bottom gate (d)
+ –V
DS
limit, subthreshold slope of such iTFET cannot go below the thermionic limit of
60 mV/decade. Moreover, high supply voltage (>2 V) is also required for
operation in some of the reported iTFETs. Studies of some of these devices have
been carried out at cryogenic temperatures with poor performance at room tem-
perature. Therefore, an improved current transport mechanism in a novel device
structure is essential for making such iTFETs competitive for next generation
more than the Moore’s era.
In iTFET, source and drain contacts are placed at the two opposite conducting
layers as seen in Figure 11.1(c) contrary to the contacts in conventional four-
terminal MOSFET shown in Figure 11.1(a) and TFET, as shown in Figure 11.1(b),
In this way, a bias between drain and source (VDS) controls the vertical interlayer
tunneling of carriers between the two conducting materials separated by a tunneling
barrier. However, VDS overshadows the actual control of channel electrostatic
potential by the gate voltage [7]. For this reason, linear resistive behavior is
obtained as opposed to the current saturation at different gate biases of output
characteristics [8]. This impedes iTFETs’ prospects in digital logic circuits. Apart
from this, observed negative differential resistance (NDR) also undermines the
Low-dimension materials-based interlayer tunnel FETs 259
channel Dirac point and no intermediate energy states exist due to roughness or
defects. Gate voltage (VG) is defined as the difference between the bottom (VGB)
and top gate voltages (VGT). To turn-on the transistor, VG (VG ¼ VGB VGT) is
applied between GT and GB. VDS is applied between source and drain located at GB.
Device off-state is defined for |VG| ¼ 0 V, |VDS| ¼ 0.1 V and on-state for |VG| 6¼ 0
V, |VDS| ¼ 0.1 V.
For low power dissipation, the supply voltage of any switching transistor needs
to be compliable with one of the ITRS requirements. Existing silicon and III-V
material-based TFETs operate at sub-0.5 V supply voltage for which it is essential
for the switching transistor to operate at equal or low supply voltage. Moreover, it
is found that the graphene-based transistors can be operated at low supply voltages
for which the assumption of 0.1 V operation of graphene JTET is in accordance
with the existing TFET performance and ITRS requirement.
Figure 11.2(a) shows the off-state of graphene JTET. EFS , EFC and EFD are the
source, channel, and drain Fermi levels, respectively. As VG is applied, interlayer
tunneling of carrier occurs between the top and bottom graphene layers. The carrier
concentration (N) due to tunneling shifts EFC from the Dirac point of the channel
graphene layer by an amount of DEF, as shown in Figure 11.2(b) [19].
This shift in Fermi level results in the change of barrier height between EFS and
D
EF which controls the current transport between source and drain due to VDS. In this
way, drain current becomes a function of vertical tunneling of carriers between the
top and bottom graphene layers. It should be noted that the bottom graphene layer
is also the channel graphene layer.
EFD
EFS EFC VDS
(a)
EFD
EFC
EFS ∆EF
Figure 11.2 (a) Energy band diagram of graphene JTET in the off-state for
VG ¼ 0 V and VDS ¼ 0.1 V and (b) on-state for VG ¼ 0.1 V and
VDS ¼ 0.1 V
262 Advanced technologies for next generation integrated circuits
Based on the experimental study in [4], it is found that a positive gate bias
shifts the Fermi level above the Dirac point whereas a negative gate bias shifts the
Fermi level below the Dirac point. Therefore, VG > 0 provides DEF < 0 and VG < 0
provides DEF > 0. The channel barrier height is controlled by the vertical interlayer
tunneling between two graphene layers. It is important to note that in conventional
iTFET, the interlayer tunneling bias results in the tunnel drain current whereas in
graphene JTET, the interlayer tunneling bias changes the channel barrier height
which regulates the source-drain ballistic transport. Conventional iTFET does not
discuss any source-drain ballistic transport mechanism.
As the Dirac point at the top and bottom graphene layers is misaligned, an
interlayer tunneling carrier crosses the tunneling barrier. Electrons having the
energy halfway between the Dirac points contribute toward this flow [4]. A change
in such tunneling of carriers due to gate voltage is also confirmed by the phe-
nomena of wave function extension of one graphene layer to the other and a cor-
responding overlap at the bottom graphene layer. For both positive and negative
gate voltages, the wave function extension is observed [17]. In this way, the out-of-
plane momentum is conserved for a longer coherent length for tunneling, pre-
ferably in a nanometer range [8]. We assume that the source and drain wave
functions do not result in any interference with the wave function extended from
the top graphene layer to the bottom graphene layer. The vertical interlayer tun-
neling, therefore, only contributes toward the barrier control of the channel elec-
trostatic potential.
graphene conduction band to hBN conduction band for electrons, and m* is the
effective mass of electron in the tunneling barrier material.
The separation between the graphene Dirac point and the top of the valence
band of hBN (D) is 1.5 eV whereas this value is >4 eV in case of hBN conduction
band [19]. Following the work of Britnell et al. [2], we have chosen D as 1.5 eV.
This yields an effective tunneling mass of holes, m* ¼ 0.5mo (mo is the free elec-
tron mass) which is also the effective mass for holes in hBN.
It has been observed that a barrier separating two graphene layers where Fermi
surface in one side is electron like and is hole like on the other side demonstrates
that electrons incident normally at one side continue to propagate as holes with
100% efficiency at the other side [20]. For this reason, the choice of D as 1.5 eV for
hole conduction remains consistent. For relativistic carriers, a perfect tunneling
probability of 1 can be obtained. However, for nonrelativistic electrons, this is not
the case for which the tunneling probability is always less than 1. With a negligible
inter-valley scatterings and very low lattice mismatch, a potential barrier shows no
reflections for the electron’s incident normal to the potential barrier [21]. In gra-
phene JTET, it is assumed that electrons incident normal to the hBN barrier where
graphene and hBN has a lattice mismatch of only 1.7%.
Similarly, the carriers tunneling from the bottom to top graphene layers can
also be expressed as follows:
ð Dj
N2 ¼ DðEÞTWKB ðEÞfB ðEÞdE (11.3)
0
Net carriers tunneling from top to bottom graphene layers can be written as
follows:
ð Dj ð Dj
N ¼ N1 N2 ¼ DðEÞTWKB ðEÞfT ðEÞdE DðEÞTWKB ðEÞfB ðEÞdE
0 0
(11.4)
ð Dj
N¼ DðEÞTWKB ðEÞðfT ðEÞ fB ðEÞdE (11.5)
0
Here, D(E) is the density of states of graphene, fT(E) is Fermi function for the
top graphene layer, fB(E) is Fermi function for the bottom graphene layer, TWKB(E)
264 Advanced technologies for next generation integrated circuits
gs gv E
DðEÞ ¼ (11.6)
2pðℏvF Þ2
where E is the energy of electron tunneling. For the proposed current transport
model of graphene JTET, energy range E is limited between 0 and Dj; gs and gv are
spin and valley degeneracy, respectively. For graphene, gs ¼ 2 and gv ¼ 2 [21].
Fermi functions in the top and bottom graphene layers are defined as follows:
1
f T ðE Þ ¼ (11.7)
EEfT =kB T
1þ e
1
f B ðE Þ ¼ (11.8)
EEfB =kB T
1þ e
In (11.7) and (11.8), EfT and EfB are the positions of the Fermi levels at the top
and bottom graphene layers, respectively. E is the energy of the electron during
tunneling. Fermi level in the top graphene layer is at EfT ¼ qVG and the Fermi level
in the bottom graphene layer is at EfB ¼ 0. Combining (11.5)–(11.8),
ð Dj !
gs gv E 1 1
N¼ T
2 WKB
ðEÞ dE
0 2pðℏvF Þ 1 þ e EEf =kB T 1 þ e EEf =kB T
T B
(11.9)
Replacing the values of EfT and EfB by qVG and 0, (11.9) can be expressed as
follows:
ð Dj
2E 1 1
N¼ TWKB ðEÞ dE (11.10)
0 pðℏvF Þ2 1 þ eðEVG Þ=kT 1 þ eðEÞ=kT
The energy window for tunneling (Dj) from the top to bottom graphene layers
is assumed as Dj ¼ EfT EfB ¼ qVG 0 ¼ qVG. Now integrating (11.10) from
E ¼ 0 to E ¼ Dj ¼ qVG, closed form of Fermi-Dirac integration becomes:
gs gv VG 2 ðpkB TÞ2
N¼ T
2 WKB
ðEÞ ðVG ÞkB T ln ½1 þ expðVG =kB T Þ
2pðℏvF Þ 12 12
!
2
ðkB T Þ Poly logð2; expðVG =kB T ÞÞ
(11.11)
Low-dimension materials-based interlayer tunnel FETs 265
Now for any qVG >> kBT, it is found that the first few terms dominate over the
later parts of (11.11) for which the higher energy terms in (11.11) can be simplified
as follows:
VG 2 ðpkB TÞ2
ðVG ÞkB T ln½1þexpðVG =kB T Þ>> ðkB TÞ2 Polylogð2;expðVG =kB T ÞÞ
2 12
Therefore, the closed-form solution of (11.11) can be expressed as follows:
2 VG 2
N¼ 2
TWKB ðEÞð ðVG ÞkB T ln ½1 þ expðVG =kB T Þ (11.12)
pðℏvF Þ 12
Equation (11.12) expresses the doping density which is the net number of
carriers tunneling from top to bottom graphene layers due to applied voltage, VG as
shown in Figure 11.3(a). Following the work of Georgiou et al. [4], a positive bias
generates electron tunneling whereas the negative bias generates hole tunneling.
The electron tunneling is shown in blue curve and hole tunneling is shown in red
curve in Figure 11.3(a) for positive and negative biases, respectively. The induced
doping density through interlayer tunneling (N), calculated using (11.12), has a
square root dependence on Fermi level of the bottom graphene layer which is
expressed as follows [4]:
pffiffiffiffiffiffiffiffiffiffi
DEF ¼ ℏuF pjN j (11.13)
The sign of the Fermi level shift (positive or negative) is determined from the
polarity of the gate voltage [20]. A positive bias shifts the Fermi level upward
which is shown in Figure 11.2(b). Figure 11.3(b) shows the change in the amount of
shift in Fermi level (DEF) due to induced carrier concentration (N) at the bottom
graphene layer. The red and blue lines in Figure 11.3(b) represent the change of
Fermi level based on the polarity of VG.
Here, G(E) is channel conductance; fS(E) and fD(E) are source and drain Fermi
functions, respectively, which can be expressed similar to (11.7) and (11.8). Based
on Landauer expression, conductance (G(E)) can be expressed as follows [23]:
×1011
2 0.05
TT = 0.2378 ∆ = 1.5eV
∆ = 1.5eV m* = 0.5m0
m* = 0.5m0
1
Hole
tunneling
∆EF [eV]
N [/cm2]
0 0
–1 Electron
tunneling
–2 –0.05
–0.1 0 0.1 –2 0 2
VG [V] N [/cm2]
(a) (b) ×1011
Step 1:
VG Applied between top and
bottom graphene layer
Step 2:
Induced charge density estimation:
2 VG2
N= TT(E)( –(VG)kT(In[1+exp(VG/kT)]))
2 12
(ħυF)
Step 3:
Change in channel Fermi level estimation:
∆EF = ±ħυF√(|N|)
Step 4:
Drain current estimation:
2q2VT 2∆EF
I= [W (–In (1+exp(∆EF/VT))+(1+
ħ (ħυF)
exp((∆EF –VDS)/VT))+In2 –In(1+exp(–VDS/VT)))
(c)
Figure 11.3 (a) Carrier concentration (N) versus VG and (b) change of Fermi
level (DEF) with N and (c) flow chart showing the operation of
graphene JTET
Low-dimension materials-based interlayer tunnel FETs 267
density through tunneling (N) of 1.76 1011/cm2 at 0.1 V gate bias is considered
for the mobility extraction. Graphene band structure is symmetric around the
Dirac point for which nearly identical value applies for both electron and hole
mobility [21].
×10–4
1 This work
TT = 0.2378
∆ = 1.5eV 10–5
m* = 0.5m0
ID [A/µm2]
Ref [2]
ID [A/µm2]
|VDS| = 0.025V
0
Ref [6]
10–10
0.025V step
Ref [8]
–1 Ref [7]
10–15
–0.1 0 0.1 0 0.05 0.1
Figure 11.4 Transfer characteristics for the graphene JTET: (a) ID–VG curve for
different VDS in linear scale with 0.025 V step and (b) comparison of
the transfer characteristics of graphene JTET with earlier similar
type of iTFETs
Low-dimension materials-based interlayer tunnel FETs 269
It is observed from both Figure 11.4(b) and Table 11.1 that graphene JTET
performs better than other similar iTFETs. Few explanations are required at this
stage for describing the high performance of graphene JTET. We have considered
three layers of hBN equivalent to 1.02 nm in thickness as the tunneling barrier,
whereas the other listed iTFETs in Figure 11.4(b) and Table 11.1 consider a thicker
tunneling barrier. Such a small barrier thickness not only induces a higher charge
density at the bottom graphene layer but also energy momentum in vertical direc-
tion remains conserved. This is consistent with having a relatively smaller coher-
ence length of tunneling which suppresses the NDR effect [6]. ITRS requires a
minimum value of on/off current ratio (ION/IOFF) as 104 at VDD < 0.7 V for the next-
generation devices for digital applications [7]. From Table 11.1, graphene JTET
provides the ION/IOFF of 2.45x104 at VDD ¼ 0.1 V which meets the ITRS require-
ment. Although graphene JTET provides low ION/IOFF compared to some other
iTFET, it is still suitable for digital circuit design. It is to be mentioned that
Georgiou et al. [4] obtained a current ratio of 106 at VDD ¼ 2 V (>VDD of graphene
JTET) range for graphene-WS2-graphene iTFET, however, subthreshold slope is
larger than that obtained for graphene JTET at 0.1 V supply voltage. Moreover,
WS2 is a wide bandgap semiconductor compare to hBN which is a wide bandgap
insulator. The electronic properties of graphene-WS2 superlattice are different from
the graphene-hBN superlattice for which ION/IOFF of graphene JTET differs from
the ION/IOFF in [4]. Using the method of average subthreshold slope, SS can be
determined as follows [25,26]:
dVGS
SS ¼ (11.20)
dðlog10 ID Þ
where ID is the drain current and VG is the gate bias. For a decade change in drain
current in the subthreshold region, required gate bias is calculated which gives the
subthreshold slope. Figure 11.5 shows the extraction of subthreshold slope. It is to
be mentioned that Figure 11.5 is plotted in log scale compared to the linear scale in
Figure 11.4(a). The values of SS mentioned in Table 11.1 are also calculated using
Figure 11.5 following the method described in the work of Appenzeller et al. [26].
270 Advanced technologies for next generation integrated circuits
10–4
–0.025V step
VDS = –0.025V
ID [A/µm2] 10–6
10–5
r2
10–6 ve 5
ID [A/µm2]
de o ge 2
ca r a
/de ave -
10–8 mV s or sub
10–7 50 cade cade ope
de /de ld sl
mV esho
thr
10–8
0 0.01 0.02 0.03 0.04 0.05
VG [V]
10–10
0 0.05 0.1
VG [V]
Figure 11.5 Subthreshold slope extraction from ID–VG curve of graphene JTET.
Inset shows the change in VG for estimating the average subthreshold
slope over three decades of drain current [25]. Note: Drain current
is plotted in the log scale compared to the linear scale, as shown in
Figure 11.4(a)
×104
monolayer 3 40
3 layers
10–5
4 layers
5 layers
SS (mV/decade)
ID [A/µm2]
ION/IOFF
6 layers 2 20
VG = 0.1V
VDS = –0.1V
10–10 VDS =–0.1V
1 0
0 0.05 0.1 2 4 6
(a) VG [V] (b) Number of hBN layers
Figure 11.6 (a) Change in the transfer characteristics of graphene JTET for
multiple hBN layers as tunneling barrier and (b) change in on/off
current ratio (ION/IOFF) and SS with the number of hBN layers
1 1
VG =0.075V VG = –0.075V
|ID| [A/µm2]
|ID| [A/µm2]
VG = 0.05V
VG = –0.05V
0.5 0.5
VG = 0.025V VG = –0.025V
V = 0V VG = 0V
0 G 0
–0.1 –0.05 0 0 0.05 0.1
(a) VDS [V] (b) VDS [V]
Figure 11.7 Output characteristics for graphene JTET: (a) p-type behavior
obtained for VG > 0, VDS < 0 and (b) n-type behavior obtained for
VG < 0, VDS > 0
VG = 0.7V VG = –0.7V
0.8 0.8
|ID| [A/µm2]
|ID| [A/µm2]
0.4 0.4
VG = 0.3V VG = –0.3V
0.2 0.2
0 0
–0.5 –0.4 –0.3 –0.2 –0.1 0 0 0.1 0.2 0.3 0.4 0.5
(a) VDS [V] (b) VDS [V]
Figure 11.8 Output characteristics of graphene JTET with increasing VDS for
varying VG: (a) p-type graphene JTET and (b) n-type graphene JTET
274 Advanced technologies for next generation integrated circuits
at higher VDS, drain current saturation is observed. For all three conditions of
VDS < VG, VDS ¼ VG and VDS > VG, graphene JTET provides drain current
saturation. This implies that the magnitude of the Coulomb drag originating at
higher drain and gate bias provides not only a precise interlayer tunneling but also
preserves superior gate control over the channel. For this reason, smooth output
characteristics are obtained.
The inverter is the basic building block of a digital integrated circuit and its per-
formance reflects the type of transistors used as switches. Complementary inverter
using vertical heterostructure transistors as switches can be used similar to a CMOS
inverter. Figure 11.9(a) and (b) shows the symbols of p-type graphene JTET and
n-type graphene JTET, respectively. Since graphene JTET has similarity with a
ballistic nanoscale MOSFET with respect to source-drain ballistic transport, such
symbols are partially designed based on the conventional depletion type MOSFET
symbols. However, since the channel barrier control is carried out through the
vertical interlayer tunneling, we have adopted the conventional sign of tunneling
between top and bottom gate electrodes. Therefore, the symbols drawn in
Figure 11.9(a) and (b) combine both the concept of vertical interlayer tunneling
between gates at the top and bottom graphene layers and source-drain ballistic
transport. Figure 11.9(c) shows the schematic of a complementary graphene JTET
vertical inverter.
The gate bias (VG) is defined as the difference between the top (VGT) and
bottom gate voltages (VGB) of the transistor (VG ¼ VGT VGB). The bottom gate of
VDD
D
p-type JTET
Top
Source Source gate Bottom
gate
S
Top Bottom
Drain Drain gate gate
n-type JTET p-type JTET S
n-type JTET
Figure 11.9 (a) Symbol for p-type JTET, (b) n-type JTET, and (c) schematic of
complementary graphene JTET-based vertical logic inverter
Low-dimension materials-based interlayer tunnel FETs 275
p-type graphene JTET is connected with the top gate of the n-type graphene JTET
for which it is termed as common gate contact. An input voltage (VIN) applied at the
common gate contact will generate two opposite type of shifts in Fermi levels in
each of these transistors independently. For example, a positive bias at the common
gate will generate a positive gate voltage, VG (VG ¼ VIN – 0 ¼ VIN) resulting
in n-type characteristics in bottom JTET whereas a negative gate voltage, VG
(VG ¼ 0 VIN ¼ VIN) resulting in p-type characteristics in top JTET. Drain of the
n-type graphene JTET is connected to the source of p-type graphene JTET. Drain
of p-type graphene JTET is connected to the supply voltage (VDD) and source of the
n-type graphene JTET is grounded (0 V). Being vertically connected, a single gate
contact is necessary for graphene JTET vertical inverter. In this way, no additional
interconnect is required to connect the two gates of the two complementary tran-
sistors. Figure 11.10(a) shows the voltage transfer characteristics (VTC) of the
complementary graphene JTET inverter operating at different supply voltages. The
inverter gain (AV) of 4.35 is obtained for VDD ¼ 0.5 V whereas the gain in 3.15 for
VDD ¼ 0.1 V. This reflects the capability of graphene JTET inverter to operate at
reduced supply voltage with higher gain.
Compared to a conventional CMOS inverter where gain plummets as supply
voltage goes below 0.5 V, graphene JTET vertical inverter can retain its gain at low
supply voltages. It is also noted from the transfer characteristics that sharp transi-
tion from off- to on-state is obtained at all supply voltages. Figure 11.10(b) shows
the extraction of noise margin for VDD ¼ 0.1 V for the graphene JTET inverter. We
have calculated the low noise margin, NML as 0.021 V and high noise margin, NMH
as 0.022 V. Both of these values are more than 20% of the original signal which
substantiates strong noise immunity.
0.5 0.1
VDD =0.5V L=1 µm
Av=4.35 W=50 nm
Slope= –1
0.4 0.08 VOH
VDD =0.3V NML=VIL –VOL
Av =2.7
NMH=VOH –VIH
0.3 0.06
VOUT
VOUT
11.6 Conclusion
A new type of graphene-switching transistor termed as “junctionless tunnel effect
transistor (JTET)” based on graphene-hBN-graphene vertical heterostructure and
interlayer tunneling is proposed and an analytical current transport model has been
developed. The drain current in graphene JTET flows between the source and drain
of bottom graphene layer. The current in the channel is regulated by the shift in
channel Fermi level which depends on the net vertical tunneling of carriers from top
graphene to bottom graphene layers through hBN. Performance of graphene JTET is
evaluated for different numbers of hBN layers. A comparison between graphene
JTET and ITRS projected 2020 nMOSFET is also provided apart from graphene
JTET performance comparison with similar iTFETs. Current saturation is observed
in graphene JTET output characteristic for both p- and n-type operations, which
makes graphene JTET suitable for digital circuit design. Graphene JTET is also
capable of suppressing NDR effect, and shows steep subthreshold slope with high
on/off current ratio and normal operation at room temperature. A complementary
vertical inverter is presented similar to a CMOS inverter and analyzed for its per-
formance. Graphene JTET vertical inverter gives inverter gain higher than unity at
the low supply voltage and both low and high noise margins. It is concluded that
with an average 25 mV/decade subthreshold slope at 0.1 V supply voltage and a
current ratio of ~104, graphene interlayer junctionless tunnel effect transistor meets
the ITRS requirement of device scaling for energy-efficient circuit design.
References
[1] International Technology Roadmap for Semiconductor. Available at: www.
itrs.net, 2013.
[2] L. Britnell, R. V. Gorbachev, R. Jalil et al., “Field-effect tunneling transistor
based on vertical graphene heterostructures,” Science, vol. 335, pp. 947–50,
2012.
[3] A. K. Geim and I. V. Grigorieva, “Van der Waals heterostructures,” Nature,
vol. 499, pp. 419–25, 2013.
[4] T. Georgiou, R. Jalil, B. D. Belle et al., “Vertical field-effect transistor based
on graphene-WS2 heterostructures for flexible and transparent electronics,”
Nat Nano, vol. 8, pp. 100–03, 2013.
[5] P. Zhao, R. M. Feenstra, G. Gong, and D. Jena, “SymFET: a proposed
symmetric graphene tunneling field-effect transistor,” IEEE Trans. Elect.
Dev., vol. 60, pp. 951–57, 2013.
[6] T. Roy, Z. R. Hesabi, C. A. Joiner, A. Fujimoto, and E. M. Vogel, “Barrier
engineering for double layer CVD graphene tunnel FETs,” Microelec. Eng.,
vol. 109, pp. 117–19, 2013.
[7] G. Fiori, S. Bruzzone, and G. Iannaccone, “Very large current modulation in
vertical heterostructure graphene/hBN transistors,” IEEE Trans. Elect. Dev.,
vol. 60, pp. 268–73, 2013.
Low-dimension materials-based interlayer tunnel FETs 277
12.1 Introduction
Scaling of planar metal-oxide semiconductor field-effect transistor (MOSFET) is
predicted to face its near end as the Moore’s law continues, down to the technology
node of 7 nm and below [1]. In addition to shrinking MOSFET channel length to
sub-10 nm for high transistor density, vertical integration of MOSFETs based on
the stacking of two-dimensional layered materials has recently been explored
[2–16]. Novel two-dimensional material systems such as graphene and non-
graphene have largely made this feasible [17]. These transistors hold the promise
for vertical integration, providing an alternative approach for maintaining the
lifeline of Moore’s law and beyond. Compared to conventional inversion mode of
operation, field effect tunneling-based current transport has been studied in these
vertical FETs. Majority of these vertical FETs consider two graphene layers sepa-
rated by a thin tunnel barrier, mostly hex boron nitride (hBN).
Considering Bose condensation of Fermions (electron–hole pairs) between two
graphene layers, BiSFET proposed by Banerjee et al. [5] was one of the theoretical
graphene-based interlayer FETs. The theoretical model of an interlayer tunneling
transistor, SymFET, proposed by Zhao et al. [7] was another graphene/hBN het-
erostructure. With an on/off current ratio of ~100, SymFET provides a large reso-
nant current peak. However, the model in [7] does not provide any insight on
SymFET subthreshold slope. Operating frequency of SymFET was also not
reported in [7]. Recently, Fiori et al. [9] have studied very large current modulation
in graphene/hBN vertical heterostructure from the multiscale simulation approach.
A large subthreshold slope of 385 mV/decade, with an on/off current ratio of ~15 is
reported. The intrinsic cut-off frequency also falls below 1 GHz.
Ghobadi and Pourfath [10] studied a vertical heterostructure similar to [9]
considering both graphene and quantum-confined graphene nanoribbon (GNR)
separated by hBN with a focus on high-frequency operation. However, low on/off
1
Department of Electrical and Computer Engineering, Louisiana State University, Baton Rouge,
LA, USA
280 Advanced technologies for next generation integrated circuits
current ratio (~3–10) and high subthreshold slope (>1,000 mV/decade) were
obtained for ~100 GHz cutoff frequency. Compared to graphene, atomically
thin molybdenum disulfide (MoS2)-based planer FET has already shown promise
[18–21]. However, unlike graphene, the study of vertical FET based on interlayer
tunneling between two MoS2 layers separated by a thin tunnel barrier has remained
largely unexplored. Moreover, the current transport mechanism proposed for gra-
phene JTET requires additional understanding for the case of JTET with large
band-gap material. Graphene is a zero band semiconductor. Therefore, the perfor-
mance of JTET other than graphene as top and bottom electrode separated by
tunneling barrier structure needs further description.
In this chapter, the operating principle of JTET discussed in Chapter 11 has
been extended for the study of MoS2 JTET considering MoS2/hBN/MoS2 for
reduced subthreshold slope operation and sustainable leakage. The interlayer
tunneling-based barrier control mechanism as proposed for graphene JTET in
Chapter 11 and [16] is used for the current transport study of MoS2 JTET through
self-consistent simulation method [22]. Similar to graphene JTET, multilayer hBN
is considered as the gate dielectric for MoS2 JTET. The performances of MoS2
JTET are compared with the earlier reported graphene-based iTFET reported in [9]
and [10].
Figure 12.1 shows the schematic of MoS2 JTET where the channel is a monolayer
MoS2 of 10 nm length and 5 nm width [21]. Compared to the graphene JTET
device structure discussed in Chapter 11, MoS2 JTET considers as single-layer
MoS2 as both the top and bottom electrodes. Following the work in [3] and [16],
gate dielectric comprises of 20 layers of hBN (~7 nm). Monolayer hBN is con-
sidered as the vertical tunneling barrier between two MoS2 layers. Compared to
conventional interlayer tunneling field-effect transistor (iTFET), MoS2 JTET con-
siders source and drain ohmic contacts on the bottom MoS2 layer.
Recently, it has been experimentally observed that chemical vapor deposition-
based direct growth of monolayer MoS2 on hBN provides smaller lattice strain, low
doping level, and clean and sharp interface [23]. Moreover, monolayer MoS2 is
stable over monolayer hexagonal BN (hBN) substrate for an inter-planer distance
of 4.89 Å [24]. Based on the density functional theory (DFT), an energy bandgap of
1.83 eV is observed between the MoS2 and hBN [24]. This is little more than the
energy bandgap (1.5 eV) between graphene and hBN valence bands. A hybridiza-
tion between dx–y orbital of MoS2 and the pz orbital of hBN originates such band-
gap [24]. Recently, it is demonstrated that monolayer MoS2 retains high carrier
mobility free of surface scattering on hBN substrate. The substrate layer of hBN
protects MoS2 layer from Coulomb scattering from charge impurities in SiO2 [25].
In a fully planar two-dimensional FET based on layered semiconductors, hBN
has also been used as the top gate dielectric layer providing superior gate control
Molybdenum disulfide–boron nitride junctionless tunnel effect transistor 281
Top Gate
VG
hBN = 20 layers
Top MoS2 = 1 layer
W= 5 nm hBN = 1 layer
Source Bottom MoS2=1 layer Drain
B hBn = 20 layers B′
SiO2
Bottom Gate
Si
VDS GND
L = 10 nm
A′
over the channel [26]. Therefore, hBN is considered as both top and bottom gate
dielectric in MoS2 JTET. Experimentally it is found that single-layer hBN is a
potential candidate for interlayer tunneling barrier for vertical iTFET [27,28]. Such
thin tunnel barrier not only allows wave function extension between two semi-
conducting layers but also preserves the coherent length of tunneling [4].
Operation of MoS2 JTET is twofold [16], i.e. (a) gate bias (VG) between the top
and bottom MoS2 layers initiates the vertical interlayer tunneling of carriers which
changes the channel Fermi level and (b) the corresponding shift in channel Fermi
level controls the height of the barrier between source and drain. In Figure 12.1,
dashed line A–A0 refers to the band diagram in vertical direction of interlayer
tunneling and B–B0 refers to the lateral direction of source-drain ballistic transport.
Figure 12.2(a) and (b) shows the MoS2/hBN vertical energy band diagram for
VG ¼ 0 V and |VG| 6¼ 0 V, respectively. For VG ¼ 0 V, Fermi levels of both top and
bottom MOS2 layers are assumed to be in equilibrium as shown in Figure 12.2(a).
As bias is applied between these two layers, the tunnel barrier hBN screens out
some electric field, however, a shift in Fermi level at the bottom (channel) MoS2
layer is still observed. This is shown in Figure 12.2(b).
282 Advanced technologies for next generation integrated circuits
OFF ON
Conduction Band
A A′ A A′
Top Gate
Top Gate
Bottom Gate
Bottom Gate
VG =0
VG ≠0
∆ϕ
MoS2 Valence Band
MoS2
MoS2
MoS2
hBN
hBN
hBN
hBN
hBN
hBN
(a) (b)
Figure 12.2 (a) Energy band diagram along vertical AA0 direction in the off-state
in MoS2 JTET and (b) in on-state. Note that Df denotes change in the
Fermi level at bottom (channel) Fermi level
As the gate bias is applied, a finite amount of carrier tunnels from top MoS2
layer to bottom MoS2 which is estimated as follows [29]:
ð Df
N1 ¼ rMoS2 T WKB ðEÞf T ðEÞdE (12.1)
0
Similarly, tunneling of carriers from bottom MoS2 to top MoS2 layer is esti-
mated from:
ð Df
N2 ¼ rMoS2 T WKB ðEÞf B ðEÞdE (12.2)
0
The net amount of tunnel carrier concentration at the bottom MoS2 channel is
described as follows:
ð Df
N¼ rMoS2 T WKB ðEÞðf T ðEÞ f B ðEÞÞdE (12.3)
0
where rMoS2 ¼ gs gv mMoS2 =ð2pℏ2 Þ is the density of states (DOS) in MoS2, gs (¼2)
and gv (¼2) are spin and valley degeneracy, respectively, mMoS2 is effective mass in
MoS2 (0.57 mo) and ℏ is the reduced Planck’s constant [29]. TWKB(E) is the tun-
neling probability between two MoS2 layers through hBN barrier and fT(E) and
fB(E) are Fermi functions at the top and bottom MoS2 layers (with the generic
Molybdenum disulfide–boron nitride junctionless tunnel effect transistor 283
where d is the thickness of the tunnel barrier (1.3 nm in this work), m* is the carrier
effective mass inside the barrier (¼0.5 mo inside hBN) [3] and D is the height of the
tunneling barrier (1.83 eV between MoS2 and hBN) [24]. Effective change in Fermi
level of the bottom MoS2 layer (which is also the channel MoS2 layer) is expressed
as Df. Using proper limits of integration, net doping density (N) from (12.3) is
integrated as follows:
2qV T mMoS2 Df Df
N¼ 2
T WKB ðEÞ ln 1þexp þln 4= 1þexp
pðℏÞ VT VT
(12.5)
1.5
SL-MoS2 EG=1.8e V
1
EC
VG =0.74 V
Fermi Level (eV) 0.5
0 /c 2
n-type
m
0
ns =1 17
Midgap p-type
–0.5 1V 2V 3V 4V
Ev
–1
–1.5
0 200 400 600 800 1,000
(a) Temperature, T (k)
1018
SL-MOS2 EG=1.8e V
m*=0.57mo
Tunnel Carrier Concentration [/cm2]
1017
1016
T = 77 k
T = 150 k
T = 300 k
T = 650 k
1015
–2 –1.5 –1 –0.5 0 0.5 1 1.5 2
(b) Gate Bias, VG [V]
Figure 12.3 (a) Change in Fermi level in n-type (above 0 eV) and p-type (below
0 eV) for a single-layer (SL) MoS2 channel with change in
temperature (T) for different gate bias (VG). The Fermi level for a
doped SL-MoS2 of ns ¼ 1 1017/cm2 at zero gate bias matches with
non-doped SL MoS2 JTET operating at |VG| ¼ 0.74 V. (b) Induced
interlayer tunnel carrier concentration (N) with change in gate
bias (VG) for different temperatures (T)
Molybdenum disulfide–boron nitride junctionless tunnel effect transistor 285
V V ¼ qN =C V (12.9)
where CV is the net vertical capacitance between the top and bottom gate electro-
des. Having similarity with MOSFET, iTFET is also assumed to suffer the effect of
drain induced barrier lowering (DIBL). We consider DIBL as
lDIBL ¼ aV DS (12.10)
where a is the fractional coefficient of DIBL and lies between 0 and 1, where
0 stands for no drain bias effect and 1 stands for full-drain bias effect [31]. Now, the
effective change in channel Fermi level Df becomes:
Df ¼ V G V ch V V lDIBL (12.11)
where fS(E) and fD(E) are the source and drain Fermi levels, respectively. TB(E) is
the ballistic transmission coefficient in the channel and is taken 1 for the ballistic
transport. M(E) is the number of modes in the channel and written as follows [32]:
qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
MðEÞ ¼ gv W 2mMoS2 ðE EC Þ=pℏ (12.14)
286 Advanced technologies for next generation integrated circuits
where W is the width of the channel and EC is the position of the channel con-
duction band. Combining (12.12)–(12.14), drain current becomes:
ð 2 qffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffiffi
2q
I D ¼ dE g v W 2m MoS2 ðE E C Þ ðf S ðEÞ f D ðEÞÞ (12.15)
pℏ2
The Fermi functions in the source and drain are described as follows:
1
f S ðEÞ ¼ (12.16)
1þ eðEEF Þ=k B T
s
and
1
f D ðEÞ ¼ (12.17)
1þ eðEEF Þ=k B T
D
Now considering:
x ¼ ðE EC Þ=k B T (12.19)
hFD ¼ ðED
F EC Þ=k B T (12.21)
Using (12.5), (12.11) and (12.25), transfer characteristics of iTFET are plotted in
Figure 12.4. A small negative differential resistance (NDR) region is observed
at different drain bias at room temperature as shown in Figure 12.4(a). For VDS ¼ 1.2 V,
an on/off current ratio of 17 with a subthreshold slope of 57 mV/decade is obtained
for VG > 0 which is 70 mV/decade for VG < 0 with an on/off current ratio of 18. The
off-state leakage current of MoS2 JTET is calculated as 25.2 mA for VDS ¼ 1.2 V.
Subthreshold slope is calculated from SS ¼ log(10)[ID/(dID/dVG)], where ID is the
drain current and VG is the gate bias. Compared to a conventional MOSFET, a reduced
subthreshold slope at low on/off current ratio in MoS2 JTET is observed and explained
through Figure 12.5(a)–(c).
The intrinsic MoS2 channel in Figure 12.5(a) considers the source (EFS),
channel (EFC) and drain (EFD) Fermi levels in equilibrium. As the negative gate
100 10–1
10 layers
VDS = 2 V
1 layer hBN
VDS = 1.2 V 4 layers
Drain Current, ID [mA]
Drain Current, ID [mA]
10–1
NDR
trend
VDS = 0.6 V
10–1
10–2
ID [mA]
NDR 10–2
trend
T = 300k 10–2 T = 300 k
–2 0 2
# hBN layers = 1 VG[v] VDS=1.2 V
–2 –1 0 1 2 –0.5 0 0.5
(a) Gate Bias, VG [V] (b) Gate Voltage, VG [V]
Figure 12.4 Transfer characteristics of MoS2 JTET. (a) ID–VG curve for different
drain biases (VDS) and (b) ID–VG curve for different number of hBN
layers as tunnel barrier between top and bottom MoS2 layers. Inset in
(b) shows drain current for complete bias operation where the effect
of number of hBN layers on drain current is non-differentiable
288 Advanced technologies for next generation integrated circuits
B B′
MoS2 conduction band
EG=1.8eV
EFS EFS EFD
Thermionic
SS≥60mV/dec
qVG>0
EFS
tunnel
∆φ qVDS SS<60mV/dec
EFS
∆φ E
EFC EFD FC qVDS
Indirect
tunneling Channel
EFD
degeneracy
(b) (c)
Figure 12.5 (a) Energy band diagram of the bottom (channel) MoS2 layer in
equilibrium at off-state of MoS2 JTET, (b) energy band diagram at
on-state for qVG > 0, and (c) energy band diagram at on-state for
qVG < 0. Red arrow points to thermionic transport and green arrow
to band-to-band tunneling transport. BB0 refers to the lateral
direction of ballistic transport between source and drain
bias (VG < 0 giving qVG > 0) is applied, the degenerately doped (from the interlayer
tunneling) n-type channel Fermi level (EFC) moves down which is shown in
Figure 12.5(b). The |qVDS| is the amount of shift between EFS and EFD due to drain-
source bias. Similar to a MOSFET, thermionic transport (red arrow) dominates the
source-drain ballistic transport. For this reason, a subthreshold slope more than the
thermionic limit of 60 mV/decade is observed. A small amount of phonon-assisted
indirect band-to-band tunneling (BTBT) is assumed which occurs between the
source and channel and is shown by a single green arrow in Figure 12.5(b). Note
that similar BTBT contributes toward the NDR trend which is also found in
ATLAS TFET for a p þ Ge source and n-MoS2 channel [19]. As the positive gate
bias (VG > 0 giving qVG < 0) is applied, the degenerately doped (from interlayer
tunneling) p-type Fermi level (EFC) of the channel moves below the channel
valence band. Hence, the channel valence band comes opposite to the drain
conduction band and channel-drain BTBT has occurred. A subthreshold slope of
57 mV/decade is observed due to this BTBT dominated drain current which is
shown by the green arrow in Figure 12.5(c).
Number of hBN layers as tunnel barriers also affects the MoS2 JTET transfer
characteristics which are shown clearly in Figure 12.4(b). As the number of hBN
Molybdenum disulfide–boron nitride junctionless tunnel effect transistor 289
0.3 0.25
T = 300 K
VG = 1.2 V
VG = 2 V 0.2
Drain Current, LD [mA]
Drain Current, LD [mA]
0.2
0.15
VG = 1.2 V
0.1
0.1
VG = 0.6 V
0.05
10 layers hBN
T = 300 K
4 layers hBN
#hBN layers =1 1 layer hBN
0 0
0 1 2 0 1 2
(a) Drain Bias, VDS [V] (b) Drain Bias, VDS [V]
Figure 12.6 Output characteristics of MoS2 JTET: (a) ID–VDS curve for different
gate biases (VG) and (b) ID–VDS curve for different number of hBN
layers as tunnel barrier between top and bottom MoS2 layers
290 Advanced technologies for next generation integrated circuits
T = 300 K
# hBN layers =1
150 VDS=1.2 V
μFE [cm2/V–s]
100
kF.|e>>1,
metallic region
50
kF./e<<1,
insulating region
0
0.5 1
VG [V]
hBN C1 C2
VG
MoS2 C3 C4
hBN C5 C6
MoS2 C7
C10 C11
hBN C8 C9 VDS
100
650 k
100
Cqch
Capacitance [F/m2]
Capacitance [F/m2]
CV
10–5
300 k
10–1
150 k CG
77 k 10–2
10–10 –2 –1 0 1 2
Gate Bias, VG [V]
–2 –1 0 1 2
Gate Bias, VG [V]
Figure 12.9 Change in channel quantum capacitance (Cqch) and total gate
capacitance (CG) with gate bias (VG) for different temperatures of
MoS2 JTET. Note: Non-channel fixed vertical capacitance (CV) is
shown in green line
292 Advanced technologies for next generation integrated circuits
1,000
100
40
400 77 k
20
200 0.5 0.6 0.7 0.8 0.9
Gate Bjas, VG [V]
–2 –1 0 1 2
Gate Bias, VG [V]
Figure 12.10 Intrinsic cut-off frequency (fT) variation of MoS2 JTET with change
in gate bias (VG)
8 100
650 k
6 10–2 # hBN layers = 1
300 k
PDP [aJ]
10–4
|VDS| = 1.2 V
t [fs]
|VDS| = 1.2 V
4
150 k 10–6
2
77 k 10–8
0 10–10
–2 0 2 –2 0 2
(a) VG [V] (b) VG [V]
Figure 12.11 (a) Intrinsic gate delay (t) versus the gate bias (VG) and
(b) corresponding power delay product (PDP) for different
temperatures of MoS2 JTET
Table 12.1 Comparison of MoS2 JTET performance with earlier similar models
Ref. [Year] Device transport type Material system/channel Channel length/tunneling Bias IOn/IOff fT
barrier thickness voltage
[9] [2013] iTFET Graphene-hBN-graphene 1.03 nm (tunneling barrier thickness) 1.2 V 15 0.5 GHz
[10] [2014] iTFET GNR-hBN-GNR 1.03 nm (tunneling barrier thickness) 1.2 V 4 97 GHz
[37] [2016] FET CVD MoS2 on flexible sub- 1 mm (channel) 2V 105 5.6 GHz
strate
[39] [2009] FET Graphene 500 nm (channel) 1.6 V ~2 4 GHz
[40] [2014] FET MoS2 240 nm (channel) 2V ~300 8.2 GHz
[41] [2012] FET Bilayer graphene 40 nm (channel) 1V ~800 1.5 THz
[42] [2010] FET Graphene 140 nm (channel) 1V ~3 300 GHz
[43] [2011] FET Graphene 40 nm (channel) 1.5 V ~800 155 GHz
[44] [2013] FET Epitaxial graphene from SiC
100 nm (channel) 0.8 V ~2 110 GHz
[45] [2013] BJT type Graphene-based 2–5 nm (SiO2 tunneling barrier 1V 104 1 THz
heterojunction thickness)
[46] [2013] Hot electron transistor Graphene base 2 nm (Al2O3 tunneling barrier 1.5 V >105 Unspecified
thickness)
[47] [2015] TFET Graphene nanoribbon (GNR) 20 nm (channel) 0.1 V 122 ~1 THz
[48] [2012] TFET Graphene-hBCN 7 nm (channel) 0.6 V 104 ~2 THz
[49] [2016] Interlayer excitonic MoS2-hBN- MoS2 5 nm (tunneling barrier thickness) - - -
generation
[50] [2014] FET Black phosphorus 300 nm (channel) 2V 2 103 12 GHz
[51] [2012] iTFET-plasma resonance- Graphene-barrier-graphene 10 nm (tunneling barrier thickness) 0.5 V Unspecified 1.42 THz
based 500 nm (channel)
[52] [2014] FET Bilayer graphene 2.5 mm (channel) 0.001 Unspecified 0.29–0.38 THz
terms of subthreshold slope, MoS2 JTET provides ~7 and ~27 times less than that
of the reported in [9] and [10], respectively, for graphene vertical FETs. Due to a
small bandgap at 5 nm width, subthreshold slope of MoS2 JTET is 23 times less
than that of the vertical GNR iTFET reported in [10]. Compared to both [9] and
[10], MoS2 JTET provides THz operation due to very low gate capacitance. The on/
off current ratio is nearly the same as reported in [9] and [10]. Furthermore, high-
frequency performance of this MoS2 JTET is also compared with the existing two-
dimensional materials (both graphene and non-graphene)-based high-frequency
devices and is summarized in Table 12.2.
Based on the data in Table 12.2, MoS2 JTET outperforms other devices at a
comparable supply voltage, on/off current ratio and channel length. The only
similar device structure like MoS2 JTET is found in the work of Calman et al. [49]
which studies controlled excitonic generation in similar van der Waals hetero-
structure. However, the work in [49] does not account for any high-frequency
performance estimation and transistor-type electronic behavior and hence becomes
unsuitable for comparison. The high-frequency performance of MoS2 JTET origi-
nates from interlayer tunneling-based barrier control mechanism and the use of
two-dimensional layered materials (in this work hBN) as the gate dielectric pro-
viding low gate-capacitance.
12.5 Conclusion
Current transport MoS2 JTET is studied in this chapter which is controlled by the
gate induced interlayer tunneling-dependent charge density unlike inversion mode
operation in MOSFETs. The current transport between source and drain is ballistic.
Compared to recently reported device structures in [9] and [10], the present device
structure gives subthreshold slope close to 60 mV/decade and demonstrates
upper GHz operation with relatively comparable on/off current ratio. Low bandgap
insulator or wide bandgap-layered semiconductor materials can be used as an
interlayer tunneling barrier to improve the on/off current ratio and making MoS2
JTET suitable for digital applications. A comparison of the performance of MoS2
JTET with other types of device structures exhibits superior performance and high-
frequency THz operation.
References
[1] M. Waldrop, “The chips are down for Moore’s law,” Nature, vol. 530,
pp. 144–7, 2016.
[2] A. B. Sachid, M. Tosun, S. B. Desai, et al. “Monolithic 3D CMOS using
layered semiconductors,” Advanced Materials, vol. 28, pp. 2547–54, 2016.
[3] L. Britnell, R. V. Gorbachev, R. Jalil, et al., “Field-effect tunneling transistor
based on vertical graphene heterostructures,” Science, vol. 335, pp. 947–50,
2012.
Molybdenum disulfide–boron nitride junctionless tunnel effect transistor 295