Aegis TA-1.001

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Operation Manual
For
Aegis Series
TRANSFORMER PROTECTION RELAY
CROMPTON GREAVES LIMITED

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MV Switchgear Division (S2)
A-3 MIDC, Ambad, Nashik 422 010
T: +91- 2382271-75, 2301104
Fax: +91-0253-2381247
Operation Manual
For
Transformer Protection Relay

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Dear Customer,
Please accept our thanks for giving us the privilege to serve you by choosing a CG make
‘Transformer Protection Relay’.
If this is your first CG Protection Relay, we hope it is the beginning of a long

relationship which delivers value to your organization. If you already own and use a CG
product, we are doubly honored by your decision of continuing this relationship.
It is our constant endeavor to partner you for the growth and success of your business.
This philosophy is reflected in our Mission statement “Smart Solutions. Strong
Relationships”. Please do give us feedback to help us realize our Mission.

`
Important
This manual contains information concerning the Operation of the AEGIS Series
Transformer Protection Relay for the Switchgear Systems.
All relevant parts of the manual should be read prior to commencing installation.
The Relay must be commissioned by an engineer approved by the manufacturer (or his
agent) before being put into service. Failure to observe this condition will invalidate any
implied warranty.
The AEGIS Series Transformer Protection Relay has been designed for Industrial use only.
If you encounter any problem with the procedures contained in this manual you should seek
immediate assistance from Crompton Greaves Limited, Sales Office from whom the
equipment was purchased. Alternatively contact the Crompton Greaves Limited Customer
Service & Support department at the address shown below:
Crompton Greaves Limited
MV Switchgear Division (S2)

A-3 MIDC, Ambad,
Nashik - 422 010, India
Phone : (00 91 253) 2382271-75

2301104
Fax : (00 91 253) 2381247
Crompton Greaves Limited pursues a policy of continual product development and reserves
the right to change the equipment without notice.
@ Copyright 2011 by Crompton Greaves Ltd.

Unauthorized reproduction prohibited
All rights reserved

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Disclaimer
The information in this document is subject to change without notice and should
not be interpreted as assurance by CG. CG assumes no responsibility for any errors that may
appear in this document.
@ Copyright 2010 by Crompton Greaves Ltd.

Unauthorized reproduction prohibited
All rights reserved

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Contents
IMPORTANT........................................................................................................................................ 4
DISCLAIMER....................................................................................................................................... 5
CONTENTS........................................................................................................................................... 6
LIST OF FIGURES .............................................................................................................................. 9
LIST OF TABLES .............................................................................................................................. 14
ABBREVIATIONS & SYMBOLS .................................................................................................... 16
1 BASIC FUNCTIONS ................................................................................................................... 1
SECTION OVERVIEW ........................................................................................................................................... 2
1.1 GENERAL ............................................................................................................................................... 3
1.1.1 Philosophy ...................................................................................................................................... 3
1.1.2 Relay Features ................................................................................................................................ 5
1.1.3 Health & Safety .............................................................................................................................. 6
1.2 HARDWARE DESCRIPTION .............................................................................................................. 11
1.2.1 Relay Front Panel ......................................................................................................................... 11
1.2.2 Current Inputs ............................................................................................................................... 15
1.2.3 Voltage Inputs ............................................................................................................................... 15
1.2.4 Binary Inputs (BIs) ....................................................................................................................... 15
1.2.5 Binary Outputs (BOs) ................................................................................................................... 15
1.2.6 Virtual Inputs / Outputs (VIs / VOs) ............................................................................................. 16
1.2.7 General Inputs (GIs) ..................................................................................................................... 16
1.2.8 Non-Volatile Memory................................................................................................................... 16
1.2.9 Flowchart For Menu Navigation ................................................................................................... 16
1.3 RELAY SETTINGS & NAVIGATION ................................................................................................. 23
1.3.1 Device Info View .......................................................................................................................... 23
1.3.2 Password Accessing ...................................................................................................................... 23
1.3.3 Error Status View ......................................................................................................................... 25
1.3.4 Protection Function Status View .................................................................................................. 25
1.3.5 Current Measurement View (CURR) ........................................................................................... 26
1.3.6 Voltage Measurement View (VOLT) ........................................................................................... 27
1.3.7 Configuration Settings (CONF) .................................................................................................... 28
1.3.8 Biased Differential Protection (BD) (87) ...................................................................................... 41
1.3.9 Restricted Earth Fault Protection (Ref) (64H) .............................................................................. 42
1.3.10 Thermal Overload Protection (THRM) (49) ............................................................................ 43
1.3.11 Over Fluxing Protection (OFLX) (24) ..................................................................................... 44
1.3.12 Over Current Protection (3I> & 3I>>) (51 / 50) ...................................................................... 45
1.3.13 Measured Earth Fault Protection (Ig> & Ig>>) (51G / 50G) ................................................... 47
1.3.14 Derived Earth Fault Protection (Io> & Io>>) (51N / 50N) ...................................................... 49
1.3.15 Negative Phase Sequence Over Current Protection (I2> & I2>>) (46) .................................... 51
1.3.16 Under Current Protection (UC) (37) ........................................................................................ 53
1.3.17 Over Voltage Protection (OV) (59) .......................................................................................... 54
1.3.18 Under Voltage Protection (UV) (27) ........................................................................................ 55
1.3.19 NDR Protection (NDR) (59N) ................................................................................................. 56
1.3.20 Breaker Failure Protection (SUPR) (50BF) ............................................................................. 57
1.3.21 Binary Input & Binary Output Settings (BI-O) ........................................................................ 58
1.3.22 Communication (COMM) ........................................................................................................ 61
1.3.23 Fault Records (FL-R) ............................................................................................................... 67
1.3.24 Disturbance Recorder (DR)...................................................................................................... 70
1.3.25 Event Records (EVNT) ............................................................................................................ 72
1.4 TECHNICAL DATA ............................................................................................................................. 78
1.4.1 Connections .................................................................................................................................. 78

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1.4.2 Test & Environmental Conditions ................................................................................................ 81

1.5 CONNECTIONS .................................................................................................................................... 83
1.5.1 Rear Panel Connections ................................................................................................................ 83
1.5.2 Wiring Diagram ............................................................................................................................ 88
1.6 DIMENSIONS ....................................................................................................................................... 89
1.7 ORDERING INFORMATION ............................................................................................................... 90
2 PROTECTION FUNCTIONS .................................................................................................. 91
SECTION OVERVIEW ......................................................................................................................................... 92
PRINCIPLE OF A PROTECTION FUNCTION .......................................................................................................... 93
2.1 DIFFERENTIAL PROTECTION .......................................................................................................... 95
2.1.1 Bias Differential Protection .......................................................................................................... 95
2.1.2 Restricted Earth Fault Protection ................................................................................................ 108
2.2 THREE PHASE CURRENT PROTECTION ....................................................................................... 118
2.2.1 Overcurrent Protection ................................................................................................................ 118
2.2.2 Derived Earth Fault Protection ................................................................................................... 131
2.2.3 Measured Earth Fault Protection ................................................................................................ 140
2.2.4 Negative Phase Sequence Overcurrent Protection ...................................................................... 150
2.2.5 Thermal Overload Protection ...................................................................................................... 159
2.2.6 Under Current Protection ............................................................................................................ 164
2.3 VOLTAGE & FREQUENCY PROTECTION ..................................................................................... 169
2.3.1 Over Voltage Protection ............................................................................................................. 169
2.3.2 Under Voltage Protection ........................................................................................................... 177
2.3.3 Neutral Displacement Protection ................................................................................................ 185
2.3.4 Over Frequency Protection ......................................................................................................... 192
2.3.5 Under Frequency Protection ....................................................................................................... 196
2.3.6 Over Fluxing Protection.............................................................................................................. 200
2.4 SUPERVISION FUNCTIONS ............................................................................................................. 206
2.4.1 Circuit Breaker Failure Protection .............................................................................................. 206
2.4.2 Trip Circuit Supervision ............................................................................................................. 210
2.4.3 Close Circuit Supervision ........................................................................................................... 213
3 COMMUNICATION ............................................................................................................... 216
SECTION OVERVIEW ....................................................................................................................................... 217
3.1 GETTING STARTED .......................................................................................................................... 218
3.1.1 Introduction................................................................................................................................. 218
3.1.2 Software Installation ................................................................................................................... 219
3.1.3 System Requirements ................................................................................................................. 220
3.1.4 Overview of the SCL .................................................................................................................. 220
3.2 CONFIGURING THE TOOL .............................................................................................................. 222
3.2.1 The User Interface ...................................................................................................................... 222
3.2.2 Project Editor .............................................................................................................................. 223
3.2.3 Configurations Editor ................................................................................................................. 225
3.2.4 IED Configuration ...................................................................................................................... 229
3.3 IED PALETTE ..................................................................................................................................... 238
3.3.1 Log Window ............................................................................................................................... 239
3.3.2 Other Settings ............................................................................................................................. 239
3.4 LOGICAL NODE DESCRIPTION ...................................................................................................... 243
3.4.1 Logical Nodes for Protection Functions ..................................................................................... 243
3.4.2 Logical Nodes for Control Functions ......................................................................................... 265
3.4.3 Logical Nodes for General Settings & Measurements ................................................................ 274
3.4.4 System Logical Nodes ................................................................................................................ 276
4 CONAEGIS RELAY COMMUNICATION SOFTWARE & LOGIC ............................... 277
SECTION OVERVIEW ....................................................................................................................................... 278
4.1 GETTING STARTED .......................................................................................................................... 279
4.1.1 What is ConAEGIS ?................................................................................................................... 279
4.1.2 Software Installation ................................................................................................................... 279
4.1.3 System Requirements ................................................................................................................. 280

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4.1.4 Connecting Relay with the Software .......................................................................................... 280

4.1.5 Tool Bar Functions ..................................................................................................................... 287
4.1.6 Tree Structure ............................................................................................................................. 288
4.1.7 Procedure to Write A Value ........................................................................................................ 289
4.2 SETTINGS ........................................................................................................................................... 291
4.2.1 Disturbance Record Settings ....................................................................................................... 291
4.2.2 Configuration Settings ................................................................................................................ 295
4.2.3 Bias Differential Protection (87BD) & Bias Differential High Set Protection (87HS) ............... 306
4.2.4 Restricted Earth Fault Protection (64H) (REF) ........................................................................... 311
4.2.5 Thermal Overload Protection (49)(THRM) ................................................................................ 312
4.2.6 Over Fluxing Protection (24) (OFLX) ........................................................................................ 313
4.2.7 Over Current Protection (51) (3I>) ............................................................................................. 314
4.2.8 Instantaneous Over Current Protection (50) (3I>>) .................................................................... 315
4.2.9 Measured Earth Fault Protection (51G) (Ig>) ............................................................................. 317
4.2.10 Instantaneous Measured Earth Fault Protection (50G) (Ig>>) ............................................... 318
4.2.11 Derived Earth Fault Protection (51N) (Io>) ........................................................................... 320
4.2.12 Instantaneous Derived Earth Fault Protection (50N) (Io>>) .................................................. 321
4.2.13 Negative Sequence Over Current Protection (46) (I2>) ......................................................... 323
4.2.14 Instantaneous Negative Sequence Over Current Protection (46) (I2>>) ................................ 324
4.2.15 Under Current Protection (37) (UC) ...................................................................................... 326
4.2.16 Over Voltage Protection (59) (OV) ........................................................................................ 328
4.2.17 Under Voltage Protection (27) (UV) ...................................................................................... 330
4.2.18 NDR Protection (59) .............................................................................................................. 332
4.2.19 Over Frequency Protection (81) (OF) .................................................................................... 334
4.2.20 Under Frequency Protection (81) (UF) .................................................................................. 335
4.2.21 Supervision Setting (SUPR) ................................................................................................... 336
4.2.22 Communication Settings ........................................................................................................ 338
4.2.23 Binary Input & Binary Output Settings (BIBO) .................................................................... 341
4.2.24 Write All ................................................................................................................................ 353
4.3 LOGIC.................................................................................................................................................. 357
4.3.1 Overview .................................................................................................................................... 357
4.3.2 Building Programmable Logic .................................................................................................... 359
4.3.3 Logic Gates & Blocks ................................................................................................................. 368
4.3.4 Generic Inputs ............................................................................................................................. 384
4.3.5 Output Commands ...................................................................................................................... 386
4.4 GRAPHS .............................................................................................................................................. 390
4.4.1 Downloading the Disturbance Records....................................................................................... 390
4.5 MEASUREMENTS ............................................................................................................................. 392
4.5.1 Current Measurement ................................................................................................................. 392
4.5.2 Voltage Measurement ................................................................................................................. 393
4.6 STATUS ............................................................................................................................................... 394
4.7 REPORTS ............................................................................................................................................ 395
4.7.1 Fault Records .............................................................................................................................. 395
4.7.2 Event Records ............................................................................................................................. 397
APPENDIX A – IDMT CURVES .................................................................................................... 398
APPENDIX B – CURVES IN IEC 61850 LOGICAL NODES ..................................................... 402
APPENDIX C –DATA ATTRIBUTES IN IEC 61850 LOGICAL NODES ................................ 405

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List of Figures
Figure 1 - Architecture of Numerical Protection Relay .......................................................................................... 3
Figure 2 - Front Panel of Transformer Protection Relay ...................................................................................... 11
Figure 3 - LED Indicators of Transformer Protection Relay ................................................................................ 12
Figure 4 - LCD Display of Transformer Protection Relay ................................................................................... 13
Figure 5 - Keypad of Transformer Protection Relay ............................................................................................ 14
Figure 6 - Principle of the menu structure and navigation in the menus .............................................................. 17
Figure 7 - Device Info View ................................................................................................................................. 23
Figure 8 - Password Accessing - 1 ....................................................................................................................... 23
Figure 9 - Password Accessing - 2 ....................................................................................................................... 24
Figure 10 - Changing the Password ...................................................................................................................... 24
Figure 11 - Error Status View ............................................................................................................................... 25
Figure 12 - Current Measurements View ............................................................................................................. 26
Figure 13 - Voltage Measurements View ............................................................................................................. 27
Figure 14 - Graphical Representation ................................................................................................................... 27
Figure 15 - Zoom view of measurement window ................................................................................................. 27
Figure 16 - Configuration Settings ....................................................................................................................... 28
Figure 17 - DI Pick up .......................................................................................................................................... 39
Figure 18 - DI Drop off ........................................................................................................................................ 40
Figure 19 - Biased Differential Protection Navigation ......................................................................................... 41
Figure 20 - Restricted Earth Fault Protection Navigation..................................................................................... 42
Figure 21 - Thermal Overload Protection Navigation .......................................................................................... 43
Figure 22 - Over Fluxing Protection navigation. .................................................................................................. 44
Figure 23 - IDMT Over Current Protection Navigation ....................................................................................... 45
Figure 24 - INST Over Current Protection Navigation......................................................................................... 46
Figure 25 - IDMT Measured Earth Fault Protection Navigation .......................................................................... 47
Figure 26 - INST Measured Earth Fault Protection Navigation ........................................................................... 48
Figure 27 - IDMT Derived Earth Fault Protection Navigation ............................................................................. 49
Figure 28 - INST Derived Earth Fault Protection Navigation .............................................................................. 50
Figure 29 - IDMT Negative Phase Sequence Overcurrent Protection Navigation ............................................... 51
Figure 30 - INST Negative Phase Sequence Overcurrent Protection Navigation ................................................. 52
Figure 31 - Under Current Protection Navigation ................................................................................................ 53
Figure 32 - Over Voltage Protection Navigation .................................................................................................. 54
Figure 33 - Under Voltage Protection Navigation ................................................................................................ 55
Figure 34 - NDR Protection Navigation ............................................................................................................... 56
Figure 35 - Breaker Failure Protection Navigation ............................................................................................... 57
Figure 36 - Binary Inputs & Outputs Settings ...................................................................................................... 58
Figure 37 - Communication Settings .................................................................................................................... 61
Figure 38 - SNTP Server Selection ...................................................................................................................... 63
Figure 39 - Fault Records View............................................................................................................................ 68
Figure 40 - Fault Records Overview..................................................................................................................... 69
Figure 41 - Disturbance Recorder......................................................................................................................... 71
Figure 42 - Rear View of Transformer Protection Relay ...................................................................................... 83
Figure 43 - Wiring Diagram for Transformer Protection Relay (AE025_00) ...................................................... 88
Figure 44 - Dimensions ........................................................................................................................................ 89
Figure 45 - Functional Block Diagram for a Basic Protection Function .............................................................. 93
Figure 46 - Differential Protection of Power Transformer ................................................................................... 95
Figure 47 - IEC 61850 Functional Blocks for Bias Differential Protection .......................................................... 96
Figure 48 - Functional Block Diagram for Bias Differential Protection............................................................... 97
Figure 49 - Bias Differential Protection Operation Characteristics .................................................................... 100
Figure 50 - High Set Bias Differential Protection Operation Characteristics ..................................................... 100
Figure 51 - Transformer Differential Protection Scheme ................................................................................... 106
Figure 52 - IEC 61850 Functional Blocks for Restricted Earth Fault Protection ............................................... 108
Figure 53 - Functional Block Diagram for Restricted Earth Fault Protection .................................................... 109
Figure 54 - Restricted Earth Fault Protection on Delta Side ............................................................................... 113
Figure 55 - Restricted Earth Fault Protection on Star Side ................................................................................. 115
Figure 56 - Restricted Earth Fault Protection (CT Connection) ......................................................................... 117
Figure 57 - IEC 61850 Functional Blocks for Overcurrent Protection ............................................................... 119

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Figure 58 - Functional Block Diagram for IDMT Overcurrent Protection ......................................................... 120
Figure 59 - Functional Block Diagram for INST Overcurrent Protection .......................................................... 121
Figure 60 - Typical transformer overcurrent application example ..................................................................... 129
Figure 61 - Reverse blocking principle of overcurrent protection using digital input and digital output channel
.................................................................................................................................................................. 130
Figure 62 - IEC 61850 Functional Blocks for Derived Earth Fault Protection ................................................... 132
Figure 63 - Functional Block Diagram for IDMT Derived Earth Fault Protection ............................................ 132
Figure 64 - Functional Block Diagram for INST Derived Earth Fault Protection .............................................. 134
Figure 65 - IEC 61850 Functional Blocks for Measured Earth Fault Protection ................................................ 141
Figure 66 - Functional Block Diagram for IDMT Measured Earth Fault Protection .......................................... 141
Figure 67 - Functional Block Diagram for INST Measured Earth Fault Protection ........................................... 143
Figure 68 - IEC 61850 Functional Blocks for Negative Phase Sequence Overcurrent Protection ..................... 151
Figure 69 - Functional Block Diagram for IDMT Negative Sequence Overcurrent Protection ......................... 151
Figure 70 - Functional Block Diagram for INST Negative Sequence Overcurrent Protection ........................... 153
Figure 71 - IEC 61850 Functional Blocks for Thermal Overload Protection ..................................................... 159
Figure 72 - Functional Block Diagram for Thermal Overload Protection .......................................................... 160
Figure 73 - IEC 61850 Functional Blocks for Under Current Protection ........................................................... 164
Figure 74 - Functional Block Diagram for Under Current Protection ................................................................ 165
Figure 75 - IEC 61850 Functional Blocks for Over Voltage Protection ............................................................. 170
Figure 76 - Functional Block Diagram for IDMT Over Voltage Protection ...................................................... 171
Figure 77 - Functional Block Diagram for INST Over Voltage Protection ........................................................ 172
Figure 78 - IEC 61850 Functional Blocks for Under Voltage Protection ........................................................... 178
Figure 79 - Functional Block Diagram for IDMT Under Voltage Protection..................................................... 178
Figure 80 - Functional Block Diagram for INST Under Voltage Protection ...................................................... 180
Figure 81 - IEC 61850 Functional Blocks for Neutral Displacement Protection ............................................... 185
Figure 82 - Functional Block Diagram for IDMT NDR Protection .................................................................... 186
Figure 83 - Functional Block Diagram for INST NDR Protection ..................................................................... 188
Figure 84 - Functional Block Diagram for Over Frequency Protection ............................................................. 193
Figure 85 - Functional Block Diagram for Under Frequency Protection ........................................................... 197
Figure 86 - IEC 61850 Functional Blocks for Over Fluxing Protection ............................................................. 200
Figure 87 - Functional Block Diagram for Over Fluxing Protection .................................................................. 201
Figure 88 - Functional Block Diagram for Circuit Breaker Failure Protection .................................................. 207
Figure 89 - Circuit Breaker Failure Protection in Aegis Relays ......................................................................... 209
Figure 90 - Functional Block Diagram for Trip Circuit Supervision Function .................................................. 210
Figure 91 - Trip Circuit Supervision Scheme ..................................................................................................... 212
Figure 92 - Functional Block Diagram for Close Circuit Supervision Function ................................................ 213
Figure 93 - Close Circuit Supervision Scheme ................................................................................................... 215
Figure 94 - Default View .................................................................................................................................... 219
Figure 95 - SCL File Types ................................................................................................................................ 221
Figure 96 - Split Window Layout ....................................................................................................................... 222
Figure 97 - Project Editor ................................................................................................................................... 223
Figure 98 - Creating a Project............................................................................................................................. 223
Figure 99 - Adding IED to Project...................................................................................................................... 224
Figure 100 - Local IED & Remote Publisher ..................................................................................................... 224
Figure 101 - Available Functions ....................................................................................................................... 225
Figure 102 - Properties ....................................................................................................................................... 225
Figure 103 - Goose Subscription Mapping ......................................................................................................... 227
Figure 104 - Data Mapping................................................................................................................................. 228
Figure 105 - Remove Mapping ........................................................................................................................... 228
Figure 106 - Subscriber Display ........................................................................................................................ 229
Figure 107 - Datapath of VI................................................................................................................................ 229
Figure 108 - Goose Control Block...................................................................................................................... 230
Figure 109 - Select Logical Device .................................................................................................................... 230
Figure 110 - Goose Details ................................................................................................................................. 231
Figure 111 - Error in deleting GCB .................................................................................................................... 232
Figure 112 - MAC Address ................................................................................................................................ 232
Figure 113 - RCB Configuration ........................................................................................................................ 233
Figure 114 - Bitstring Format ............................................................................................................................. 233
Figure 115 - New RCB ....................................................................................................................................... 234
Figure 116 - Datasets Configuration ................................................................................................................... 235

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Figure 117 - New Dataset ................................................................................................................................... 236

Figure 118 - Error in deleting Dataset ................................................................................................................ 236
Figure 119 - Cloning a Dataset ........................................................................................................................... 237
Figure 120 - IED Pallete ..................................................................................................................................... 238
Figure 121 - Import IED ..................................................................................................................................... 238
Figure 122 - Log Window .................................................................................................................................. 239
Figure 123 - File Menu ....................................................................................................................................... 239
Figure 124 - Goose Mapping .............................................................................................................................. 240
Figure 125 - Edit Menu ...................................................................................................................................... 241
Figure 126 - Change Password ........................................................................................................................... 241
Figure 127 - About the Developer ...................................................................................................................... 242
Figure 128 - dwns Control Model ...................................................................................................................... 266
Figure 129 - sboes Control Model ...................................................................................................................... 267
Figure 130 - ConAegis Software Icon ................................................................................................................ 279
Figure 131 - Default View .................................................................................................................................. 280
Figure 132 - Offline Mode .................................................................................................................................. 282
Figure 133 - Connecting the relay serially .......................................................................................................... 283
Figure 134 - Connecting serially using Auto-Synchronize option...................................................................... 284
Figure 135 - Connection Error ............................................................................................................................ 285
Figure 136 - Connection Through Ethernet ........................................................................................................ 286
Figure 137 - Invalid IP Address .......................................................................................................................... 287
Figure 138 - Tool Bar ......................................................................................................................................... 287
Figure 139 - Tree Structure................................................................................................................................. 288
Figure 140 – Bias Differential Settings .............................................................................................................. 289
Figure 141 - Write Successful ............................................................................................................................ 290
Figure 142 - Disturbance Record Settings .......................................................................................................... 291
Figure 143 - Disturbance Record Trigger Settings ............................................................................................. 293
Figure 144 - DR Trigger BI Settings .................................................................................................................. 294
Figure 145 - Configuration Settings ................................................................................................................... 295
Figure 146 - Phase & Earth CT & VT Settings .................................................................................................. 296
Figure 147 - Configuration Settings ................................................................................................................... 298
Figure 148 - ICT Settings ................................................................................................................................... 299
Figure 149 - Harmonics Block Settings .............................................................................................................. 300
Figure 150 - Trip / Close BO Settings ................................................................................................................ 301
Figure 151 - Trip / Close BI Settings .................................................................................................................. 302
Figure 152 – Pickup-Reset Time Settings .......................................................................................................... 304
Figure 153 - DI Debounce Settings .................................................................................................................... 305
Figure 154 - Biased Differential ......................................................................................................................... 306
Figure 155 - Biased Differential Highset ............................................................................................................ 307
Figure 156 – Bias Differential LED Setting Step-1 ............................................................................................ 308
Figure 157 - Bias Differential LED Setting Step-2............................................................................................. 309
Figure 158 - SwBI / BO Setting Configuration .................................................................................................. 310
Figure 159 - Restricted Earth Fault Settings ....................................................................................................... 311
Figure 160 - Thermal Overload Settings ............................................................................................................ 312
Figure 161 - Over Fluxing Settings .................................................................................................................... 313
Figure 162 - Over Current Settings..................................................................................................................... 314
Figure 163 - Instantaneous Over Current Settings .............................................................................................. 315
Figure 164 - Measured Earth Fault Settings ....................................................................................................... 317
Figure 165 - Instantaneous Measured Earth Fault Settings ................................................................................ 318
Figure 166 - Derived Earth Fault Settings .......................................................................................................... 320
Figure 167 - Instantaneous Derived Earth Fault Settings ................................................................................... 321
Figure 168 - Negative Sequence IDMT Over Current Settings .......................................................................... 323
Figure 169 - Instantaneous Negative Sequence Over Current Settings .............................................................. 324
Figure 170 - Under Current Settings................................................................................................................... 326
Figure 171 - Over Voltage Settings .................................................................................................................... 328
Figure 172 - Under Voltage Settings .................................................................................................................. 330
Figure 173 - NDR Protection .............................................................................................................................. 332
Figure 174 - Over Frequency Protection ............................................................................................................ 334
Figure 175 - Under Frequency Protection .......................................................................................................... 335
Figure 176 – Supervision Settings ...................................................................................................................... 336

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Figure 177 - TCS / CCS Settings ........................................................................................................................ 337

Figure 178 - IEC 103 & MODBUS Settings ...................................................................................................... 338
Figure 179 - IEC 61850 Settings ........................................................................................................................ 339
Figure 180 - IEC 61850 IP Settings .................................................................................................................... 340
Figure 181 - BI / BO Settings Menu ................................................................................................................... 341
Figure 182 - Configuring External BI/BO .......................................................................................................... 342
Figure 183 - Configuring External BI – LED Setting ......................................................................................... 343
Figure 184 - Self / Hand Reset Setting ............................................................................................................... 344
Figure 185 - Protection on BI Settings ............................................................................................................... 346
Figure 186 - Setting Group on BI Settings ......................................................................................................... 347
Figure 187 - Protection on VI Settings ............................................................................................................... 349
Figure 188 - Setting Group on VI ....................................................................................................................... 350
Figure 189 - Protection on GI Settings ............................................................................................................... 351
Figure 190 – Setting Group on GI ...................................................................................................................... 352
Figure 191 - Read All Settings ........................................................................................................................... 353
Figure 192 - Save the Setting File ...................................................................................................................... 354
Figure 193 - Opening the Settings file ................................................................................................................ 355
Figure 194 - Updating Settings from the file ...................................................................................................... 356
Figure 195 - Reading Relay Logic ...................................................................................................................... 357
Figure 196 - Main Window for Logic ................................................................................................................ 358
Figure 197 - Creating a New Logic File ............................................................................................................. 359
Figure 198 - Selecting the Relay Type ............................................................................................................... 360
Figure 199 - Placing a Gate ................................................................................................................................ 361
Figure 200 - Connecting the Inputs .................................................................................................................... 362
Figure 201 - Placing the Connectors................................................................................................................... 362
Figure 202 - Placing the Outputs (LED) ............................................................................................................. 363
Figure 203 - Placing the Outputs (LED & BO) .................................................................................................. 363
Figure 204 - Compilation Successful .................................................................................................................. 364
Figure 205 - Compilation Failed......................................................................................................................... 364
Figure 206 - Transferring the Logic File ............................................................................................................ 365
Figure 207 - Saving the Logic File ..................................................................................................................... 365
Figure 208 - Export the Logic File ..................................................................................................................... 366
Figure 209 - Import the Logic File ..................................................................................................................... 366
Figure 210 - Outline Window ............................................................................................................................. 367
Figure 211 - AND Gate ...................................................................................................................................... 368
Figure 212 - OR Gate ......................................................................................................................................... 368
Figure 213 - NOT Gate ....................................................................................................................................... 369
Figure 214 - XOR Gate ...................................................................................................................................... 369
Figure 215 - XNOR Gate .................................................................................................................................... 370
Figure 216 - NAND Gate ................................................................................................................................... 370
Figure 217 - NOR Gate ...................................................................................................................................... 371
Figure 218 - Pulse Timers................................................................................................................................... 372
Figure 219 - Timing Diagram for Pulse Timers ................................................................................................. 372
Figure 220 - Fixed Pulse Timers ........................................................................................................................ 374
Figure 221 - Timing Diagram for Fixed Pulse Timers ....................................................................................... 374
Figure 222 - Pulse Retrigger Timers................................................................................................................... 376
Figure 223 - Timing Diagram for Pulse Retrigger Timers ................................................................................. 376
Figure 224 - Delay-On Timers ........................................................................................................................... 378
Figure 225 - Timing Diagram for Delay-On Timers .......................................................................................... 378
Figure 226 - SR Flip-flop: Logic Block & Truth Table ...................................................................................... 380
Figure 227 - Select Input .................................................................................................................................... 380
Figure 228 - < / > Comparators .......................................................................................................................... 381
Figure 229 - ≤ / ≥ Comparators .......................................................................................................................... 381
Figure 230 - Input v/s Input Comparison............................................................................................................ 382
Figure 231 - Value v/s Input Comparison .......................................................................................................... 383
Figure 232 - Generic Inputs ................................................................................................................................ 384
Figure 233 - Reset Relay .................................................................................................................................... 386
Figure 234 - Reset Status .................................................................................................................................... 386
Figure 235 - Trip Command ............................................................................................................................... 387
Figure 236 - Close Command ............................................................................................................................. 387

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Figure 237 - DR Trigger Command ................................................................................................................... 388

Figure 238 - Protection on GI Command ........................................................................................................... 388
Figure 239 - Setting Group on GI Command ..................................................................................................... 389
Figure 240 - DR Menu........................................................................................................................................ 390
Figure 241 - Downloading the Disturbance Records .......................................................................................... 390
Figure 242 - Saving the DR file .......................................................................................................................... 391
Figure 243 - Current Measurements ................................................................................................................... 392
Figure 244 - Voltage Measurements ................................................................................................................... 393
Figure 245 - Status Menu ................................................................................................................................... 394
Figure 246 - Fault Records ................................................................................................................................. 396
Figure 247 - Event Records ................................................................................................................................ 397
Figure 248 - IEC VI & SI Curves Characteristics .............................................................................................. 398
Figure 249 - IEC EI & LTI Curves Characteristics ............................................................................................ 399
Figure 250 - IEEE EI, MI & VI Curves Characteristics ..................................................................................... 400
Figure 251 - IEEE SI Curve & IAC Curve Characteristics ................................................................................ 401

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List of Tables
Table 1 - Relay Features ......................................................................................................................................... 5

Table 2 - LED Indications .................................................................................................................................... 12
Table 3 - Relay Settings ........................................................................................................................................ 22
Table 4 - Configuration Settings - I ...................................................................................................................... 29
Table 5 - Configuration Settings - II..................................................................................................................... 30
Table 6 - Configuration Settings - III ................................................................................................................... 30
Table 7 - Configuration Settings - IV ................................................................................................................... 31
Table 8 - Configuration Settings - V .................................................................................................................... 32
Table 9 - Configuration Settings - VI ................................................................................................................... 33
Table 10 - Configuration Settings - VII ................................................................................................................ 34
Table 11 - Configuration Settings - VIII .............................................................................................................. 35
Table 12 - Configuration Settings - IX ................................................................................................................. 36
Table 13 - Local / Remote BI Settings ................................................................................................................. 37
Table 14 - Configuration Settings - X .................................................................................................................. 37
Table 15 - Configuration Settings - XI ................................................................................................................. 38
Table 16 - Configuration Settings - XII ................................................................................................................ 40
Table 17 - Communication Settings - I ................................................................................................................. 65
Table 18 - Communication Settings - II ............................................................................................................... 66
Table 19 - DR Settings ......................................................................................................................................... 71
Table 20 - Event Records ..................................................................................................................................... 77
Table 21 - Bias Differential Protection Settings ................................................................................................. 101
Table 22 - Bias Differential Protection Signals .................................................................................................. 102
Table 23 - Bias Differential Protection Settings in IEC 61850 Logical Node .................................................... 102
Table 24 - Bias Differential Protection Signals in IEC 61850 Logical Node ..................................................... 103
Table 25 - Interposing CT Selection ................................................................................................................... 105
Table 26 - Restricted Earth-fault Protection Settings ......................................................................................... 110
Table 27 - Restricted Earth-fault Protection Signals .......................................................................................... 110
Table 28 - Restricted Earth fault Protection in IEC 61850 Settings Logical Node ............................................. 111
Table 29 - Restricted Earth fault Protection Signals in IEC 61850 Logical Node .............................................. 111
Table 30 - Standard IDMT Curves for Overcurrent Protection .......................................................................... 123
Table 31 - Overcurrent Protection Settings ........................................................................................................ 124
Table 32 - Overcurrent Protection Signals ......................................................................................................... 126
Table 33 - Overcurrent Protection Settings in IEC 61850 Logical Node ........................................................... 126
Table 34 - Overcurrent Protection Signals in IEC 61850 Logical Node ............................................................ 127
Table 35 - Standard IDMT Curves for Derived Earth-fault Protection .............................................................. 136
Table 36 - Derived Earth-fault Protection Settings............................................................................................. 137
Table 37 - Derived Earth-fault Protection Signals .............................................................................................. 138
Table 38 - Derived Earth fault Protection in IEC 61850 Settings Logical Node ................................................ 139
Table 39 - Derived Earth fault Protection Signals in IEC 61850 Logical Node ................................................. 139
Table 40 - Standard IDMT Curves for Measured Earth-fault Protection ........................................................... 145
Table 41 - Measured Earth-fault Protection Settings .......................................................................................... 146
Table 42 - Measured Earth-fault Protection Signals ........................................................................................... 147
Table 43 - Measured Earth fault Protection in IEC 61850 Settings Logical Node ............................................. 148
Table 44 - Measured Earth fault Protection Signals in IEC 61850 Logical Node .............................................. 148
Table 45 - Standard IDMT Curves for Negative Phase Sequence Overcurrent Protection ................................ 155
Table 46 - Negative Phase Sequence Overcurrent Protection Settings ............................................................... 156
Table 47 - Negative Phase Sequence Overcurrent Protection Signals ................................................................ 157
Table 48 - Negative Phase Sequence Overcurrent Protection in IEC 61850 Settings Logical Node ................. 158
Table 49 - Negative Phase Sequence Overcurrent Protection Signals in IEC 61850 Logical Node ................... 158
Table 50 - Standard IDMT Curves for Thermal Overload Protection ................................................................ 161
Table 51 - Thermal Overload Protection Settings .............................................................................................. 161
Table 52 - Thermal Overload Protection Signals ............................................................................................... 162
Table 53 - Thermal Overload Protection in IEC 61850 Settings Logical Node ................................................. 162
Table 54 - Thermal Overload Protection Signals in IEC 61850 Logical Node .................................................. 163
Table 55 - Under Current Protection Settings..................................................................................................... 166
Table 56 - Under Current Protection Signals ...................................................................................................... 167

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Table 57 - Under Current Protection Settings in IEC 61850 Logical Node ....................................................... 167
Table 58 - Under Current Protection Signals in IEC 61850 Logical Node......................................................... 168
Table 59 - Standard IDMT Curves for Over Voltage Protection ........................................................................ 173
Table 60 - Over Voltage Protection Settings ...................................................................................................... 174
Table 61 - Over Voltage Protection Signals ....................................................................................................... 174
Table 62 - Over Voltage Protection Settings in IEC 61850 Logical Node ......................................................... 175
Table 63 - Over Voltage Protection Signals in IEC 61850 Logical Node .......................................................... 175
Table 64 - Standard IDMT Characteristics for Under Voltage Protection ......................................................... 181
Table 65 - Under Voltage Protection Settings .................................................................................................... 182
Table 66 - Under Voltage Protection Signals ..................................................................................................... 182
Table 67 - Under Voltage Protection Settings in IEC 61850 Logical Node ....................................................... 183
Table 68 - Under Voltage Protection Signals in IEC 61850 Logical Node ........................................................ 183
Table 69 - Standard IDMT Characteristic for Neutral Displacement Protection ................................................ 189
Table 70 - Neutral Displacement Protection Settings ......................................................................................... 189
Table 71 - Neutral Displacement Protection Signals .......................................................................................... 190
Table 72 - NDR Protection in IEC 61850 Settings Logical Node ...................................................................... 190
Table 73 - NDR Protection Signals in IEC 61850 Logical Node ....................................................................... 190
Table 74 - Over Frequency Protection Settings .................................................................................................. 194
Table 75 - Over Frequency Protection Signals ................................................................................................... 194
Table 76 - Under Frequency Protection Settings ................................................................................................ 198
Table 77 - Under Frequency Protection Signals ................................................................................................. 198
Table 78 - Standard IDMT Curves for Over Fluxing Protection ........................................................................ 202
Table 79 - Over Fluxing Protection Settings ...................................................................................................... 203
Table 80 - Over Fluxing Protection Signals ....................................................................................................... 203
Table 81 - Over Fluxing Protection Settings in IEC 61850 Logical Node ......................................................... 203
Table 82 - Over Fluxing Protection Signals in IEC 61850 Logical Node .......................................................... 204
Table 83 - Circuit Breaker Failure Protection Settings ....................................................................................... 208
Table 84 - Circuit Breaker Failure Protection Signals ........................................................................................ 208
Table 85 - Trip Circuit Supervision Settings ...................................................................................................... 211
Table 86 - Close Circuit Supervision Settings .................................................................................................... 214
Table 87 - IEC 61850 Structure .......................................................................................................................... 218
Table 88 - Startup Parameters............................................................................................................................. 226
Table 89 - Startup Parameters & their maximum values .................................................................................... 227
Table 90 - Goose Parameters .............................................................................................................................. 231
Table 91 - RCB Option Fields ............................................................................................................................ 233
Table 92 - RCB Parameters ................................................................................................................................ 234
Table 93 - System Requirements ........................................................................................................................ 280

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Abbreviations & Symbols
3I> IDMT OC Protection

3I>> High set OC Protection
ANSI American National Standards Institute
AWG American Wire Gauge
BI Binary Input
BO Binary Output
BD Biased differential Protection
BD HS BD High set Protection
BF Breaker Failure
CONF Configuration
CURR Current Measurements
DR Disturbance Recorder
DT Definite Time
EF Earth Fault
ESD Electrostatic Discharge
FL-R Fault Record
HV High Voltage
ICT Interposing Current Transformer
Inst Instantaneous
IDMT Inverse Definite Minimal Time
IEC International Electro technical Commission
IEEE Institute of Electrical and Electronics Engineers
INFO Information
Io> IDMT Derived Earth fault protection
Io>> High set Derived Earth fault protection
Ig> IDMT Measured Earth fault protection
Ig>> High set Measured Earth fault protection
I2> IDMT Negative Sequence OC Protection
I2>> High set Negative Sequence OC Protection
LCD Liquid Crystal Display
LED Light Emitting Diode
LV Low Voltage
MESR Measurements
NDR Neutral Voltage Displacement
NV No Volt
OC Over Current
OFLX Over fluxing
OV Over Voltage
PROT Protection
Ref Restricted earth fault Protection
SCADA Supervisory Control and Data Acquisition

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SUPR Supervision
THRM Thermal Overload Protection
UC Under current
USB Universal Serial Bus
UV Under Voltage
VOLT Voltage Measurements
VT Voltage Transformer

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1 BASIC FUNCTIONS
CROMPTON GREAVES LIMITED PAGE 1

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Section Overview
This section describes the overall functioning of CG Aegis Series Transformer

Protection Relays. The section includes following aspects related to the relay:
 Relay Features
 Hardware Description
 Relay Settings & Navigation of each menu
 Technical Data
 Connections & Wiring Diagram
 Dimensions of the relay
 Ordering Information

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1.1 GENERAL
The first part of the publication contains general description & operating instructions of
AEGIS Series Transformer Protection Relay. It also includes instructions for
parameterization and configuration of the Relay.
1.1.1 Philosophy
The following figure shows the architecture for a numerical protection relay:
Figure 1 - Architecture of Numerical Protection Relay
The device samples 3 phase quantities (current and voltage) which are at power system
level. The levels of these signals are reduced by transducers, i.e voltage and current
transformers. Current transformer converts a primary current into a secondary current through
a magnetic medium. Voltage transformer steps down the system voltage to a safer value for
further processing.
Transformers provide electric & static isolation between analog input variables and
internal electronic circuits, and adjust the signal to a suitable level for processing. The outputs
of transducers are applied to Signal Conditioner or analog input subsystem.

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Signal Conditioner brings real world signals into the digitizer. This block includes
various amplifiers to increase the gain, and thus strengthen the signals. It also converts
currents to equivalent voltages. Filtering is done to avoid aliasing effect and suppress HF
interferences.
The outputs of Signal Conditioner containing the phase information are applied to the a
16-bit SAR analog to digital converter. After sampling and quantization by ADC, analog
electrical signals are represented by discrete values of samples taken at specified instants of
time. The output from ADC is fed to the 32-bit Digital Signal Processor. Also, the status of
CB is given to the ADC via digital input subsystem. Digital Inputs allows the DSP to detect
logic states.
The device is fully designed using numerical technology. This means that all the signal
filtering, protection and control functions are implemented through digital signal processing.
The DSP processes the signals in form of discrete numbers by a incorporating a relaying
algorithm using numerical methods. A relaying algorithm which processes the acquired
information is a part of the software. The algorithm uses signal processing technique to
estimate the real and imaginary components of fundamental voltage and frequency phasors.
The computed quantities are compared with pre-specified thresholds to decide whether
the system is experiencing a fault or not. If there is a fault, the device issues an alarm signal
or sends a trip command to the circuit breakers to isolate the faulted zone of power system.
The trip output is transmitted to the power system through digital output subsystem. Digital
Outputs allow the processor to output the logic states.
It is important to know the occurrence of an event, fault, and its type, and the time at
which it occurs. This job is accurately done by Real Time Clock by giving time stamps at
regular intervals. Non-volatile memories are used to store the fault records, various
parameters and settings which determine functioning of the device. A graphical LCD display
is provided to view the relay features, system voltages, current phase angle values and
various settings. Keypad is given for configuring the relay input parameters.
The IED needs to communicate with the outside world. So, a requirement of an
Ethernet port is mandatory in these types of devices, which is required for MODBUS on
TCP/IP, IEC61850, and IEC60870-103 on TCP/IP types of protocol. But, DSP does not have
any Ethernet (MAC) port, also it is dedicated for signal and application processing purposes
and hence, it does not possess the power for Ethernet communication. An ARM processor is
therefore incorporated in the design, which has a 32-bit RISC core and operates at, upto 456
MHz. It is capable of processing 32-bit, 16-bit, or 8-bit data.

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1.1.2 Relay Features
The comprehensive protection functions of the relay make it ideal for utility & industrial
power distribution applications. The relay features following protection functions:
ANSI No. FUNCTION NAME

87 Biased Differential - Two Winding
87 HS High-Set Differential
64H High Impedance REF
Instantaneous and Inverse time phase over current
50/51
protection
Instantaneous and Inverse time Derived Earth fault
PROTECTION FUNCTIONS
50N/51N
protection
Instantaneous and Inverse time Measured Earth fault
50G/51G
protection
37 Under Current
Instantaneous and Inverse time phase Under Voltage
27
protection
Instantaneous and Inverse time phase Over Voltage
59
protection
59N Neutral Displacement Protection
46 Negative Phase Sequence Over current
49T Three-phase thermal overload
50BF Circuit Breaker failure Protection
81HBL2/4/5 Inrush Detector ( 2nd,,4th & 5th Harmonic blocking)
24 Over Fluxing
81U / O Under / Over frequency
74TCS Trip Circuit Supervision
MEASUREMENTS
Three Phase HV & LV side Current
& MONITORING
Neutral current for both HV & LV
FUNCTIONS
Sequence Components of Currents
IEC 60870-5-103
COMM
MODBUS
IEC61850
Table 1 - Relay Features
The comprehensive protection functions of the relay make it ideal for utility &
industrial power distribution applications. The relay features following protection Functions.

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1.1.3 Health & Safety
The information in the Safety Section of the equipment documentation is intended to

ensure that equipment is properly installed and handled in order to maintain it in a safe
condition.
It is assumed that everyone who will be associated with the equipment will be familiar
with the contents of that Safety Section, or this Safety Guide.
When electrical equipment is in operation, dangerous voltages will be present in certain

parts of the equipment. Failure to observe warning notices, incorrect use, or improper use
may endanger personnel and equipment and cause personal injury or physical damage.
Before working in the terminal strip area, the equipment must be isolated.
Proper and safe operation of the equipment depends on appropriate shipping and
handling, proper storage, installation and commissioning, and on careful operation,
maintenance and Servicing. For this reason only qualified personnel may work on or operate
the equipment.
Qualified personnel are individuals who
 are familiar with the installation, commissioning, and operation of the equipment and of
the system to which it is being connected;
 are able to safely perform switching operations in accordance with accepted safety
engineering practices and are authorised to energize and de-energize equipment and to
isolate, ground, and label it;
 are trained in the care and use of safety apparatus in accordance with safety Engineering
practices;
 are trained in emergency procedures (first aid).
The operating manual for the equipment gives instructions for its installation,
commissioning, and operation. However, the manual cannot cover all conceivable
circumstances or include detailed information on all topics. In the event of questions or
specific problems, do not take any action without proper authorization.
1.1.3.1 Installing, Commissioning & Servicing
Equipment connection
Personnel undertaking installation, commissioning or servicing work for this equipment

should be aware of the correct working procedures to ensure safety.

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The equipment documentation should be consulted before installing, commissioning or

servicing the equipment.
Terminals exposed during installation, commissioning and maintenance may present a

hazardous voltage unless the equipment is electrically isolated.
Any disassembly of the equipment may expose the parts at hazardous voltage, also
electronic parts may be damaged if suitable electrostatic voltage discharge (ESD)
precautions are not taken.
If there is unlocked access to the rear of the equipment, care should be taken by all
personnel to avoid electric shock or energy hazards.
Voltage and current connections should be made using insulated crimp terminations to
ensure that terminal block insulation requirements are maintained for safety.
To ensure that wires are correctly terminated the correct crimp terminal and tool for the
wire size should be used.
The equipment must be connected in accordance with the appropriate connection diagram.
Equipment use
If the equipment is used in a manner not specified by the manufacturer, the protection
provided by the equipment may be impaired.
Removal of equipment front panel/cover
Removal of the equipment front panel/cover may expose hazardous live parts which must
not be touched until the electrical power is removed.
Equipment operations conditions
The equipment should be operated within the specified electrical and environmental limits.

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Current Transformer Circuits
Do not open the secondary circuit of a live CT since the high voltage produced may be
lethal to personnel and could damage insulation. Generally, for safety, the secondary of the
line CT must be shorted before opening any connections to it.
For most equipment with ring-terminal connections, the threaded terminal block for current
transformer termination has automatic CT shorting on removal of the module. Therefore
external shorting of the CTs may not be required; the equipment documentation should be
checked to see if this applies.
For equipment with pin-terminal connections, the threaded terminal block for current
transformer termination does NOT have automatic CT shorting on removal of the module.
Insulation & Dielectric Strength Testing
Insulation testing may leave capacitors charged up to a hazardous voltage. At the end of
each part of the test, the voltage should be gradually reduced to zero, to discharge
capacitors, before the test leads are disconnected.
Insertion of modules & PCB cards
Modules and PCB cards must not be inserted into or withdrawn from the equipment whilst
it is energised, since this may result in damage.
Cleaning
The equipment may be cleaned using a lint free cloth dampened with clean water, when no
connections are energised.
1.1.3.2 Decommissioning & Disposal
Decommissioning:
The supply input (auxiliary) for the equipment may include capacitors across the supply or
to earth. To avoid electric shock or energy hazards, after completely isolating the supplies
to the equipment (both poles of any dc supply), the capacitors should be safely discharged
via the external terminals prior to decommissioning.

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Disposal:
It is recommended that incineration and disposal to water courses is avoided. The

equipment should be disposed of in a safe manner.
1.1.3.3 General Considerations
Receipt of relays
Protective relays, although generally of robust construction, require careful treatment

prior to installation on site. Upon receipt, relays should be examined immediately to ensure
no damage has been sustained in transit. If damage has been sustained during transit a claim
should be made to the transport contractor and Crompton Greaves Ltd. should be promptly
notified.
Electrostatic discharge
The relays use components that are sensitive to electrostatic discharges. The
electronic circuits are well protected by the metal case and the internal module should not
be withdrawn unnecessarily. When handling the module outside its case, care should be
taken to avoid contact with components and electrical connections. If removed from the
case for storage, the module should be placed in an electrically conducting antistatic bag.
There are no setting adjustments within the module and it is advised that it is not
unnecessarily disassembled. Although the printed circuit boards are plugged together, the
connectors are a Manufacturing aid and not intended for frequent dismantling; in fact
considerable effort may be required to separate them. Touching the printed circuit board
should be avoided, since complementary metal oxide semiconductors (CMOS) are used,
which can be damaged by static electricity discharged from the body.
1.1.3.4 Handling of Electronic Equipment
A person‟s normal movements can easily generate electrostatic potentials of several

thousand volts. Discharge of these voltages into semiconductor devices when handling
electronic circuits can cause serious damage, which often may not be immediately apparent
but the reliability of the circuit will have been reduced.
The electronic circuits are completely safe from electrostatic discharge when housed in
the case. Do not expose them to risk of damage by withdrawing modules unnecessarily.
Each module incorporates the highest practicable protection for its semiconductor
devices. However, if it becomes necessary to withdraw a module, the following precautions

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should be taken to preserve the high reliability and long life for which the equipment has
been designed and manufactured.
 Before removing a module, ensure that you are at the same electrostatic potential as the
equipment by touching the case.
 Handle the module by its front plate, frame or edges of the printed circuit board. Avoid
touching the electronic components, printed circuit track or connectors.
 Do not pass the module to another person without first ensuring you are both at the same
electrostatic potential. Shaking hands achieves equipotential.
 Place the module on an antistatic surface, or on a conducting surface which is at the same
potential as yourself.
 Store or transport the module in a conductive bag.
If you are making measurements on the internal electronic circuitry of equipment in service,
it is preferable that you are earthed to the case with a conductive wrist strap. Wrist straps
should have a resistance to ground between 500kΩ – 10MΩ.
If a wrist strap is not available you should maintain regular contact with the case to prevent a
build-up of static. Instrumentation which may be used for making measurements should be
earthed to the case whenever possible.
1.1.3.5 Storage
If relays are not to be installed immediately upon receipt they should be stored in a
place free from dust and moisture in their original cartons. Where de-humidifier bags have
been included in the packing they should be retained. The action of the de-humidifier crystals
will be impaired if the bag has been exposed to ambient conditions and may be restored by
gently heating the bag for about an hour, prior to replacing it in the carton. Dust which
collects on a carton may, on subsequent unpacking, find its way into the relay; in damp
conditions the carton and packing may become impregnated with moisture and the
dehumidifier will lose its efficiency.
Storage temperature: –25°C to +70°C.

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1.2 HARDWARE DESCRIPTION

1.2.1 Relay Front Panel
The below figure 1 shows the front panel of the AEGIS Series Transformer Protection Relay
and the location of the user interface elements for the local control of relay.
Figure 2 - Front Panel of Transformer Protection Relay
1. LED Indicators
2. 160x160 LCD Display
3. Keypad
4. Serial Port
5. Model Number

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1.2.1.1 LED Indicators
This Relay provided with 16 LED Indicators:
Power
Alarm
Trip
Error
Figure 3 - LED Indicators of Transformer Protection Relay
LED Indicator Meaning Remarks

Power Auxiliary power has been switched ON Normal operation state
Indicates that any one of the Protection
Fault indication of the Protection
Alarm or Monitoring function has been picked
and Monitoring functions
up due to fault
Indicates that Protection, Monitoring
functions has been operated due to
Trip Refer fault record for type of faults
faults which are in the enabled
condition.
For the particular error in the Relay
Error Indicates the internal faults of the Relay
refer section 3.3
We can set the LED operations as
12 Configurable LEDs for the indication self or hand resets while the
LEDS of Alarm & Trip signals of the operation of Protection and
Protection & Monitoring functions. Monitoring elements in the BI/BO
menu.
Table 2 - LED Indications
Resetting the Operated LEDs / Binary Outputs:
All the LEDs, Output Relays can be configured as Self reset or Hand Reset by using the
menus in the BI/BO window.
 If any protection function is operated and LEDs/Output Relays are Hand Reset, then
acknowledgement or Resetting is done by pressing the Esc( ) key in the keypad.

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 If any protection function is operated and LEDs/Output Relays are Self Reset, then
acknowledgement or Resetting is done automatically when the fault is cleared.
 We can activate or deactivate the LEDs/Output Relays by using the external Binary
Input.
1.2.1.2 LCD Display
AEGIS Series Feeder Protection Relay is having the display 160*160 Graphical
display. The purpose of this display is to show the configuration and parameterization values
of the relay.
Figure 4 - LCD Display of Transformer Protection Relay
Menu navigation and pointers
 Use the arrow keys UP ( ) and DOWN ( ) to move up and down in the main
Menu, that is on the left side of the display, the active main menu option is indicated
with a cursor. The options in the main menu are abbreviations. Ex: INFO (Information)
 After any selection in the Main Menu, the possible navigating directions are indicated
on the top of the Display window by arrows (,)
 The complete description of the selected menu is indicated on the top of Display
window(Ex: Information)
Backlight control
The display backlit is automatically switched OFF after 1 minute when left idle. It can be
switched on by pressing any key.

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1.2.1.3 Keypad
You can navigate the menu and set the required parameter values using the key pad and
directions indicated on the top of the display. Key pad is composed of four arrow keys for
navigation UP ( ), down ( ), Left ( ), Right ( ), ESC ( ), ENTER ( )
keys and CLOSE ( 0 ), TRIP ( I ) keys for the control of breaker.
3 4
5 6
Figure 5 - Keypad of Transformer Protection Relay
1. UP/DOWN Keys to navigate in Main Menu, to Increase/Decrease Numerical Values

and for Enable/Disable operations.
2. RIGHT/LEFT Keys to navigate in Sub-menu.
3. ESC Key to cancel the current selection and to reset the output relays/LED.
4. ENTER Key for edit & save the changed value.
5. CLOSE key is to close the breaker from the relay.
6. TRIP key is to trip the breaker from the relay.
1.2.1.4 Communication Port
The Front port of the relay is a standard USB port provided to communicate with PC. This
port is used for relay configuration, downloading fault, event and disturbance records.
The rear port is either a,
 Serial port
 Ethernet port
This port is used for communication with standard SCADA master/client softwares.

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1.2.2 Current Inputs
In total, eight current inputs are provided on the analog input modules. Terminals are
available for both 1A and 5A inputs. CT ratios are input by the user in the CONF menu.
Current is sampled at 1600Hz for 50Hz systems and 1920Hz for 60Hz systems (32 samples
per cycle). Depending on the frequency, the data will always be sampled according to 32
samples / cycle.
1.2.3 Voltage Inputs
A single voltage inputs is provided on the analog input modules. VT ratio is input by
the user in the CONF menu. Voltage is sampled at 1600Hz for 50Hz systems and 1920Hz for
60Hz systems (32 samples per cycle). Depending on the frequency, the data will always be
sampled according to 32 samples / cycle.
1.2.4 Binary Inputs (BIs)
The binary inputs are opto-couplers operated from a suitably rated dc supply. The
Aegis relays can be configured with 4 / 8 / 12 / 16 binary inputs (BI) as per the ordering
information. The user can assign any binary input to any of the available functions from the
BIBO menu. Pick-up and drop-off time delays are associated with each binary input. These
settings can be done from the DI Debounce settings in Configuration menu. Each BI may be
mapped to any of the front fascia LEDs and / or to any Binary output contact and can also be
used with the internal user programmable logic. This allows the relay to provide panel
indications and alarms.
1.2.5 Binary Outputs (BOs)
The Aegis relays can be configured with 4 / 8 / 12 / 16 binary outputs (BO) as per the
ordering information. All outputs are fully user configurable and can be programmed to
operate from any or all of the available functions. Out of the available BOs (eg. 8 BOs in this
case), six binary outputs are normally open (NO) contacts (BO 3 – BO 8) & two binary
outputs are change-over (CO) contacts (BO 1 & BO 2). BOs 1 – 4 & BOs 7 - 8 are signaling
contacts, whereas BOs 5 – 6 are heavy-duty contacts. In the default mode of operation, binary
outputs are self reset. If required, outputs can be programmed to operate as „hand reset‟. The
binary outputs can also be used to operate the trip coils of the circuit breaker directly.

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1.2.6 Virtual Inputs / Outputs (VIs / VOs)
The relays have 16 virtual input/outputs & these are internal logic states. The number of
these virtual I/Os can be extended upto 64 through the user programmable Logic in the
ConAegis Relay Communication Software. The Virtual I/O is assigned in the same way as
Binary Inputs and Binary Outputs. Virtual I/Os can be mapped from the BIBO menu, and can
be used to enable / disable a protection function or to change a setting group.
1.2.7 General Inputs (GIs)
The relays have 2 general inputs & these are internal logic states. The general input is
assigned in the same way as Binary Inputs, but the logic for operation of these inputs is to be
designed in the user programmable Logic in the ConAegis Relay Communication Software.
General inputs can be mapped from the BIBO menu, and can be used to enable / disable a
protection function or to change a setting group.
1.2.8 Non-Volatile Memory
The device stores some data in the non-volatile memory. This includes the 500 events
are visible on the display or from the ConAegis software. The Disturbance Record can be
stored in the memory for upto 3 days, and all the setting parameters remain saved
approximately upto 5 years at power off.
1.2.9 Flowchart For Menu Navigation
All the menu functions are based on the main menu/sub menu structure:
1. Use the arrow keys UP and DOWN to move up and down in the main menu.
2. To move to a sub menu, repeatedly push the RIGHT, LEFT key until the requested
submenu is shown as per the Indicated Arrows on the top of Display window
3. To move up and down in the Submenu use the UP and DOWN
4. At the any time to edit the value use the ENTER key, to increase or decrease the any
parameter value use UP and DOWN keys. Use the enter key to save the value.
5. To cancel the settings at any time press the Esc key.
6. At any time to return to main Menu Press the Esc key.

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Figure 6 - Principle of the menu structure and navigation in the menus
Main Menu
Menu structure of AEGIS Transformer Relay as shown in the below table, it describes the
total parameters available in the sub menus.

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No. of
Main
Submenus Para. in Description of Parameters
Menu
Submenus
Information 2 Relay Description, Model No. and Serial No.
Password 2 Setting Password and Default load password
Old Password, New Password & Confirm
Change Password 3
Password
INFO
Error 29 Internal faults indication in the relay.
Status of Protection Function: Enabled /
Protection Function Status 29
Disabled
BI - BO Status - Status of Binary inputs / outputs : ON / OFF
Primary phase Currents 6
Secondary phase Currents &
12
Phase Angle
Primary Earth Currents 4 Measured Values of the Primary &
Secondary Earth & Sequence Secondary System Currents, ICT Currents,
8
Currents Differential, Average and Harmonic
ICT Measured Currents 6 Currents.
CURR
Diff/Average Currents 6
2nd Harmonic Currents 6
4th Harmonic Currents 6
5th Harmonic Currents 6
Cum. Breaking Current 6 Cumulative Breaking Current
Phasor values of HV & LV in Graphical
Vector diagram -
vector representation
Primary/Secondary voltages 2
VOLT Measured Values of the System voltages.
Freq. Metering 2
Last 10 faults can be stored by the Relay.
Fault description shows the Fault No, Date &
FL-R Fault Recorder 21
time, Magnitudes and Phase angles of the
Fault Currents and Voltages.
Contains features for enabling/disabling , Pre
DR Disturbance Recorder 8 & Post fault conditions, sample rate &
trigger options for DR
Setting group Configuration 6 Setting groups can be changed.
Primary and Secondary Settings for the
Phase CT Configuration 4
phase CT
Primary and Secondary Settings for the
Earth CT Configuration 4
Earth CT
VT Configuration 6 Primary and Secondary Settings for the VT
CONF
Logic 2 Enable / Disable
ICT Multiplication and Phase correction
ICT Configuration 4
factors
2nd ,4th & 5th Harmonic
6 Settings of the 2nd, 4th and 5th Harmonics.
configuration
Trip / Close BO 4 Breaker control settings i.e. Close, Trip and

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IRF BO, Trip Alert, No. of BI / BO.

Trip / Close BI 4 Trip BI, Close BI, Loc / Rmt BI, Rmt Trip
DI Debounce Time 2 DI Pickup Time, DI Dropout Time
Auxiliary Fail BO 1 Auxiliary Fail BO
Calibration Settings 4 Calibration Settings

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Main No. of Para.

Submenus Description of Parameters
Menu in Submenus
Pickup. slope 1 and slope 1 limit, slope 2 and Inrush,
Bias differential 9
4th Harmonic & 5th harmonic can be set
Bias differential Bias differential high set settings , Inrush, 4th Harmonic
BD 6
high set & 5th harmonic can be set
LED/BO You can set LEDs & output Relays for the indication
2
Configuration and control on a fault.
REF Settings
6 REF settings for the HV and LV
(Stage1)
REF Settings
REF 6 REF settings for the HV and LV
(Stage2)
2
Configuration and control on a fault.
Thermal setting and operating time can be set for
Thermal HV 4
winding 1
Thermal setting and operating time can be set for
THRM Thermal LV 4
winding 2
2
Configuration and control on a fault
Over fluxing setting, operation characteristics and time
Over fluxing stage1 5
can be set for stage 1
Over fluxing Over fluxing setting, operation characteristics and time
OFLX 5
stage2 can be set for stage 2
2
Over current setting, operational characteristics and
HV Stage 1 7
time can be set for HV stage1
LV Stage 1 7
time can be set for LV stage1
3I> HV Stage 2 7
LV Stage 2 7
2
OC High set setting and operational time can be set for
HV Stage 1 4
HV Stage 1
LV Stage 1 4
LV Stage 1
3I>> HV Stage 2 4
HV Stage 2
LV Stage 2 4
LV Stage 2
2
Ig> HV Stage 1 7 Measured Earth fault setting, operational characteristics

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and time can be set for HV stage1

Measured Earth fault setting, operational characteristics
LV stage 1 7
and time can be set for LV stage1
HV Stage 2 7
LV Stage2 7
2
High set Measured Earth fault setting, operational
HV Stage 1 4
characteristics and time can be set for HV stage1
LV stage 1 4
Ig>> HV Stage 2 4
LV Stage 2 4
2
Derived Earth fault setting, operational characteristics
HV Stage 1 7
LV stage 1 7
Io> HV Stage 2 7
LV Stage2 7
2
Under current setting, operational time for the HV and
UC Set (Stage1) 8
LV windings can be set
UC Set Under current setting, operational time for the HV and
UC 8
(Stage 2) LV windings can be set
2
Over voltage setting, operational characteristics and
OV SET-IDMT 5
time can be set for selected winding
Instantaneous Over voltage setting, operational time
OV OV SET-INST 3
can be set for selected winding
2
Under voltage setting, operational characteristics and
UV SET-IDMT 6
UV
Instantaneous under voltage setting, operational time
UV SET-INST 3
LED/BO 2 You can set LEDs & output Relays for the indication

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NDR voltage setting, operational characteristics and
NDR SET-IDMT 6
Instantaneous NDR voltage setting, operational time
NDR NDR SET-INST 3
2
Over frequency setting, operational characteristics and
OF SET (Stage 1) 4
OF SET (Stage 2) 4
OFRQ OF SET (Stage 3) 4
OF SET (Stage 4) 4
2
Under frequency setting, operational characteristics and
UF SET (Stage 1) 4
Under frequency setting, operational characteristics and
UFRQ UF SET (Stage 2) 4
2
Breaker fail 4 Breaker fail settings can be set for both stage 1 and 2
Trip Circuit Supervision setting, operational
TCS Setting 5
characteristics and time can be set for selected winding
SUPR Close Circuit Supervision setting, operational
CCS Setting 5
characteristics and time can be set for selected winding
2
COMM Communication 6 Communication parameters can be set by this menu.
This menu allows user to set
1) External BIs to BOs
2) External BIs to LEDs
3) Internal (S/W) BIs to BOs
BI-O BI-BO settings 11 4) Internal (S/W) BIs to LEDs
5) LED and BO self/hand reset
6) Protection & Setting Group on BI
7) Protection & Setting Group on VI
8) Protection & Setting Group on GI
Latest 500 events can be stored by the Relay. Record
EVNT Event Records 9
shows the Event No & time
Table 3 - Relay Settings

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1.3 RELAY SETTINGS & NAVIGATION

The Relay has different setting windows as shown in figures below. The Relay Setup is
password protected for changing any parameter. The purpose of password is to prevent
accidental change of configurations, parameters or settings.
1.3.1 Device Info View
As you POWER ON the relay, INFORMATION window will appear on the screen. It
gives the information about the Relay‟s Type, Version, Model number & Serial number.
Figure 6 gives the complete idea about this menu.
Figure 7 - Device Info View
1.3.2 Password Accessing
The navigation described below is to set the password for changing the relay
configuration as shown in figure 7.
Figure 8 - Password Accessing - 1

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The password is to be entered is SETTING PASS setting. The password contains four
digits. These digits are entered from left to right one by one by moving to the position of digit
using the RIGHT key and then setting the desired digit value using the UP key. To save the
password, press the ENTER key. Please note that the default relay password is 0002.
In case of configuration data loss or any other file system error that prevents the IED
from working properly, the whole file system can be restored to the original factory state. All
default settings and configuration files stored in the factory are restored. The password to
load default settings is to be entered is DEFAULT LOAD setting. Please note that the
default relay password is 0009.
If the user tries to change any of the settings without entering the password, the device
shows following window:
Enter Setting
Password 1
Press ESC Key
Figure 9 - Password Accessing - 2
On Pressing ESC key, the next window appears where the user can enter the password.
After entering the correct password, the display screen shifts to the menu where the user was
previous trying to change the settings.
If the user wants to set a password of his choice, move into INFO  CHANGE
PASSWORD window. Enter the old / current password, & then, set the new password &
give the confirmation in respective settings as shown below.
CHANGE PASSWORD
OLD PASSWORD
XXXX
1 2 NEW PASSWORD
XXXX
CONFIRM PASS
XXXX
Figure 10 - Changing the Password

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1.3.3 Error Status View
This window is used to determine the type of internal error generated in the relay. The
errors can be Calibration Error, Memory Error, Protection function or Monitoring function
related error. Whenever the relay encounters a particular type of error, the ERROR LED
glows, and the corresponding status Ok / Err value is indicated in ERROR window. To
navigate the ERROR window follow procedure described below in figure 8.
1 2
Figure 11 - Error Status View
1.3.4 Protection Function Status View
This window determines the various protection functions currently enabled in the relay.
Similarly, the status of the binary input / outputs can also be observed.

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1.3.5 Current Measurement View (CURR)
This menu displays measured values of system Primary, Secondary Phase & Earth
currents, Differential and average currents, Sequence components of currents along with Date
and Time. It also displays Measured ICT Currents& Harmonic currents (2nd, 4th & 5th).
1 2 3
3 4 5 6
6 7 8
Figure 12 - Current Measurements View

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1.3.6 Voltage Measurement View (VOLT)
This menu displays Primary & Secondary voltages, frequency and V/f Measurements.
Figure 13 - Voltage Measurements View
The Last window in the measurement menu displays vector representation of 3 phase
system Currents as shown in figure 11.
IL3
IL1
IL2
Figure 14 - Graphical Representation
If the measurement window is left idle for 5 sec, you can observe the larger view than the
default one as shown in the figure 11.
Figure 15 - Zoom view of measurement window

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1.3.7 Configuration Settings (CONF)
Configuration Menu allows the user to set the system parameters like HV & LV Phase
and Earth CT Primary, Secondary ratios, system frequency, ICT, Harmonic and Breaker
control settings and the setting groups for the protection parameters. Figure shows some of
the navigation from the Configuration menu, & settings in each of the submenus have been
explained below.
1 2 3
3 4 5 6
6 7
Figure 16 - Configuration Settings

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 Active Group: The total active functional, protection parameter settings are based on the
ACTIVE GRP setting. Operation of the relay is based on the currently Active Group.
 Default Frequency: Decides the frequency of operation. The device calculates the
fundamental frequency from the 3-phase voltage and current when these incoming signals
are present. But in case of no load, the device uses this default frequency. If the panel is
operated / turned ON in such a situation, the device immediately samples the 3 –phase
quantities according to its sampling rate.
 View / Edit Group: The user can edit any group parameters irrespective of the Active
Group set by using VW/EDT GRP setting.
 Date: Sets the date in dd / mm / yy format.
 Time: Sets the time in hr / min / sec format.
 Trip Alert: This setting indicates the fault alert on the display. When Enabled, the
occurrence of a Trip will cause the relay to display the Fault Record screen & the only
way to leave this screen is by acknowledging the trip through the ESC key on the relay
front end.
Permissible Values
Configuration
Setting Range / Available Options Default
ACTIVE GRP 1/2/3/4 1
SYS FREQ 50Hz / 60Hz 50Hz
VW / EDT GRP 1/2/3/4 1
DATE dd / mm / yy -
TIME hr / min / sec -
TRIP ALERT Yes / No Yes
Table 4 - Configuration Settings - I

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 HV Phase CT Primary: These ratings can be configured as per user‟s requirement.
 HV Phase CT Secondary: Selects whether 1 or 5 Amp terminals are being used.
 LV Phase CT Primary: These ratings can be configured as per user‟s requirement.
 LV Phase CT Secondary: Selects whether 1 or 5 Amp terminals are being used.
Permissible Values
Configuration - Phase CT
HV CT PRI 1A - 5000A (Steps of 1A) 100A
HV CT SEC 1A / 5A 1A
LV CT PRI 1A - 5000A (Steps of 1A) 100A
LV CT SEC 1A / 5A 1A
Table 5 - Configuration Settings - II
 HV Earth CT Primary: These ratings can be configured as per user‟s requirement.
 HV Earth CT Secondary: Selects whether 1 or 5 Amp terminals are being used.
 LV Earth CT Primary: These ratings can be configured as per user‟s requirement.
 LV Earth CT Secondary: Selects whether 1 or 5 Amp terminals are being used.
Permissible Values
Configuration - Earth CT
HV CT PRI 1A - 5000A (Steps of 1A) 100A
HV CT SEC 1A / 5A 1A
LV CT PRI 1A - 5000A (Steps of 1A) 100A
LV CT SEC 1A / 5A 1A
Table 6 - Configuration Settings - III

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 VT Primary & Secondary: These ratings can be configured as per user‟s requirement.
 VT Connection Type: The user can change the VT connection type as PH-N or PH-PH.
 VT Type: If the user selects the VT TYPE as PH VT, the user can achieve OV, UV and
OFLX protections. For NDR protection function, VT TYPE setting should be NDR VT.
 CT Type: This parameter allows user to operate the relay in REF or EF (Ig) mode.
Default this relay supplied with inbuilt REF protection. For the Ig protection function,
Hardware CTs should comply with the selection.
Note: We can‟t select the both protection functions at a time.
 Auxiliary Protection: Back up protections like over current, Earth fault etc will protect
either HV or LV windings but not both.
Configuration
VT PRI 3.3kV-500kV (In steps of 0.1KV) 11.00kV
VT SEC 40V – 120V (In steps of 0.1V) 63.5V
VT CN TYPE PH-N / PH-PH PH - N
VT TYPE PH VT / NDR VT PH VT
CT TYPE REF / EF REF
AUX PROT HV / LV HV
Table 7 - Configuration Settings - IV

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 Logic: The logic file downloaded in the device will work only if this setting is enabled.
 Protection & Setting Group on Binary Inputs (BIs): The enabling / disabling of the
protection functions and the setting group changes to be done on activation of a BI will
work only if this setting is enabled.
 Measurement Scroll: The various windows in the Measurement menu keep scrolling
after a fixed time (approximately 1 minute) if this setting is enabled. If any other settings
are being configured in the device, and if device goes in idle state, the screen jumps to the
Measurement menu and all the windows in this menu keep scrolling. If disabled, the
window does not changed unless changed from the front end.
Permissible Values
Configuration
LOGIC Enable / Disable Disable
ProtSgOnIP Enable / Disable Disable
MESR SCROL Enable / Disable Enable
Table 8 - Configuration Settings - V

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1.3.7.1 Interposing Current Transformers
Internal current multipliers are used to adjust the CT secondary currents to

accommodate for any mismatch between the winding 1 and winding 2 CT ratios. Internal
interposing current transformers (ICT) are used to correct the CT secondary current phase
relationships in line with any phase change introduced by the transformer connections. Note
that the choice of interposing CT vector group will modify the effective operating levels of
the protection due to the current distribution for the various fault conditions.
 HV ICT Multiplier and LV ICT Multiplier: Sets the multiplying factor at HV and LV
side.
 HV ICT Connection and LV ICT Connection: Sets the current phase relationship.
Configuration
HV ICT MULT 0.25-5(In steps of 0.01) 1.00
HV ICT CONN Yy0 / Yd1 / Yy2 / Yd3 / Yy4 / Yd5 / Yy6 / Yd7 / Yy8 Yy0
/ Yd9 / Yy10 / Yd11 / Ydy0 / Ydy6
LV ICT MULT 0.25-5(In steps of 0.01) 1.00
LV ICT CONN Yy0 / Yd1 / Yy2 / Yd3 / Yy4 / Yd5 / Yy6 / Yd7 / Yy8 Yy0
/ Yd9 / Yy10 / Yd11 / Ydy0 / Ydy6
Table 9 - Configuration Settings - VI

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1.3.7.2 Harmonics Blocking
The settings in this submenu allow the user to set pickup values for harmonics & the DT
for which tripping of the respective protection functions will be blocked. 2nd harmonic
blocking has been provided for all the current protection functions, whereas 2nd & 5th
harmonic blocking has been provided for bias differential protection function. The user has to
select the setting If2> ACT as Yes to enable harmonic blocking.
 If2>, If4>, If5> Set Value: Sets the pickup value for 2nd, 4th, & 5th harmonics
respectively.
 If2>, If4>, If5> DT: Sets the delay after which tripping occurs.
Permissible Values
Configuration
68 If2> SET 0.30
68 If4> SET 0.10-0.50 (In steps of 0.01) 0.30
68 If5> SET 0.30
68 If2> DT 0.50s
68 If4> DT 0.02-10.00s (In steps of 0.02) 0.50s
68 If5> DT 0.50s
Table 10 - Configuration Settings - VII

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1.3.7.3 Trip / Close BO
 Trip BO: The assigned BO operates when trip signal is issued from the relay. This
operation is possible whether the selected CB Operation setting is Local or Remote.
 Close BO: The assigned BO operates when close signal is issued from the relay. This
operation is possible only when the setting CB Operation is Local.
 IRF BO: The assigned BO operates in case an LED glows due to some Internal Relay
Failure (IRF).
 CB Operation: Selects the Circuit Breaker Operation: Local / Remote. If the CB is

selected to operate locally, the CB trip / close can be performed from the front HMI of the
device. If the CB is selected to operate remotely, the CB trip / close can be performed
from the SCADA.
Note: We can‟t set the same output relay for both Trip and close.
Permissible Values
Trip / Close BO
TRIP BO None / BO 5 / BO 6 None
CLOSE BO None / BO 5 / BO 6 None
IRF BO None / BO 1 to BO 6 None
CB OPER Local / Remote Local
Table 11 - Configuration Settings - VIII

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1.3.7.4 Trip / Close BI
 CB OFF BI: This BI is used to check the CB OFF status coming from the switchgear.
 CB ON BI: This BI is used to check the CB ON status coming from the switchgear.
 SPC BI: This BI is used to check if the breaker spring is charged or not.
 TCS BI: The assigned BI is triggered to check if the trip circuit is healthy, else the
assigned LED & relay indicates unhealthy trip circuit.
 CCS BI: The assigned BI is triggered to check if the close circuit is healthy, else the
assigned LED & relay indicates unhealthy close circuit.
Permissible Values
Trip / Close BI
TRIP BI None
CLOSE BI None
SPC BI None / Any of the max. available BIs None
TCS BI None
CCS BI None
Table 12 - Configuration Settings - IX
 Remote BI Setting: This setting determines whether the operation of CB is remote based
on activation of BI.
 Local BI Setting: This setting determines whether the operation of CB is local based on
activation of BI.
The operation of both Local BI & Remote BI Setting in various scenarios can be
explained with the help of the following table:

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Local BI Remote BI Description

When neither of the BIs are selected for both the
Not Selected / Not Selected / settings, i.e. NONE, the operation of CB will be
NONE NONE determined by the CB OPERN setting, which can be
either local, or remote.
When any BI is selected in LOCAL BI setting, eg. BI
2, & none of the BIs is selected in REMOTE BI
Not Selected /
Selected / BIx setting, i.e. NONE, the CB operation will be Local if BI
NONE
2 is logic 1 / True. If BI 2 is logic 0 / False, the CB
operation will be Remote.
When any BI is selected in REMOTE BI setting, eg.
BI 2, & none of the BIs is selected in LOCAL BI
Not Selected /
Selected / BIx setting, i.e. NONE, the CB operation will be Remote if
NONE
BI 2 is logic 1 / True. If BI 2 is logic 0 / False, the CB
operation will be Local.
When BIs have been assigned for both the settings, the
REMOTE BI setting supersedes the LOCAL BI
Selected / BIx Selected / BIx
setting, i.e. the CB operation will be remote on priority,
irrespective of the settings configured elsewhere.
Table 13 - Local / Remote BI Settings
 Remote Trip: Whenever a selected BI in this setting is activated, it results in a remote

trip. This trip condition is time stamped & shown in the fault record menu.
Permissible Values
Configuration
RMT BI None
LOCBI None / Any of the max. available BIs None
RMT TRIP None
Table 14 - Configuration Settings - X

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1.3.7.5 Hysteresis
This submenu helps the user to configure the pickup and dropout values for IDMT and
Instantaneous Settings in case of hysteresis.
 IDMT Pickup: Sets the pick up value, i.e, alarm signal will be issued when the measured
quantity exceeds this value.
 IDMT Reset: Sets the drop off value, i.e, normal operation will resume when the
measured quantity drops down below this value.
 INST Pickup: Sets the pick up value, i.e, alarm signal will be issued when the measured
 INST Reset: Sets the drop off value, i.e, normal operation will resume when the
Hysteresis
IDMT PKUP 1.01 - 1.10 1.050
IDMT RST 0.90 - 0.99 0.950
INST PKUP 1.01 - 1.10 1.050
INST RST 0.90 - 0.99 0.950
Table 15 - Configuration Settings - XI

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1.3.7.6 DI Debounce Time
 DI Debounce Pick up: Sets the minimum time for which the assigned DI should be
triggered so as to be considered as active. The DI Debounce Time helps to eliminate
debounces and short disturbances on a binary input. Consider a following example shown
in figure which shows two possible scenarios. The DI pick up time is set as 20ms. In the
first case, the input signal picks up but drops off immediately before the 20ms. Hence, the
output signal stays low and DI remains to be logic „0‟. In the second case, the input signal
picks up & stays high for more than 20ms, i.e. the DI Debounce Pick up time. Hence the
output signal goes high and DI status becomes logic „1‟, or we can say that DI pick up has
occurred.
Figure 17 - DI Pick up
 DI Debounce Drop off: Sets the minimum time for which the assigned DI should drop
down so as to be considered as inactive. The DI Debounce Time helps to eliminate
debounces and short disturbances on a binary input. Consider a following example shown
in figure which shows two possible scenarios. The DI drop off time is set as 20ms. In the
first case, the input signal drops off but picks up immediately before the 20ms. Hence, the
output signal stays high and DI remains to be logic „1‟. In the second case, the input
signal drops off & stays low for more than 20ms, i.e. the DI Debounce Drop off time.
Hence the output signal goes low and DI status becomes logic „0‟, or we can say that DI
drops off has occurred.

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Figure 18 - DI Drop off
Permissible Values
DI DBNC Time
DI DBNC PICKUP 030ms
10 - 100 ms
DI DBNC DROP 030ms
Table 16 - Configuration Settings - XII
 The Calibration Settings submenu is for internal use only.
 Total BIs / BOs: This is a non-editable setting and gives the number of BIs / BOs present
in the device.
 DSP Program: This setting is for internal use only.

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1.3.8 Biased Differential Protection (BD) (87)
The biased differential protection 87BD is used to detect transformer faults within the
zone defined by comparing the current on the primary and secondary side of transformer.
Therefore current transformers are located on primary and secondary side of power
transformer. The differential protection is based on difference of the winding currents
between HV and LV side. In transformer applications the current calculation depends on
transformer connection group.
The following figure shows navigation of various settings & LED & BO configurations
for both stages of bias differential protection.
1 2 3
3 4
Figure 19 - Biased Differential Protection Navigation

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1.3.9 Restricted Earth Fault Protection (Ref) (64H)
The restricted earth-fault protection function is useful in protection of generators and

power transformers. The single phase current input is derived from the residual output of
line/neutral CTs connected in parallel. An external stabilising resistor must be connected in
series with this input to ensure that this element provides a high impedance path.
for both stages of Restricted earth fault protection for both, HV & LV side.
1 2 3
Figure 20 - Restricted Earth Fault Protection Navigation

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1.3.10 Thermal Overload Protection (THRM) (49)
Transformer thermal overload protection is designed to protect the equipment from

sustained overload that results in the machine‟s thermal rating being exceeded. Thermal
overload protection compliments the transformer overcurrent protection by allowing modest
but transient overload conditions to occur, while tripping for sustained overloads that the
overcurrent protection will not detect.
for Thermal Overload Protection for both, HV & LV side.
1 2 3
Figure 21 - Thermal Overload Protection Navigation

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1.3.11 Over Fluxing Protection (OFLX) (24)
Magnetic flux in the transformer core is directly proportional to the voltage and
inversely proportional to the frequency. Higher the V/f ratio, the greater is the magnetizing
current that might to heating and insulation failure. The over fluxing protection function
detects high flux level in the iron core of transformers as caused by a voltage increase or a
frequency decrease, or both.
for Over Fluxing Protection.
1 2 3
Figure 22 - Over Fluxing Protection navigation.

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1.3.12 Over Current Protection (3I> & 3I>>) (51 / 50)
Overcurrent is an occurrence of a situation where a higher magnitude than the intended

current exists through a conductor, which may lead to damage to the equipment. Most of the
power system faults result in overcurrent of one kind or another, and it is the duty of
protection devices, to protect the power system from such faults.
for IDMT & INST stages of Overcurrent Protection for both, HV & LV side.
1 2 3
3 4 5
Figure 23 - IDMT Over Current Protection Navigation

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1 2 3
3 4 5
Figure 24 - INST Over Current Protection Navigation

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1.3.13 Measured Earth Fault Protection (Ig> & Ig>>) (51G /

50G)
Earth faults are nothing but overcurrent faults, where fault current flows to earth. This
is the most commonly occurring fault, and is hence covered by all the protection devices.
Earth fault protection is used to detect earth faults in low impedance earthed networks. Here,
the earth current which is measured directly via dedicated current analog inputs.
for IDMT & INST stages of Measured Earth Fault Protection for both, HV & LV side.
1 2 3
3 4 5
Figure 25 - IDMT Measured Earth Fault Protection Navigation

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1 2 3
3 5
4
Figure 26 - INST Measured Earth Fault Protection Navigation

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1.3.14 Derived Earth Fault Protection (Io> & Io>>) (51N / 50N)
Earth fault protection is used to detect earth faults in low impedance earthed networks. Here,
the earth current is derived by calculating the sum of the measured line currents.
for IDMT & INST stages of Derived Earth Fault Protection for both, HV & LV side.
1 2 3
3 4 5
Figure 27 - IDMT Derived Earth Fault Protection Navigation

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1 2 3
3 4 5
Figure 28 - INST Derived Earth Fault Protection Navigation

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1.3.15 Negative Phase Sequence Over Current Protection (I2>

& I2>>) (46)
Any unbalance fault condition produces negative phase sequence current of some
magnitude which could not be previously identified by the traditional phase overcurrent as
well as the residual overcurrent protection techniques. This can be now achieved by the
Negative phase sequence overcurrent protection element. A negative phase sequence element
can operate for both phase and earth faults. This kind of protection gives greater sensitivity
compared overcurrent and earth fault protection elements.
for IDMT & INST stages of Negative Phase Sequence Overcurrent Protection for both, HV
& LV side.
1 2 3
3 4 5
Figure 29 - IDMT Negative Phase Sequence Overcurrent Protection Navigation

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1 2
3
Figure 30 - INST Negative Phase Sequence Overcurrent Protection Navigation

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1.3.16 Under Current Protection (UC) (37)
Drop in current beneath the defined level this indicates a low load or CB open
condition. It may also be possible that no current is flowing. The undercurrent function can
be used as a fault current check i.e. that no fault current continues to flow, or as a check that a
CB has opened. This can be used in addition to or in place of CB auxiliary switch indications.
for both stages of Undercurrent Protection for both, HV & LV side.
1 2 3
Figure 31 - Under Current Protection Navigation

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1.3.17 Over Voltage Protection (OV) (59)
Overvoltage conditions are generally related to loss of load conditions, where the
supply voltage is increased in magnitude. Abnormally high voltages often occur in low
loaded, long distance transmission lines, in islanded systems when generator voltage
regulation fails, or after full load rejection of a generator from the system.
for IDMT & INST stages of Over Voltage Protection.
1 2 3
Figure 32 - Over Voltage Protection Navigation

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1.3.18 Under Voltage Protection (UV) (27)
Under voltage conditions may occur on a power system for a variety of reasons and is
mostly related to increased loads, where the supply voltage decreases in magnitude. This
situation would normally be rectified by voltage regulating equipment. However, if the
regulating equipment proves to be unsuccessful in restoring healthy system voltage, tripping
by means of an under voltage element is required.
for IDMT & INST stages of Under Voltage Protection.
1 2 3
Figure 33 - Under Voltage Protection Navigation

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1.3.19 NDR Protection (NDR) (59N)
Due to occurrence of earth fault on the primary system, the balance of three-phase
power system gets disturbed producing a residual voltage. This circumstance causes a rise in
the neutral voltage with respect to earth. Therefore, this protection is also commonly referred
to as 'Neutral Voltage Displacement'. Voltage Setting applied to the protection elements is
dependent on the magnitude of the residual voltage that is expected to occur during the fault
conditions.
for IDMT & INST stages of NDR Protection.
1 2 3
Figure 34 - NDR Protection Navigation

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1.3.20 Breaker Failure Protection (SUPR) (50BF)
The operation of circuit breaker is vital to isolate the fault or at least limit the damage to
the power system. After protection function generates a trip command, it is expected that the
circuit breaker opens and/or the fault current drops below the pre-defined normal level. But if
the fault does not disappear within a given time after the initial trip command, circuit breaker
failure protection can be used to trip any upstream circuit breaker (CB). CBF protection
monitors the circuit breaker and establishes whether it has opened within a reasonable time. If
the fault current has not been interrupted following a set time delay from circuit breaker trip
initiation, the CBF protection will operate, whereby the upstream circuit breakers are tripped
to ensure that the fault is isolated.
for both stages of breaker failure protection.
1 2
Figure 35 - Breaker Failure Protection Navigation

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1.3.21 Binary Input & Binary Output Settings (BI-O)
The relay has multiple Binary inputs & Binary outputs. This configuration allows
programming or assigning any relay output for any fault Pick-up and trip condition. The
binary outputs can also be configured on to operate on activation of binary inputs. Also,
protection on binary inputs (BI), virtual inputs (VI), or general inputs (GI) can be enabled.
Figure shows navigation of some of the screens from the BI-O menu, & settings in
each of the settings have been explained below.
Figure 36 - Binary Inputs & Outputs Settings
1.3.21.1 Configuring External Binary Inputs (BIs) to Binary Outputs

(BOs)
If a user wishes to configure an external BI to operate any BO, for eg., on occurrence of
a alarm, trip or settings of a protection function, the function can be used. When the user
selects Yes in EXT BI-BO setting, the display shows a matrix which allows the user to
configure any BI to any BO. Selecting the crosspoint and changing the value from OFF to
ON ensures this assignment.
1.3.21.2 Configuring External Binary Inputs (BIs) to LEDs
LEDs can be assigned to indicate the status of external BIs (active / inactive). When the
user selects Yes in EXT BI-LED setting, the display shows a matrix which allows the user to
configure any BI to any of the LEDs 5 - 16. Selecting the crosspoint and changing the value
from OFF to ON ensures this assignment.

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1.3.21.3 Self / Hand Reset
All the LEDs and BOs can be configured as Self Reset or Hand Reset. These are
usually Self Reset by default, i.e. the dedicated LEDs and BOs operate at the end of the DT.
In case of Hand Reset, the LEDs and BOs do not reset after the condition is passed, unless the
ESC key is pressed on the relay. When the user selects Yes in SELF / HAND RESET
setting, the display shows the status of LEDs and BOs, whether they are configured to
operate on self reset or hand reset. Hand Reset and Self Reset are denoted as HR and SR
respectively. Selecting the particular LED / BO and changing the value from SR to HR, or
vice versa ensures this assignment.
1.3.21.4 Protection on Binary Inputs (BIs)
This setting is used to enable / disable the operation of any protection function based on
an active BI. When the user selects Yes in PROT ON BI setting, the display shows a matrix
which allows the user to configure any protection function to any of the available BIs.
Selecting the crosspoint and changing the value from ENABLE to DISABLE or vice versa
ensures this assignment. If NONE is selected, the protection function can be only enabled
from the respective protection function settings.
1.3.21.5 Setting Group on Binary Inputs (BIs)
This setting enables the user to assign a BI to a particular Setting Group. This means
that the various protection settings defined in a Setting Group can be enabled, simply on the
activation of the assigned BI. Any of the available BIs can be assigned to any setting group.
When the user selects Yes in SET. GRP ON BI setting, the display shows the status of BIs.
Selecting the particular BI and changing the value from Group 1 to Group 4 ensures this
assignment. If NONE is selected, the setting group selected in the Configuration menu will
be active.
1.3.21.6 Protection on Virtual Inputs (VIs) (Applicable to IEC 61850

compatible IEDs only)
Similar to Protection on BI setting, this setting is used to enable / disable the operation
of any protection function based on an active VI. When the user selects Yes in PROT ON VI
setting, the display shows a matrix which allows the user to configure any protection function
to any of the VIs. Selecting the crosspoint and changing the value from ENABLE to
DISABLE or vice versa ensures this assignment. If NONE is selected, the protection
function can be only enabled from the respective protection function settings.

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1.3.21.7 Setting Group on Virtual Inputs (VIs) (Applicable to IEC 61850

compatible IEDs only)
Similar to the Setting Group on BI setting, this setting enables the user to assign a VIs
to a particular Setting Group. This means that the various protection settings defined in a
Setting Group can be enabled, simply on the activation of the assigned VI. Any of the VIs
can be assigned to any setting group. When the user selects Yes in SET. GRP ON VI setting,
the display shows the status of VIs. Selecting the particular VI and changing the value from
Group 1 to Group 4 ensures this assignment. If NONE is selected, the setting group selected
in the Configuration menu will be active.
1.3.21.8 Protection on General Inputs (GIs)
of any protection function based on an active GI. When the user selects Yes in PROT ON GI
setting, the display shows a matrix which allows the user to configure any protection function
to any of the GIs. Selecting the crosspoint and changing the value from ENABLE to
DISABLE or vice versa ensures this assignment. If NONE is selected, the protection
function can be only enabled from the respective protection function settings. Here, the user
must note that the logic for operation of these inputs is to be designed in the user
programmable Logic in the ConAegis Relay Communication Software.
1.3.21.9 Setting Group on General Inputs (GIs)
Similar to the Setting Group on BI setting, this setting enables the user to assign a GIs to a
particular Setting Group. This means that the various protection settings defined in a Setting
Group can be enabled, simply on the activation of the assigned GI. Any of the GIs can be
assigned to any setting group. When the user selects Yes in SET. GRP ON GI setting, the
display shows the status of GIs. Selecting the particular GI and changing the value from
Group 1 to Group 4 ensures this assignment. If NONE is selected, the setting group selected
in the Configuration menu will be active. Here, the user must note that the logic for
operation of these inputs is to be designed in the user programmable Logic in the ConAegis
Relay Communication Software.

`
1.3.22 Communication (COMM)
The relay can be configured for various communication protocol settings as like
MODBUS, IEC 103, IEC 61850. The following figure shows navigation of various settings
in the Communication Menu, & each of the setting for the respective protocol has been
described below.
Figure 37 - Communication Settings
1.3.22.1 MODBUS Protocol
MODBUS is a simple and robust serial communication protocol, and is now, a

commonly available means of connecting industrial electronic devices. MODBUS enables
communication among many devices connected to the same network. The main reasons for
the use of MODBUS are:
 developed with industrial applications in mind

 openly published and royalty-free
 easy to deploy and maintain
 moves raw bits or words without placing many restrictions on vendors
The protocol has been standardized such that any master can communicate with the
device by referring to the MODBUS Interoperability Table.
1.3.22.2 IEC 103 Protocol
IEC103 is a standard for power system control and associated communications. It

defines a companion standard that enables interoperability between protection equipment and
devices of a control system in a substation. The device complying with this standard can send
the information using two methods for data transfer - either using the explicitly specified

`
application service data units (ASDU) or using generic services for transmission of all the
possible information. The standard supports some specific protection functions and provides
the vendor a facility to incorporate its own protective functions on private data ranges.
IEC 61850 is a standard for the design of electrical substation automation. IEC 61850
is a part of the International Electrotechnical Commission's (IEC) Technical Committee 57
(TC57) reference architecture for electric power systems. The abstract data models defined in
IEC 61850 can be mapped to a number of protocols. The current mappings in the standard
are to MMS (Manufacturing Message Specification) & GOOSE (Generic Object Oriented
Substation Event). These protocols can run over TCP/IP networks or substation LANs using
high speed switched Ethernet.
1.3.22.4 Time Synchronization
Time synchronization is very critical, since each aspect of managing, securing,

planning, and debugging a network involves determining when the events occur. Time also
provides the only frame of reference between all devices on the network. Without
synchronized time, correlating log files between these devices accurately is very difficult.
Simple Network Time Protocol (SNTP) is a networking protocol for clock

synchronization between devices & computer systems over packet-switched, variable-latency
data networks. SNTP is intended to synchronize all participating devices to within a few
milliseconds of Coordinated Universal Time (UTC).
The IED has an internal real-time clock (RTC) for time stamping events, recorded data
and disturbance recordings. The device is provided with a 48-hour capacitor back-up that
enables the real-time clock to keep time in case of an auxiliary power failure. The device can
use one of two SNTP servers, the primary SNTP server or the secondary SNTP server. The
primary server is the default SNTP server in use, whereas the secondary server is used if the
primary server cannot be reached. This scenario can be explained using a flowchart:

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Start
Request to connect
to SNTP 1
Connected No
?
Yes
SNTP 1 Connected Re - connect

to SNTP 1
Connected No
?
Yes
SNTP 1 Connected Request to connect

to SNTP 2
Connected No
?
Yes
SNTP 2 Connected Re - connect

to SNTP 2
Connected No
?
Yes
SNTP 2 Connected
Figure 38 - SNTP Server Selection

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The device connects to the Primary SNTP Server first. The time is requested from the
SNTP server every 1 minute. In case of unavailability of Primary SNTP server, 2 attempts are
made to obtain synchronization with this server. If Primary SNTP server responds within this
time, the device is synced with this server. If Primary SNTP server does not respond on the
2nd attempt, the IED switches to the Secondary SNTP server on third SNTP request.
In case of unavailability of Secondary SNTP server, 2 attempts are made to obtain

synchronization with this server. If Secondary SNTP server responds within this time, the
device is synced with this server. If Secondary SNTP server does not respond on the 2nd
attempt, the IED again switches back to the Primary SNTP server on third SNTP request.
If both the SNTP servers are offline, event time stamps have the time invalid status.
1.3.22.5 Communication Settings
The description of settings & their permissible values for MODBUS & IEC 103
protocol is given below.
 Protocol: Selects the required communication protocol out of the available options on the
rear communications port.
 Baud Rate: Controls the communication speed between relay and master. Both, the relay
and master station must be set to the same speed.
 Parity: Controls the parity format used in the data frames. Both the relay and master
station must be set to the same parity.
 Relay Address: sets the unique address for the relay so that only one relay is accessed by
master software.
 Period: Defines the measurement period.
 Scaling: Selects the scaling factor.

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Permissible Values for MODBUS & IEC 103 Protocol
Communication
PROTOCOL MODBUS / IEC 103 / IEC 61850 -
BAUDRATE 2400 / 4800 / 9600 / 19200 / 38400 / 57600 9600
PARITY None / Even / Odd Even
RLY ADRS 000 - 254 (In steps of 001) Yes
PERIOD 000s – 060s (In steps of 001) 060s
SCALING 1.2X / 2.4X 1.2X
Table 17 - Communication Settings - I
The description of settings & their permissible values for IEC 61850 protocol is given below.
 Protocol: Selects the required protocol out of the available options.
 Operation: Enables / Disables IEC 61850 Communication.
 Timeout: Duration of time waited, after receiving a select command and awaiting an
operate confirmation from the master.
 Pulse Length: Sets the time for which output must be ON.
 Control Model: Selects the required control model
 Reset Server: This setting is required for purposes only, and is to be performed only
when CID file of the device is updated from CGL IED 61850 Tool.
 Device IP: Sets the unique network IP address that identifies the relay.
 Net Mask: Sets the sub-network the relay is connected to.
 Primary SNTP Server: Sets the IP address of the primary SNTP server.
 Secondary SNTP Server: Sets the IP address of the secondary SNTP server. This server
is used as a back-up server, in case the primary SNTP server fails. Priority is always
given to the primary SNTP server, if both servers are available.
 Gateway: Sets the gateway IP for the device.

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 Time Zone: Selects the time zone with respect to GMT.
Permissible Values for IEC 61850 Protocol
Communication
PROTOCOL MODBUS / IEC 103 / IEC 61850 -
OPERATION Enable / Disable Enable
TIMEOUT 10s – 300s (In steps of 1s) 10sEven
PULSE LEN 0.10s – 60s (In steps of 0.1s) 0.20s
CTL MODEL StsOnly / dWns / sboWes dWns
RST SERVER Yes / No No
SERVER IP - -
NET MASK - -
PRI. SNTP SERVER - -
SEC. SNTP SERVER - -
GATEWAY - -
TIME ZONE - -
Table 18 - Communication Settings - II

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1.3.23 Fault Records (FL-R)
Aegis Transformer Protection Relay stores the latest 10 faults occurred in the system.
On occurrence of a fault, the display instantly jumps to the Fault Record (FL-R) menu if the
setting Trip Alert is enabled in Configuration menu. These records consist of, for example,
the trip count, fault type, fault location, and fault measurements. The time stamp is also
accurately given in the fault record. The fault records can also be viewed from the ConAegis
The relay records latest 10 faults and stores them in non volatile memory. This enables
the user to obtain the sequence of faults that occurred in the relay. When the allocated
memory is used up, the oldest fault record is automatically overwritten by the new one.
This menu also gives a setting CLEAR FAULT REC to clear the fault records. If the
user says Yes to this setting, all the fault records will be cleared. Also, the user must note
here that all the event records will also get cleared. The following figure shows navigation of
for the Fault Record menu.

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4 5 13
5 6 14
6 7 15
Figure 39 - Fault Records View

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The following figure gives an idea about the various parameters displayed in the fault record.
Fault Number
Date & Time on which Fault Occurred
Fault Currents
4
Fault Voltages
Phase angle, Polarization type & Polarizing

5 voltage for IL1 when fault occurred

voltage for IL2 when fault occurred

voltage for IL3 when fault occurred
Phase angle, Polarization type & for ILo when
fault occurred
6
Fault type
Figure 40 - Fault Records Overview

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1.3.24 Disturbance Recorder (DR)
Aegis Transformer Protection Relay stores the latest 15 disturbance records occurred in
the system. The device is provided with a disturbance recorder featuring up to 9 analog and
200 binary signal channels. The analog channels can be set to record the trend of the currents
and voltage measured. The analog channels can be set to trigger the recording function when
the measured value falls below or exceeds the set values. The binary signal channels can be
set to start a recording on the rising or the falling edge of the binary signal or both.
By default, the binary channels are set to record external or internal device signals, like
the alarm & trip signals of the various protection stages stages, or external blocking or control
signals. Also, these signals generated over a binary input can be set to trigger the recording.
The recorder can be triggered by any start or trip signal from any protection stage or by
a binary input. The triggering signal is selected in the output matrix. The recording can also
be triggered manually. All the recordings are time stamped. The disturbance records can be
downloaded from the ConAegis Relay Communication Software & can be viewed in standard
Comtrade player such as Transwin.
The recorded information is stored in a non-volatile memory in FIFO manner and can
be uploaded for subsequent fault analysis. Disturbance records continue to be recorded until
the allocated memory is exhausted. When the allocated memory is used up, the oldest fault
record is automatically overwritten by the new one.
Also, this menu gives a pre-fault recording time which sets the trigger point as a
percentage of the duration. For example, the default settings show that the trigger point is set
to be 20%, which gives 0.2s pre-fault and 0.8s post-fault recording times for a DR time of 1s.
The DR file is saved in standard COMTRADE format and can be viewed in ConAegis Relay
Communication Software.
A provision has been given to clear the disturbance records from DR CLEAR setting.
If the user says Yes to this setting, the DR gets cleared. Here, it means that the memory gets
cleared, but the DR COMTRADE file remains intact. This file can be regenerated & retrieved
from the CGL IED 61850 Tool.
The following figure shows navigation of for the Disturbance Record menu, & each
setting has been explained below.

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Figure 41 - Disturbance Recorder
 Disturbance Record: Enables / Disables the recording facility.
 Pre - fault: Sets the trigger point as a percentage of the duration.
 No. of samples per cycle: Required for data sampling
 Trip Triggering: Selects the trip signals of the protection functions to trigger the DR.
 Pickup Triggering: Selects the pickup signals of the protection functions to trigger the
DR.
 DR on Binary Inputs: Selects a BI from the available BIs, on activation of which, the
DR will be triggered.
 Clearing the DR: Erases all the previously stores disturbance records.
 DR Triggering LED: The selected LED will give a blink on triggering of a DR.
Permissible Values
DIST. RECORDS
DIST. REC Enable / Disable Enable
PRE-FAULT 1% - 99% 20%
SAMPLE 8 / 16 / 32 32/cycle
TRIP TRGR Trip Signals for all Protection functions -
PICK TRGR Pickup Signals for all Protection functions -
DR ON BI None / Max. available BIs -
DR CLEAR Yes / No No
TRIG LED No LED / LED 5 - 16 No LED
Table 19 - DR Settings

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1.3.25 Event Records (EVNT)
Aegis Transformer Protection Relay stores the latest 500 events occurred in the system.
The events records display the event number, the frame type, which is distinctive for
occurrence of an event (ASDU 1) and occurrence of a fault (ASDU 2), information related to
faults, the fault number, and the date & time at which fault has occurred. The events are
stored in the non-volatile memory. This enables the user to obtain the sequence of events that
occurred in the relay. When the allocated memory is used up, the oldest event is
automatically overwritten by the new one. The event records can be viewed from the front
end or remotely using the ConAegis Relay Communication Software.
An event may be a change of state of a control input or BI, an alarm condition, or a

setting change. The various items that constitute an event:
 Change of state of binary inputs

 Change of state of one or more binary output contacts
 Protection element alarm and trip signal
 Setting changes
The generated event is a combination of Function Code & Information No. The
following table gives the various events generated in Feeder Protection Relay along with their
function codes.

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IEC 103 Function Code Mapping for Event Records

Sr. No NAME SYMBOL FUN INF
System Functions in Monitor Direction

1 End of General Interrogation 255 0
2 Time Synchronization 255 0
3 Reset FCB FUN 2
4 Reset CU FUN 3
5 start/restart FUN 4
6 power on FUN 5
Status Indications in Monitor Direction
7 Protection Active FUN 18
8 LED Reset FUN 19
9 Local parameter settings FUN 22
10 characteristics 1 FUN 23
Fault Indications in Monitor Direction
14 U1> Stage 1 Pickup 163 160
15 3 Phase Over Voltage and Neutral NDR Stage 1 Pickup 163 163
16 Displacement - IDMT Stage 1 U1> Stage 1 Trip 163 164
17 NDR Stage 1 Trip 163 167
18 3 Phase Under Voltage - IDMT U1< Stage 1 Pickup 164 160
19 Stage 1 U1< Stage 1 Trip 164 164
20 I1> Stage 1 Pickup 165 160
24 I1> Stage 1 Trip 165 164
25 I2> Stage 1 Trip 165 165
26 I3> Stage 1 Trip 165 166
27 HV 3 Phase Over Current and I0> Stage 1 Trip 165 167
28 Earth Fault -IDMT Stage 1 & 2 I1> Stage 2 Pickup 165 210
32 I1> Stage 2 Trip 165 214
33 I2> Stage 2 Trip 165 215
34 I3> Stage 2 Trip 165 216
35 I0> Stage 2 Trip 165 217
36 OF Stage 1 Pickup 166 170
37 OF Stage 1 Trip 166 180
Over Frequency Stage 1 & 2(HV)
38 OF Stage 2 Pickup 166 175
39 OF Stage 2 Trip 166 185
40 UF Stage 1 Pickup 167 170
41 Under Frequency Stage 1 & 2(HV) UF Stage 1 Trip 167 180

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43 UF Stage 2 Trip 167 185

48 U1>> Pickup 170 160
49 3 Phase Over Voltage -INST Stage NDR>> Picup 170 163
50 1 U1>> Trip 170 164
51 NDR>> Trip 170 167
52 I1< Stage 1 Pickup 173 160
55 I1< Stage 1 Trip 173 164
56 I2< Stage 1 Trip 173 165
57 3 Phase Under Current Stage 1 & I3< Stage 1 Trip 173 166
58 Stage 2 (HV) I1< Stage 2 Pickup 173 210
61 I1< Stage 2 Trip 173 214
62 I2< Stage 2 Trip 173 215
63 I3< Stage 2 Trip 173 216
64 ∆IT L1> Trip 176 86
Transformer Differential (Bias
65 ∆IT L2> Trip 176 87
Differential)
66 ∆IT L3> Trip 176 88
67 I1>> Stage 1 Pickup 178 160
71 I1>> Stage 1 Trip 178 164
72 I2>> Stage 1 Trip 178 165
73 I3>> Stage 1 Trip 178 166
74 HV 3 Phase Over Current and I0>> Stage 1 Trip 178 167
75 Earth Fault -INST Stage 1 & 2 I1>> Stage 2 Pickup 178 210
79 I1>> Stage 2 Trip 178 214
80 I2>> Stage 2 Trip 178 215
81 I3>> Stage 2 Trip 178 216
82 I0>> Stage 2 Trip 178 217
83 DI1 179 1
84 DI2 179 2
85 DI3 179 3
86 DI4 179 4
DI Status
87 DI5 179 5
88 DI6 179 6
89 DI7 179 7
90 DI8 179 8

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91 DO1 180 1
92 DO2 180 2
93 DO3 180 3
94 DO4 180 4
DO Status
95 DO5 180 5
96 DO6 180 6
97 DO7 180 7
98 DO8 180 8
99 THRM L1 Pickup 181 160
Thermal Overload (HV)
102 THRM L1 Trip 181 164
103 THRM L2 Trip 181 165
104 THRM L3 Trip 181 166
105 Io IDMT Stage 1 Pickup 183 170
106 I0 IDMT Stage 1 Trip 183 180
107 I0 IDMT Stage 2 Pickup 183 175
HV I0 IDMT & INST Stage 1 & 2
109 Io INST Stage 1 Pickup 183 190
110 I0 INST Stage 1 Trip 183 200
111 I0 INST Stage 2 Pickup 183 195
113 I2> IDMT Stage 1 Pickup 184 170
114 I2> IDMT Stage 1 Trip 184 180
HV Negative Sequence
OverCurrent IDMT & INST Stage
117 I2> INST Stage 1 Pickup 184 190
1&2
118 I2> INST Stage 1 Trip 184 200
121 OV Flx Stage 1 Pickup 185 170
122 OV Flx Stage 1 Trip 185 180
Over Flux Stage 1 & 2
123 OV Flx Stage 2 Pickup 185 175
124 OV Flx Stage 2 Trip 185 185
125 ∆IT L1>> Trip 186 86
Transformer Differential (Bias
126 ∆IT L2>> Trip 186 87
Differential) HighSet
127 ∆IT L3>> Trip 186 88
128 REF Stage 1 Pickup 187 170
129 HV Restricted Earth Fault (REF) REF Stage 1 Trip 187 180
130 Stage 1 & 2 REF Stage 2 Pickup 187 175
131 REF Stage 2 Trip 187 185
LV 3 Phase Over Current and
Earth Fault -IDMT Stage 1 & 2
136 I1> Stage 1 Trip 210 164
137 I2> Stage 1 Trip 210 165
138 I3> Stage 1 Trip 210 166

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139 I0> Stage 1 Trip 210 167

144 I1> Stage 2 Trip 210 214
145 I2> Stage 2 Trip 210 215
146 I3> Stage 2 Trip 210 216
147 I0> Stage 2 Trip 210 217
148 I1>> Stage 1 Pickup 211 160
149 I2>> Stage 1 Pickup 211 161
150 I3>> Stage 1 Pickup 211 162
151 I0>> Stage 1 Pickup 211 163
152 I1>> Stage 1 Trip 211 164
153 I2>> Stage 1 Trip 211 165
154 I3>> Stage 1 Trip 211 166
155 LV 3 Phase Over Current and I0>> Stage 1 Trip 211 167
156 Earth Fault -INST Stage 1 & 2 I1>> Stage 2 Pickup 211 210
157 I2>> Stage 2 Pickup 211 211
158 I3>> Stage 2 Pickup 211 212
159 I0>> Stage 2 Pickup 211 213
160 I1>> Stage 2 Trip 211 214
161 I2>> Stage 2 Trip 211 215
162 I3>> Stage 2 Trip 211 216
163 I0>> Stage 2 Trip 211 217
167 I1< Stage 1 Trip 212 164
168 I2< Stage 1 Trip 212 165
169 3 Phase Under Current Stage 1 & I3< Stage 1 Trip 212 166
170 Stage 2 (LV) I1< Stage 2 Pickup 212 210
173 I1< Stage 2 Trip 212 214
174 I2< Stage 2 Trip 212 215
175 I3< Stage 2 Trip 212 216
Thermal Overload (LV)
179 THRM L1 Trip 213 164
180 THRM L2 Trip 213 165
181 THRM L3 Trip 213 166
182 Io IDMT Stage 1 Pickup 214 170
184 LV I0 IDMT & INST Stage 1 & 2 I0 IDMT Stage 2 Pickup 214 175
186 Io INST Stage 1 Pickup 214 190

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188 I0 INST Stage 2 Pickup 214 195
LV Negative Sequence
OverCurrent IDMT & INST Stage
1&2
198 REF Stage 1 Pickup 216 170
199 LV Restricted Earth Fault (REF) REF Stage 1 Trip 216 180
201 Stage 1 & 2 REF Stage 2 Pickup 216 175
202 REF Stage 2 Trip 216 185
205 Breaker Failure 1 BF1 FUN 85
206 Breaker Failure 2 BF2 FUN 95
1 to
208 Goose message Subscribe virtual input 194 64
1 to
209 Goose message Publish virtual input 195 64
Table 20 - Event Records

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1.4 TECHNICAL DATA

1.4.1 Connections
1.4.1.1 Measuring Circuitry
Rated phase Current (In) 1A/5A (Configurable)
- Current measuring range 5% to 4000% of CT Secondary
- Thermal withstand 2xIn (Continuously)

20xIn (for 3 seconds)
- Burden <0.3VA@1A
<0.5VA@5A
- Terminal Block Maximum wire dimensions:

6mm²
- Accuracy ± 0.5 % or better

Rated Voltage (Un) 63.5Vac (L-N)
- Voltage measuring range 5% to 200% of VT Secondary
- Voltage withstand 2xUn (Continuously)
- Burden <0.15VA@70VAC
<0.3VA@120VAC
- Terminal Block Maximum wire dimensions:

2.5mm² (12-28AWG)
- Accuracy ± 0.1 % or better

Rated Frequency
- Frequency measuring range 50Hz/60Hz
Note: The minimum sensing current for Aegis Protection Relays is 40mA.
Note: The device calculates the fundamental frequency from the 3-phase voltage and current
when these incoming signals are present. But in case of no load, the device uses this default
frequency. If the panel is operated / turned ON in such a situation, the device immediately
samples the 3 – phase quantities according to its sampling rate.

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1.4.1.2 Auxiliary Voltage
Rated Voltage 18-52VDC 75-250VDC
Power Consumption <10W <10W
Terminal Block Maximum wire dimensions: Maximum wire dimensions:

2.5mm² (12-28AWG) 2.5mm² (12-28AWG)
1.4.1.3 Binary Inputs
Number of Inputs 4 / 8 / 12 / 16
External Operating Similar to the Auxiliary supply of relay
voltage
Terminal Block Maximum wire dimensions: 2.5mm² (12-28AWG)
Voltage rating of One time configurable for 24,30,110 and 220VDC
Binary Inputs
Starting Vtg. for BIs For 24V / 30 V BI: 17V For 110 V BI: 75V For 220V BI: 175V
Current Consumption 11 mA respective of Voltage rating of the BI
1.4.1.4 Binary Outputs
Number of Outputs 4 / 8/ 12 / 16
Normal Contact
Contact Material Ag-Alloy + gold plating (standard)
Rated Switching Current 8A@250VAC, 5A@30VDC
Rated Carry Current 8A
Max. Switching Voltage 250VAC, 30VDC
Max. Switching Capacity 2000VA, 150W
Min. Permissible Load 10mA, 5VDC
Heavy Duty Trip Contact

Contact Material Ag-Alloy
Rated Switching Current 16A@250VAC, 16A@30VDC
Rated Carry Current 16A
Max. Switching Voltage 380VAC, 125VDC
Max. Switching Capacity 4000VA, 480W
Min. Permissible Load 100mA, 5VDC
Terminal Block Maximum wire dimensions:
2.5mm² (12-28AWG)

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1.4.1.5 Local Serial Communication Port
Number of ports 1 on front panel

Electrical connection USB
Protocol CG PROPERIETARY
1.4.1.6 Remote Control Connections
Number of ports 2
Electrical connection RS-485 Ethernet 10 Base-T
Data transfer rate 2400 - 57600 100 Mbps
Protocol Refer ordering information section 7

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1.4.2 Test & Environmental Conditions

1.4.2.1 Type Test
Electrical Fast Transient Test IEC 60255-22-4 (Edition-2008)

High Frequency Disturbance Test IEC 60255-22-1 (2nd Edition-2005)
Impulse Voltage Test IEC 60255-5 (2nd Edition-2000)
Radiated Emission Test IEC 60255-25 (1st Edition-2000)
Radiation Susceptibility Test IEC 60255-22-3 (Edition-2007)
Conducted Emission Test IEC 60255-25 (1st Edition-2000)
Conducted Susceptibility Test IEC 60255-22-6 (1st Edition-2001)
Electrostatic Discharge Test IEC 60255-22-2 (3.0 Edition-2008)
Surge Immunity Test IEC 60255-22-5 (Edition 2008)
Power Frequency Magnetic Field Test IEC 61000-4-8 (Edition-2009)
Vibration Endurance Test (Class1) IEC 60255-21-1
Shock Response Test (Class1) IEC 60255-21-2
Shock Withstand Test (Class1) IEC 60255-21-2
Bump Test (Class 1) IEC 60255-21-2
Seismic Test
Ingress Protection Test IEC 60529 Ed.2.1:2001
●IP:5X Test (Ingress of Dust for Enclosure
CAT 2)
●IP:X4 Test (Splashing of Water for
Enclosure)
Insulation Resistance Test IEC 60255-27:2005 Cl.10.5.3.3
Dielectric Test IEC 60255-27:2005 Cl.10.5.3.2
Relay Characteristics, Performance & IEC 60255-12:1980
Accuracy Test IEC 60255-3:1989
● Operating (pickup) Value & Reset
(Dropout) Value Test
● Pick up Test for High Fault
● Operating characteristics Test
(IDMT Timing Test)
Rated Burden Test IEC 60255-1:2009 Cl.6.10
● VA Burden for Auxiliary Power Supply
● VA Burden on Current Transformers
● VA Burden on Voltage Transformers
Thermal Requirement Test IEC 60255-27:2005 Cl.No.7.2
Mechanical Endurance Test IEC 60255-1:2009 Cl.6.11
Contact Performance Test IEC 60255-1:2009 Cl.6.11
Making Capacity Test IEC 60255-1:2009 Cl.6.11
● AC Resistive Load

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● DC Resistive Load
Breaking Capacity Test IEC 60255-1:2009 Cl.6.11
● AC Inductive Load
Short Time Capacity Test IEC 60255-1:2009 Cl.6.11
Effect of Interruption to DC Auxiliary IEC 60255-11:2008
Energizing Quantity
Alternating Component (Ripple) in DC IEC 60255-11:2008
Auxiliary Energizing Quanity
Climatic/Environmental Test
● Damp Heat Cyclic Test IEC 60068-2-30
● Dry Heat Test IEC 60068-2-2
● Cold Test IEC 60068-2-1
● Damp Heat, Steady State Test IEC 60068-2-78
Communication Protocol Conformance Test IEC 61850
1.4.2.2 Casing
Degree of protection (IEC 60529) IP54

Dimensions (W x H x D) 188.58 x 199.18 x 228.40 mm
Material 0.8mm CRCA MS
Weight 750 gm
1.4.2.3 Package
Dimensions (W x H x D) 188.58 x 199.18 x 228.40

Weight (Terminal, Package and 4.8 kg
Manual)

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1.5 CONNECTIONS
1.5.1 Rear Panel Connections
Figure 42 - Rear View of Transformer Protection Relay

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Terminal Details (X1)
X1
NO. SYMBOL DESCRIPTION

3 3 UL PH
Voltage Input
4 4 UL N
5 5 IL1 (HV) PH Rph Current Input (1A/5A)
6 6 IL1 (HV) N HV Winding
7 7 IL2 (HV) PH Yph Current Input (1A/5A)
9 9 IL3 (HV) PH Bph Current Input (1A/5A)
11 11 IL1 (LV) PH Rph Current Input (1A/5A)
12 LV Winding
12 IL1 (LV) N
X2
13 NO. SYMBOL DESCRIPTION

14
13 P (BO5) Binary Output Contact 5
14 NO (BO5) (Heavy Duty)
15
15 P (BO6) Binary Output Contact 6
16
16 NO (BO6) (Heavy Duty)
17
17 + ve
18 Auxiliary DC Input
18 - ve
19 19 NC Not Connected
20 20 EARTH Earth

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X3

21 21 IL2 (LV) PH Yph Current Input (1A/5A)
22 22 IL2 (LV) N LV Winding
23 23 IL3 (LV) PH Bph Current Input (1A/5A)

24 IL3 (LV) N LV Winding
24
25 25 REF (HV) PH REF Current Input (1A/5A)

26 REF (HV) N HV Winding
26
27 27 REF (LV) PH REF Current Input (1A/5A)

28 REF (LV) N LV Winding
28

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X4

29
29 P (BO1)
30
30 NO (BO1) Binary Output Contact 1
31
31 NC (BO1)
32
32 P (BO2)
33
33 NO (BO2) Binary Output Contact 2
34
34 NC (BO2)
35
35 P (BO3)
36 Binary Output Contact 3
36 NO (BO3)
37
37 P (BO4)
38 Binary Output Contact 4
38 NO (BO4)
39
39 + (BI1)
40 Binary Input 1
40 - (BI1)
41
41 + (BI2)
42 Binary Input 2
42 - (BI2)
43
43 + (BI3)
44 Binary Input 3
44 - (BI3)
45
45 + (BI4)
46 Binary input 4
46 - (BI4)
47
47 NC
48
48 NC
49 Not Connected
49 NC
50
50 NC

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X5

51 51 + (BI5)
Binary Input 5
52 52 - (BI5)
53 53 + (BI6)
Binary Input 6
54 54 - (BI6)
55 55 + (BI7)
Binary Input 7
56 56 - (BI7)
57 57 + (BI8)
Binary Input 8
58 58 - (BI8)
61 61 P (BO8)
Binary Output 8
62 62 NO (BO8)
63 63 P(BO7)
Binary Output 7
64 64 NO (BO7)
65 65 NC
66 66 NC
Not Connected
67 67 NC
68 68 NC

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1.5.2 Wiring Diagram
Figure 43 - Wiring Diagram for Transformer Protection Relay (AE025_00)

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1.6 DIMENSIONS
FRONT VIEW
SIDE VIEW
CUT OUT
Figure 44 - Dimensions

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1.7 ORDERING INFORMATION
AEGIS T
PROTECTION FUNCTIONS
Three Phase O/C & Derived E/F (50, 51, 50N, 51N)
Biased Differential (87) - 2 winding
Thermal Overload (49)
Negative Phase Sequence O/C (46) I
Under Current (37)
2nd,4th & 5th Harmonic Restraint
CBFP (50BF)
Model I + Following Functions = Model A

Measured E/F (50G, 51G)
Restricted Earth fault (64N)
Over Fluxing (24) A
One Phase O/V, U/V & NDR (27, 59, 59N)
Over & Under Frequency (81)
Model A + Following Functions = Model B

Biased Earth fault (Low Impedance REF) (87N)
Three Phase O/V, U/V & NDR (27, 59, 59N)
CT Supervision (60 CTS)
VT Fuse Failure (60 VTS) B
Directional O/PWR, U/PWR (32)
Auto Reclose (79)
Power Measurement (P)

Energy KWH, KVAH, KVARH
COMMUNICATION
Non-Communicable 0
IEC 60870-5-103 on RS-485 Port 1
MODBUS on RS-485 Port 3
IEC 61850 on Single Ethernet RJ45 Port 6
IEC 61850 on Single Fiber Optic Port 7
IEC 61850 on Dual Ethernet RJ45 Port 8
IEC 61850 on Dual Fiber Optic Port 9
DIGITAL INPUTS & DIGITAL OUTPUTS
4 DI + 6 DO 1
8 DI + 10 DO 2
10 DI + 8 DO 3
12 DI + 6 DO 4
4 DI + 14 DO 5
12 DI + 10 DO 6
16 DI + 10 DO + 4 RTD Inputs 7
8 DI + 8 DO 8
Reserved 9
AUXILIARY POWER SUPPLY
18-52VDC 1
75-250VDC 2
CASE
NON DRAWOUT X
DRAWOUT D
OPERATING VOLTAGE FOR DIGITAL INPUT
30VDC 1
110VDC 2
220VDC 3

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2 PROTECTION FUNCTIONS

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Section Overview
This section includes all the protection functions provided by Aegis Series
Transformer Protection Relay. A brief description of the functionality, operating principle,
relay & IEC 61850 settings, signals, setting guidelines and application for each of the
protection function has been given. The section contains following chapters:
 Differential Protection
 Three Phase Current Protection
 Voltage Protection
 Supervision Functions

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Principle of a Protection Function

The Aegis Series Transformer Protection Relay provides a wide range of protection
functionality. Although each protection function operates in its own unique way, some of the
building blocks remain the same for most the protection functions. The general principle is to
isolate the faults as quickly as possible to limit the danger and prevent unwanted fault
currents flowing through systems, which can cause severe damage to equipment and systems.
At the same time, we need to switch off only the parts of the grid that are absolutely
necessary, so as to prevent unnecessary blackouts.
Figure shows functional block diagram of a basic protection function along with a brief
description of each block.
Figure 45 - Functional Block Diagram for a Basic Protection Function
 Actuating Quantities
An actuating quantity may be current or voltage from the respective transformers of any
of the windings, HV or LV. These quantities at power system level are stepped down into
analog signals and are converted into equivalent digital signals, which make them suitable
for further processing.
 Enable / Disable Protection Function

The IED provides a setting to enable a particular protection function. The actuating
quantity will be compared with the threshold only when that particular protection function
has been enabled. The function can also be enabled through the ConAegis Relay
 Blocking Signals
The function contains a blocking functionality. It is possible to block function outputs and
the function itself, if desired.

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 Comparator
An actuating quantity is always compared with a threshold value, which can be set by the
user in the given permissible range, depending on the protection function. On
comparison, one the following three situations may occur:
i. If the injected quantity is less than the set threshold for overvalues, or greater than the
threshold for undervalues, normal operation of the device continues without any
alarming or tripping.
ii. If the injected quantity is greater than the set threshold for overvalues or less than the
threshold for undervalues, that stage picks up and the device issues an Alarm Signal.
This signal is further passed onto the Timer block. Timer calculates the time to trip,
based on the selected IDMT / DT curve. If the fault continues to persist till this time,
the device issues a Trip Signal. An event is registered at this time and stored in the
memory.
iii. When comparing an injected value against pickup value, some amount of hysteresis is
to be considered to avoid oscillations near equilibrium condition, i.e. if the injected
quantity is fluctuating near the set threshold, it may lead to ambiguous situation. To
achieve precise decision making in this case, a pickup and dropout level is defined
above and below the set threshold, the values for which, may be user programmable
or hard-coded. In case of IDMT operation, as soon as the Alarm Signal is issued, an
added feature of RST DT is activated. This is a Reset DT Timer, & its value
corresponds to the minimum time for which the injected quantity needs to be lower
than defined % of the threshold (typically 90 - 95 %) before the corresponding phase
time delay is reset.
 Timer
The timer block calculates the delay after which a Trip Signal is to be issued to the
breaker. It can be configured by a choosing type of the curve and Time Multiplier Setting
(TMS) to so as to select the required trip time.
 Reset DT Timer
This timer comes into picture when the injected quantity rides in the defined hysteresis.
This condition may generate a series of fault current pulses, until the fault becomes
permanent. If Reset DT Timer is set to non – zero value (eg. 2 sec), the resetting of the
protection element timers will be delayed for this period. When the reset time is
instantaneous, the device will repeatedly reset and will not be able to trip until the fault
becomes permanent. By using the Reset DT Timer, the device will integrate the fault
current pulses, and reduce the fault clearance time.

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2.1 DIFFERENTIAL PROTECTION

2.1.1 Bias Differential Protection
The biased differential protection 87BD is used to detect transformer faults within the
zone defined by comparing the current on the primary and secondary side of transformer.
Therefore current transformers are located on primary and secondary side of power
transformer. The differential protection is based on difference of the winding currents
between HV and LV side. In transformer applications the current calculation depends on
transformer connection group.
Figure 46 - Differential Protection of Power Transformer
The differential protection function compares the phase currents on both sides of the
transformer. Whenever the differential current of the phase currents in one of the phases
exceed the predefined threshold of a particular stage, that stage picks up and an Alarm
Signal is issued. If the fault situation persists for longer than the estimated trip time
configured in the relay, a Trip Signal is issued.
2.1.1.1 Identification
Protection Function ANSI No. IEC Symbol IEC 61850 Logical Nodes
Bias Differential Protection 87BD 3dI> A87BD_PDIF1
Bias Differential Protection –
87HS 3dI>> A87HS_PDIF2
Instantaneous Stage
2.1.1.2 Functionality
The settings for Bias Differential protection can be found in BD Settings menu in the
device. Aegis Transformer Protection Relay provides two adjustable bias differential stages
for low set (slope characteristics) as well as INST operation. Both, BD & BDHS stage always
operates with a definite time (DT) operation characteristic. By setting the definite delay value
to its minimum, an instantaneous operation is obtained, also known as High Set Bias
Differential Protection. The function contains a blocking functionality. It is possible to block
function outputs and the function itself, if desired. The various settings for each stage can
also be configured through the ConAegis Relay Communication Software.

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2.1.1.3 IEC 61850 Functional Blocks
A87BD_PDIF1 A87HS_PDIF2
IL1HV IL1HV
IL2HV Start IL2HV Start
IL3HV Operate IL3HV Operate
IL1LV IL1LV
IL2LV IL2LV
IL3LV IL3LV
Enable Enable
Block Block
Figure 47 - IEC 61850 Functional Blocks for Bias Differential Protection
 IL1, IL2, IL3: Measured currents in phase A, B, C in both the windings respectively
 Enable : Enable the protection function
 Block : Block the protection via BI / VI
 Start : Pickup instance due to BD
 Operate : Trip instance due to BD
2.1.1.4 Operation Principle
Figure shows the functional block diagram for both the stages of bias differential &
each block has been described below:
A. Bias Differential Stage (87BD) (3dI>) (A87BD_PDIF1):
 This function can be enabled by configuring the 87BD PROT setting to ENABLE. A
threshold can be defined using 87BD PICK UP, ranging from 10% - 200% of the rated
current. The fundamental frequency current is measured with the line CT inputs. These
line currents are both multiplied and vector corrected before being applied to the current
differential elements. The difference current is calculated in the ICT block.
 Interposing CT multipliers are used for effective CT secondary currents to accommodate

for any mismatch between the winding 1 and winding 2 CT ratios. The output of ICT
multiplier for each winding must be equal during the load or through fault condition,
notwithstanding variation in OLTC position. The biased differential elements calculate
the operate current for each phase from the vector sum of winding 1 and winding 2
currents and the bias (or restraint) current is calculated from the total current of winding 1
and winding 2 currents.

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Figure 48 - Functional Block Diagram for Bias Differential Protection
Operate Current, Id = Iw1 Iw2
Bias (Restraint) Current, Ib = │Iw1│ + │Iw2│

2
 If differential current is more, as compared to restrain current of if the phase angle

between the winding 1 and winding 2 phase current is close to zero, in the normal
situation phase difference is 1800.
 If difference current is 5% above the set threshold, this stage picks up, and an Alarm
Signal is issued by the device. This current is known as pickup current. This signal is also
made available directly to the user for use in Logic in the ConAegis Relay
Communication Software. The operation of the biased differential elements can be
inhibited from a binary or virtual input (BI/ VI).The protection function may be disabled
on activation of a BI or VI. Also, the protection may be blocked if 2nd, 4th, or 5th harmonic
is detected. This can be done by configuring 87BD If2>ACT, 87BD If4>ACT, 87BD
If5>ACT setting.

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 The inrush current contains a large amount of second harmonics. The transformer
magnetizing inrush currents occur when energizing the transformer after a period of de-
energization. To the bias differential protection, the inrush current represents a
differential current, which would cause the differential protection to operate almost
always when the transformer is connected to the network. The blocking of bias
differential protection at a magnetizing inrush current is based on the ratio of the
amplitudes of the second harmonic digitally filtered from the differential current and the
fundamental frequency. Blocking on the fifth harmonic ensures that the protection does
not operate on apparent differential current caused by a harmless transformer
overexcitation. The blocking of bias differential protection in the situations of
overexcitation is based on the ratio of the fifth harmonic and the fundamental component
of the differential current.
 Bias differential protection includes dual slope characteristics. The operation

characteristic is determined by 87BD PICK UP, 87BD SLOPE1, 87BD SLP1 LMT &
87BD SLOPE2 value. When the differential current exceeds the operating value
determined by the operating characteristic, the bias differential picks up awakes and
operates after definite time configured in 87BD DT setting. When the timer has reached
the value of DT delay, Trip Signal is issued by the device.
 When comparing an injected value against pickup value, some amount of hysteresis is to
be considered to avoid oscillations/ fluctuations near equilibrium condition. To achieve
precise decision making in this case, a pick up and a dropout current is defined above and
below the set threshold in the Configuration Menu, which is typically 95% to 105%.
 At the same instant at which Trip Signal is issued, a fault record is also time stamped
and its details can be viewed in the FL-R menu, wherein the timings & causes of the
tripping can be found out. Alarming and tripping is indicated by the dedicated LEDs on
the front panel of the device. The user can assign any of the LEDs 5-16 to indicate pickup
or trip in any of the phases from Config LED setting. Also, the BIs for pickup and trip in
any of the phases can be mapped to the BOs from Config S/W BI setting.
B. Bias Differential High Set Stage (87BDHS) (3dI>>) (A87BDHS_PDIF2):
 This function can be enabled by configuring the 87HS PROT setting to ENABLE. A
threshold can be defined using 87HS SET, ranging from 1A to 30A. The fundamental
frequency current is measured with the line CT inputs. These line currents are both multiplied
and vector corrected before being applied to the current differential elements. The difference
current is calculated in the ICT block.
 The operation of the high set stage is not biased. If fundamental frequency component of
the differential current is 5% above the set threshold, this stage picks up, and an Alarm

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Communication Software. The operation of the high set biased differential elements can
be inhibited from a binary or virtual input (BI/ VI).The protection function may be
disabled on activation of a BI or VI. Also, the protection may be blocked if 2 nd, 4th, or 5th
harmonic is detected. This can be done by configuring 87HS If2> ACT, 87HS If4>
ACT, 87HS If5> ACT setting.
2.1.1.5 Operation Characteristics
The operating characteristics of the biased differential protection (87BD) are as shown
in the figure. The 87BD elements provide differential protection for phase and earth fault.
Slope 1 and slope 2 characteristic for protection sensitivity are dictated by the need to ensure
protection stability during load or through fault conditions.
Initial differential setting (Minimum 87BD pick up)

This is the minimum value of differential current at which relay will operate with zero bias
current. This setting is selected to ensure stability in presence of CT and relay errors when
small amount of bias current are present. Normally its setting would be the same as that for
differential bias slope value.
Differential Bias Slope 1

Steady state unbalance current appears in the differential circuit of the relay for predictable
reason like transformer tap position, CT error, and Relay tolerance. Bias current will increase
with increasing in the load or through fault current in the transformer so, to maintain the
stability biasing current must increase proportionally. The bias slope express the current to
operate the relay of the biasing current, the differential bias slope setting chosen must be
greater than the maximum predictable unbalance current. It is selected to ensure the stability
when through fault or heavy load current flows in the transformer and the tap changer is in its
extreme position.

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Figure 49 - Bias Differential Protection Operation Characteristics
Differential Bias Slope 1 Limit

Differential bias slope 1 limit setting defines the upper limit of the bias slope 1. It is the ratio
of differential current to bias current and is expressed in multiples of nominal rated current. A
setting value must be chosen which will cover the maximum through fault current of the
transformer. When a through fault occurs, saturation of one or more CTs may cause a
transient differential current to be detected by the relay. The bias slope limit is chosen to
ensure the biased differential function is stable for high through fault currents coincident with
CT saturation. This setting gives more stability during CT saturation for heavy through fault.
Differential Bias Slope 2

Differential bias slope 2 settings are chosen to ensure the biased differential function is stable
for high through fault currents coincident with CT saturation.
Similarly, the following figure shows the operating characteristics for bias differential high
set stage:
Figure 50 - High Set Bias Differential Protection Operation Characteristics

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2.1.1.6 Bias Differential Settings & Signals
The following table gives functioning and ranges for each of the settings of both the
stages in BD Settings menu for Bias Differential Protection.
Bias Differential Protection (87BD)

Description
Setting Range /Available Options Step Size Default
Protection: Enables/ disables bias differential protection.
87BD PROT Enable - Disable - Disable
Pickup Setting: Sets the pick-up differential current level.
87BD PICKUP 0.10 – 2.00 xIn 0.05 20 %
Slope 1: Used to ensure protection stability in the presence of steady state errors.
87BD SLOPE1 0.10 – 0.70 0.10 0.30
Slope 1 Limit: Defines the border between the 1st & 2nd bias slopes.
87BD SLP1 LMT 1A – 20A 1A 2A
Slope 2: Used to modify the sensitivity of the differential algorithm at higher current levels.
87BD SLOPE 2 1.00 – 2.00 0.05 1.25
DT Delay: Sets the time delay after which tripping occurs.
87BD DT 0.000s – 1.000s 0.005s 0.050s
2 Harmonic Blocking: Blocks the protection on 2nd harmonic detection.
nd
87BD If2> ACT ON / OFF - ON

4 Harmonic Blocking: Blocks the protection on 4th harmonic detection.
th
87BD If4> ACT ON / OFF - OFF

5th Harmonic Blocking: Blocks the protection on 5th harmonic detection.
87BD If5> ACT ON / OFF - ON
High Set Bias Differential Protection (87HS)
Description
Protection: Enables/ disables high set bias differential protection.
87HS PROT Enable - Disable - Disable
Pickup Setting: Sets the pick-up differential current level.
87HS PICKUP 1A – 30A 1A 6A
87HS DT 0.000s – 1.000s 0.005s 0.050s
nd
87HS If2> ACT ON / OFF - ON

4 Harmonic Blocking: Blocks the protection on 4th harmonic detection.
th
87HS If4> ACT ON / OFF - OFF

5th Harmonic Blocking: Blocks the protection on 5th harmonic detection.
87HS If5> ACT ON / OFF - ON
Table 21 - Bias Differential Protection Settings
The following table gives description of various pickup & trip signals for both the
stages of Bias Differential Protection. LEDs can be assigned to indicate these signals and BIs
for pickup and trip in any of the phases can be mapped to the BOs.

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Bias Differential Protection (87BD)

Selectable Selectable
Signals Description
LEDs BOs
BD1 TRP Bias Differential Trip Signal for phase-A
BD2 TRP Bias Differential Trip Signal for phase-B
BD3 TRP Bias Differential Trip Signal for phase-C
BDHS1 TRP High Set Bias Differential Trip Signal for phase-A
BDHS2 TRP High Set Bias Differential Trip Signal for phase-B
BDHS3 TRP High Set Bias Differential Trip Signal for phase-C LEDs BOs
BD1 PKP Bias Differential Pickup Signal for phase-A 5 - 16 1–8
BD2 PKP Bias Differential Pickup Signal for phase-B
BD3 PKP Bias Differential Pickup Signal for phase-C
BDHS1 PKP High Set Bias Differential Pickup Signal for phase-A
BDHS2 PKP High Set Bias Differential Pickup Signal for phase-B
BDHS3 PKP High Set Bias Differential Pickup Signal for phase-C
Table 22 - Bias Differential Protection Signals
All of these settings can be configured from ConAegis Relay Communication

Software. Also, all the settings and status of pickup and trip signals can be viewed in the
logical nodes A51BD_PDIF1, A87HS_PDIF2 of IEC 61850 defined for both stages of Bias
Differential Protection.
A87BD_PDIF1: Bias Differential Protection

Data Objects Functional Constraint Available Options
Description
(DO) (FC) / Range
LoSet 10 % - 200 % Pickup Value
1 - None
Set Point (SP) 2 - 2nd Harmonic
RstMod Harmonic Blocking
3 - 5th Harmonic
4 – 2nd & 5th Harmonic
A87HS_PDIF2: High Set Bias Differential Protection
Description
(DO) (FC) / Range
HiSet 1A – 30A Pickup Value
1 - None
Set Point (SP) 2 - 2nd Harmonic
RstMod Harmonic Blocking
3 - 5th Harmonic
nd th
4 – 2 & 5 Harmonic
Table 23 - Bias Differential Protection Settings in IEC 61850 Logical Node

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A87BD_PDIF1: Bias Differential Protection

Data Objects Functional
Description
(DO) Constraint (FC)
Str-gen Bias Differential Pickup Signal in any of the phase
Str-phsA Bias Differential Pickup Signal in Phase A
Str-phsB Bias Differential Pickup Signal in Phase B
Str-phsC Status (ST) Bias Differential Pickup Signal in Phase C
Op-gen Bias Differential Trip Signal in any of the phase
Op-phsA Bias Differential Trip Signal in Phase A
Op-phsB Bias Differential Trip Signal in Phase B
Op-phsC Bias Differential Trip Signal in Phase C
A87HS_PDIF2: High Set Bias Differential Protection
Description
Str-gen High Set Bias Differential Pickup Signal in any of the phase
Str-phsA High Set Bias Differential Pickup Signal in Phase A
Str-phsB High Set Bias Differential Pickup Signal in Phase B
Str-phsC Status (ST) High Set Bias Differential Pickup Signal in Phase C
Op-gen High Set Bias Differential Trip Signal in any of the phase
Op-phsA High Set Bias Differential Trip Signal in Phase A
Op-phsB High Set Bias Differential Trip Signal in Phase B
Op-phsC High Set Bias Differential Trip Signal in Phase C
Table 24 - Bias Differential Protection Signals in IEC 61850 Logical Node
Setting Guidelines
Differential Calculations:
Differential current under normal condition is zero, i.e. Id =0, and incoming (Īw1), outgoing
(Īw2) current of power transformer are equal in magnitude i.e. no fault inside the protected zone,
protected zone is defined by CT‟s mounted on Primary side and secondary side of Power transformer.
But In practice differential current deviates from zero under No fault condition of power transformer
due to the current magnitude change introduced by the transformer HV/LV turns ratio, current
ratio may also be variable due to the presence of an On-Load-Tap-Changer, transformer
connections which may introduce a phase change between the currents flowing into each
winding of the transformer and Magnetizing inrush current which flows in only one winding
of the transformer when energized.
During the normal operation or external fault condition biased differential protection
will not operate. If load current increase, higher biased differential current required for
tripping and if internal fault occurs, the currents on both sides of the protected object are
flowing into it. Therefore less amount of biased differential current is required for tripping,
which increase the sensitivity of biased differential protection operation, during the internal
faults of Power transformer.

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Interposing CT multiplier for current magnitude balance (HV & LV):

Interposing CT multipliers are used for effective CT secondary currents to
accommodate for any mismatch between the winding 1 and winding 2 CT ratios. The output
of ICT multiplier for each winding must be equal during the load or through fault condition,
notwithstanding variation in OLTC position.
Interposing CT connection for Vector group correction (HV & LV):

Interposing current transformers connection is used to correct the CT secondary current
phase relationships in line with any phase change introduced by the transformer connections.
An equivalent interposing CT connection can be selected from this range of settings. The
settings define the LV and HV winding configuration. E.g. Yd followed by the angular
position of the LV phasor with respect to the HV phasor. The angular position is described by
the hour - hand position on the twelve-hour clock face, e.g. Yd1 or Yd11. In each setting, this
is followed by the same angular relationship expressed in degrees. The complete Yd11 setting
will therefore read Yd11, +30° and Yd6 will read Yd6, +180°.
Interposing CT Selection Guide:

Power Transformer Vector Group HV LV
Interposing Interposing
CT Selection CT Selection
Yy0, YNy0, Yyn0, YNyn0, Ydy0, Yndy0, Ydyn0, Ydy0,0° Ydy0,0°
Yndyn0, Dz0
Yd1, YNd1 Yd1,-30° Yy0,0°
Yd1, YNd1 + Earthing Transformer Yd1,-30° Ydy0,0°
Yy2, YNy2, Yyn2, YNyn2, Ydy2, YNdy2, Ydyn2, Ydy2,-60° Ydy0,0°
Yndyn2, Dz2
Yd3, YNd3 Yd3,-90° Yy0,0°
Yy4, YNy4, Yyn4, YNyn4, Ydy4, YNdy4, Ydyn4, Ydy4,-120° Ydy0,0°
Yndyn4, Dz4
Yd5, YNd5 Yd5,-150° Yy0,0°
Yy6, YNy6, Yyn6, YNyn6, Ydy6, YNdy6, Ydyn6, Ydy6,180° Ydy0,0°
Yndyn6, Dz6
Yd7, YNd7 Yd7,150° Yy0,0°
Yd7, YNd7 + Earthing Transformer Yd7,150° Ydy0,0°
Yy8, YNy8, Yyn8, YNyn8, Ydy8, YNdy8, Ydyn8, Ydy8,120° Ydy0,0°
Yndyn8, Dz8
Yd9, YNd9 Yd9,90° Yy0,0°
Yd9, YNd9 + Earthing Transformer Yd9,90° Ydy0,0°
Yy10, Yny10, Yyn10, YNyn10, Ydy10, YNdy10, Ydy10,60° Ydy,0°
Ydyn10, Yndyn10, Dz10
Yd11, Ynd11 Yd11,30° Yy0,0°

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Yd11, Ynd11 + Earthing Transformer Yd11,30° Ydy0,0°

Dy1, Dyn1 Yy0,0° Yd11,30°
Dy1, Dyn1 + Earthing Transformer Ydy0,0° Yd11,30°
Dy3, Dyn3 Yy0,0° Yd9,90°
Dy5, Dyn5 Yy0,0° Yd7,150°
Dy7, Dyn7 Yy0,0° Yd5,-150°
Dy7, Dyn7 + Earthing Transformer Ydy0,0° Yd5,-150°
Dy9, Dyn9 Yy0,0° Yd3,-90°
Dy11, Dyn11 Yy0,0° Yd1,-30°
Table 25 - Interposing CT Selection
1. Y or y denotes an unearthed star connection on the HV or LV side of the transformer

respectively.
2. YN or yn denotes an earthed star connection on the HV or LV side of the transformer
respectively.
3. D or d denotes a delta connection on the HV or LV side of the transformer respectively.
4. Z or z denotes a zigzag connection on the HV or LV side of the transformer respectively.
Differential High Set Settings:

Differential high set element operate on the differential current measured by the relay,
this is an unbiased, instantaneous element in the differential circuit to provide the fast
tripping for heavy internal faults. It must be set to a value in excess of any predictable
differential current, i.e. the differential current under maximum through fault conditions with
the transformer tap changer in its extreme position and the differential current due to
magnetizing inrush. The highest should be set as low as possible but not less than the
maximum three phase through fault current and not less than the maximum magnetizing
current.

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2.1.1.7 Applications
Relay Setting Calculation Example
Figure 51 - Transformer Differential Protection Scheme
Power Transformer Details:

Transformer Rating = 90 MVA
Voltage = 132/33kv
Tap range = +10% to -20%
Vector group = Yd11
Current Transformer Details:

CT ratio for HV side = 400/1
CT ratio for LV side = 1600/1
Setting Calculation:
HV Rated current = 90MVA / 1.73*132KV
= 393.7A
CT ratio for HV side is = 400/1A
LV Rated current = 90MVA / 1.73*33KV
= 1574A
CT ratio for LV side is = 1600/1A
HV CT secondary current = 393.7/400 = 0.98A
LV CT secondary current = 1574/1600 = 0.98A
HV ICT Multiplier = 1/0.98 = 1.02
LV ICT Multiplier = 1/0.98 = 1.02

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Initial setting (Minimum 87BD pick up) = 300mA (30%) based on tap range or 2 times of
maximum spill current, whichever is greater
Differential Bias (87BD) slope 1 = 0.30 (30%) 2 times of maximum tap changes %
Differential Bias (87BD) slope1 Limit = 3.6 (Depends on the impedance of transformer)
Differential Bias (87BD) slope2 = 1.50
HV ICT vector connection = Yd11
LV ICT vector connection = Yy0

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2.1.2 Restricted Earth Fault Protection
The restricted earth-fault protection function is useful in protection of generators and

power transformers. The single phase current input is derived from the residual output of
line/neutral CTs connected in parallel. An external stabilising resistor must be connected in
series with this input to ensure that this element provides a high impedance path.
The protection is sensitive to the fundamental frequency component of the differential

neutral current. Whenever this value exceeds the predefined threshold of a particular stage,
that stage picks up and an Alarm Signal is issued. If the fault situation persists for longer
than the estimated trip time configured in the relay, a Trip Signal is issued.
ANSI
Protection Function IEC 61850 Logical Node
No.
Restricted Earth Fault A64RH1_PTOC1, A64RH2_PTOC1,
64
Protection A64RL1_PTOC1, A64RL2_PTOC1
The settings for Restricted Earth-fault protection can be found in REF Settings menu
respectively in the device. Aegis Transformer Protection Relay gives restricted earth-fault
protection to either or both the windings, HV & LV, and provides two adjustable stages
which operate with a definite time (DT) characteristic. The function contains a blocking
functionality. It is possible to block function outputs and the function itself, if desired. The
various settings for each stage can also be configured through the ConAegis Relay
A64Rx_PTOC1
Ig
Start
Enable
Operate
Block
Figure 52 - IEC 61850 Functional Blocks for Restricted Earth Fault Protection
 Ig : Differential Residual current


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 Start : Pickup instance due to restricted earth fault
 Operate : Trip instance due to restricted earth fault
Figure shows the functional block diagram for restricted earth fault protection & each
block has been described below:
Figure 53 - Functional Block Diagram for Restricted Earth Fault Protection
 This function can be enabled by configuring the 64 PROT setting to ENABLE. A

threshold can be defined using 64 SET, ranging from 5% to 95% of the rated current.
The earth current Ig from the dedicated analog input is sensed and compared with the
threshold value by the comparator, wherein, there are two possible cases:
 If injected earth current is 5% above the set threshold, this stage picks up, and an Alarm
Communication Software. The Blocking Signal can be controlled by a binary input
(BI), a virtual input (VI), or an internal signal of the IED program.
 Further, according to the DT curve, the device operates after predefined time in 64 DT
setting, when current exceeds its pickup value. Here, the operational time is constant,
irrespective of the magnitude of the current. When the timer has reached the value of DT
delay in the DT mode or the maximum value defined by the inverse time curve, Trip
Signal is issued by the device.

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2.1.2.5 Restricted Earth Fault Settings & Signals
The following table gives functioning and ranges for each of the settings in REF
Settings menu for Restricted Earth-fault Protection. These settings are same for both the
stages & windings of IDMT & INST operation.
Restricted Earth-fault Protection (64)

Description
Protection: Enables/ disables Restricted earth-fault protection.
64 PROT Enable - Disable - Disable
Pickup Setting: Sets the pick-up current level.
64 SET 0.05 – 0.95 xIn 0.05 0.1
64 DT 0.00s – 600.0s 0.1s 2.00s
Table 26 - Restricted Earth-fault Protection Settings
stages of Restricted Earth-fault Protection. LEDs can be assigned to indicate these signals and
BIs for pickup and trip in any of the phases can be mapped to the BOs.
Restricted Earth-fault Protection

Signals Description
LEDs BOs
HVREF S1T Restricted Earth Fault HV Stage 1 Trip Signal
HVREF S2T Restricted Earth Fault HV Stage 2 Trip Signal
LVREF S1T Restricted Earth Fault LV Stage 1 Trip Signal
LVREF S2T Restricted Earth Fault LV Stage 2 Trip Signal LEDs BOs
HVREF S1P Restricted Earth Fault HV Stage 1 Pickup Signal 5 - 16 1–8
HVREF S2P Restricted Earth Fault HV Stage 2 Pickup Signal
LVREF S1P Restricted Earth Fault LV Stage 1 Pickup Signal
LVREF S2P Restricted Earth Fault LV Stage 2 Pickup Signal
Table 27 - Restricted Earth-fault Protection Signals

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logical nodes A64RH1_PTOC1, A64RH2_PTOC1, A64RL1_PTOC1, A64RL2_PTOC1
of IEC 61850 defined for stages of Restricted Earth-fault Protection respectively.
A64RH1_PTOC1: Restricted Earth fault Protection

Data Objects Functional Constraint Available
Description
(DO) (FC) Options / Range
OpDITmms Set Point (SP) 0s – 600s DT Timer
Table 28 - Restricted Earth fault Protection in IEC 61850 Settings Logical Node
A64RH2_PTOC1: IDMT Restricted Earth fault Protection

Description
Str-neut Restricted Earth fault HV Stage1Pickup Signal
Status (ST)
Op-neut Restricted Earth fault HV Stage1 Trip Signal
Table 29 - Restricted Earth fault Protection Signals in IEC 61850 Logical Node
Similarly, the settings & status of pickup & trip signals for both the stages of both the
windings can be viewed in logical nodes A64RH2_PTOC1, A64RL1_PTOC1,
A64RL2_PTOC1.
Setting Guidelines
Stability Requirement:
All CTs must have the same ratio. The use of class PX/PS CTs is recommended and
ensures steady state CT errors are minimised. A class PX/PS CT has a defined secondary
excitation characteristic and secondary winding resistance, this is sufficient to allow an
assessment of its transient performance. Transient CT errors are caused by CT saturation e.g.
due to high currents flowing at times of through faults. Where CT saturation conditions are
different in each CT this will cause differential current to flow in the CT secondary circuit
wiring. The highest level of differential current will flow when one set of CTs is fully
saturated, providing zero output and all other CTs transform normally. When fully saturated
the CT secondary provides no current and it behaves as a resistance in the secondary circuit.
Differential current in the secondary circuit will flow either through this „resistance‟ or
through the relay. A „stabilising‟ resistance is added in series with the relay input to ensure
that the operate voltage at the current setting is greater than the maximum voltage which can
appear across the element/stabilising resistor during the maximum assigned through fault
current. It is assumed that any earthing resistor can become short-circuit.
The maximum voltage that can appear across the relay circuit can be determined by a
simple calculation which makes the following assumptions:

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One current transformer is fully saturated making its excitation current negligible. The
remaining current transformers maintain their ratio.
The resistance of the secondary winding of the saturated CT together with the leads
connecting it to the relay circuit terminals constitutes the only burden in parallel with the
relay.
The minimum required relay operates voltage setting (Vs) is given by:
Vs ≥ If (RCT+RL) x T
To ensure high speed relay operation, the relay circuit operating voltage should be selected in
accordance with the stability requirement as given in above equation. Also, the operate
voltage should not exceed 0.5 x CT knee point voltage (Vk).
VS ≤ Vk /2
Current Transformer Requirements
The minimum Current transformer Knee point voltage (Vk)
Vk = 2Vs
The exciting current to be drawn by the current transformer at the relay stability voltage Vs
will be
Ie < ( Is - Ir ) / n
where, Is = relay effective current

Ir = relay setting
REF menu of the Aegis relay can be configured with required differential current
setting. Typically it would be set to give primary operating current of either 30% of minimum
earth fault level for resistance earthed system or 10 to 60% of rated current for solidly earthed
system.

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Example 1: Restricted Earth fault Protection on Delta Side of the Power

Transformer
Figure 54 - Restricted Earth Fault Protection on Delta Side
Power transformer rating: 10MVA, 33/11kv

Rated current of power transformer = 10MVA/ 1.73*33KV
= 175A.
Transformer percentage impedance = 6.5%
Primary fault current = 175 / (6.5%),

= 2692.30A (network impedance is not considered)
Fault current on secondary side (If) = 2692.30 x (1/200)

= 13.46A
Required primary operating current, typically 10-25% of protected winding rated current or
as specified by the user.
Primary operating current (10%-25% of Irated) = 17.5A - 43.75A, say 20A.

i.e. 0.1A on secondary side.
Calculation of required stability voltage:
Vs ≥ If (RCT+RL)

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CT Details:
Voltage Knee point (Vk): 120V
Magnetising Current (Imag): 30mA
CT secondary resistance (RCT) 2.5 Ohms
CT lead loop resistance (RL) 0.15 Ohms max.
Vs ≥ 13.46 x ( 2.5+0.15)
Vs = 35.67V
Vs ≤ Vk/2 =120/2 =60V.
.·. 35.67V ≤ Vs ≤ 60V
Calculation of stabilizing Resistor Value:
Required relay setting (Is) can be calculated from primary operating current =(3Imag + Is) / T
Is = primary operating current x T- 3Imag
= 0.1-3(Imag)
Say Provisional relay circuit setting voltage = 50V (from 35.67V ≤ Vs ≤ 60V ),
at 50V Imag=8mA.
Is =0.1-3(0.008) = 0.076A. say 0.08A
Rstab = 50/0.08 = 625 Ohm,

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Example 2: Restricted Earth fault Protection on Star Side of the Power

Transformer
Figure 55 - Restricted Earth Fault Protection on Star Side
Power transformer rating: 10MVA, 33/11kv

Rated current of power transformer on 11Kv side = 10MVA/ 1.73*11KV
= 525A.
Transformer percentage impedance = 6.5%
Fault current on 11kv side = 525 / (6.5%),
= 8076A (network impedance is not consider)
Fault current on secondary side of CT (If) = 8076 x (1/600) = 13.46A
Required primary operating current, typically 10-25% of protected winding rated current or
as specified by the user.
Primary operating current (10%-25% of Irated) = 52.5A – 131.25A, say 60A.

i.e. 0.1A on secondary side.
Calculation of required stability voltage:
Vs ≥ If (RCT+RL)

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CT Details:
Line CT Knee point Voltage (Vk): 360V

Earth CT Knee point Voltage (Vk): 300V
Line CT Magnetising Current (Imag): 30mA
Earth CT Magnetising Current (Imag): 40mA
Line CT secondary resistance (RCT): 7.5 Ohms
Earth CT secondary resistance (RCT): 6 Ohms
Line CT lead loop resistance (RL) 0.15 Ohms max
Earth CT lead loop resistance (RL) 0.2 Ohms max.
Vs ≥ 13.46 x (7.5+0.15) = 102.96V
Vs ≥ 13.46 x (6+0.2) = 83.45V
Vs ≤ Vk/2 = 300/2 = 150V.
.·. 102.96V ≤ Vs ≤ 150V
Calculation of stabilizing Resistor Value:
Required relay setting (Is) can be calculated from primary operating current
= (3Imag + Imag + Is) / T
Is = primary operating current x T- ( 3Imag+Imag)
= 0.1-(3Imag+Imag)
Say Provisional relay circuit setting voltage = 120V (from 102.96V ≤ Vs ≤ 150V), at
120V Imag= 7mA, and Imag of earth CT = 9mA
Is =0.1-((3 x 0.007) + 0.009) = 0.07A.
Rstab = 120/0.07 = 1714 Ohm, say 1800ohm giving Vs =120V
High-impedance restricted earth fault principle:
High-impedance principle is stable for all types of faults outside the zone of protection.
The stabilization is obtained by a stabilizing resistor in the differential circuit. This method
requires that all the CTs used have a similar magnetizing characteristic, same ratio and
relatively high knee point voltage. CTs on each sides are connected in parallel along with a
relay-measuring branch as shown in figure.

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Figure 56 - Restricted Earth Fault Protection (CT Connection)
The impedance-based restricted earth-fault protection is used for the restricted earth-
fault protection of power transformers. Restricted earth fault protection can be applied to
either or both windings of the transformer.
In solidly earthed systems, the restricted earth-fault protection is always deployed as a

complement to the normal transformer differential protection. The advantage of the restricted
earth-fault protection is its high sensitivity. The level for restricted earth fault protection is
dependent of the current transformers' magnetizing currents. The restricted earth-fault
protection is also very fast due to the simple measuring principle as it is a unit type of
protection.
The zone of REF protection is defined by the position of the CTs and/or the transformer
winding. REF protection provides a low operate current (fault setting) for in zone earth faults
and stability during external faults. The restricted earth-fault protection relay is connected
across each directly or to low-ohmic earthed transformer winding. If the same CTs are
connected to relay for current other protection, separate cores are to be used.
REF is more sensitive than overall biased differential protection (87BD) to earth faults it
can protect against faults for a greater portion of the transformer windings or where the
impedance in the earth fault path is relatively high. For a solidly earthed star winding, the
REF function is roughly twice as sensitive in detecting a winding earth fault, than biased
differential protection.

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2.2 THREE PHASE CURRENT PROTECTION

Overcurrent is an occurrence of a situation where a higher magnitude than the intended
current exists through a conductor, which may lead to damage to the equipment. Most of the
power system faults result in overcurrent of one kind or another, and it is the duty of
protection devices, to protect the power system from such faults.
The Aegis Series Transformer Protection Relay offers a wide range of overcurrent
protection functions including:
 Overcurrent Protection
 Derived Earth Fault Protection
 Measured Earth Fault Protection
 Negative Sequence Overcurrent Protection
 Thermal Overload Protection
 Under Current Protection
2.2.1 Overcurrent Protection
This protection function is used as one-phase, two-phase or three-phase overcurrent

and short circuit protection against the heavy over loads. The protection measures the
fundamental frequency components of the phase currents and is sensitive for the highest of
the three phase currents. Whenever this value exceeds the predefined threshold of a particular
stage, that stage picks up and an Alarm Signal is issued. If the fault situation persists for
longer than the estimated trip time configured in the relay, a Trip Signal is issued.
ANSI IEC
Protection Function IEC 61850 Logical Nodes
No. Symbol
Overcurrent Protection – A51H1_PTOC1, A51H2_PTOC1,
51 3I>
IDMT Stage A51L1_PTOC1, A51L2_PTOC1
Overcurrent Protection – A50H1_PIOC1, A50H2_PIOC1,
50 3I>>
Instantaneous Stage A50L1_PIOC1, A50L2_PIOC1
The settings for IDMT & Instantaneous Overcurrent protection can be found in 3I>
Settings & 3I>> Settings menu respectively in the device. Aegis Transformer Protection
Relay gives overcurrent protection to either of the windings, HV or LV, and provides two
adjustable overcurrent stages for IDMT as well as INST operation. 3I> stage can be

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configured either for definite time (DT) or inverse time operation characteristics (IDMT).
3I>> stage always operates with a definite time (DT) operation characteristic. By setting the
definite delay value to its minimum, an instantaneous operation is obtained, also known as
High Set Phase Overcurrent Protection. The function contains a blocking functionality. It is
possible to block function outputs and the function itself, if desired. The various settings for
each stage can also be configured through the ConAegis Relay Communication Software.
A51x_PTOC1 A50x_PIOC1
IL1 IL1
IL2 Start IL2 Start
IL3 Operate IL3 Operate
Enable Enable
Block Block
Figure 57 - IEC 61850 Functional Blocks for Overcurrent Protection
 IL1, IL2, IL3 : Measured currents in phase A, B, C respectively

 Start : Pickup instance due to overcurrent
 Operate : Trip instance due to overcurrent
A. Overcurrent Protection – IDMT Stage (51) (3I>) (A51x_PTOC1):
Figure shows the functional block diagram for overcurrent protection – IDMT Stage, &

The highest of the three phase currents is sensed and compared with the threshold value
by the comparator, wherein, there are two possible cases:
 If injected current is 5% above the set threshold, this stage picks up, and an Alarm Signal
is issued by the device. This current is known as pickup current. This signal is also made
available directly to the user for use in Logic in the ConAegis Relay Communication
Software. The Blocking Signal can be controlled by a binary input (BI), a virtual input
(VI), or an internal signal of the IED program. The protection function may be disabled
on activation of a BI or VI. Also, the protection may be blocked if 2nd harmonic is
detected. This can be done by configuring 51 If2>ACT setting.

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Figure 58 - Functional Block Diagram for IDMT Overcurrent Protection
 Further, according to the type of time - current characteristics chosen in 51 CURVE

setting (IDMT / DT), the timer block calculates the delay according to the respective
equations. When IDMT curves are selected, the operation time characteristics are defined
by the type of the curve, 51 CURVE, and the Time Multiplier Setting, 51 TMS. If DT
curve is chosen, relay operates after definite time configured in 51 DT setting, when
current exceeds its pickup value. Here, the operational time is constant, irrespective of the
magnitude of the current. When the timer has reached the value of DT delay in the DT
mode or the maximum value defined by the inverse time curve, Trip Signal is issued by
the device.
precise decision making in this case, a pick up current and a dropout current is defined
above and below the set threshold in the Configuration Menu, which is typically 95% to
105%. In case of DT operation, as soon as the Alarm Signal is issued, an added feature
of Reset DT Timer comes into picture, and its value corresponds to the minimum time
during which the current value needs to be lower than 95% of the phase threshold to
dropout, or higher than 105% of the phase threshold to pickup, before the corresponding
phase time delay is reset. This delay can be set in the 51 RST DT setting.

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B. Overcurrent Protection – Instantaneous Stage (50) (3I>>) (A50x_PIOC1):
The High Set Stage of Aegis Transformer Protection Relay has DT Characteristic of
variable time operation with respect to the fault current. Figure shows the functional block
diagram for overcurrent protection – Instantaneous Stage, & each block has been described
below:
Figure 59 - Functional Block Diagram for INST Overcurrent Protection

The highest of the three phase currents is sensed and compared with the threshold value
on activation of a BI or VI. Also, the protection may be blocked if 2nd harmonic is
detected. This can be done by configuring 50 If2>ACT setting.

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2.2.1.5 Timer Characteristics
The overcurrent protection supports both DT and IDMT characteristics. The device
provides 11 IDMT characteristics curves, complying with ANSI, IEC & IAC standards. The
following table gives the standard IDMT characteristics for Overcurrent protection along
with their equations:
Operation Time Characteristics Equation (IEC /IEEE)
IEC SI3
(Standard Inverse 3)
IEC SI1
IEC VI
(Very Inverse)
IEC EI
(Extremely Inverse)
IEC LTI
(Long Time Inverse)
ANSI EI
Extremely Inverse
ANSI VI
Very Inverse

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ANSI MI
Moderately Inverse
IAC SI3
IAC VI
(Very Inverse)
IAC EI
(Extremely Inverse)
Table 30 - Standard IDMT Curves for Overcurrent Protection
where,
t = operating time,
I = measured current,
Is = current threshold setting,
TMS = Time Multiplier Setting value

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2.2.1.6 Overcurrent Settings & Signals
The following table gives functioning and ranges for each of the settings in 3I> & 3I>>
Settings menu for Overcurrent Protection. These settings are same for both the stages &
windings of IDMT & INST operation.
Note: LV settings are disabled and cannot be configured when the selected Auxiliary
Function is HV, & vice versa.
IDMT Overcurrent Protection (3I>)

Description
Protection: Enables/ disables IDMT overcurrent protection.
51 SET 0.05 – 2.50 xIn 0.01 1.00
Curve Type: Selects the required IDMT characteristics.
DT, ANSI EI, ANSI VI, ANSI MI,
51 CURVE IEC SI1, IEC SI3, IEC EI, IEC VI, IEC LTI, - IEC SI3
IAC SI3, IAC VI, IAC EI
Time Multiplier: Sets the Time Multiplier Setting to adjust operating time.
For IEC & ANSI Curves: 0.02 - 2 0.01
51 TMS 1.00
For IAC Curve: 1-100 0.1
nd
51 If2>ACT ON / OFF - OFF

Reset DT Timer: Sets the reset time for Reset DT characteristics.
51 RST DT 0.10s – 60.0s 0.1s 0.10s
51 DT 0.00s – 600.0s 0.1s 1.00s
Instantaneous Overcurrent Protection (3I>>)
Description
Protection: Enables/ disables instantaneous non-directional overcurrent protection.
0.05 for 0.05 - 5.00
50 SET 0.05 – 40.00 xIn 2.50
0.10 for 5.00 - 40.00
50 DT 0.00s – 600.0s 0.1s 1.00s
nd nd
2 Harmonic Blocking: Blocks the protection on 2 harmonic detection.
50 If2>ACT ON / OFF - OFF
Table 31 - Overcurrent Protection Settings

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stages of IDMT & INST Overcurrent Protection. LEDs can be assigned to indicate these
signals and BIs for pickup and trip in any of the phases can be mapped to the BOs.
IDMT Overcurrent Protection (3I>)

Signals Description
LEDs BOs
HVI>1 S1T IDMT Overcurrent HV Stage 1 Trip Signal for phase-A
HVI>2 S1T IDMT Overcurrent HV Stage 1 Trip Signal for phase-B
HVI>3 S1T IDMT Overcurrent HV Stage 1 Trip Signal for phase-C
HVI>1 S2T IDMT Overcurrent HV Stage 2 Trip Signal for phase-A
HVI>2 S2T IDMT Overcurrent HV Stage 2 Trip Signal for phase-B
HVI>3 S2T IDMT Overcurrent HV Stage 2 Trip Signal for phase-C
LVI>1 S1T IDMT Overcurrent LV Stage 1 Trip Signal for phase-A
LVI>2 S1T IDMT Overcurrent LV Stage 1 Trip Signal for phase-B
LVI>3 S1T IDMT Overcurrent LV Stage 1 Trip Signal for phase-C
LVI>1 S2T IDMT Overcurrent LV Stage 2 Trip Signal for phase-A
LVI>2 S2T IDMT Overcurrent LV Stage 2 Trip Signal for phase-B
LVI>3 S2T IDMT Overcurrent LV Stage 2 Trip Signal for phase-C LEDs BOs
HVI>1 S1P IDMT Overcurrent HV Stage 1 Pickup Signal for phase-A 5 - 16 1–8
HVI>2 S1P IDMT Overcurrent HV Stage 1 Pickup Signal for phase-B
HVI>3 S1P IDMT Overcurrent HV Stage 1 Pickup Signal for phase-C
HVI>1 S2P IDMT Overcurrent HV Stage 2 Pickup Signal for phase-A
HVI>2 S2P IDMT Overcurrent HV Stage 2 Pickup Signal for phase-B
HVI>3 S2P IDMT Overcurrent HV Stage 2 Pickup Signal for phase-C
LVI>1 S1P IDMT Overcurrent LV Stage 1 Pickup Signal for phase-A
LVI>2 S1P IDMT Overcurrent LV Stage 1 Pickup Signal for phase-B
LVI>3 S1P IDMT Overcurrent LV Stage 1 Pickup Signal for phase-C
LVI>1 S2P IDMT Overcurrent LV Stage 2 Pickup Signal for phase-A
LVI>2 S2P IDMT Overcurrent LV Stage 2 Pickup Signal for phase-B
LVI>3 S2P IDMT Overcurrent LV Stage 2 Pickup Signal for phase-C
Instantaneous Overcurrent Protection (3I>>)
Signals Description
LEDs BOs
HVI>>1 S1T INST Overcurrent HV Stage 1 Trip Signal for phase-A
HVI>>2 S1T INST Overcurrent HV Stage 1 Trip Signal for phase-B
HVI>>3 S1T INST Overcurrent HV Stage 1 Trip Signal for phase-C
HVI>>1 S2T INST Overcurrent HV Stage 2 Trip Signal for phase-A
HVI>>2 S2T INST Overcurrent HV Stage 2 Trip Signal for phase-B
HVI>>3 S2T INST Overcurrent HV Stage 2 Trip Signal for phase-C
LVI>>1 S1T INST Overcurrent LV Stage 1 Trip Signal for phase-A LEDs BOs
LVI>>2 S1T INST Overcurrent LV Stage 1 Trip Signal for phase-B 5 - 16 1–8
LVI>>3 S1T INST Overcurrent LV Stage 1 Trip Signal for phase-C
LVI>>1 S2T INST Overcurrent LV Stage 2 Trip Signal for phase-A
LVI>>2 S2T INST Overcurrent LV Stage 2 Trip Signal for phase-B
LVI>>3 S2T INST Overcurrent LV Stage 2 Trip Signal for phase-C
HVI>>1 S1P INST Overcurrent HV Stage 1 Pickup Signal for phase-A
HVI>>2 S1P INST Overcurrent HV Stage 1 Pickup Signal for phase-B

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HVI>>2 S1P INST Overcurrent HV Stage 1 Pickup Signal for phase-C

HVI>>1 S2P INST Overcurrent HV Stage 2 Pickup Signal for phase-A
HVI>>2 S2P INST Overcurrent HV Stage 2 Pickup Signal for phase-B
HVI>>3 S2P INST Overcurrent HV Stage 2 Pickup Signal for phase-C
LVI>>1 S1P INST Overcurrent LV Stage 1 Pickup Signal for phase-A
LVI>>2 S1P INST Overcurrent LV Stage 1 Pickup Signal for phase-B
LVI>>3 S1P INST Overcurrent LV Stage 1 Pickup Signal for phase-C
LVI>>1 S2P INST Overcurrent LV Stage 2 Pickup Signal for phase-A
LVI>>2 S2P INST Overcurrent LV Stage 2 Pickup Signal for phase-B
LVI>>3 S2P INST Overcurrent LV Stage 2 Pickup Signal for phase-C
Table 32 - Overcurrent Protection Signals

logical nodes A51H1_PTOC1, A51H2_PTOC1, A51L1_PTOC1, A51L2_PTOC1, &
A50H1_PIOC1, A50H2_PIOC1, A50L1_PIOC1, A50L2_PIOC1 of IEC 61850 defined
for IDMT & INST stages of Overcurrent Protection respectively.
A51H1_PTOC1: IDMT Overcurrent Protection HV Stage 1

Description
1- ANSI EI
2- ANSI VI
4-ANSI MI
9- IEC SI1
10- IEC VI
12- IEC EI
TmACrv IDMT Curve Type
Set Point (SP) 13- IEC SI3
14- IEC LTI
15- DT
39- IAC EI
40- IAC VI
41- IAC SI3
OpDITmms 0s – 600s DT Timer
Table 33 - Overcurrent Protection Settings in IEC 61850 Logical Node
A51H1_PTOC1: IDMT Overcurrent Protection HV Stage 1

Description
Str-gen IDMT Overcurrent Pickup Signal in any of the phase
Str-phsA IDMT Overcurrent Pickup Signal in Phase A
Str-phsB IDMT Overcurrent Pickup Signal in Phase B
Str-phsC Status (ST) IDMT Overcurrent Pickup Signal in Phase C
Op-gen IDMT Overcurrent Trip Signal in any of the phase
Op-phsA IDMT Overcurrent Trip Signal in Phase A
Op-phsB IDMT Overcurrent Trip Signal in Phase B
Op-phsC IDMT Overcurrent Trip Signal in Phase C

`
A50H1_PIOC1: INST Overcurrent Protection HV Stage 1

Description
Str-gen INST Overcurrent Pickup Signal in any of the phase
Str-phsA INST Overcurrent Pickup Signal in Phase A
Str-phsB INST Overcurrent Pickup Signal in Phase B
Str-phsC Status (ST) INST Overcurrent Pickup Signal in Phase C
Op-gen INST Overcurrent Trip Signal in any of the phase
Op-phsA INST Overcurrent Trip Signal in Phase A
Op-phsB INST Overcurrent Trip Signal in Phase B
Op-phsC INST Overcurrent Trip Signal in Phase C
Table 34 - Overcurrent Protection Signals in IEC 61850 Logical Node
Similarly, all the settings & the status of pickup & trip signals for both the stages of
both the windings can be viewed in logical nodes A51H2_PTOC1, A51L1_PTOC1,
A51L2_PTOC1 & A50H2_PIOC1, A50L1_PIOC1, & A50L2_PIOC1 for IDMT & INST
operation respectively.
Setting Guidelines
For calculation of pick up current and time setting co-ordination, standard principles
should be applied. The following setting calculation example describes how the settings can
be configured in the relay.
Before configuring the current setting, ensure that the entered CT ratio is correct. Aegis
relay allows the pickup current setting in the percentage of In, where In is either CT
secondary or primary, depending on what we consider during the calculation. Assume that
the parameters mentioned below are feeding power to power transformer.
Current Transformer Ratio: 200/1 A

Full load current of circuit: 180A
Aegis relay setting must account for maximum load current.

I> Must be greater than : 180/0.95 = 190A,
Hence, the required setting in terms of secondary will be 0.95A, i.e. 95%, and in terms of
primary 190A, i.e. (190/200) *100 = 95%
Inverse Definite Minimum Time (IDMT) and definite time characteristics need to be
selected with TMS value or DT operate time, depending on the network co-ordination with
upstream and downstream relay.

`
Non directional overcurrent protection is used in several application of the power

system, & is most commonly used protection in the power system network. It provides main
protection to feeder and busbar in the transmission and distribution system, and is also used
as back-up protection of power transformer and generators when unit protection is not used.
Furthermore, it is used for protection of various costly industrial equipments like capacitor
bank, motors, power cables and rectifier etc.
Non directional overcurrent protection is used to clear three phase overload and short-
circuit faults of power system with Inverse definite minimum time (IDMT) characteristic and
definite time (DT) for fast and selective operation. User can select this characteristic with
minimum pick up current level. To operate the overcurrent protection, the current should be
above the pick-up level. If current exceeds the pick-up level, relay will operate and generate
the tripping signal with LED indication and output contact configuration.
Transformer Overcurrent Protection
Overcurrent protection for transformer is used to operate as main overcurrent protection

when differential protection schemes are not used, or it can be used as back-up protection for
differential protection of power transformer. It protects primary and secondary winding of
transformer, LV side busbar and equipments connected on LV side. The purpose of
protecting LV side busbar and equipments is to protect the transformer from short circuits
occurring outside the protection zone. The magnitude of fault current depends on fault
location, impedance of transformer and source impedance of feeding network, which will be
several times of In. From this point of view, protection operation must be very fast and
selective, which is usually achieved by using current setting. In case of overcurrent fault, if
circuit breaker malfunctions, the breaker fail protection is used to confirm the scheme. The
application example for overcurrent protection of transformer as shown in figure 58.

`
50 51 68
50 51 BF
INCOMING
BUSBAR
50 51 BF 50 51 68 50 51 68 50 51 BF
OUTGOING OUTGOING OUTGOING OUTGOING

Figure 60 - Typical transformer overcurrent application example
The operating time of the main and backup overcurrent protection of the above scheme
becomes quite long. This applies especially in the busbar faults and transformer LV-terminal
faults. In order to improve the performance of the above scheme, overcurrent protection
stages with reverse blocking is proposed. Figure 59 shows reverse blocking arrangement of
overcurrent protection of transformer and busbar.

`
50 51 68 50 51 68
50 51 BF 50 51 BF
INCOMING INCOMING
BUSBAR
50 51 BF 50 51 68 50 51 68 50 51 BF
OUTGOING OUTGOING OUTGOING OUTGOING

Figure 61 - Reverse blocking principle of overcurrent protection using digital input and digital output channel

`
2.2.2 Derived Earth Fault Protection
Earth fault protection is used to detect earth faults in low impedance earthed networks.
The protection is sensitive to the fundamental frequency component of the earth

current which is derived by calculating the sum of the measured line currents. Whenever this
value exceeds the predefined threshold of a particular stage, that stage picks up and an Alarm
ANSI IEC
No. Symbol
Derived Earth Fault Protection A51NH1_PTOC1, A51NH2_PTOC1,
51N Io>
– IDMT Stage A51NL1_PTOC1, A51NL2_PTOC1
Derived Earth Fault Protection A50NH1_PTOC1, A50NH2_PTOC1,
50N Io>>
– Instantaneous Stage A50NL1_PTOC1, A50NL2_PTOC1,
The settings for IDMT & Instantaneous Derived Earth-fault protection can be found in
Io> Settings & Io>> Settings menu respectively in the device. Aegis Transformer Protection
Relay gives earth-fault protection to either of the windings, HV or LV, and provides two
adjustable stages for IDMT as well as INST operation. Io> stage can be configured either for
definite time (DT) or inverse time operation characteristics (IDMT). Io>> stage always
operates with a definite time (DT) operation characteristic. By setting the definite delay value
to its minimum, an instantaneous operation is obtained, also known as High Set Phase
Derived Earth-fault Protection. The function contains a blocking functionality. It is possible
to block function outputs and the function itself, if desired. The various settings for each
stage can also be configured through the ConAegis Relay Communication Software.

`
A51Nx_PTOC1 A50Nx_PTOC2
Io Io
Start Start
Enable Enable
Operate Operate
Block Block
Figure 62 - IEC 61850 Functional Blocks for Derived Earth Fault Protection
 Io : Measured residual current

 Start : Pickup instance due to derived earth fault
 Operate : Trip instance due to derived earth fault
A. Derived Earth Fault Protection – IDMT Stage (51N) (Io>) (A51Nx_PTOC1):
Figure shows the functional block diagram for derived earth fault protection – IDMT
Stage, & each block has been described below:
Figure 63 - Functional Block Diagram for IDMT Derived Earth Fault Protection
 This function can be enabled by configuring the 51N PROT setting to ENABLE. A
threshold can be defined using 51N SET, ranging from 5% to 250% of the rated current.
The earth current IN is calculated as a sum of three phase current & is sensed and
compared with the threshold value by the comparator, wherein, there are two possible
cases:

`
(BI), a virtual input (VI), or an internal signal of the IED program. The protection
function may be disabled on activation of a BI or VI. Also, the protection may be blocked
if 2nd harmonic is detected. This can be done by configuring 51N If2>ACT setting.
 Further, according to the type of time - current characteristics chosen in 51N CURVE
by the type of the curve, 51N CURVE, and the Time Multiplier Setting, 51N TMS. If DT
curve is chosen, relay operates after definite time configured in 51N DT setting, when
the device.
below the set threshold in the Configuration Menu, which is typically 95% to 105%. In
case of DT operation, as soon as the Alarm Signal is issued, an added feature of Reset
DT Timer comes into picture, and its value corresponds to the minimum time during
which the current value needs to be lower than 95% of the phase threshold to dropout, or
higher than 105% of the phase threshold to pickup, before the corresponding phase time
delay is reset. This delay can be set in the 51N RST DT setting.
B. Derived Earth Fault Protection – Instantaneous Stage (50N) (Io>>) (A50Nx_PTOC1):
diagram for derived earth fault protection – Instantaneous Stage, & each block has been
described below:

`
Figure 64 - Functional Block Diagram for INST Derived Earth Fault Protection
threshold can be defined using 50N SET, ranging from 5% to 4000% of the rated current.
The earth current IN is calculated as a sum of three phase current & is sensed and
compared with the threshold value by the comparator, wherein, there are two possible
cases:
if 2nd harmonic is detected. This can be done by configuring 50N If2>ACT setting.
 Further, according to the DT curve, the device operates after predefined time in 50N DT

`
The derived earth-fault protection supports both DT and IDMT characteristics. The
device provides 11 IDMT characteristics curves, complying with ANSI, IEC & IAC
standards. The following table gives the standard IDMT characteristics for derived earth-fault
protection along with their equations:
IEC SI3
IEC SI1
IEC VI
(Very Inverse)
IEC EI
(Extremely Inverse)
IEC LTI
(Long Time Inverse)
ANSI EI
Extremely Inverse
ANSI VI
Very Inverse
ANSI MI
Moderately Inverse
IAC SI3
IAC VI
(Very Inverse)

`
IAC EI
(Extremely Inverse)
Table 35 - Standard IDMT Curves for Derived Earth-fault Protection
where,
t = operating time,

`
2.2.2.6 Derived Earth Fault Settings & Signals
The following table gives functioning and ranges for each of the settings in Io> & Io>>
Settings menu for Derived Earth-fault Protection. These settings are same for both the stages
& windings of IDMT & INST operation.
IDMT Derived Earth-fault Protection (Io>)

Description
Protection: Enables/ disables IDMT derived earth-fault protection.
51N PROT Enable - Disable - Disable
51N SET 0.05 – 2.50 xIn 0.01 0.20
51N CURVE IEC SI1, IEC SI3, IEC EI, IEC VI, IEC LTI, - IEC SI3
51N TMS 1.00
nd
51N If2>ACT ON / OFF - OFF

51N RST DT 0.10s – 60.0s 0.1s 0.10s
51N DT 0.00s – 600.0s 0.1s 1.00s
Instantaneous Derived Earth-fault Protection (Io>>)
Description
Protection: Enables/ disables instantaneous derived earth-fault protection.
0.05 for 0.05 - 5.00
50N SET 0.05 – 40.00 xIn 2.50
0.10 for 5.00 - 40.00
50N DT 0.00s – 600.0s 0.1s 1.00s
nd
50N If2>ACT ON / OFF - OFF

Table 36 - Derived Earth-fault Protection Settings
stages of IDMT & INST Derived Earth-fault Protection. LEDs can be assigned to indicate
these signals and BIs for pickup and trip in any of the phases can be mapped to the BOs.

`
IDMT Derived Earth-fault Protection (Io>)

Signals Description
LEDs BOs
HVIo> S1T IDMT Derived Earth Fault HV Stage 1 Trip Signal
HVIo> S2T IDMT Derived Earth Fault HV Stage 2 Trip Signal
LVIo> S1T IDMT Derived Earth Fault LV Stage 1 Trip Signal
LVIo> S2T IDMT Derived Earth Fault LV Stage 2 Trip Signal LEDs BOs
HVIo> S1P IDMT Derived Earth Fault HV Stage 1 Pickup Signal 5 - 16 1–8
HVIo> S2P IDMT Derived Earth Fault HV Stage 2 Pickup Signal
LVIo> S1P IDMT Derived Earth Fault LV Stage 1 Pickup Signal
LVIo> S2P IDMT Derived Earth Fault LV Stage 2 Pickup Signal
Instantaneous Derived Earth-fault Protection (Io>>)
Signals Description
LEDs BOs
HVIo>> S1T INST Derived Earth Fault HV Stage 1 Trip Signal
HVIo>> S2T INST Derived Earth Fault HV Stage 2 Trip Signal
LVIo>> S1T INST Derived Earth Fault LV Stage 1 Trip Signal
LVIo>> S2T INST Derived Earth Fault LV Stage 2 Trip Signal LEDs BOs
HVIo>> S1P INST Derived Earth Fault HV Stage 1 Pickup Signal 5 - 16 1–8
HVIo>> S2P INST Derived Earth Fault HV Stage 2 Pickup Signal
LVIo>> S1P INST Derived Earth Fault LV Stage 1 Pickup Signal
LVIo>> S2P INST Derived Earth Fault LV Stage 2 Pickup Signal
Table 37 - Derived Earth-fault Protection Signals

logical nodes A51NH1_PTOC1, A51NH2_PTOC1, A51NL1_PTOC1, A51L2_PTOC1, &
A50NH1_PTOC2, A50NH2_PTOC2, A50NL1_PTOC2, A50NL2_PTOC2 of IEC 61850
defined for IDMT & INST stages of Derived Earth-fault Protection respectively.
A51NH1_PTOC1: IDMT Derived Earth fault Protection

Description
1- ANSI EI
2- ANSI VI
4-ANSI MI
9- IEC SI1
10- IEC VI
12- IEC EI
14- IEC LTI
15- DT
39- IAC EI
40- IAC VI
41- IAC SI3

`
A50NH1_PTOC2: INST Derived Earth fault Protection

Description
Table 38 - Derived Earth fault Protection in IEC 61850 Settings Logical Node
A51NH1_PTOC1: IDMT Derived Earth fault Protection

Description
Str-neut IDMT Derived Earth fault HV Stage1Pickup Signal
Status (ST)
Op-neut IDMT Derived Earth fault HV Stage1 Trip Signal
A50NH1_PTOC2: INST Derived Earth fault Protection
Description
Str-neut INST Derived Earth fault HV Stage1Pickup Signal
Status (ST)
Op-neut INST Derived Earth fault HV Stage1 Trip Signal
Table 39 - Derived Earth fault Protection Signals in IEC 61850 Logical Node
windings can be viewed in logical nodes A51NH2_PTOC1, A51NL1_PTOC1,
A51NL2_PTOC1 & A50NH2_PTOC2, A50NL1_PTOC2, & A50NL2_PTOC2 for IDMT
& INST operation respectively.
Setting Guidelines
In derived earth fault protection, earth fault current value is calculated internally based on
phase current input of all phases. For pick up settings, standard principle should be applied.
The recommended earth fault setting is10-20% of In.
Earth fault protection is used to protect distribution system and sub transmission system
against fault involving ground. Earth faults pose a potential safety risk to personnel and an
earth fault, if undetected, can cause serious damage to costly equipment. The function of
earth fault protection is to detect the earth fault and give the tripping signal to breaker, when
the fault occurs. Earth fault occurs when energized conductor comes in contact with ground
and return path of fault current is through the grounding system. Typically, earth faults are
single line to ground fault or double line to ground fault. If clearance between phases to earth
is below the required clearance or loss of insulation between live conductor and ground, earth
fault protection operates. It also applies to solidly earthed networks and earth fault protection
of different equipment connected to power system.

`
2.2.3 Measured Earth Fault Protection
Earth fault protection is used to detect earth faults in low impedance earthed networks.
The protection is sensitive to the fundamental frequency component of the earth

current which is measured directly via dedicated current analog inputs. Whenever this value
exceeds the predefined threshold of a particular stage, that stage picks up and an Alarm
ANSI IEC
No. Symbol
Measured Earth Fault A51GH1_PTOC1, A51GH2_PTOC1,
51G Ig>
Protection – IDMT Stage A51GL1_PTOC1, A51GL2_PTOC1
Measured Earth Fault
A50GH1_PTOC1, A50GH2_PTOC1,
Protection – Instantaneous 50G Ig>>
A50GL1_PTOC1, A50GL2_PTOC1,
Stage
The settings for IDMT & Instantaneous Measured Earth-fault protection can be found
in Ig> Settings & Ig>> Settings menu respectively in the device. Aegis Transformer
Protection Relay gives earth-fault protection to either of the windings, HV or LV, and
provides two adjustable stages for IDMT as well as INST operation. Ig> stage can be
Ig>> stage always operates with a definite time (DT) operation characteristic. By setting the
High Set Phase Measured Earth-fault Protection. The function contains a blocking

`
A51Gx_PTOC1 A50Gx_PTOC2
Ig Ig
Start Start
Enable Enable
Operate Operate
Block Block
Figure 65 - IEC 61850 Functional Blocks for Measured Earth Fault Protection
 Ig : Measured residual current

 Start : Pickup instance due to Measured earth fault
 Operate : Trip instance due to Measured earth fault
A. Measured Earth Fault Protection – IDMT Stage (51G) (Ig>) (A51Gx_PTOC1):
Figure shows the functional block diagram for measured earth fault protection – IDMT
Stage, & each block has been described below:
Figure 66 - Functional Block Diagram for IDMT Measured Earth Fault Protection
 This function can be enabled by configuring the 51G PROT setting to ENABLE. A
threshold can be defined using 51G SET, ranging from 5% to 250% of the rated current.
The earth current Ig measured from the dedicated analog input is sensed and compared
with the threshold value by the comparator, wherein, there are two possible cases:

`
if 2nd harmonic is detected. This can be done by configuring 51G If2>ACT setting.
 Further, according to the type of time - current characteristics chosen in 51G CURVE
by the type of the curve, 51G CURVE, and the Time Multiplier Setting, 51G TMS. If
DT curve is chosen, relay operates after definite time configured in 51G DT setting, when
the device.
precise decision making in this case, a pick up current and a dropout current is defined
above and below the set threshold in the Configuration Menu, which is typically 95% to
105%. In case of DT operation, as soon as the Alarm Signal is issued, an added feature
of Reset DT Timer comes into picture, and its value corresponds to the minimum time
during which the current value needs to be lower than 95% of the phase threshold to
dropout, or higher than 105% of the phase threshold to pickup, before the corresponding
phase time delay is reset. This delay can be set in the 51G RST DT setting.
B. Measured Earth Fault Protection – Instantaneous Stage (50G) (Ig>>)

(A50Gx_PTOC1):
diagram for measured earth fault protection – Instantaneous Stage, & each block has been
described below:

`
Figure 67 - Functional Block Diagram for INST Measured Earth Fault Protection
 This function can be enabled by configuring the 50G PROT setting to ENABLE. A
threshold can be defined using 50G SET, ranging from 5% to 4000% of the rated current.
The earth current Ig measured from the dedicated analog input is sensed and compared
with the threshold value by the comparator, wherein, there are two possible cases:
if 2nd harmonic is detected. This can be done by configuring 50G If2>ACT setting.
 Further, according to the DT curve, the device operates after predefined time in 50G DT

`
The measured earth-fault protection supports both DT and IDMT characteristics. The
device provides 11 IDMT characteristics curves, complying with ANSI, IEC & IAC
standards. The following table gives the standard IDMT characteristics for measured earth-
fault protection along with their equations:
IEC SI3
IEC SI1
IEC VI
(Very Inverse)
IEC EI
(Extremely Inverse)
IEC LTI
(Long Time Inverse)
ANSI EI
Extremely Inverse
ANSI VI
Very Inverse
ANSI MI
Moderately Inverse

`
IAC SI3
IAC VI
(Very Inverse)
IAC EI
(Extremely Inverse)
Table 40 - Standard IDMT Curves for Measured Earth-fault Protection
where,
t = operating time,

`
2.2.3.6 Measured Earth Fault Settings & Signals
The following table gives functioning and ranges for each of the settings in Ig> & Ig>>
Settings menu for Measured Earth-fault Protection. These settings are same for both the
stages & windings of IDMT & INST operation.
IDMT Measured Earth-fault Protection (Ig>)

Description
Protection: Enables/ disables IDMT Measured earth-fault protection.
51G PROT Enable - Disable - Disable
51G SET 0.05 – 2.50 xIn 0.01 0.20
51G CURVE IEC SI1, IEC SI3, IEC EI, IEC VI, IEC LTI, - IEC SI3
51G TMS 1.00
nd
51G If2>ACT ON / OFF - OFF

51G RST DT 0.10s – 60.0s 0.1s 0.10s
51G DT 0.00s – 600.0s 0.1s 1.00s
Instantaneous Measured Earth-fault Protection (Ig>>)
Description
Protection: Enables/ disables instantaneous Measured earth-fault protection.
50G PROT Enable - Disable - Disable
0.05 for 0.05 - 5.00
50G SET 0.05 – 40.00 xIn 2.50
0.10 for 5.00 - 40.00
50G DT 0.00s – 600.0s 0.1s 1.00s
nd nd
2 Harmonic Blocking: Blocks the protection on 2 harmonic detection.
50G If2>ACT ON / OFF - OFF
Table 41 - Measured Earth-fault Protection Settings
stages of IDMT & INST Measured Earth-fault Protection. LEDs can be assigned to indicate
these signals and BIs for pickup and trip in any of the phases can be mapped to the BOs.

`
IDMT Measured Earth-fault Protection (Ig>)

Signals Description
LEDs BOs
HVIg> S1T IDMT Measured Earth Fault HV Stage 1 Trip Signal
HVIg> S2T IDMT Measured Earth Fault HV Stage 2 Trip Signal
LVIg> S1T IDMT Measured Earth Fault LV Stage 1 Trip Signal
LVIg> S2T IDMT Measured Earth Fault LV Stage 2 Trip Signal LEDs BOs
HVIg> S1P IDMT Measured Earth Fault HV Stage 1 Pickup Signal 5 - 16 1–8
HVIg> S2P IDMT Measured Earth Fault HV Stage 2 Pickup Signal
LVIg> S1P IDMT Measured Earth Fault LV Stage 1 Pickup Signal
LVIg> S2P IDMT Measured Earth Fault LV Stage 2 Pickup Signal
Instantaneous Measured Earth-fault Protection (Ig>>)
Signals Description
LEDs BOs
HVIg>> S1T INST Measured Earth Fault HV Stage 1 Trip Signal
HVIg>> S2T INST Measured Earth Fault HV Stage 2 Trip Signal
LVIg>> S1T INST Measured Earth Fault LV Stage 1 Trip Signal
LVIg>> S2T INST Measured Earth Fault LV Stage 2 Trip Signal LEDs BOs
HVIg>> S1P INST Measured Earth Fault HV Stage 1 Pickup Signal 5 - 16 1–8
HVIg>> S2P INST Measured Earth Fault HV Stage 2 Pickup Signal
LVIg>> S1P INST Measured Earth Fault LV Stage 1 Pickup Signal
LVIg>> S2P INST Measured Earth Fault LV Stage 2 Pickup Signal
Table 42 - Measured Earth-fault Protection Signals

logical nodes A51GH1_PTOC1, A51GH2_PTOC1, A51GL1_PTOC1, A51L2_PTOC1, &
A50GH1_PTOC2, A50GH2_PTOC2, A50GL1_PTOC2, A50GL2_PTOC2 of IEC 61850
defined for IDMT & INST stages of Measured Earth-fault Protection respectively.
A51GH1_PTOC1: IDMT Measured Earth fault Protection

Description
1- ANSI EI
2- ANSI VI
4-ANSI MI
9- IEC SI1
10- IEC VI
12- IEC EI
14- IEC LTI
15- DT
39- IAC EI
40- IAC VI
41- IAC SI3

`
A50GH1_PTOC2: INST Measured Earth fault Protection

Description
(DO) (FC) / Range
Table 43 - Measured Earth fault Protection in IEC 61850 Settings Logical Node
A51GH1_PTOC1: IDMT Measured Earth fault Protection

Description
Str-neut IDMT Measured Earth fault HV Stage1Pickup Signal
Status (ST)
Op-neut IDMT Measured Earth fault HV Stage1 Trip Signal
A50GH1_PTOC2: INST Measured Earth fault Protection
Description
Str-neut INST Measured Earth fault HV Stage1Pickup Signal
Status (ST)
Op-neut INST Measured Earth fault HV Stage1 Trip Signal
Table 44 - Measured Earth fault Protection Signals in IEC 61850 Logical Node
windings can be viewed in logical nodes A51GH2_PTOC1, A51GL1_PTOC1,
A51GL2_PTOC1 & A50GH2_PTOC2, A50GL1_PTOC2, & A50GL2_PTOC2 of IEC
61850 for IDMT & INST operation respectively.
Setting Guidelines
For the Earth-fault relay setting calculations, standard principle should be applied in
calculating the necessary current and time setting. A recommended earth fault setting is 20%
of In.
Consider a 2.5 MVA, 11kV / 3.3kV transformer and CTR 500/5. The full load
secondary current of 2.5MVA transformer will be:
2.5MVA/√3 x3.3kV = 437A,
The earth fault relay should not pick up for unbalance current 20% of 437A =87.47 A.
Hence, choose a pick up value 100A. Now, the relay will pick up at 100 × 5 / 500 = 1A.
Time setting should be set as per coordination with other relays.

`
Earth fault protection is used to protect distribution system and sub transmission system
against fault involving ground. Earth faults pose a potential safety risk to personnel and an
earth fault, if undetected, can cause serious damage to costly equipment. The function of
earth fault protection is to detect the earth fault and give the tripping signal to breaker, when
the fault occurs. Earth fault occurs when energized conductor comes in contact with ground
and return path of fault current is through the grounding system. Typically, earth faults are
single line to ground fault or double line to ground fault. If clearance between phases to earth
is below the required clearance or loss of insulation between live conductor and ground, earth
fault protection operates. It also applies to solidly earthed networks and earth fault protection
of different equipment connected to power system.

`
2.2.4 Negative Phase Sequence Overcurrent Protection
Any unbalance fault condition produces negative phase sequence current of some
magnitude which could not be previously identified by the traditional phase overcurrent as
well as the residual overcurrent protection techniques. This can be now achieved by the
Negative phase sequence overcurrent protection element. A negative phase sequence element
can operate for both phase and earth faults. This kind of protection gives greater sensitivity
compared overcurrent and earth fault protection elements.
The protection measures the fundamental frequency component of the negative phase
sequence current I2. Whenever this value exceeds the predefined threshold of a particular
stage, that stage picks up and an Alarm Signal is issued. If the fault situation persists for
longer than the estimated trip time configured in the relay, a Trip Signal is issued.
ANSI IEC
No. Symbol
Negative Phase Sequence
A46SH1_PTOC1, A46SH2_PTOC1,
Overcurrent Protection – 46 I2>
A46SL1_PTOC1, A46SL2_PTOC1
IDMT Stage
Negative Phase Sequence
A46SH1_PTOC1, A46SH2_PTOC1,
Overcurrent Protection – 46 I2>>
A46SL1_PTOC1, A46SL2_PTOC1,
Instantaneous Stage
The settings for IDMT & Instantaneous Negative Phase Overcurrent protection can be
found in I2> Settings & I2>> Settings menu respectively in the device. Aegis Transformer
Protection Relay gives overcurrent protection to either of the windings, HV or LV, and
provides two adjustable stages for IDMT as well as INST operation. I2> stage can be
I2>> stage always operates with a definite time (DT) operation characteristic. By setting the
High Set Negative Phase Sequence Overcurrent Protection. The function contains a blocking

`
A46Sx_PTOC1 A46Sx_PTOC2
I2 I2
Start Start
Enable Enable
Operate Operate
Block Block
Figure 68 - IEC 61850 Functional Blocks for Negative Phase Sequence Overcurrent Protection
 IL2 : Measured negative phase sequence current

 Start : Pickup instance due to negative phase sequence overcurrent
 Operate : Trip instance due to negative phase sequence overcurrent
A. Negative Phase Sequence Overcurrent Protection – IDMT Stage (46) (I2>)

(A46Sx_PTOC1):
Figure shows the functional block diagram for negative phase sequence overcurrent
protection – IDMT Stage, & each block has been described below:
Figure 69 - Functional Block Diagram for IDMT Negative Sequence Overcurrent Protection

`

The negative phase sequence current I2 is sensed and compared with the threshold value
 If current I2 is 5% above the set threshold, this stage picks up, and an Alarm Signal is
issued by the device. This current is known as pickup current. This signal is also made
on activation of a BI or VI.
 Further, according to the type of time - current characteristics chosen in 46 CURVE

by the type of the curve, 46 CURVE, and the Time Multiplier Setting, 46 TMS. If DT
curve is chosen, relay operates after definite time configured in 46 DT setting, when
the device.
delay is reset. This delay can be set in the 46 RST DT setting.

`
B. Negative Phase Sequence Overcurrent Protection – Instantaneous Stage (46) (I2>>)

(A46Sx_PTOC2):
diagram for negative phase sequence overcurrent protection – Instantaneous Stage, & each
Figure 70 - Functional Block Diagram for INST Negative Sequence Overcurrent Protection
 This function can be enabled by configuring the 46HV PROT setting to ENABLE. A
threshold can be defined using 46HV SET, ranging from 5% to 400% of the rated
current. The negative phase sequence current I2 is sensed and compared with the
 If current I2 is 5% above the set threshold, this stage picks up, and an Alarm Signal is
issued by the device. This current is known as pickup current. This signal is also made
(VI), or an internal signal of the IED program.
 Further, according to the DT curve, the device operates after predefined time in 46HV
50G DT setting, when current exceeds its pickup value. Here, the operational time is
constant, irrespective of the magnitude of the current. When the timer has reached the
value of DT delay, Trip Signal is issued by the device.

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The negative phase sequence overcurrent protection supports both DT and IDMT
characteristics. The device provides 11 IDMT characteristics curves, complying with ANSI,
IEC & IAC standards. The following table gives the standard IDMT characteristics for
negative phase sequence overcurrent protection along with their equations:
IEC SI3
IEC SI1
IEC VI
(Very Inverse)
IEC EI
(Extremely Inverse)
IEC LTI
(Long Time Inverse)
ANSI EI
Extremely Inverse
ANSI VI
Very Inverse
ANSI MI
Moderately Inverse

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IAC SI3
IAC VI
(Very Inverse)
IAC EI
(Extremely Inverse)
Table 45 - Standard IDMT Curves for Negative Phase Sequence Overcurrent Protection
where,
t = operating time,

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2.2.4.6 Negative Sequence Overcurrent Settings & Signals
The following table gives functioning and ranges for each of the settings in I2> & I2>>
Settings menu for Negative Phase Sequence Overcurrent Protection. These settings are same
for both the stages & windings of IDMT & INST operation.
IDMT Negative Phase Sequence Overcurrent Protection (I2>)

Description
Protection: Enables/ disables IDMT Negative phase sequence overcurrent protection.
46 SET 0.05 – 2.50 xIn 0.01 0.30
46 CURVE IEC SI1, IEC SI3, IEC EI, IEC VI, IEC LTI, - IEC SI3
46 TMS 1.00
46 RST DT 0.10s – 60.0s 0.1s 0.10s
46 DT 0.00s – 600.0s 0.1s 1.00s
Instantaneous Negative Phase Sequence Overcurrent Protection (I2>>)
Description
Protection: Enables/ disables instantaneous Negative phase sequence overcurrent protection.
46 SET 0.05 – 4.00 xIn 0.01 1.00
46 DT 0.00s – 600.0s 0.1s 1.00s
Table 46 - Negative Phase Sequence Overcurrent Protection Settings
stages of IDMT & INST Negative phase sequence overcurrent Protection. LEDs can be
assigned to indicate these signals and BIs for pickup and trip in any of the phases can be
mapped to the BOs.

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IDMT Negative Phase Sequence Overcurrent Protection (I2>)

Signals Description
LEDs BOs
HVI2> S1T IDMT Negative Phase Sequence Overcurrent HV Stage 1 Trip Signal
HVI2> S2T IDMT Negative Phase Sequence Overcurrent HV Stage 2 Trip Signal
LVI2> S1T IDMT Negative Phase Sequence Overcurrent LV Stage 1 Trip Signal
LVI2> S2T IDMT Negative Phase Sequence Overcurrent LV Stage 2 Trip Signal LEDs BOs
HVI2> S1P IDMT Negative Phase Sequence Overcurrent HV Stage 1 Pickup Signal 5 - 16 1–8
HVI2> S2P IDMT Negative Phase Sequence Overcurrent HV Stage 2 Pickup Signal
LVI2> S1P IDMT Negative Phase Sequence Overcurrent LV Stage 1 Pickup Signal
LVI2> S2P IDMT Negative Phase Sequence Overcurrent LV Stage 2 Pickup Signal
Instantaneous Negative Phase Sequence Overcurrent Protection (I2>>)
Signals Description
LEDs BOs
HVI2>> S1T INST Negative Phase Sequence Overcurrent HV Stage 1 Trip Signal
HVI2>> S2T INST Negative Phase Sequence Overcurrent HV Stage 2 Trip Signal
LVI2>> S1T INST Negative Phase Sequence Overcurrent LV Stage 1 Trip Signal
LVI2>> S2T INST Negative Phase Sequence Overcurrent LV Stage 2 Trip Signal LEDs BOs
HVI2>> S1P INST Negative Phase Sequence Overcurrent HV Stage 1 Pickup Signal 5 - 16 1–8
HVI2>> S2P INST Negative Phase Sequence Overcurrent HV Stage 2 Pickup Signal
LVI2>> S1P INST Negative Phase Sequence Overcurrent LV Stage 1 Pickup Signal
LVI2>> S2P INST Negative Phase Sequence Overcurrent LV Stage 2 Pickup Signal
Table 47 - Negative Phase Sequence Overcurrent Protection Signals

logical nodes A46SH1_PTOC1, A46SH2_PTOC1, A46SL1_PTOC1, A51SL2_PTOC1, &
A46SH1_PTOC2, A46H2_PTOC2, A46SL1_PTOC2, A46SL2_PTOC2 of IEC 61850
defined for IDMT & INST stages of negative phase sequence overcurrent protection
respectively.
A46SH1_PTOC1: IDMT Negative Phase Sequence Overcurrent Protection

Description
1- ANSI EI
2- ANSI VI
4-ANSI MI
9- IEC SI1
10- IEC VI
12- IEC EI
14- IEC LTI
15- DT
39- IAC EI
40- IAC VI
41- IAC SI3

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A46SH1_PTOC2: INST Negative Phase Sequence Overcurrent Protection

Description
Table 48 - Negative Phase Sequence Overcurrent Protection in IEC 61850 Settings Logical Node
A46SH1_PTOC1: IDMT Negative Phase Sequence Overcurrent Protection

Description
Str-general IDMT Negative Phase Sequence Overcurrent HV Stage1Pickup Signal
Status (ST)
Op- general IDMT Negative Phase Sequence Overcurrent HV Stage1 Trip Signal
A46SH1_PTOC2: INST Negative Phase Sequence Overcurrent Protection
Description
Str- general INST Negative Phase Sequence Overcurrent HV Stage1Pickup Signal
Status (ST)
Op- general INST Negative Phase Sequence Overcurrent HV Stage1 Trip Signal
Table 49 - Negative Phase Sequence Overcurrent Protection Signals in IEC 61850 Logical Node
windings can be viewed in logical nodes A46SH2_PTOC1, A46SL1_PTOC1,
A46SL2_PTOC1 & A46SH2_PTOC2, A46SL1_PTOC2, & A46SL2_PTOC2 for IDMT
& INST operation respectively.
Setting Guidelines
The negative phase sequence overcurrent protection does not respond to balanced load
or three-phase faults. The pickup value for negative sequence overcurrent protection is the
maximum expected negative sequence current value during normal condition of the system.
IDMT characteristic or definite time (DT) can be selected as per time network co-ordination.
Negative sequence overcurrent protection does not respond to balanced condition of the
system, and thus can be set to operate faster and more sensitive than the phase overcurrent
protection for phase to phase faults on distribution system. Phase overcurrent elements must
be set above the load current and therefore are less sensitive to phase to phase fault.
Negative-sequence currents can arise whenever any system unbalance is present.
In rotating machinery, negative sequence overcurrent protection is most commonly

used. Unbalanced loading or faults on the power system which are not removed or isolated
can cause serious damage to rotating machinery even over a short time period. It also
provides a back up protection to feeder earth fault protection in solid and low resistance
earthed network.

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2.2.5 Thermal Overload Protection
Transformer thermal overload protection is designed to protect the equipment from

sustained overload that results in the machine‟s thermal rating being exceeded. Thermal
overload protection compliments the transformer overcurrent protection by allowing modest
but transient overload conditions to occur, while tripping for sustained overloads that the
overcurrent protection will not detect.
Aegis Protection Relays incorporate a current-based thermal characteristic. The

protection measures the fundamental frequency components of the phase currents and is
sensitive for the highest of the three phase currents. Whenever this value exceeds the
predefined thermal trip threshold of a particular stage, that stage picks up and an Alarm
Protection Function ANSI No. IEC Symbol IEC 61850 Logical Node
A49H1_PTTR1,
Thermal Overload Protection 49 3Ith>
A49L1_PTTR1
The settings for thermal overload protection can be found in THRM Settings menu in
the device. Aegis Transformer Protection Relay gives thermal overload protection to either of
the windings, HV or LV, and provides single stage, which is configured according to inverse
time operation characteristics (IDMT). The function contains a blocking functionality. It is
possible to block function outputs and the function itself, if desired. The various settings for
each stage can also be configured through the ConAegis Relay Communication Software.
A49_PTTR1
IL1
IL2 Start
IL3 Operate
Enable
Block
Figure 71 - IEC 61850 Functional Blocks for Thermal Overload Protection
 IL1, IL2, IL3 : Measured currents in phase A, B, C respectively

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 Start : Pickup instance due to thermal overload
 Operate : Trip instance due to thermal overload
Figure shows the functional block diagram for thermal overload protection, & each
Figure 72 - Functional Block Diagram for Thermal Overload Protection

The highest of the three phase currents is sensed and compared with the thermal trip
threshold value by the comparator.
 Further, according to the time - current characteristics the timer block calculates the delay
according to the defined equation. The operation time characteristics are defined by the
curve, and the set time, 49 Topr. When the timer has reached the value of DT delay
maximum value defined by the inverse time curve, Trip Signal is issued by the device.

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The thermal overload protection supports IDMT characteristics. The following table
gives the standard IDMT characteristic for thermal overload along with its equation:
Curve 1
Table 50 - Standard IDMT Curves for Thermal Overload Protection
where,
t = operating time,
Iop = measured current,
Iset = current threshold setting,
Topr = Set Time
2.2.5.6 Thermal Overload Settings & Signals
The following table gives functioning and ranges for each of the settings in THRM
Settings menu for Thermal Overload Protection. These settings are same for both windings.
Thermal Overload Protection (3Ith>)

Description
Protection: Enables/ disables thermal overload protection.
49 SET 0.10 - 3.00 xIn 0.01 3.00
Operating Time: Selects the thermal state threshold at which an alarm will be generated. This corresponds to a
percentage of the trip threshold.
49 Topr 1.00 min – 1000.00 min 0.5 min 10.00 min
Table 51 - Thermal Overload Protection Settings

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The following table gives description of various pickup & trip signals for Thermal
Overload Protection. LEDs can be assigned to indicate these signals and BIs for pickup and
trip in any of the phases can be mapped to the BOs.
Signals Description
LEDs BOs
HVTH1 S1T Thermal Overload HV Stage 1Trip Signal for phase-A
HVTH2 S1T Thermal Overload HV Stage 1Trip Signal for phase-B
HVTH3 S1T Thermal Overload HV Stage 1Trip Signal for phase-C
LVTH1 S1T Thermal Overload LV Stage 1Trip Signal for phase-A
LVTH2 S1T Thermal Overload LV Stage 1Trip Signal for phase-B
LVTH3 S1T Thermal Overload LV Stage 1Trip Signal for phase-C LEDs BOs
HVTH1 S1P Thermal Overload HV Stage 1Pickup Signal for phase-A 5 - 16 1-8
HVTH2 S1P Thermal Overload HV Stage 1Pickup Signal for phase-B
HVTH3 S1P Thermal Overload HV Stage 1Pickup Signal for phase-C
LVTH1 S1P Thermal Overload LV Stage 1Pickup Signal for phase-A
LVTH2 S1P Thermal Overload LV Stage 1Pickup Signal for phase-B
LVTH3 S1P Thermal Overload LV Stage 1Pickup Signal for phase-C
Table 52 - Thermal Overload Protection Signals

logical nodes A49H1_PTTR & A49L1_PTTR of IEC 61850 defined for HV & LV winding
of thermal overload protection respectively.
A49H1_PTTR: HV Thermal Overload Protection

Data
Functional Constraint Available
Objects Description
(FC) Options / Range
(DO)
A49L1_PTTR: LV Thermal Overload Protection
Description
Table 53 - Thermal Overload Protection in IEC 61850 Settings Logical Node

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A49H1_PTTR: HV Thermal Overload Protection

Description
Str-general IDMT Thermal Overload HV Pickup Signal
Status (ST)
Op- general IDMT Thermal Overload HV Trip Signal
A49L1_PTTR: LV Thermal Overload Protection
Description
Str- general INST Thermal Overload LV Pickup Signal
Status (ST)
Op- general INST Thermal Overload LV Trip Signal
Table 54 - Thermal Overload Protection Signals in IEC 61850 Logical Node
Setting Guidelines
Thermal overload setting is expressed as a multiple of the relay nominal current and it
is the value of current above which 100% of thermal capacity will be reached after a period
of time. This setting should be set to 110% of the secondary current flowing when the
transformer is at its full rating and on its minimum voltage tap position.
Transformer overheating can be caused due to failures of the cooling system, external
faults that are not clear promptly, overload and abnormal system conditions. These abnormal
conditions include low frequency, high voltage, non-sinusoidal load current, or phase-voltage
unbalance. Overheating shortens the life of the transformer insulation in proportion to the
duration and magnitude of the high temperature. Overheating can generate gases that could
result in electrical failure. Thermal protection is provided to supplement the Winding
Temperature device. This function provides a general overload thermal protection i.e. not a
winding hot spot protection.
Transformer overloading can result in:-
 Reduced transformer life expectancy.

 Lower insulation voltage withstand due to degradation of the insulation.
 Increased mechanical stress due to expansion.
 Gas bubble production in the mineral oil at extreme levels of overload

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2.2.6 Under Current Protection
Drop in current beneath the defined level this indicates a low load or CB open
condition. It may also be possible that no current is flowing. The undercurrent function can
be used as a fault current check i.e. that no fault current continues to flow, or as a check that a
CB has opened. This can be used in addition to or in place of CB auxiliary switch indications.
The device measures the fundamental frequency components of the phase currents and
is sensitive for the lowest of the three phase currents. Whenever smallest of the phase
currents drops below predefined threshold of a particular stage, that stage picks up and an
Alarm Signal is issued. If the fault situation persists for longer than the estimated trip time
Protection
ANSI No. IEC Symbol IEC 61850 Logical Node
Function
Under Current A37H1_PTUC1, A37H2_PTUC1,
37 3I<
Protection A37L1_PTUC1, A37L2_PTUC1,
The settings for Under Current protection can be found in UC Settings menu in the
device. Aegis Transformer Protection Relay gives thermal overload protection to either of the
windings, HV or LV, & provides two adjustable Under Current stages, both operating with a
definite time (DT) operation characteristic. The function contains a blocking functionality. It
is possible to block function outputs and the function itself, if desired. The various settings
for each stage can also be configured through the ConAegis Relay Communication Software.
A37x_PTOC1
IL1
IL2 Start
IL3 Operate
Enable
Block
Figure 73 - IEC 61850 Functional Blocks for Under Current Protection
 IL1, IL2, IL3 : Measured current in phase A, B, C

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 Start : Pickup instance due to Under Current
 Operate : Trip instance due to Under Current
Figure shows the functional block diagram for under current protection & each block
has been described below:
Figure 74 - Functional Block Diagram for Under Current Protection

threshold can be defined using 37 SET, ranging from 50% to 500% of the rated voltage.
The current is sensed and compared with the threshold value by the comparator, wherein,
there are two possible cases:
 If injected current is 5% below the set threshold, this stage picks up, and an Alarm Signal
setting. Here, the operational time is constant, irrespective of the magnitude of the
current. When the timer has reached the value of DT delay, Trip Signal is issued by the
device.

`
 In some situations, the user may not want the Under Current protection to operate. Hence,
a 37 IGrd setting is given. Below this current, the protection function will be blocked and
will not operate.
2.2.6.5 Under Current Settings & Signals
The following table gives functioning and ranges for each of the settings in UC
Settings menu for Under Current Protection. These settings are same for both the stages &
windings.
Under Current Protection (3I<)

Description
Protection: Enables/ disables inverse time phase Under Current protection.
37 SET 0.05 - 5.00 0.05 0.50
37 DT 0.100s – 600.0s 2.00s INST.
Under Current Guard: Sets the current level below which the protection function will not operate. This
setting is common for both the stages.
37 Igrd 0.05A – 1.00A 0.05A 0.10A
Table 55 - Under Current Protection Settings

Software. The following table gives description of various pickup & trip signals for both the
stages of Under Current Protection. LEDs can be assigned to indicate these signals and BIs

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Undercurrent Protection (3I<)

Signals Description
LEDs BOs
HVUC1 S1T Under Current HV Stage 1 Trip Signal for phase-A
HVUC2 S1T Under Current HV Stage 1 Trip Signal for phase-B
HVUC3 S1T Under Current HV Stage 1 Trip Signal for phase-C
HVUC1 S2T Under Current HV Stage 2 Trip Signal for phase-A
HVUC2 S2T Under Current HV Stage 2 Trip Signal for phase-B
HVUC3 S2T Under Current HV Stage 2 Trip Signal for phase-C
LVUC1 S1T Under Current LV Stage 1 Trip Signal for phase-A
LVUC2 S1T Under Current LV Stage 1 Trip Signal for phase-B
LVUC3 S1T Under Current LV Stage 1 Trip Signal for phase-C
LVUC1 S2T Under Current LV Stage 2 Trip Signal for phase-A
LVUC2 S2T Under Current LV Stage 2 Trip Signal for phase-B
LVUC3 S2T Under Current LV Stage 2 Trip Signal for phase-C LEDs BOs
HVUC1 S1P Under Current HV Stage 1 Pickup Signal for phase-A 5 - 16 1–8
HVUC2 S1P Under Current HV Stage 1 Pickup Signal for phase-B
HVUC3 S1P Under Current HV Stage 1 Pickup Signal for phase-C
HVUC1 S2P Under Current HV Stage 2 Pickup Signal for phase-A
HVUC2 S2P Under Current HV Stage 2 Pickup Signal for phase-B
HVUC3 S2P Under Current HV Stage 2 Pickup Signal for phase-C
LVUC1 S1P Under Current LV Stage 1 Pickup Signal for phase-A
LVUC2 S1P Under Current LV Stage 1 Pickup Signal for phase-B
LVUC3 S1P Under Current LV Stage 1 Pickup Signal for phase-C
LVUC1 S2P Under Current LV Stage 2 Pickup Signal for phase-A
LVUC2 S2P Under Current LV Stage 2 Pickup Signal for phase-B
LVUC3 S2P Under Current LV Stage 2 Pickup Signal for phase-C
Table 56 - Under Current Protection Signals
Also, all the settings and status of pickup and trip signals can be viewed in the logical
nodes A37H1_PTUC1, A37H2_PTUC1, & A37L1_PTUC1, A37L2_PTUC1 of IEC 61850
defined for IDMT & INST stages of Under Current protection respectively.
A37H1_PTUC1: Under Current Protection HV Stage - 1

Description
A37H2_PTUC1: Under Current Protection HV Stage - 2
Description
Table 57 - Under Current Protection Settings in IEC 61850 Logical Node

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A37H1_PTUC1: Under Current Protection HV Stage 1

Description
Str-gen Under Current HV Stage 1 Pickup Signal in any of the phase
Str-phsA Under Current HV Stage 1 Pickup Signal in Phase A
Str-phsB Under Current HV Stage 1 Pickup Signal in Phase B
Str-phsC Status (ST) Under Current HV Stage 1 Pickup Signal in Phase C
Op-gen Under Current HV Stage 1 Trip Signal in any of the phase
Op-phsA Under Current HV Stage 1 Trip Signal in Phase A
Op-phsB Under Current HV Stage 1 Trip Signal in Phase B
Op-phsC Under Current HV Stage 1 Trip Signal in Phase C
A37H2_PTUC1: Under Current Protection HV Stage 2
Description
Str-gen Under Current HV Stage 2 Pickup Signal in any of the phase
Str-phsA Under Current HV Stage 2 Pickup Signal in Phase A
Str-phsB Under Current HV Stage 2 Pickup Signal in Phase B
Str-phsC Status (ST) Under Current HV Stage 2 Pickup Signal in Phase C
Op-gen Under Current HV Stage 2 Trip Signal in any of the phase
Op-phsA Under Current HV Stage 2 Trip Signal in Phase A
Op-phsB Under Current HV Stage 2 Trip Signal in Phase B
Op-phsC Under Current HV Stage 2 Trip Signal in Phase C
Table 58 - Under Current Protection Signals in IEC 61850 Logical Node
Similarly, the settings & status of pickup & trip signals for both the stages of LV
windings can be viewed in logical nodes A37L1_PTUC1 & A37L2_PTUC1.
Setting Guidelines
For undercurrent protection, minimum under current Set value to be selected with
definite time. This value is to be selected by considering minimum load of the system. Igrd
setting is the minimum current value during the under current condition. If the under current
goes below the Igrd value, function will not operate.
Under current protection function operates when the current decreases below the pre-
determined value. It is based on the phase current measurement. Under current condition
indicates low load or CB open condition. It can also be used to indicate that no current is
flowing.

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2.3 VOLTAGE & FREQUENCY PROTECTION

The Aegis Series Transformer Protection Relay offers a wide range of voltage protection
functions. The frequency protection is used to protect network components against abnormal
frequency conditions. The Aegis Series Transformer Protection Relay offers the following
voltage & frequency protection functions:
 Over Voltage Protection

 Under Voltage Protection
 NDR Protection
 Over Frequency Protection
 Under Frequency Protection
 Over Fluxing Protection
2.3.1 Over Voltage Protection
Overvoltage conditions are generally related to loss of load conditions, where the
supply voltage is increased in magnitude. Abnormally high voltages often occur in low
loaded, long distance transmission lines, in islanded systems when generator voltage
regulation fails, or after full load rejection of a generator from the system.
The device measures the fundamental frequency components of phase-to-neutral or

line-to-line voltage. Then the voltage calculation is performed, assuming that, no zero
sequence voltage is present, i.e. all the voltages are symmetrical. Whenever this value
exceeds the predefined threshold of a particular stage, that stage picks up and an Alarm
Over Voltage Protection –
59 U> A59_PTOV1
IDMT Stage
Over Voltage Protection –
59 U>> A59_PTOV2
Instantaneous Stage

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The settings for over voltage protection can be found in OV Settings menu in the
device. Aegis Transformer Protection Relay provides two adjustable over voltage stages,
Inverse Time Over Voltage Protection (U>) & Instantaneous Over Voltage Protection (U>>).
U> stage can be configured either for definite time (DT) or inverse time operation
characteristics (IDMT). U>> stage always operates with a definite time (DT) operation
characteristic. By setting the definite delay value to its minimum, an instantaneous operation
is obtained, also known as High Set Over Voltage Protection. The function contains a
blocking functionality. It is possible to block function outputs and the function itself, if
desired. The various settings for each stage can also be configured through the ConAegis
A59_PTOV1 A59_PTOV2
UL1 UL1
Start Start
Operate Operate
Enable Enable
Block Block
Figure 75 - IEC 61850 Functional Blocks for Over Voltage Protection
 UL1 : Measured voltage in phase A

 Start : Pickup instance due to over voltage
 Operate : Trip instance due to over voltage
A. Over Voltage Protection – IDMT Stage (59) (U>) (A59_PTOV1):
Figure shows the functional block diagram for over voltage protection – IDMT Stage,
& each block has been described below:

The voltage is sensed and compared with the threshold value by the comparator, wherein,

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Figure 76 - Functional Block Diagram for IDMT Over Voltage Protection
 If injected voltage is 5% above the set threshold, this stage picks up, and an Alarm
Signal is issued by the device. This current is known as pickup voltage. This signal is also
function may be disabled on activation of a BI or VI.
 Further, according to the type of IDMT characteristics chosen in 59 CURVE setting

(IDMT / DT), the timer block calculates the delay according to the respective equations.
When IDMT curves are selected, the operation time characteristics are defined by the
type of the curve, 59 CURVE, and the Time Multiplier Setting, 59 TMS. If DT curve is
chosen, relay operates after definite time configured in 59 DT setting, when voltage
exceeds its pickup value. Here, the operational time is constant, irrespective of the
magnitude of the voltage. When the timer has reached the value of DT delay in the DT
the device.

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B. Over Voltage Protection – Instantaneous Stage (59) (U>>) (A59_PTOV2):
variable time operation. Figure shows the functional block diagram for over voltage
protection – Instantaneous Stage, & each block has been described below:
Figure 77 - Functional Block Diagram for INST Over Voltage Protection
threshold can be defined using 59HS SET, ranging from 150% to 200% of the rated
voltage. The voltage is sensed and compared with the threshold value by the comparator,
wherein, there are two possible cases:
 If injected voltage is 5% above the set threshold, this stage picks up, and an Alarm
 Further, according to the DT curve, the device operates after predefined time in 59HS DT
setting, when voltage exceeds its pickup value. Here, the operational time is constant,
irrespective of the magnitude of the voltage. When the timer has reached the value of DT

`
Over voltage protection supports both DT and IDMT characteristics. The device
provides IDMT characteristic curve. The following table gives the standard IDMT
characteristics for over voltage protection along with their equations:
Curve 1
Table 59 - Standard IDMT Curves for Over Voltage Protection
where,
t = operating time,
V = measured voltage,
Vset = voltage threshold setting,

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2.3.1.6 Over Voltage Settings & Signals
The following table gives functioning and ranges for each of the settings in OV
Settings menu for Over Voltage Protection.
Inverse Time Over Voltage Protection (3U>)

Description
Protection: Enables/ disables inverse time phase over voltage protection.
Pickup Setting: Sets the pick-up voltage level.
59 SET 1.05 – 1.70 xVn 0.01 1.20
59 CURVE DT & Curve 1 - DT
59 TMS 0.02 - 2 0.01s 1.00s
59 DT 0.100s – 600.0s 0.1s 2.00s
Instantaneous Over Voltage Protection (3U>>)
Description
Protection: Enables/ disables instantaneous over voltage protection.
59HS SET 1.50 – 2.00 xVn 0.01 1.50
59HS DT 0.100s – 600.0s 0.1s 2.00s
Table 60 - Over Voltage Protection Settings
stages of Over Voltage Protection. LEDs can be assigned to indicate these signals and BIs for
pickup and trip in any of the phases can be mapped to the BOs.
Signals Description
LEDs BOs
U> Trip IDMT Over Voltage Trip Signal
U>> Trip Instantaneous Over Voltage Trip Signal LEDs BOs
U> Pkp IDMT Over Voltage Pickup Signal 5 - 16 1-8
U>> Pkp Instantaneous Over Voltage Pickup Signal
Table 61 - Over Voltage Protection Signals

logical nodes A59_PTOV1 & A59_PTOV2 of IEC 61850 defined for IDMT & INST stages
of over voltage protection respectively.

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A59_PTOV1: IDMT Over Voltage Protection

Description
15- DT
TmVCrv IDMT Curve Type
Set Point (SP) 33-Curve 1
A59_PTOV2: INST Over Voltage Protection
Description
Table 62 - Over Voltage Protection Settings in IEC 61850 Logical Node
A59_PTOV1: IDMT Over Voltage Protection

Description
Str-general IDMT Over Voltage Pickup Signal in Phase A
Status (ST)
Op-general IDMT Over Voltage Trip Signal in Phase A
A59_PTOV2: INST Over Voltage Protection
Description
Str-general INST Over Voltage Pickup Signal in Phase A
Status (ST)
Op-general INST Over Voltage Trip Signal in Phase A
Table 63 - Over Voltage Protection Signals in IEC 61850 Logical Node
Setting Guidelines
Two over voltage protection stages are provided in Aegis relay. First stage can be used
with IDMT characteristics, and stage two used for instant tripping in definite time (DT). For
first stage pick up setting, set value should be set just above the maximum expected voltage.
Recommended pick up setting for first stage with prolonged time using IDMT curves is in the
range of 110% to 115% of nominal system voltage. To enable over voltage protection it is
necessary to select the VT type as PH-VT.
Over voltage occurs in the network because of transient surges on the network or due to
power frequency over voltage. To protect the power transformer from the transient over
voltage, surge arresters are used, and for protection against power frequency over voltage,
protection relays are used. Over voltage protection is used to protect the network elements
like power transformers, generator, motor, insulator etc. from high voltage. Power frequency
over voltage occurs in the network due to switching of circuit breaker, sudden variation of
load or sudden loss of load, defective operation of automatic voltage regulator. Over voltage
of sufficient magnitude causes insulation breakdown of equipment and protective devices.

`
This condition could cause overheating of power system elements, reduction of product
lifetime and destruction of equipment. For over voltage protection delta connected VT input
is required to relay.

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2.3.2 Under Voltage Protection
Under voltage conditions may occur on a power system for a variety of reasons and is
mostly related to increased loads, where the supply voltage decreases in magnitude. This
situation would normally be rectified by voltage regulating equipment. However, if the
regulating equipment proves to be unsuccessful in restoring healthy system voltage, tripping
by means of an under voltage element is required.
The device measures line to line voltages, and whenever the smallest of them drops
below predefined threshold of a particular stage, that stage picks up and an Alarm Signal is
issued. If the fault situation persists for longer than the estimated trip time configured in the
relay, a Trip Signal is issued.
Under Voltage Protection –
27 U< A27_PTUV1
IDMT Stage
Under Voltage Protection –
27 U<< A27_PTUV2
Instantaneous Stage
The settings for under voltage protection can be found in UV Settings menu in the
device. Aegis Transformer Protection Relay provides two adjustable under voltage stages,
Inverse Time Under Voltage Protection (U<) & Instantaneous Under Voltage Protection
(U<<). U< stage can be configured either for definite time (DT) or inverse time operation
characteristics (IDMT). U<< stage always operates with a definite time (DT) operation
characteristic. By setting the definite delay value to its minimum, an instantaneous operation
is obtained, also known as High Set Under Voltage Protection. The function contains a

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A27_PTUV1 A27_PTUV2
UL1 UL1
Start Start
Operate Operate
Enable Enable
Block Block
Figure 78 - IEC 61850 Functional Blocks for Under Voltage Protection
 UL1 : Measured voltage in phase A

 Start : Pickup instance due to under voltage
 Operate : Trip instance due to under voltage
A. Under Voltage Protection – IDMT Stage (27) (U<) (A27_PTUV1):
Figure shows the functional block diagram for under voltage protection – IDMT Stage,
& each block has been described below:
Figure 79 - Functional Block Diagram for IDMT Under Voltage Protection

The voltage is sensed and compared with the threshold value by the comparator, wherein,

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 If injected voltage is 5% below the set threshold, this stage picks up, and an Alarm

chosen, relay operates after definite time configured in 27 DT setting, when voltage drops
down. Here, the operational time is constant, irrespective of the magnitude of the voltage.
When the timer has reached the value of DT delay in the DT mode or the maximum value
defined by the inverse time curve, Trip Signal is issued by the device.
 In some situations, the user may not want the under voltage protection to operate. When
the circuit breaker is opened, or the protected feeder is de-energised, an under voltage
condition would be definitely detected, but we would not want to start protection. Hence,
a 27 UV Grd setting is given. Below this voltage, the protection function will be blocked
and won‟t operate.
B. Under Voltage Protection – Instantaneous Stage (27) (U<<) (A27_PTUV2):
variable time operation. Figure shows the functional block diagram for over voltage
protection – Instantaneous Stage, & each block has been described below:

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Figure 80 - Functional Block Diagram for INST Under Voltage Protection
threshold can be defined using 27HS SET, ranging from 25% to 50% of the rated
voltage. The voltage is sensed and compared with the threshold value by the comparator,
 If injected voltage is 5% below the set threshold, this stage picks up, and an Alarm
 Further, according to the DT curve, the device operates after predefined time in 3U<<
DT setting. Here, the operational time is constant, irrespective of the magnitude of the
voltage. When the timer has reached the value of DT delay in the DT mode or the
maximum value defined by the inverse time curve, Trip Signal is issued by the device.
 In some situations, the user may not want the under voltage protection to operate. When
the circuit breaker is opened, or the protected feeder is de-energised, an under voltage
condition would be definitely detected, but we would not want to start protection. Hence,
a 27 UV Grd setting is given. Below this voltage, the protection function will be blocked
and will not operate.

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Under voltage protection supports both DT and IDMT characteristics. The device
provides 1 IDMT characteristic curve. The following table gives the standard IDMT
characteristics for under voltage protection along with their equations:
Curve 1
Table 64 - Standard IDMT Characteristics for Under Voltage Protection
where,
t = operating time,

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2.3.2.6 Under Voltage Settings & Signals
The following table gives functioning and ranges for each of the settings in UV
Settings menu for Under Voltage Protection.
Inverse Time Phase Under Voltage Protection (3U<)

Description
Protection: Enables/ disables inverse time phase under voltage protection.
27 SET 0.45 – 0.90 xVn 0.01 0.5
27 CURVE DT & Curve 1 - DT
27 TMS 0.02 - 2 0.01 1.00
27 DT 0.100s – 600.0s 2.00s INST.
Under Voltage Guard: Sets the voltage level below which the protection function will not operate. This setting
is common for both the stages.
27 UV grd 0V – 20V 0.5V 5.00V
Instantaneous Phase Under Voltage Protection (3U<<)
Description
Protection: Enables/ disables instantaneous under voltage protection.
27HS SET 0.25 – 0.50 0.01 0.30
27HS DT 0.100s – 600.0s 2.00s INST.
Table 65 - Under Voltage Protection Settings
stages of Under Voltage Protection. LEDs can be assigned to indicate these signals and BIs
Signals Description
LEDs BOs
U< Trip IDMT Under Voltage Trip Signal
U<< Trip Instantaneous Under Voltage Trip Signal LEDs BOs
U< Pkp IDMT Under Voltage Pickup Signal 5 - 16 1-8
U<< Pkp Instantaneous Under Voltage Pickup Signal
Table 66 - Under Voltage Protection Signals

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logical nodes A27_PTUV1 & A27_PTUV2 of IEC 61850 defined for IDMT & INST stages
of under voltage protection respectively.
A27_PTUV1: IDMT Under Voltage Protection

Description
15- DT
Set Point (SP) 37-Curve 1
A27_PTUV2: INST Under Voltage Protection
Description
Table 67 - Under Voltage Protection Settings in IEC 61850 Logical Node
A27_PTUV1: IDMT Under Voltage Protection

Description
Str-general IDMT Under Voltage Pickup Signal in Phase A
Status (ST)
Op-general IDMT Under Voltage Trip Signal in Phase A
A27_PTUV2: INST Under Voltage Protection
Description
Str-general INST Under Voltage Pickup Signal in Phase A
Status (ST)
Op-general INST Under Voltage Trip Signal in Phase A
Table 68 - Under Voltage Protection Signals in IEC 61850 Logical Node
Setting Guidelines
Under voltage protection set value should be configured below the minimum expected
system voltage. This minimum expected system voltage should be at normal system
operating condition. In healthy system, the minimum expected voltage may be in order of
10% of nominal value. During the loss of voltage condition, the outgoing circuit is required
to isolate from the system. We can set the minimum voltage required to operate this
protection in the system during fault condition. Here, no volt protection can be used, for
which UV Grd set value is to be selected. IDMT or DT time characteristic can be selected as
per time coordination.

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Under voltage protection is used to detect the under voltage condition of power system
and to isolate the costly equipment like Power transformer, generator, motor and power lines
from the power system. Under voltages could cause overheating of this equipment and thus
shorten their life and expectancy. Under voltage protection applied to generator, motor,
transformer and power lines.
Under voltage condition occurs due to increase system loading, malfunctioning of

voltage regulator. Faults occurring on power system and abnormal operations result in
reduction of voltage phase which are involved in fault. Sometimes, total loss of voltage
occurs due to fault present at incomer side or busbar in switchboard. It may be required to
complete isolation of each outgoing circuit, No volt protection may be applied for this type of
condition. Under voltage protection can be used to disconnect system from the network
devices, which are damaged when subjected to service under low voltage conditions. For
Under voltage protection delta connected VT input is required to relay.

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2.3.3 Neutral Displacement Protection
Due to occurrence of earth fault on the primary system, the balance of three-phase
power system gets disturbed producing a residual voltage. This circumstance causes a rise in
the neutral voltage with respect to earth. Therefore, this protection is also commonly referred
to as 'Neutral Voltage Displacement'. Voltage Setting applied to the protection elements is
dependent on the magnitude of the residual voltage that is expected to occur during the fault
conditions.
This protection is sensitive to the fundamental frequency component of zero sequence

voltage. Whenever the measured value exceeds the predefined threshold of a particular stage,
that stage picks up and an Alarm Signal is issued. If the fault situation persists for longer
than the estimated trip time configured in the relay, a Trip Signal is issued.
NDR Protection –IDMT Stage 59N Uo> A59N_PTOV1
NDR Protection –INST Stage 59N Uo>> A59N_PTOV2
The settings for neutral displacement protection can be found in NDR Settings menu in
the device Aegis Transformer Protection Relay provides two adjustable NDR stages, Inverse
Time NDR Protection (Uo>) & Instantaneous NDR Protection (U0>>). Uo> stage can be
Uo>> stage always operates with a definite time (DT) operation characteristic. By setting the
High Set NDR Protection. It is possible to block function outputs and the function itself, if
A59N_PTOV1 A59N_PTOV2
U0 U0
Start Start
Enable Enable
Operate Operate
Block Block
Figure 81 - IEC 61850 Functional Blocks for Neutral Displacement Protection

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 U0 : Measured zero sequence voltage

 Start : Pickup instance due to neutral displacement
 Operate : Trip instance due to neutral displacement
Figure shows the functional block diagram for NDR protection & each block has been
described below:
A. NDR Protection – IDMT Stage (59N) (U0<) (A59N_PTOV1):
Figure 82 - Functional Block Diagram for IDMT NDR Protection
 This function can be enabled by configuring the Uo> PROT setting to ENABLE. A
threshold can be defined using Uo> SET, ranging from 5% to 30% of the rated voltage.
The residual voltage is sensed and compared with the threshold value by the comparator,
 If residual voltage is 5% above the set threshold, this stage picks up, and an Alarm

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 Further, according to the type of IDMT characteristics chosen in Uo> CURVE setting
type of the curve, Uo> CURVE, and the Time Multiplier Setting, Uo> TMS. If DT curve
is chosen, relay operates after definite time configured in Uo> DT setting, when voltage
the device.
delay is reset. This delay can be set in the 59N RST DT setting.
B. NDR Protection – Instantaneous Stage (59N) (Uo>>) (A59N_PTOV2):
variable time operation. Figure shows the functional block diagram for NDR protection –
Instantaneous Stage, & each block has been described below:
threshold can be defined using 59N SET, ranging from 5% to 30% of the rated voltage.
The residual voltage is sensed and compared with the threshold value by the comparator,
 If residual voltage is 5% above the set threshold, this stage picks up, and an Alarm

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Figure 83 - Functional Block Diagram for INST NDR Protection
 Further, according to the DT curve, the device operates after predefined time in 59N DT
setting, when voltage exceeds its pickup value. Here, the operational time is constant,
irrespective of the magnitude of the voltage. When the timer has reached the value of DT
NDR protection supports both DT and IDMT characteristics. The following table gives
the standard IDMT characteristics for NDR protection along with their equations:

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Curve 1
Table 69 - Standard IDMT Characteristic for Neutral Displacement Protection
where,
t = operating time,
2.3.3.6 Neutral Displacement Settings & Signals
The following table gives functioning and ranges for each of the settings in NDR
Settings menu for Neutral Displacement Protection.
IDMT Neutral Displacement Protection (U0>)

Description
Protection: Enables/ disables inverse time NDR protection.
59N SET 0.05 – 0.30 xVn 0.01 0.15
59N CURVE DT, Curve 1 - DT
59N TMS 0.02 - 2 0.01 1.00
59N RST DT 0.00s – 60.0s 0.1s 0.10s
59N DT 0.100s – 600.0s 0.1s 2.00s
INST Neutral Displacement Protection (U0>>)
Description
Protection: Enables/ disables instantaneous NDR protection.
59N SET 0.05 – 0.30 0.01 0.15
59N DT 0.100s – 600.0s 0.1s 2.00s
Table 70 - Neutral Displacement Protection Settings

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stages of Over Voltage Protection. LEDs can be assigned to indicate these signals and BIs for
Signals Description Selectable LEDs Selectable BOs

NDR T Neutral Displacement Trip Signal LEDs BOs
NDR P Neutral Displacement Pickup Signal 5 - 16 1-8
Table 71 - Neutral Displacement Protection Signals

logical node A59N_PTOV1 & A59N_PTOV2 defined for neutral displacement protection.
A59N_PTOV1 : IDMT NDR Protection

Description
15 - DT
Set Point (SP) 33 – Curve 1
A59N_PTOV2 : INST NDR Protection
Description
Table 72 - NDR Protection in IEC 61850 Settings Logical Node
A59N_PTOV1 & A59N_PTOV2 : IDMT & INST NDR Protection

Description
Str-neut IDMT NDR Pickup Signal
Op-neut IDMT NDR Trip Signal
Status (ST)
Str-neut INST NDR Pickup Signal
Op-neut INST NDR Trip Signal
Table 73 - NDR Protection Signals in IEC 61850 Logical Node
Setting Guidelines
Neutral voltage picks up setting depending on the expected residual voltage during the
earth fault condition and earthing system. It must also ensure that the relay is set above any
standing level of residual voltage that is present on the system to avoid unnecessary tripping.
In configuration, the selected VT type must be NDR VT. If not selected, the user can‟t use
this protection. We can select IDMT characteristic with TMS values for time selectivity.

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Neutral displacement (residual overvoltage) relay is used to protect the network from
earth fault using neutral displacement which occurs in the neutral voltage, when earth fault
take place. Residual voltage could be measured at secondary terminal connected in broken
delta connection of voltage transformer. Therefore neutral displacement protection relay can
be used for earth fault detection. Residual voltage also can be measured from single phase
voltage transformer connected to transformer star point and earth.
Neutral voltage increase in case of any fault connected to earth, highest neutral voltage
equal to phase-earth voltage is achieved for single phase earth fault. The value of neutral
voltage is depending on fault type and fault resistance. Increased neutral voltage will affect
on the whole system and does not providing any guidance in finding the faulty component.
Therefore this function is used as back up protection.

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2.3.4 Over Frequency Protection
The system frequency may increase when there is a sudden loss of load due to tripping
of an outgoing feeder from the plant to a load centre. It is therefore essential to provide
protection for such over frequency conditions.
Whenever the frequency exceeds a predefined threshold of a particular stage, that stage
picks up and an Alarm Signal is issued. If the fault situation persists for longer than the
estimated trip time configured in the relay, a Trip Signal is issued.
Protection Function ANSI No. IEC Symbol

Over Frequency Protection 81O f>
The settings for over frequency protection can be found in OFRQ Settings menu in the
device. Aegis Transformer Protection Relay provides four adjustable over frequency stages,
which operate with a definite time (DT) operation characteristic. The function contains a
Figure shows the functional block diagram for over frequency protection, which is
similar for all the stages, & each block has been described below:

threshold can be defined using 81 SET, ranging from 40Hz to 70Hz. The frequency is
sensed and compared with the threshold value by the comparator, wherein, there are two
possible cases:
 If the frequency above the set threshold, this stage picks up, and an Alarm Signal is
issued by the device. This current is known as pickup frequency. This signal is also made

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Figure 84 - Functional Block Diagram for Over Frequency Protection
setting, when frequency exceeds its pickup value. Here, the operational time is constant,
irrespective of the magnitude of the frequency. When the timer has reached the value of
DT delay in the DT mode or the maximum value defined by the DT, Trip Signal is
issued by the device.
 Also, a under voltage guard 81 GRD SET setting is provided. Below this voltage, the
protection function will be blocked and will not operate.

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2.3.4.4 Over Frequency Settings & Signals
The following table gives functioning and ranges for each of the settings in OFRQ
Settings menu for Over Frequency Protection.
Over Frequency Protection (81O)

Description
Protection: Enables/ disables over frequency protection.
Pickup Setting: Sets the pick-up frequency level.
81 SET 40Hz – 70Hz 0.1Hz 55.0Hz
81 DT 0.100s – 600.0s 0.1s 1.00s
Guard Set: Sets the Under Voltage Guard below which the protection function will not operate.
81 GRD SET 5.00V – 200V 0.5V 5.00V
Table 74 - Over Frequency Protection Settings
The above settings and their ranges are similar for the other stages. All of these settings
can be configured from ConAegis Relay Communication Software. The following table
gives description of various pickup & trip signals for both the stages of Over Frequency
Protection. LEDs can be assigned to indicate these signals and BIs for pickup and trip in any
of the phases can be mapped to the BOs.

HVOF S1 T Over Frequency Trip Signal in Stage-1
HVOF S4 T Over Frequency Trip Signal in Stage-4 LEDs BOs
HVOF S1 P Over Frequency Pickup Signal in Stage-1 5 - 16 1-8
HVOF S2 P Over Frequency Pickup Signal in Stage-2
Table 75 - Over Frequency Protection Signals
Setting Guidelines
Excess generation of the power or sudden loss of the load condition means generation
exceed the existing load will be subjected to over frequency condition. The generator speeds
will increase causing a proportional frequency rise. This may be unacceptable to industrial
loads, for example, where the running speeds of synchronous motors will be affected. Four
stages of over frequency protection have been provided in the relay with minimum guard
voltage setting to operate the over frequency protection.

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Due to sudden loss of load, the generator speeds will increase causing a proportional
frequency rise. This may be unacceptable to industrial load, for example, where the running
speeds of synchronous motors will be affected. Over frequency could happen, for instance,
when there is a sudden loss of load due to tripping of an outgoing feeder from the plant to a
load centre. Under such over speed conditions, the governor should respond quickly to obtain
a balance between the mechanical input and electrical output, thereby restoring normal
frequency. Over frequency protection is required as a backup to cater for slow response of
frequency control equipment.

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2.3.5 Under Frequency Protection
A drop in system frequency implies that the net load is in excess of the available
generation. Such a condition arises, when an interconnected system splits, and the load left
connected to one of the subsystems is in excess of the capacity of the generators in that
particular subsystem. Industrial plants that are dependent on utilities to supply part of their
loads will experience under frequency conditions when the incoming lines are lost. Sustained
under frequency has implications on the stability of the system, whereby any subsequent
disturbance may damage equipment and even lead to blackouts. It is therefore essential to
provide protection for under frequency conditions.
Whenever the frequency drops below predefined threshold of a particular stage, that
stage picks up and an Alarm Signal is issued. If the fault situation persists for longer than the
estimated trip time configured in the relay, a Trip Signal is issued.
Protection Function ANSI No. IEC Symbol

Under Frequency Protection 81U f<
The settings for under frequency protection can be found in UFRQ Settings menu in
the device. Aegis Transformer Protection Relay provides two adjustable under frequency
stages, Stage 1 & Stage 2, where both the stages always operate with a definite time (DT)
operation characteristic. The function contains a blocking functionality. It is possible to block
Figure shows the functional block diagram for under frequency protection & each
block has been described below. The operation for both the stages is similar:

threshold can be defined using 81 SET, ranging from 40Hz to 70Hz. The frequency is
sensed and compared with the threshold value by the comparator.

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Figure 85 - Functional Block Diagram for Under Frequency Protection
 If the frequency below the set threshold, this stage picks up, and an Alarm Signal is
issued by the device. This current is known as pickup frequency. This signal is also made
setting, when frequency drops below its pickup value. Here, the operational time is
constant, irrespective of the magnitude of the frequency. When the timer has reached the
value of DT delay in the DT mode or the maximum value defined by the DT, Trip Signal
is issued by the device.
 Also, a under voltage guard 81 GRD SET setting is provided. Below this voltage, the
protection function will be blocked and will not operate.

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2.3.5.4 Under Frequency Settings & Signals
The following table gives functioning and ranges for each of the settings in UFRQ
Settings menu for Under Frequency Protection.
Under Frequency Protection (81U)

Description
Protection: Enables/ disables under frequency protection.
Pickup Setting: Sets the pick-up frequency level.
81 SET 40Hz – 70Hz 0.1Hz 55.0Hz
81 DT 0.100s – 600.0s 0.1s 1.00s
Guard Set: Sets the Under Voltage Guard below which the protection function will not operate.
81 GRD SET 5.00V – 200V 0.5V 5.00V
Table 76 - Under Frequency Protection Settings
The above settings and their ranges are similar for the other stages. All of these settings
can be configured from ConAegis Relay Communication Software (Refer Section ). The
following table gives description of various pickup & trip signals for both the stages of Under
Frequency Protection. LEDs can be assigned to indicate these signals and BIs for pickup and
trip in any of the phases can be mapped to the BOs.

HVUF S1 T Under Frequency Trip Signal in Stage-1
HVUF S2 T Under Frequency Trip Signal in Stage-2 LEDs BOs
HVUF S1 P Under Frequency Pickup Signal in Stage-1 5 - 16 1-8
HVUF S2 P Under Frequency Pickup Signal in Stage-2
Table 77 - Under Frequency Protection Signals
Setting Guidelines
Two stages of under frequency protection have been provided in the relay with definite
time setting. Under frequency set value is to be selected by considering the plant load, or loss
of main supply. Load shedding scheme can be used to reduce the effect of under frequency
protection. Plant load is to be divided into the priority based group. If the frequency of the
system reduces from the nominal system frequency load group of the system are
disconnected as per the load priority basis. Load shedding depends on the power generation,
if load is too small compared to prevailing generation deficiency, the improvement in the
frequency may be nonexistent, this should be considered during the load group forming.
Typically, a 10% under frequency condition should be continuously sustainable. The
frequency pick up setting and definite time for each stage should be selected with minimum

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guard voltage set value to operate the under frequency protection during the under frequency
condition of the system.
During normal system operation the frequency will continuously vary over a relatively
small range due to the changing generation/load balance. Generation and utilization need to
be well balanced in any industrial, distribution or transmission network. As load increases,
the generation needs to be stepped up to maintain frequency of the supply because there are
many frequency-sensitive electrical apparatus that can be damaged when network frequency
departs from the allowed band for safe operation. At times, when sudden overloads occur, the
frequency drops at a rate decided by the system inertia constant, magnitude of overload,
system damping constant and various other parameters. Unless corrective measures are taken
at the appropriate time, frequency decay can go beyond the point of no return and cause
widespread network collapse. This can result in “Blackouts”. To put the network back in
healthy condition, a considerable amount of time and effort is required to resynchronize and
re-energize. Protective relays that can detect a low frequency condition are generally used in
such cases to disconnect unimportant loads to save the network, by re-establishing the
“generation-load equation”. However, with such devices, the action is initiated only after the
event and while some salvaging of the situation can be achieved, this form of corrective
action may not be effective enough and cannot cope with sudden load increases, causing
large frequency decays in very short times. In such cases a device that can anticipate the
severity of frequency decay and act to disconnect loads before the frequency actually reaches
dangerously low levels, can become very effective in containing damage.
In the situation where the system frequency is falling rapidly it is common practice to
disconnect non-essential loads until the generation-load balance can be restored. Usually,
automatic load shedding, based on under frequency is implemented. Under frequency relays
are usually installed on the transformer incomers of distribution or industrial substations as
this provides a convenient position from which to monitor the busbar frequency. Loads are
disconnected (shed) from the busbar in stages until the frequency stabilizes and returns to an
acceptable level.

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2.3.6 Over Fluxing Protection
Magnetic flux in the transformer core is directly proportional to the voltage and
inversely proportional to the frequency. Higher the V/f ratio, the greater is the magnetizing
current that might to heating and insulation failure. The over fluxing protection function
detects high flux level in the iron core of transformers as caused by a voltage increase or a
frequency decrease, or both.
The device measures the fundamental frequency components of voltage & calculates
voltage to frequency ratio. Whenever this value exceeds the predefined threshold of a
particular stage, that stage picks up and an Alarm Signal is issued. If the fault situation
persists for longer than the estimated trip time configured in the relay, a Trip Signal is
issued.
A24H1PVPH1,
Over Fluxing Protection 24 V/f>
A24H2PVPH1
The settings for over fluxing protection can be found in OFLX Settings menu in the
device. Aegis Transformer Protection Relay provides two adjustable over fluxing stages,
where both stages can be configured either for definite time (DT) or inverse time operation
characteristics (IDMT). The function contains a blocking functionality. It is possible to block
A24H1PVPH1
V
f Start
Operate
Enable
Block
Figure 86 - IEC 61850 Functional Blocks for Over Fluxing Protection
 V : Measured voltage
 f : Measured frequency

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 Start : Pickup instance due to over fluxing
 Operate : Trip instance due to over fluxing
Figure shows the functional block diagram for over fluxing protection & each block
has been described below:
Figure 87 - Functional Block Diagram for Over Fluxing Protection

threshold can be defined using 24 SET, ranging from 1.10pu to 4.00pu of the rated V / f
ratio, which rated 63.5 / 50 = 1.27. The V/f ratio is calculated and compared with the
 If the V/f ratio is 5% above the set threshold, this stage picks up, and an Alarm Signal is
issued by the device. This signal is also made available directly to the user for use in
Logic in the ConAegis Relay Communication Software. The Blocking Signal can be
controlled by a binary input (BI), a virtual input (VI), or an internal signal of the IED
program. The protection function may be disabled on activation of a BI or VI.

chosen, relay operates after definite time configured in 24 DT setting, when voltage

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the device.
Over voltage protection supports both DT and IDMT characteristics. The device
provides 1 IDMT characteristic curve. The following table gives the standard IDMT
characteristics for over voltage protection along with their equations:
Curve 1
Table 78 - Standard IDMT Curves for Over Fluxing Protection
where,
t = operating time,
V/f = measured voltage / frequency ratio,
V/f set = voltage / frequency ratio threshold setting,

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2.3.6.6 Over Fluxing Settings & Signals
The following table gives functioning and ranges for each of the settings in OFLX
Settings menu for Over Fluxing Protection. These settings are same for both the stages.
Over Fluxing Protection (V/f>)

Description
Protection: Enables/ disables over fluxing protection.
Pickup Setting: Sets the pick-up voltage / frequency ratio level.
24 SET 1.10pu – 4.00pu 0.01pu 3.00pu
24 CURVE DT & IDMT - IDMT
24 TMS 0.01 – 12.00 0.01 1.00
24 DT 0.100s – 600.0s 0.1s 2.00s
Table 79 - Over Fluxing Protection Settings
stages of Over Fluxing Protection. LEDs can be assigned to indicate these signals and BIs for
Signals Description
LEDs BOs
OFLX S1T Over Fluxing Stage 1 Trip Signal
OFLX S2T Over Fluxing Stage 1 Trip Signal LEDs BOs
OFLX S1P Over Fluxing Stage 1 Pickup Signal 5 - 16 1-8
OFLX S2P Over Fluxing Stage 1 Pickup Signal
Table 80 - Over Fluxing Protection Signals

logical nodes A24H1PVPH1 & A24H2PVPH1 of IEC 61850 defined for both stages of over
fluxing protection.
A24HxPVPH1: Over Fluxing Protection

Description
15- DT
VHzCrv IDMT Curve Type
Set Point (SP) 47- IDMT
Table 81 - Over Fluxing Protection Settings in IEC 61850 Logical Node

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A24HxPVPH1: Over Fluxing Protection

Description
Str-general IDMT Over Fluxing Pickup Signal
Status (ST)
Op-general IDMT Over Fluxing Trip Signal
Table 82 - Over Fluxing Protection Signals in IEC 61850 Logical Node
Setting Guidelines
In over fluxing protection, the user needs to set the V/Hz ratio. The pick up for the over
fluxing elements depends on the nominal core flux density levels. Generator transformers are
generally run at higher flux densities than transmission and Distribution transformers, so they
require a pick up setting and shorter tripping times which reflect this. Transmission
transformers can also be at risk from over fluxing conditions and withstand levels should be
consulted when deciding on the required settings. Over excitation of a transformer can occur
whenever the ratio of per unit voltage to per unit frequency (V/Hz) at the secondary terminals
of a transformer exceeds its set value or rating, function operates with time characteristic
selection. The element is set in terms of the actual ratio of voltage to frequency; the over
fluxing threshold setting, V/Hz>x Trip Set.
Over fluxing protection is used to protect power transformer form excessive flux,
excessive flux can cause transformer core saturation and some of the flux will radiate as
leakage flux through the transformer tank. This leakage flux causes eddy currents and the I2R
losses from these currents heat the transformer tank and can cause overheating. Over fluxing
or over excitation occurs if the ratio of voltage to frequency exceed certain limit. Low
frequency or high voltage causing rise in the voltage to frequency ratio will produce high flux
densities in the magnetic core of the transformer.
A transformer is designed to operate at or below a maximum magnetic flux density in

the transformer core. Above this design limit the eddy currents in the core and nearby
conductive components cause overheating which within a very short time may cause severe
damage. The magnetic flux in the core is proportional to the voltage applied to the winding
divided by the impedance of the winding. The flux in the core increases with either increasing
voltage or decreasing frequency. During startup or shutdown of generator-connected
transformers, or following a load rejection, the transformer may experience an excessive ratio
of volts to hertz, that is, become overexcited. When a transformer core is overexcited, the
core is operating in a non-linear magnetic region, and creates harmonic components in the
exciting current. A significant amount of current at the 5th harmonic is characteristic of over
excitation.

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For momentary system disturbances can cause transient over fluxing that is not
dangerous, time delayed tripping is required. The normal protection is an IDMT or definite
time characteristic, initiated if a defined V/f threshold is exceeded. Often separate alarm and
trip elements are provided. The alarm function would be definite time-delayed and the trip
function would be an IDMT characteristic. Over fluxing protection is provided in the aegis
relay with two stages, both stages can be set DT or IDMT curve setting.

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2.4 SUPERVISION FUNCTIONS

Along with providing a range of protection functions, the product includes
comprehensive monitoring and control functionality.
2.4.1 Circuit Breaker Failure Protection
The operation of circuit breaker is vital to isolate the fault or at least limit the damage to
the power system. After protection function generates a trip command, it is expected that the
circuit breaker opens and/or the fault current drops below the pre-defined normal level. But if
the fault does not disappear within a given time after the initial trip command, circuit breaker
failure protection can be used to trip any upstream circuit breaker (CB). CBF protection
monitors the circuit breaker and establishes whether it has opened within a reasonable time. If
the fault current has not been interrupted following a set time delay from circuit breaker trip
initiation, the CBF protection will operate, whereby the upstream circuit breakers are tripped
to ensure that the fault is isolated.
Protection Function ANSI No.

Circuit Breaker Failure Protection 50BF
The settings for circuit breaker failure protection can be found in BREAKER
FAILURE submenu of the SUPR Settings menu in the device. Aegis Transformer
Protection Relay provides two stages circuit breaker failure protection stage for either or both
the windings, which always operates with a definite time (DT) operation characteristic. The
circuit breaker failure function can be activated by trip commands from the overcurrent or
earth-fault functions. The operating values of the current measuring elements can be set
within a predefined setting range. The various settings for each stage can also be configured
through the ConAegis Relay Communication Software.
Figure shows the functional block diagram for circuit breaker failure protection, & each

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Figure 88 - Functional Block Diagram for Circuit Breaker Failure Protection
 Whenever an overcurrent or earth-fault occurs, a Trip Signal is issued by the device as

soon as the timer reaches the set DT value. The breaker failure protection comes into
picture if the fault has not disappeared after the initial Trip Signal.
 The dedicated comparators again compare the three phase quantities / earth current with
the set thresholds 50BF OC & 50BF EF respectively, in presence of the fault current.
The breaker failure can be detected either by persistent fault current in winding HV or
LV, or on activation of a BI or as a combination of both current & BI, as selected in 50
BF Mode setting. If breaker failure is to be detected on presence of fault current, this
setting monitors the fault in the selected winding mode. If breaker failure is to be detected
on activation of BI, the user must assign a BI for this purpose in the TRIP BI setting in
the CONF Menu. However, the user must note that if a BI is not assigned in the TRIP BI
setting and the user chooses to detect breaker failure on BI, this may lead to an
undesirable / erroneous end result as the intended operation will not be performed.
 The breaker failure protection function must be enabled by configuring the 50BF PROT
setting to ENABLE. If the CB is closed and, any of the measured current exceeds the set
threshold, this stage picks up. Further, according to the DT curve, the device operates
after predefined time in 50BF DT setting. When the timer has reached the value of
maximum value defined by the DT, Trip Signal is issued by the device.
 The user can assign any of the LEDs 5-16 to indicate these trip signals from Config LED
setting. Also, the BIs for re-trip or back-trip can be mapped to the BOs from Config S/W
BI setting.

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2.4.1.4 Circuit Breaker Failure Settings & Signals
The following table gives functioning and ranges for each of the settings for circuit
breaker failure protection found in BREAKER FAIL submenu of the SUPR Settings menu
in the device. These settings are same for both the stages.
Circuit Breaker Failure Protection (50BF)

Description
Protection: Enables/ disables circuit breaker failure protection.
50BF PROT Enable - Disable - Disable
Overcurrent Pickup Setting: Sets the pick-up three phase current level.
50BF OC 0.05 – 2.00 0.05 1.00
Earth-fault Pickup Setting: Sets the pick-up earth current level.
50BF EF 0.05 – 2.00 0.05 2.00
Back trip DT: Sets the time delay after which the upstream breaker will be tripped.
50BF DT 0.1s – 600s 0.1s 10.00s
Breaker Failure Mode: Selects the parameter on which breaker failure will be detected.
HV1 & LV1 / LV1 & LV2 / HV1 & HV2 / BIS1 &
50BF Mode - HV1 – LV1
BIS2 / HV1 & BIS2 / LV1 & BIS2
Table 83 - Circuit Breaker Failure Protection Settings
The following table gives description of pickup & trip signals for Broken Conductor
Detection Protection. LEDs can be assigned to indicate these signals and BIs for trip signals
can be mapped to the available BOs.

BF-1 Breaker Failure Stage 1Trip Signal LEDs BOs
BF-2 Breaker Failure Stage 2 Trip Signal 5 - 16 1-8
Table 84 - Circuit Breaker Failure Protection Signals
Setting Guidelines
Breaker failure protection can be enable or disable from the breaker fail menu, with
minimum fault current level to check after breaker trip command issued by the relay with
definite time setting of function operation. Breaker fail detection mode can be selected from
the 50BF menu of the relay. If detection mode is binary input then trip BI to be configured in
the confirmation Menu.
Breaker failure protection is used in the design of fault clearance system. Where a
circuit breaker fails to operate to clear fault current the power system will remain in a
hazardous state until the fault is cleared by remote or back-up protections. To minimize any

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delay, circuit breaker Failure protection provides a signal to back-trip the next „upstream‟
circuit breaker. The detection of breaker failure is made by measuring the current or by
detecting trip BI status after issuing trip command from the relay.
Figure 89 - Circuit Breaker Failure Protection in Aegis Relays

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2.4.2 Trip Circuit Supervision
The trip circuit supervision function is designed to supervise the control circuit of the
circuit breaker. The invalidity of a control circuit is detected by using a dedicated output
contact that contains the supervision functionality. Whenever a trip circuit failure, i.e.
unhealthy condition occurs, the device operates the assigned contacts after the predefined
time.

Trip Circuit Supervision 74TCS
The settings for trip circuit supervision function can be found in TCS submenu of the
SUPR Settings menu in the device, & the function always operates with a definite time (DT)
characteristic. The trip circuit supervision function is activated by the dedicated BI. The
Figure shows the functional block diagram for trip circuit supervision function, & each
Figure 90 - Functional Block Diagram for Trip Circuit Supervision Function
 This function can be enabled by configuring the TCS PROT setting to ENABLE. A
binary input is to be selected in TCS BI setting in the Configuration menu. The BI is
connected to the trip circuit such that it is energized when the trip circuit wiring is intact.
This condition is termed as “trip circuit healthy” condition.

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 If the BI becomes de-energized due to a break in the trip circuit wiring or loss of supply,
a binary output (BO) is activated. This condition is termed as “trip circuit unhealthy”
condition. The TCS DT setting prevents this failure being incorrectly indicated during
circuit breaker operation. This delay should be greater than the operating time of the
circuit breaker.
2.4.2.4 Trip Circuit Supervision Settings
The following table gives functioning and ranges for each of the settings for circuit trip
circuit supervision function found in TCS submenu of the SUPR Settings menu in the
device. These settings are same for both the stages.
Trip Circuit Supervision (74 TCS)

Description
Protection: Enables/ disables trip circuit supervision function.
TCS PROT Enable - Disable - Disable
DT Delay: Time delay before trip circuit supervision operates
TCS DT 0.1s – 60s 0.1s 0.50s
LED Indication: Indicates Trip Circuit Unhealthy condition
TCS LED NONE / LED 05- LED 16 - NONE
Output Contact 1: Selects the binary output contact which will operate on Trip Circuit Unhealthy condition.
TCS BO1 NONE / BO 1 – BO 6 - NONE
Output Contact 2: Selects the binary output contact which will operate on Trip Circuit Unhealthy condition.
TCS BO2 NONE / BO 1 – BO 6 - NONE
Table 85 - Trip Circuit Supervision Settings
Setting Guidelines
For trip circuit supervision BI to be programmed in the configuration menu 'TCS BI’ of
the relay, assigned BI will work for TCS. During the breaker operation assigned BI will holds
pick up condition for defined time in the relay, recommended time setting is 0.5Sec. LED
and two BO can be configured for trip circuit supervision.
Trip circuit supervision is used for continuous monitoring of tripping circuit of circuit
breaker. Trip circuit supervision function is used for both Open and Close condition of circuit
breaker. In protection system trip circuit of breaker is important because, if trip circuit of
breaker is opened somewhere and fault occurs in the network. Fault will not be disconnected
from system because of interruption of trip circuit breaker it has to clear from upstream
breaker. Trip circuit supervision function is particularly important when there is only one
tripping coil.

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Trip circuit supervision is designed for continuous supervision of circuit breaker trip
circuit and to give an alarm for loss of auxiliary supply, faults on the trip coil or trip circuit.
Schematic wiring diagram for trip circuit supervision is shown in figure.
Figure 91 - Trip Circuit Supervision Scheme

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2.4.3 Close Circuit Supervision
The close circuit supervision function is used to monitor different parameters of the
circuit breaker. The invalidity of a control circuit is detected by using a dedicated output
contact that contains the supervision functionality. Whenever a close circuit failure, i.e.
unhealthy condition occurs, the device operates the assigned contacts after the predefined
time.

Close Circuit Supervision 74CCS
The settings for close circuit supervision function can be found in CCS submenu of the
SUPR Settings menu in the device, & the function always operates with a definite time (DT)
characteristic. The close circuit supervision function is activated by the dedicated BI. The
Figure shows the functional block diagram for close circuit supervision function, &
Figure 92 - Functional Block Diagram for Close Circuit Supervision Function
 This function can be enabled by configuring the CCS PROT setting to ENABLE. A
binary input is to be selected in CCS BI setting in the Configuration menu. The BI is
connected to the close circuit such that it is energized when the close circuit wiring is
intact. This condition is termed as “Close circuit healthy” condition.

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 If the BI becomes de-energized due to a break in the close circuit wiring or loss of
supply, a binary output (BO) is activated. This condition is termed as “Close circuit
unhealthy” condition. The CCS DT setting prevents this failure being incorrectly
indicated during circuit breaker operation. This delay should be greater than the operating
time of the circuit breaker.
2.4.3.4 Close Circuit Supervision Settings
The following table gives functioning and ranges for each of the settings for circuit
Close circuit supervision function found in CCS submenu of the SUPR Settings menu in the
device. These settings are same for both the stages.
Close Circuit Supervision (74 CCS)

Description
Protection: Enables/ disables close circuit supervision function.
CCS PROT Enable - Disable - Disable
DT Delay: Time delay before close circuit supervision operates
CCS DT 0.1s – 60s 0.1s 0.50s
LED Indication: Indicates Close Circuit Unhealthy condition
CCS LED NONE / LED 05- LED 16 - NONE
Output Contact 1: Selects the binary output contact which will operate on Close Circuit Unhealthy condition.
CCS BO1 NONE / BO 1 – BO 6 - NONE
Output Contact 2: Selects the binary output contact which will operate on Close Circuit Unhealthy condition.
CCS BO2 NONE / BO 1 – BO 6 - NONE
Table 86 - Close Circuit Supervision Settings
Setting Guidelines
For close circuit supervision BI to be programmed in the configuration menu 'CCS BI’
of the relay, assigned BI will work for CCS. During the breaker operation assigned BI will
holds pick up condition for defined time in the relay, recommended time setting is 0.5Sec.
LED and two BO can be configured for close circuit supervision.
Close circuit supervision function is used for continuous monitoring of close circuit.
Close circuit supervision function is used for both open and close condition of circuit breaker.
This function is design for continuous supervision of circuit breaker close circuit, loss of
auxiliary supply, interruption of close circuit. Schematic wiring diagram is shown in figure.

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Figure 93 - Close Circuit Supervision Scheme

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3 COMMUNICATION

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Section Overview
This section describes the operation of IEC 61850 Communication Protocol for Feeder
Protection Relay. The section contains working description of CGL 61850 IED Configuration
Tool and the Logical Nodes assigned for various operations performed by the relay.
Read and follow the instructions in the Getting Started chapter. This chapter includes
instructions on installing the software. After you install the software, and to see how quick
and easy it is to use this software, CG recommends you to read the entire section. This
document applies to the use of CGL 61850 IED Configuration Tool only with the CG Aegis
Series Protection Relays.

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3.1 GETTING STARTED

3.1.1 Introduction
IEC 61850 is an important international standard for the design of electrical substation
automation. IEC 61850 is a part of the International Electrotechnical Commission's (IEC)
Technical Committee 57 (TC57) reference architecture for electric power systems. The
model-driven approach of the TC57 standards, including IEC61850, is an innovative
approach that requires a new way of thinking about substation automation that will result in
very significant improvements in both costs and performance of electric power systems. The
abstract data models defined in IEC 61850 can be mapped to a number of protocols. Current
mappings in the standard are to MMS (Manufacturing Message Specification), GOOSE,
SMV (Sampled Measured Values), and soon to Web Services. These protocols can run over
TCP/IP networks or substation LANs using high speed switched Ethernet.
The IEC 61850 Standard defines the various aspects of the substation communication
network in 10 major sections as shown in Table 1 below.
Part # Title
1 Introduction and Overview
2 Glossary of terms
3 General Requirements
4 System and Project Management
5 Communication Requirements for Functions and Device Models
6 Configuration Description Language for Communication in Electrical
Substations Related to IEDs
7 Basic Communication Structure for Substation and Feeder Equipment
- 7.1 Principles and Models
- 7.2 Abstract Communication Service Interface (ACSI)
- 7.3 Common Data Classes (CDC)
- 7.4 Compatible logical node classes and data classes
8 Specific Communication Service Mapping (SCSM)
- 8.1 Mappings to MMS(ISO/IEC 9506 – Part 1 and Part 2) and to ISO/IEC 8802-3
9 Specific Communication Service Mapping (SCSM)
- 9.1 Sampled Values over Serial Unidirectional Multidrop Point-to-Point Link
- 9.2 Sampled Values over ISO/IEC 8802-3
10 Conformance Testing
Table 87 - IEC 61850 Structure
The CGL 61850 IED Configuration Tool will be used to configure CGL IEC 61850
based devices for substation automation. The tool helps the user to map data from remote
Goose into CGL IED data.

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3.1.2 Software Installation
To install CGL 61850 IED Configuration Tool, run CGL 61850 IED Configuration
Tool.exe from the CD. Follow the instructions shown on the screen, and complete the
installation procedure.
After the CGL 61850 IED Configuration Tool installer has finished executing, you
should have an desktop icon called CGL 61850 IED Configuration Tool. To launch the
tool, simply double click on the icon. Fig.1 shows the default view of the CGL 61850 IED
Configuration Tool.
Figure 94 - Default View

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3.1.3 System Requirements

3.1.3.1 Software Requirements
Operating Systems: Windows 2000 SP3, Windows XP SP2, Windows Server 2003,
Windows Vista, Windows7, Windows 8
.NET framework 2.0 is required
3.1.3.2 Hardware Requirements
1.2 GHz or higher

512 MB RAM
1280*1024 Screen resolution (Recommended)
3.1.4 Overview of the SCL
SCL, the Substation Configuration Language is used for the configuration of electrical
substation IEDs (61850-6 and IEC 61850-7-x). It does the interoperable exchange of
communication system configuration data between an IED configuration tool and a system
configuration tool. The configuration language is based on the Extensible Markup Language
(XML) version 1.0
Substation Terminology:
IED: A substation automation device performing functions by means of logical nodes

(LNs).
Server: A communication entity within an IED.
LDevice: Contained in a server of an IED.
LNode: Contained in a logical device of an IED
DO: The DATA contained in the LNs.
SCL File Types:
.ICD - IED Capability Description: Data exchange from the IED configuration tool to
the system configuration tool.
.SSD - Substation Specification Description: Data exchange from a system
specification tool to the system configuration tool.
.SCD - Substation Configuration Description: Data exchange from the system
configuration tool to IED configuration tools.

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.CID - Configured IED Description: Data exchange from the IED configuration tool to
the IED
Figure 95 - SCL File Types

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3.2 CONFIGURING THE TOOL

3.2.1 The User Interface
CGL 61850 IED Configuration Tool GUI has a split based window layout. The
Configuration Tool facilitates project creation, editing and saving. The project has to be
saved as binary file with a unique extension. The files with this extension shall be allowed
open and edit in Configuration Tool. Windows can be resized for convenience.
Figure 96 - Split Window Layout
The Configuration Tool screen is divided into four parts:
Project Editor: Lists all the local and remote IEDs

Configurations Editor: Contains Properties Editor, GOOSE Subscription Mapping, IED
Configuration.
IED Palette: Stores and displays CGL IED templates and other imported templates.
Log Window: Displays history of events and error for the present project

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3.2.2 Project Editor
Project Editor lists all the local and remote IEDs added for a project created in the
Configuration tool.
A new project in Configuration Tool shall open an empty project editor.
Figure 97 - Project Editor
IEDs can be added to Project from IED Palette. After you add a new IED, the
configuration tool displays an icon representing the new IED in the Project Editor.
3.2.2.1 Creating A Project
You can start a new project using the menu File New Project or key board shortcut
Ctrl+N.
Figure 98 - Creating a Project
3.2.2.2 Adding IED To Project
You can add IEDs to the project by dragging the template from IED palette and
dropping it in the project editor. After dropping into project editor user will be asked for
selecting the IED as shown below.

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Figure 99 - Adding IED to Project
User can select the desired IED and enter the instance name and click OK to finish the
process. Now the newly added IED will be shown in the project editor. If the manufacturer
(in icd file) of the IED is CGL, it will be added under the node Local IEDs otherwise under
the node Remote Publisher. You can distinguish between Local IEDs and Remote
Publisher by the different icons.
Figure 100 - Local IED & Remote Publisher
3.2.2.3 Functions Available For An IED In Project
User has the functionalities for deleting an IED from the project (note that if any
GOOSE elements are used for GOOSE subscription mapping delete request will be rejected),
renaming an IED in the project, sending the CID file to CGL device, Downloading CID file
from CGL device. (All operations of sending or downloading to / from the device will be
using the IP Address configured in the IED Properties window)

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Figure 101 - Available Functions
Note: The functionalities other than Delete IED and Rename IED are not available for
Remote Publishers (Non CGL).
3.2.3 Configurations Editor

3.2.3.1 Properties
Properties screen displays IED properties and Startup cfg file properties.
Based on the settings of startup properties, Startup file will be generated and send to IED
device while sending CID file.
Figure 102 - Properties

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Note: The IP Address indicates the IP Address of CGL IED. All ftp related operations of an
IED will be used by this address.
Startup Parameter Details
Parameter Description
SCLFileName Name of SCL(CID) File to be parsed by IEC61850
application
IEDName Name of IED to be parsed by IEC61850 application
from SCL(CID) File
AccessPointName Access point information to IEC61850 application
ReportLog Scan Rate (milliseconds) Internal Data Scan Rate for the generation of Reports
based on data changes
Report BufferSize (bytes) Circular Buffer allocated for storing buffered reports in
IEC61850 application
NetworkCardID NetworkCardID
IPAddress IPAddress
MAX_CALLED_CONNECTIONS Maximum number of client connections that can be
accepted by IED
MAX_DYNAMIC_TYPES Buffer allocated for storing data types. Configuration
file parsing will fail if maximum limit is reached
MAX_LN_VARS Buffer allocated for storing variables inside a logical
Node. Configuration file parsing will fail if maximum
limit is reached
MAX_NUM_DATASETS Buffer allocated for storing datasets. Configuration file
parsing will fail if maximum limit is reached
MAX_PDU_SIZE (bytes) Maximum Size of MMS Packets; Data exchange with
IEC61850 Client will use this parameter
MAX LOG FILE SIZE (KBs) Maximum Size of the Circular Log file
LogLevel Logging mode of IEC61850 application while running
MAX_NUM_DS_VARS Buffer allocated for storing dataset variables of a
subscribed GOOSE. Configuration file parsing will fail
if maximum limit is reached
MAX_SUB_GOOSE Buffer allocated for storing subscribed GOOSE
information. Configuration file parsing will fail if
maximum limit is reached
Table 88 - Startup Parameters
The following table shows the maximum values for the GOOSE parameters. These values
can be set from the CGL 61850 IED Configuration Tool.

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Parameter Maximum Value

Number of Datasets Upto 32
Number of elements / dataset Upto128
Number of URCBs Upto 32
Number of unique GOOSE messages published / subscribed Upto 32
Number of Data Attributes per GOOSE message subscribed Upto 64
Table 89 - Startup Parameters & their maximum values
3.2.3.2 Goose Subscription Mapping
This configuration screen allows the user to map the desired data from GOOSE
publication to 61850 inputs of the selected IED in the project editor.
Figure 103 - Goose Subscription Mapping
In the GOOSE Publication section, the display is in the following format

Level1 - <IEDName>
Level2 - <LogicalDeviceName>.<GOOSE Name>
Level3 - <DataSet>
Level4 - <LogicalDeviceName>/<FCDA>
FCDA: Functionally Constraint Data Attribute
In the GOOSE Subscription-Mapping section the listview displays all BOOLEAN

elements in all logical node with lnClass="GGIO" and prefix="SUBDIG" as subscription
points.
3.2.3.3 Data Mapping
User can browse through the GOOSE publication to identify the desired data item then
drag it and drop on the desired 61850 input on the GOOSE Subscription Mapping section.

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Figure 104 - Data Mapping
User can remove the mapping of a data item by using the function Remove Mapping
Figure 105 - Remove Mapping
3.2.3.4 Subscriber Display

In Subscriber section, Logical Node drop down lists the logical nodes predefined for
subscription in the selected IED in project editor. According to the selection of logical node
available BOOLEAN data items (in fc ST) will be listed in GOOSE subscription section.

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Figure 106 - Subscriber Display
User can see the data path of a VI (e.g VI03 in below shown screen) in tool tip by
clicking on the GOOSE IN item.
Figure 107 - Datapath of VI
3.2.4 IED Configuration

3.2.4.1 Goose Control Blocks Configuration
This displays the GOOSE control blocks' details. The publisher part shows the GOOSE
control blocks details in the selected IED in project editor. The Subscriber part shows the
incoming GOOSE (Mapped GOOSE) details for the selected IED.

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Figure 108 - Goose Control Block
Adding a GOOSE Control Block
Click on the Add button in the GOOSE Control Blocks Configuration which will
display the screen shown below from which user has to select the logical device to which
GOOSE control block has to be added.
Figure 109 - Select Logical Device
After selecting the logical device click Ok button which will display the below shown
screen

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Figure 110 - Goose Details
User can enter the Goose details in this screen and click Ok button. (Note that duplicate
Goose name is not allowed in the same logical device and the dataset drop down list contains
datasets in the selected logical device). Please find the min, max limits for the parameters
below:
Parameters Min Max

Config Revision 1 1000
MinTime 2 ms 10000 ms
Maxtime 1000 ms 600000 ms
App ID 0000x 3FFFx
VLAN ID 000x FFFx
Table 90 - Goose Parameters
Editing a GOOSE Control Block
Select the GOOSE Control Block from GOOSE Control Block Configuration screen.
Now either double clicking on the selected GOOSE or clicking Edit button will display the
Edit GOOSE screen where user can edit the GOOSE details.
Deleting a GOOSE Control Block
Select the GOOSE Control Block from GOOSE Control Block Configuration screen and
click on delete button.
Note: If the selected GOOSE Control Block is used for mapping purpose in other IEDs the
delete request will be rejected as shown below.

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Figure 111 - Error in deleting GCB
Editing Subscriber GOOSE
The subscriber section of GOOSE Control Block Configuration screen contains all the
GOOSE mapped to the selected IED. User can edit the MAC-Address of the selected
Subscriber GOOSE by either double clicking on the subscriber goose or using Edit button
Figure 112 - MAC Address
3.2.4.2 Report Control Blocks Configuration

This screen shows the buffered and unbuffered reports of the selected IED. This also
provides the user functionalities to add, edit and delete Report control Blocks.

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Figure 113 - RCB Configuration
Bitstring format for displaying RCB Options fileds and Trigger Options
In IED Configuration Tool, the RCB Options fields are displayed in bitstring format as
shown below
Figure 114 - Bitstring Format
RCB Options Fields are displayed in the following order of bits
Table 91 - RCB Option Fields

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RCB Trigger options are displayed in the following order of bits
Adding a Report Control Block
To add a Report Control Block, click on Add button. It will display the below shown screen.
Figure 115 - New RCB
User can enter the Report Control Block details in this screen. User can select to which
logical device report control block has to be added. Datasets from the LLN0 of selected the
logical device will be listed in the dataset drop down. After entering the details user has to
click Ok button. Please note that all report control block shall be created in LLN0 of logical
device. Please find the min, max limits for the parameters below:
Parameters Min Max

Buffer Time 0 ms 3600000 ms
Integrity period 0 ms 1800000 ms
Number of Instances 1 16
Table 92 - RCB Parameters

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Editing a Report Control Block
Select the Report Control Block from Report Control Block Configuration screen. Now either
double clicking on the selected Report Control Block or clicking Edit button will display the
Edit RCB screen where user can edit the Report control block details.
Deleting a Report Control Block
Select the Report Control Block from Report Control Block Configuration screen and click
on delete button. User will be asked to confirm the action.
Printing Report Control Blocks information
User shall print report control blocks information sing Print button
3.2.4.3 Datasets Configuration

This configuration screen displays all the datasets in a list, IED Data Items of the
selected IED and the dataset items of the selected dataset.
Figure 116 - Datasets Configuration

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Adding a Dataset
User can add a new dataset by clicking on Add button. It will display a screen as shown
below.
Figure 117 - New Dataset
User shall enter the dataset details and click on Ok button. The data set will be added to the
selected logical node (logical node is fixed as LLN0) in selected logical device. (Note that
while adding the dataset user is not selecting the data items (FCDA/FCD) for the dataset.
This can be later configured from the Datasets Configuration screen).
Configuring a Dataset
User can select the dataset to be edited from the list. Dataset Items (FCDA/FCD) section
shows the data items present in the selected dataset. IED Data Items shows the Logical
devices and logical nodes in the logical device. User can select the desired data object or data
attribute from the logical node and drag it and drop in the Dataset Items (FCDA/FCD)
section.
Editing a Dataset
User can change the description of a dataset by editing the dataset.
Deleting a Dataset
User shall select the desired dataset from the list and click on Delete button. User will be
asked to confirm the action. If the dataset it referenced by a GOOSE control block or Report
control block it cannot be deleted.
Figure 118 - Error in deleting Dataset

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Cloning a Dataset
This functionality is for creating a dataset from an existing dataset. User can select the
desired dataset from the drop down list to be cloned and click on Clone button. User can see
the below shown screen in which user can enter the dataset name and description.
Figure 119 - Cloning a Dataset

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3.3 IED PALETTE

IED Palette shall store and display CGL IED templates as well as other remote
IEDs.ICD files will be allowed to import as templates. CGL IED files are categorized by their
manufacturer name in SCL file.
Figure 120 - IED Pallete
You can import new IED template to IED Palette using the functionality Import IED.
User will get the below shown menu when right clicking on the IED Palette.
You can browse the desired ICD, CID or SCD file to be added to the IED Palette.
Figure 121 - Import IED

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User can delete a IED template from IED palette using Remove IED option.
3.3.1 Log Window
This window shows the different information and errors related to IED Configuration Tool.
Figure 122 - Log Window
3.3.2 Other Settings

3.3.2.1 File Menu
Select File from the Menu Bar to obtain a drop-down listing similar to the following
Figure 123 - File Menu
New: Creates a New Project.
Open: Opens a project.
Save: Saves the project.
Save As: Save as the project.
Import IED into Palette: Importing a ICD/CID file to IED Palette

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Export CID & Startup: This option is for exporting the selected IED in project editor to
CID file with Goose Subscription (mapping) information and IED configuration
information and corresponding Startup settings to startup file.
View GOOSE Mapping: This functionality allows the user to connect to an IED selected
in the project editor. By default this will connect to the IP Address present in the IED
properties.
Once the cid file is retrieved from the IED the mapping present in the cid file will be shown
as below.
Figure 124 - Goose Mapping

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Recent Projects: This shows the recently opened IED Configuration Tool project files
3.3.2.2 Edit Menu
Edit contains undo and redo functions.
Figure 125 - Edit Menu
Undo/Redo is available for following operations of IED Configuration Tool:

Adding a IED to project
Deleting a IED from project
IED instance renaming in project editor
GOOSE subscription mapping
GOOSE subscription mapping removal
GOOSE control block Add, Edit, Delete
Report control block Add, Edit, Delete
Dataset Add, Delete, Configure
3.3.2.3 Settings Menu
Change Password: This functionality allows the user to change the login password for
CGL IED Configuration Tool.
Figure 126 - Change Password

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About
Figure 127 - About the Developer

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3.4 LOGICAL NODE DESCRIPTION

This chapter gives description of each of the logical nodes for protection functions,
control functions and other general settings.
3.4.1 Logical Nodes for Protection Functions

3.4.1.1 Logical Node For Over Current Protection: A51xPTOC1
This LN handles the over current protection function for both the stages of HV & LV as
shown below.
A51H1PTOC1: LN for Over Current Protection for HV Stage 1

A51H2PTOC1: LN for Over Current Protection for HV Stage 2
A51L1PTOC1: LN for Over Current Protection for LV Stage 1
A51L2PTOC1: LN for Over Current Protection for LV Stage 2
All of these LNs include the following Functional Constraints (FC).
1. Configuration (CF)
This FC represents configuration setting values whose values can be read. DOs in CF
show all the settings similar to the 3I> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3I> DT. The fields minVal, maxVal,
and stepSize denote the minimum and maximum settable values, and the step size for
3I>DT respectively.
2. Setpoint (SP)
This FC represents set-point information whose value may be controlled and read. Values
controlled become effective immediately. DOs in SP allow the user to view the set-points
similar to the 3I> Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 3I> DT after which tripping occurs.
setCharact in TmACrv represents the required IDMT curve. The selected curve is
denoted by a value as defined by IEC 61850-7-3. Refer Appendix A to see the table.

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3. Status (ST)
This FC represents status information whose value may be read, substituted, reported, and
logged but shall not be written. The user can view the pickup or trip instances for each of the
phases from the respective DOs as follows:
For pickup instances, view Str DO.

When phsA / phsB / phsC = 0(false), normal operation continues.
When phsA / phsB / phsC = 1(true), over current pickup for phsA / phsB / phsC has
occurred.
general = 0 if no pickup has occurred in any of the phases.
general = 1 if pickup has occurred in any of the phases.
For trip instances, view Op DO.

When phsA / phsB / phsC = 0 (false), normal operation continues.
When phsA / phsB / phsC = 1 (true), over current tripping for phsA / phsB / phsC has
occurred.
general = 0 if no tripping has occurred in any of the phases.
general = 1 if tripping has occurred in any of the phases.
3.4.1.2 Logical Node For Instantaneous Over Current Protection:

A50xPIOC1
This LN handles the instantaneous over current protection function for both the stages of
HV & LV as shown below.
A50H1PIOC1: LN for Instantaneous Over Current Protection for HV Stage 1

A50H2PIOC1: LN for Instantaneous Over Current Protection for HV Stage 2
A50L1PIOC1: LN for Instantaneous Over Current Protection for LV Stage 1
A50L2PIOC1: LN for Instantaneous Over Current Protection for LV Stage 2
1. Status (ST)

When phsA / phsB / phsC = 1(true), instantaneous over current pickup for phsA / phsB /
phsC has occurred.

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When phsA / phsB / phsC = 1 (true), instantaneous over current tripping for phsA /
phsB / phsC has occurred.
3.4.1.3 Logical Node For Measured Earth Fault Protection: A51GxPTOC1
This LN handles the measured earth fault protection function for both the stages of HV &
LV as shown below.
A51GH1PTOC1: LN for Measured Earth Fault Protection for HV Stage 1

A51GL1PTOC1: LN for Measured Earth Fault Protection for LV Stage 1
show all the settings similar to the Ig> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for Ig> DT. The fields minVal, maxVal,
and stepSize denote the minimum and maximum settable values, and the step size for Ig>
DT respectively.
2. Setpoint (SP)
controlled shall become effective immediately. DOs in SP allow the user to view the set-
points similar to the Ig> Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of Ig> DT after which tripping occurs.

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3. Status (ST)

When neut = 0(false), normal operation continues.
When neut = 1(true), measured earth fault pickup for neut has occurred.

When neut = 1(true), measured earth fault tripping for neut has occurred.
3.4.1.4 Logical Node For Instantaneous Measured Earth Fault Protection:

A50GxPTOC2
This LN handles the instantaneous measured earth fault protection function for both the
stages of HV & LV as shown below.

show all the settings similar to the Ig>> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for Ig>> DT. The fields minVal, maxVal,
Ig>> DT respectively.
2. Setpoint (SP)
points similar to the Ig>> Settings menu of the relay as shown below.

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setVal in OpDITmms DO represents the time of Ig>> DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), instantaneous measured earth fault pickup for neut has occurred.

When neut = 1(true), instantaneous measured earth fault tripping for neut has occurred.
3.4.1.5 Logical Node For Derived Earth Fault Protection: A51NxPTOC1
This LN handles the derived earth fault protection function for both the stages of HV &
LV as shown below.
A51NH1PTOC1: LN for Derived Earth Fault Protection for HV Stage 1

A51NL1PTOC1: LN for Derived Earth Fault Protection for LV Stage 1
show all the settings similar to the Io> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for Io> DT. The fields minVal, maxVal,
and stepSize denote the minimum and maximum settable values, and the step size for Io>
DT respectively.
2. Setpoint (SP)
points similar to the Io> Settings menu of the relay as shown below.

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setVal in OpDITmms DO represents the time of Io> DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), measured earth fault pickup for neut has occurred.

When neut = 1(true), measured earth fault tripping for neut has occurred.
3.4.1.6 Logical Node For Instantaneous Derived Earth Fault Protection:

A50NxPTOC2
This LN handles the instantaneous derived earth fault protection function for both the

show all the settings similar to the Io>> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for Io>> DT. The fields minVal, maxVal,
Io>> DT respectively.

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2. Setpoint (SP)
points similar to the Io>> Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of Io>> DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), instantaneous derived earth fault pickup for neut has occurred.

When neut = 1(true), instantaneous derived earth fault tripping for neut has occurred.
3.4.1.7 Logical Node For Restricted Earth Fault Protection: A64RxPTOC1
This LN handles the derived earth fault protection function for both the stages of HV &
LV as shown below.
A64RH1PTOC1: LN for Restricted Earth Fault Protection for HV Stage 1

A64RH2PTOC1: LN for Restricted Earth Fault Protection for HV Stage 2
A64RL1PTOC1: LN for Restricted Earth Fault Protection for LV Stage 1
A64RL2PTOC1: LN for Restricted Earth Fault Protection for LV Stage 2
show all the settings similar to the 64R Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 64R DT. The fields minVal, maxVal,
64R DT respectively.

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2. Setpoint (SP)
points similar to the 64R Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 64R DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), restricted earth fault pickup for neut has occurred.

When neut = 1(true), restricted earth fault tripping for neut has occurred.
3.4.1.8 Logical Node For Negative Sequence Over Current Protection:

A46SxPTOC1
This LN handles the negative sequence over current protection function for both the
A46SH1PTOC1: LN for Negative Sequence Over Current Protection for HV Stage 1

A46SH2PTOC1: LN for Negative Sequence Over Current Protection for HV Stage 2
A46SL1PTOC1: LN for Negative Sequence Over Current Protection for LV Stage 1
A46SL2PTOC1: LN for Negative Sequence Over Current Protection for LV Stage 2
show all the settings similar to the I2> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for I2> DT. The fields minVal, maxVal,
and stepSize denote the minimum and maximum settable values, and the step size for I2>
DT respectively.

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2. Setpoint (SP)
similar to the I2> Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of I2> DT after which tripping occurs.
3. Status (ST)

general = 1 if negative sequence over current pickup has occurred in any of the phases.

general = 1 if negative sequence over tripping has occurred in any of the phases.
3.4.1.9 Logical Node For Instantaneous Negative Sequence Over Current

Protection: A46SxPTOC2
This LN handles the instantaneous negative sequence over current protection function for
both the stages of HV & LV as shown below.
A46SH1PTOC2: LN for Instantaneous Negative Sequence Over Current Protection for

HV Stage 1
A46SH2PTOC2: LN for Instantaneous Negative Sequence Over Current Protection for
HV Stage 2
A46SL1PTOC2: LN for Instantaneous Negative Sequence Over Current Protection for
LV Stage 1
A46SL2PTOC2: LN for Instantaneous Negative Sequence Over Current Protection for
LV Stage 2

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show all the settings similar to the I2>> Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for I2>> DT. The fields minVal, maxVal,
I2>> DT respectively.
2. Setpoint (SP)
similar to the I2>> Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of I2>> DT after which tripping occurs.
3. Status (ST)

general = 1 if instantaneous negative sequence over current pickup has occurred in any of
the phases.

general = 1 if instantaneous negative sequence over current tripping has occurred in any
of the phases.
3.4.1.10 Logical Node For Under Current Protection: A37xPTUC1
This LN handles the under current protection function for both the stages of HV & LV as
shown below.
A37H1PTUC1: LN for Under Current Protection for HV Stage 1

A37H2PTUC1: LN for Under Current Protection for HV Stage 2
A37L1PTUC1: LN for Under Current Protection for LV Stage 1
A37L2PTUC1: LN for Under Current Protection for LV Stage 2

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show all the settings similar to the 3I< Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3I< DT. The fields minVal, maxVal,
and stepSize denote the minimum and maximum settable values, and the step size for 3I<
DT respectively.
2. Setpoint (SP)
similar to the 3I< Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 3I< DT after which tripping occurs.
3. Status (ST)

When phsA / phsB / phsC = 1(true), under current pickup for phsA / phsB / phsC has
occurred.

When phsA / phsB / phsC = 1 (true), under current tripping for phsA / phsB / phsC has
occurred.

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3.4.1.11 Logical Node For Thermal Overload Protection: A49xPTTR1
This LN handles the thermal overload protection function for both, HV & LV as shown
below.
A49H1PTTR1: LN for Thermal Overload Protection for HV Stage 1

A49L1PTTR1: LN for Thermal Overload Protection for LV Stage 1
The above LNs include the following Functional Constraints (FC).
show all the settings similar to the THRM Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for THRM DT. The fields minVal,
maxVal, and stepSize denote the minimum and maximum settable values, and the step
size for THRM DT respectively.
2. Setpoint (SP)
similar to the THRM Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of THRM DT after which tripping occurs.
3. Status (ST)

When phsA / phsB / phsC = 1(true), thermal overload pickup for phsA / phsB / phsC
has occurred.


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When phsA / phsB / phsC = 1 (true), thermal overload tripping for phsA / phsB / phsC
has occurred.
3.4.1.12 Logical Node For Bias Differential Protection: A87BD_PDIF1 &

A87HS_PDIF2
This LN handles the bias differential protection function for both the stages as shown
below.
A87BD_PDIF1: LN for Bias Differential Protection for Stage 1

This LN includes the following Functional Constraints (FC).
1. Setpoint (SP)
similar to the 87BD Settings menu of the relay as shown below.
setVal in LoSet DO represents the pickup value.
setVal in RstMod DO represents the restraint mode according to settings for 2nd, 4th, and
5th harmonics.
2. Status (ST)

When phsA / phsB / phsC = 1(true), bias differential pickup for phsA / phsB / phsC has
occurred.

When phsA / phsB / phsC = 1 (true), bias differential tripping for phsA / phsB / phsC
has occurred.

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A87HSPDIF2: LN for Bias Differential Protection for Stage 2 / High set
1. Setpoint (SP)
similar to the 87HS Settings menu of the relay as shown below.
setVal in HiSet DO represents the pickup value.
setVal in RstMod DO represents the restraint mode according to settings for 2nd, 4th, and
5th harmonics.
2. Status (ST)

When phsA / phsB / phsC = 1(true), high set bias differential pickup for phsA / phsB /
phsC has occurred.

When phsA / phsB / phsC = 1 (true), high set bias differential tripping for phsA / phsB /
phsC has occurred.

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3.4.1.13 Logical Node For Over Fluxing Protection: A24xPVPHx
This LN handles the over fluxing protection function for both the stages as shown below.
A24H1PVPH1: LN for Over Fluxing Protection for Stage 1

A24H2PVPH2: LN for Over Fluxing Protection for Stage 2
show all the settings similar to the OFLX Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for OFLX DT. The fields minVal,
size for OFLX DT respectively.
2. Setpoint (SP)
similar to the I OFLX Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of OFLX DT after which tripping occurs.
setCharact in VHzCrv represents the required IDMT curve. The selected curve is
3. Status (ST)

general = 1 if over fluxing pickup has occurred in any of the phases.

general = 1 if over fluxing has occurred in any of the phases.

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3.4.1.14 Logical Node For Under Voltage Protection: A27_ PTUVx
This LN handles the under voltage protection function for both the stages as shown
below.
A27_PTUV1: LN for Under Voltage Protection for Stage 1(3U<)

show all the settings similar to the UV Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3U< DT. The fields minVal, maxVal,
3U< DT respectively.
2. Setpoint (SP)
This FC represents set-point information whose value may be controlled and read. The
values controlled become effective immediately. DOs in SP allow the user to view the set-
points similar to the UV Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 3U< DT after which tripping occurs.
setCharact in TmVCrv represents the required IDMT curve. The selected curve is
3. Status (ST)

general = 0 if no pickup has occurred.
general = 1 if under voltage pickup has occurred.
general = 0 if no tripping has occurred.
general = 1 if under voltage tripping has occurred.

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A27_PTUV2: LN for Under Voltage Protection for Stage 2 / High set

(3U<<)
show all the settings similar to the UV Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3U<< DT. The fields minVal,
size for 3U<< DT respectively.
2. Setpoint (SP)
similar to the UV Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 3U< DT after which tripping occurs.
3. Status (ST)

general = 1 if instantaneous under voltage pickup has occurred.

general = 1 if instantaneous under voltage tripping has occurred.

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3.4.1.15 Logical Node For Over Voltage Protection: A59_PTOVx
This LN handles the over voltage protection function for both the stages as shown below.
A59_PTOV1: LN for Under Voltage Protection for Stage 1(3U>)

show all the settings similar to the OV Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3U> DT. The fields minVal, maxVal,
3U> DT respectively.
2. Setpoint (SP)
setVal in OpDITmms DO represents the time of 3U> DT after which tripping occurs.
3. Status (ST)

general = 1 if over voltage pickup has occurred.

general = 1 if over voltage tripping has occurred.

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A59_PTOV2: LN for Under Voltage Protection for Stage 2 / High set

(3U>>)
show all the settings similar to the OV Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for 3U>> DT. The fields minVal,
size for 3U>> DT respectively.
2. Setpoint (SP)
similar to the UV Settings menu of the relay as shown below.
setVal in OpDITmms DO represents the time of 3U> DT after which tripping occurs.
setVal in RsDITmms DO represents the delay for Reset DT Timer / 3U> RST DT.
3. Status (ST)

general = 1 if instantaneous over voltage pickup has occurred.

general = 1 if instantaneous over voltage tripping has occurred.

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3.4.1.16 Logical Node For NDR Protection: A59N_PTOVx
This LN handles the NDR protection function for both the stages as shown below.
A59N_PTOV1: LN for NDR Protection for Stage 1

show all the settings similar to the NDR Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for NDR DT. The fields minVal, maxVal,
NDR DT respectively.
2. Setpoint (SP)
setVal in OpDITmms DO represents the time of NDR DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), NDR pickup for neut has occurred.

When neut = 1(true), NDR tripping for neut has occurred.

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A59N_PTOV2: LN for NDR Protection for Stage 2 / High Set
show all the settings similar to the NDR Settings menu of the relay as shown below.
OpDITmms DO represents the range settings for NDR DT. The fields minVal, maxVal,
NDR DT respectively.
2. Setpoint (SP)
setVal in OpDITmms DO represents the time of NDR DT after which tripping occurs.
3. Status (ST)

When neut = 1(true), high set NDR pickup for neut has occurred.

When neut = 1(true), high set NDR tripping for neut has occurred.

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3.4.1.17 Logical Node for Protection Tripping: Gen_PTRC1
This LN is used to combine and condition various signals intended for tripping into a
single trip condition. This LN includes the following Functional Constraints (FC).
1. Status (ST)
logged, but shall not be written. The Tr DO of ST contains the data. According to IEC
61850-7-3, the data has the following DataAttributes:
Tr general (status value): Represents the actual data, i.e. protection tripping status
Tr t (time stamp): Represents the recently updated time
When general = 1(true), tripping has occurred due to activation of any of the protection
functions.
When general = 0(false), normal operation continues.

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3.4.2 Logical Nodes for Control Functions

3.4.2.1 Logical Node For Circuit Breaker: CB_XCBR
This LN is used for modeling switches with short circuit breaking capability. It checks
the authorization of the commands. In AEGIS relays, The Trip and Close commands can be
subscribed from CSWI. This LN includes the following Functional Constraints (FC).
This FC represents configuration setting values whose values can be read. Pos DO shows
all the settings similar to the Comm. Settings  IEC 61850 menu of the relay as shown
below.
ctlModel represents the selected Control Model. Control model defines which IEC61850
control model will be used in CSWI LNs representing control objects of relay. The
AEGIS relays provide three Control Models:
stsOnly (Status only)
dwns OR do (direct with normal security)
SBOes (select before operate with enhanced security)
2. Status (ST)
logged but shall not be written. The Pos DO of ST contains the data. According to IEC
61850-7-3, the data has the following DataAttributes:
Pos stVal (status value): Represents the actual data
Pos t (time stamp): Represents the recently updated time
The status of Trip / Close Command can be seen in stVal. This is a 2-bit data, as shown
below:
00: Intermediate Operation

01: OFF
10: ON
11: Bad State

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3.4.2.2 Logical Node For Switch Controller: CSWI1
The switch control LN handles all switchgear operations from the operators and from
related automatics. It checks the authorization of the commands. In AEGIS relays, CSWI is
used to issue Trip / Close Commands through IEC 61850 Communication. This LN includes
the following Functional Constraints (FC).
This FC represents configuration setting values whose values can be read. Pos DO shows
all the settings similar to the Comm. Settings  IEC 61850 menu of the relay as shown
below.
pulseConfig$onDur and pulseConfig$offDur represents the Pulse Length.
control model will be used in CSWI LNs representing control objects of relay. The
AEGIS relays provide three Control Models:
stsOnly (Status only)
dwns OR do (direct with normal security)
SBOes (select before operate with enhanced security)
sbo Timeout can be edited within the prescribed range from the client, and the changes
are updated on the relay.
2. Control Objects (CO)
Data related to external devices, control outputs, or other internal functions may require
to be controlled by a client. The control model provides services to operate on data with
DataAttribute having the functional constraint FC (=CO).The Pos DO of CO represents
control information whose values may be operated & read.
The dwns control model is a single step control procedure, and the data is sent without
any time lag.
Cmd Send
ACK
Recieved
Operate
Figure 128 - dwns Control Model

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The SBOes is a two step control procedure. Here, the data to be sent is to be selected first
and is to be then updated and sent within the permissible sboTimeout. This model uses
the services SelectWithValue, Cancel, Operate.
Select data
ACK
Received Resend Cmd
Data sent No
within Sbo
Timeout ?
Yes
Operate
Figure 129 - sboes Control Model
3. Status (ST)
Represents status information whose value may be read, substituted, reported, and logged
but shall not be written. The Pos DO of ST contains the data. According to IEC 61850-7-3,
the data has the following DataAttributes:
Pos stVal (status value): Represents the actual data
Pos t (time stamp): Represents the recently updated time
The Trip / Close Command can be operated from stVal. This is a 2-bit data, as shown below:
00: Intermediate Operation
01: OFF
10: ON
11: Bad State

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3.4.2.3 Logical Node for DO Status: DOSts_GGIO1
This Generic Logical Node GIO is used for determining status of Digital Outputs. This
LN includes the following Functional Constraints (FC).
This FC represents configuration setting values whose values may be read or written.
SPCSO1 – SPCSO8 DOs of CF give the settings of the ctlModel similar to the Comm.
Settings  IEC 61850 menu of the relay.
control model will be used in CSWI LNs representing control objects of relay. Here the
default Control Model is dwns OR do (direct with normal security).
2. Control Objects (CO)
Data related to external devices, control outputs, or other internal functions may require
to be controlled by a client. The control model provides services to operate on data with
DataAttribute having the functional constraint FC (=CO). The SPCSO1 – SPCSO8 DOs of
CO represents control information whose values may be operated & read.
The dwns control model is a single step control procedure, and the data is sent without
any time lag.
3. Status (ST)
logged but shall not be written. The SPCSO1 – SPCSO8 DOs of ST contains the data.
According to IEC 61850-7-3, the data has the following DataAttributes:
SPCSO1 – SPCSO8 stVal (status value): Represents the actual data, i.e. the DO status
SPCSO1 – SPCSO8 t (time stamp): Represents the recently updated time
The DO Status can be changed from stVal.
When stVal = 1(true), the assigned DO has operated.

When stVal = 0(false), no DO has operated.
The DOs can be operated from the COs in the following scenarios:
Scenario 1:
If DO is ON for any condition (protection, DIs, VIs, etc.), and this results in a trip.

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Action Taken:
The DO will be operated from a CO, and the DO status will be unchanged if the user sets
stVal = 1, as setting stVal = 1 itself denotes that the DO is supposed to operate.
Scenario 2:
If DO is ON for any condition (protection, DIs, VIs, etc.), and this results in a trip due to a
persistent fault.
Action Taken:
The DO will be operated from a CO, and the DO status will be unchanged even if the user
sets stVal = 0, as the fault being persistent means that DO will continue to operate.
Scenario 3:
If DO is ON for any condition (protection, DIs, VIs, etc.), resulting in a trip, and user sets the
DO to be cleared on Hand Reset.
Action Taken:
In case of Hand Reset function on the relay, pressing Esc key on the front panel resets the
DO. A similar job is done by stVal. The DO will be operated from a CO, and the DO will be
reset when user sets stVal = 0.
Scenario 4:
If DO is currently OFF and is to set ON for any condition (protection, DIs, VIs, etc.)
Action Taken:
The DO will be operated from a CO, and if the user sets stVal = 1, the DO will operate for
the period Pos pulseConfig$onDur as defined in CO of CSWI LN.
Note: SPCSO1 - SPCSO8 DOs depend on number of available DOs (8 DOs in this case),
similarly applicable for other configurations of DO.
3.4.2.4 Logical Node For DI Status: DISTS_GGIO1
This Generic Logical Node GIO is used for determining status of Digital Inputs. This LN
includes the following Functional Constraints (FC).
default Control Model is stsOnly, as no data is sent from the client

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2. Status (ST)
SPCSO1 – SPCSO8 stVal (status value): Represents the actual data, i.e. the DI status
The DI Status can be changed from stVal.
When stVal = 1(true), the assigned DI has operated.

When stVal = 0(false), no DI has operated.
Note: SPCSO1 - SPCSO8 DOs depend on number of available DIs (8 DIs in this case),
similarly applicable for other configurations of DI.
3.4.2.5 Logical Node For VI Status: VIRTIP_GGIO1
This Generic Logical Node GIO is used for determining status of Virtual Inputs. VIs can
be mapped for protection as well as control functions from the relay or via Logic in the
ConAegis Relay Configuration Software. Protection on VI facilitates operation of any
protection function based on an active VI. Setting Group on VI enables the user to assign a
VI to a particular Setting Group. DR Triggering on VI generates disturbance record for the
assigned protection function on activation of VI. In all, 64 VIs have been provided, out of
which, VI 1 - VI 16 are dedicated for protection functions. This LN includes the following
Functional Constraints (FC).
default Control Model is stsOnly, as no data is sent from the client.

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2. Status (ST)

When stVal = 1(true), the assigned VI has operated.

When stVal = 0(false), no VI has operated.
3.4.2.6 Logical Node For VO Status: VIRTOP_GGIO1
This Generic Logical Node GIO is used for determining status of Virtual Outputs. VOs
can be configured for protection as well as control functions. VOs can be mapped to the VIs
via Logic in the ConAegis Relay Configuration Software. 64VOs have been provided whose
status can be denoted by an LED on the relay or can be further mapped to the VIs. This LN
2. Status (ST)

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When stVal = 1(true), the assigned VI has operated.
When stVal = 0(false), no VI has operated.
3.4.2.7 Logical Node For LED Status: LED_GGIO1
This Generic Logical Node GIO is used for determining status of LEDs. This LN includes
the following Functional Constraints (FC).
2. Status (ST)
SPCSO1 – SPCSO16 stVal (status value): Represents the actual data, i.e. the LED status
When stVal in SPCSOx DO = 1(true), the LEDx has operated.
When stVal in SPCSOx DO = 0(false), none of the LEDs have operated.
3.4.2.8 Logical Node for Generic Commands: SPC_GGIO1
This Generic Logical Node GIO is used to operate the commands remotely through
SCADA. This LN includes the 8 Oper structures as shown below, and these inputs can be
further configured in Logic software for the relay to enact accordingly. The inputs are:
SPCSO1 - Error: Error Signal due to some internal relay operation failure.
SPCSO2 - General Pickup: Pickup in any of the protection function.
SPCSO3 - General Trip: Trip in any of the protection function.

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SPCSO4 - CSWI Close: The Close BO in the device operates when this is given from
SCADA and in further configured in Logic.
SPCSO5 - CSWI Trip: The Trip BO in the device operates when this is given from
SCADA and in further configured in Logic.
SPCSO6 - LED Reset: Operates the LED on Hand Reset.
SPCSO7 - Local Position: Sets the operation of circuit breaker.
SPCSO8 - Remote Position: Sets the operation of circuit breaker.

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3.4.3 Logical Nodes for General Settings & Measurements

3.4.3.1 Logical Node For HV Measurements: MESRMMXU1
This LN is used for calculation of currents, voltages, powers and impedances in a

three-phase system. The main use is for operative applications and includes the following
1. Measurands (MX)
This FC represents measurand information whose value may be read, substituted,

reported, and logged but shall not be written. According to IEC 61850-7-3, the data has the
following DataAttributes:
status value: Represents the actual data
time stamp: Represents the recently updated time
Here, various DOs for denoting the measured values and the time at which the measurements
have been recorded.
A DO represents the phase current measurements as follows:

phsA$cVal$mag$f, phsB$cVal$mag$f, phsC$cVal$mag$f and neut$cVal$mag$f give
the HV current magnitude in respective phases.
In Hz DO, mag$f represents the operating frequency.
phsA$cVal$mag$f represents the ph-N voltage magnitude in PhV DO
3.4.3.2 Logical Node For LV Measurements: MESRMMXU2
This LN is used for calculation of currents, voltages, powers and impedances in a

three-phase system. The main use is for operative applications and includes the following
1. Measurands (MX)


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have been recorded.
A DO represents the phase current measurements as follows:

phsA$cVal$mag$f, phsB$cVal$mag$f, phsC$cVal$mag$f and neut$cVal$mag$f give
the LV current magnitude in respective phases.
In Hz DO, mag$f represents the operating frequency.
phsA$cVal$mag$f represents the ph-N voltage magnitude in PhV DO
3.4.3.3 Logical Node For Differential Current Measurements:

MESRMDIF1
This LN is used to provide calculated process values representing the other side of the
line as used for differential protection (PDIF). The main use is for operative applications and
1. Measurands (MX)

have been recorded.
OpARem DO represents the differential current measurements as follows:

phsA$cVal$mag$f, phsB$cVal$mag$f and phsC$cVal$mag$f give the differential
current magnitude in respective phases.

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3.4.4 System Logical Nodes

3.4.4.1 Logical Node Device: LLN0
The LN is a special logical node per LD used to address common issues for Logical
Devices. It contains for example the data sets, the various control blocks, inputs (from
GOOSE messages). The LN also contains the data related to the IED of the physical device
independent from all included logical nodes (device identification/name plate, messages from
device self-supervision, etc.). This LN includes the following Data Objects (DO).
Loc DO represents local operation for complete logical device

OpTmh DO represents the Operation time
LEDRs DO represents LED reset
3.4.4.2 Logical Node for Physical Device Information: LPHD
This LN is a special logical node per Logical Device (LD) and contains data objects that
describe the status of the physical device (the IED). This LN includes the following
1. Status (ST)
logged, but shall not be written. According to IEC 61850-7-3, the data has the following Data
Attributes:
stVal (status value): Represents the actual data
t (time stamp): Represents the recently updated time
Here, various DOs describe the status of the physical device.
PhyHealth DO represents the physical device health.

Proxy DO indicates if this LN is a proxy.
2. Description (DC)
This FC represents description of the Logical Node. According to IEC 61850-7-3, the
data has the following Data Attributes:
PhyNam DO represents the Physical device name plate.

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4 CONAEGIS RELAY
COMMUNICATION SOFTWARE &
LOGIC

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Section Overview
This section describes the operation of Crompton Greaves Ltd™ ConAEGIS v2.0
Relay Communication Software which also includes the Logic Software for Feeder
Protection Relay. This section describes only the Windows version of the Communication
Software. Read and follow the instructions in the Getting Started chapter. This chapter
includes instructions on installing the software. After you install the software, and to see how
quick and easy it is to use this software, CG recommends you to read all of this section. This
document applies to the use of ConAEGIS v2.0 Relay Communication Software only with
the CG Aegis Series Protection Relays.

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4.1 GETTING STARTED

This chapter provides instructions on installing the software, and describes how to
establish communication between the software and the relay.
4.1.1 What is ConAEGIS ?
ConAEGIS is a relay communication software for AEGIS series protection relays. This
software provides a user-friendly graphical interface for making various configurations. The
user does not need to know anything about the model or hardware of the relay being used;
ConAEGIS reads all information directly from the device. Provisions have been made to
download and analyze the disturbance records encountered by the relays. The disturbance
records are saved by using a standard COMTRADE file format. Also, a state-of-the-art
facility of developing a user-defined programmable logic has been provided. ConAEGIS can
save the relay settings as a separate file. This file can be read from the relay and can be
transferred between similar kinds of relays. The file can also be saved to the PC, and can be
loaded back to ConAEGIS software and to the relay.
4.1.2 Software Installation
To get started with the ConAegis Relay Communication Software, simply extract the
.rar file from the CD. After the extraction is completed, you should have the following
executable file in your folder, ConAegis_v2.0.exe.
Figure 130 - ConAegis Software Icon
To launch ConAEGIS software, simply double click on this icon. If the user wishes to
copy / move this executable file to any other location, or to the desktop, please note that the
Support folder extracted along with this .exe file must also be copied / moved to the
respective location.

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4.1.3 System Requirements
Table shows the system requirements necessary for installation of ConAEGIS

Software. Also the software requires Java v.1.7.0.21 to be installed on the PC.
Minimum System Requirements

RAM 512 MB
Free Disk Space 210 MB
Operating System Microsoft® Windows® XP / Windows Vista® / Windows 7®
Table 93 - System Requirements
4.1.4 Connecting Relay with the Software
The following screenshot shows a default view of the ConAEGIS Relay

Communication Software. The relay can be interfaced serially with the software or through
Ethernet. Also, if no relay is connected, the software can be used in Offline Mode.
Figure 131 - Default View

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 Connecting the software in Offline Mode: In this mode, the user can configure all the
settings in the relay by selecting the required relay model. All the settings can be then
saved in a file which can be later downloaded in the relay. The procedure to save and
download the file has been described in further sections. To configure the settings in
Offline Mode, click on Offline Mode in the Connection Options setting. Choose the
required relay model from the available options and click on Select. The screen shows
serial number and all the information about the selected device.

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Figure 132 - Offline Mode

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 Connecting the relay serially: Click on the Serial mode in the Connection Options
setting, and simply plug-in the USB cable to the front panel of the relay and other end to
the serial port of the computer. Select the appropriate Communication Port & Baud
Rate, & Hit Connect. The software will connect to the port which is assigned to the
relay.
Figure 133 - Connecting the relay serially
If user faces any difficulty in selecting the Communication Port, one can give a tick on the
Auto Synchronize option, which scans the ports automatically, chooses the correct one, and
connects the device to that port.

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Figure 134 - Connecting serially using Auto-Synchronize option
Once the connection is established, the screen shows the status, that the relay has been
connected, along with the port to which is connected, the Baud rate and the parity. Also, the
screen shows serial number and all the information about the selected device. If any incorrect
setting is done, for eg., communication port or baud rate, the screen shows a error message.

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Figure 135 - Connection Error
If such an error message appears:

Check the cable connection
Verify the mode of communication used.
Check if the serial port is used for any other application.

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 Connecting the relay through Ethernet: Click on the Ethernet mode in the
Connection Options setting, and simply plug-in the Ethernet cable at rear port of the
relay and other end to the Ethernet port of the computer. Enter the IP address assigned to
the relay, and hit Connect.
Figure 136 - Connection Through Ethernet

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If the entered IP address is invalid, an error message is displayed.
Figure 137 - Invalid IP Address
4.1.5 Tool Bar Functions
Figure 138 - Tool Bar
The tool bar on the main window of the software shows the following functions. Some
of the tools are required only when Logic is to be developed. The function of each menu has
been given below:
Open: This tool allows the user to select the previously saved setting file from the
desired location, which is to be downloaded in the relay.
Save: This tool allows the user to save the settings file to the desired location of the
PC, which can later be downloaded in a different relay.

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4.1.6 Tree Structure
A tree structure can be seen in the left pane of your screen. This tree shows all the
menus & submenus available in a device, i.e. Connection, Settings, Logic, Graphs,
Measurements, & Reports, in a hierarchical manner. Furthermore, each of the submenus in
the device show a number of settings similar to that in the device, which have been described
in the further sections of the document.
Figure 139 - Tree Structure

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4.1.7 Procedure to Write A Value
 Go to the settings wherein the editable values are to be changed. Consider the settings for
Bias Differential function as shown in the figure.
 After you change this setting value from Disable to Enable, & 0.20 to 0.45 in this case,
click on Write tab in the top-left corner of the settings window.
Figure 140 – Bias Differential Settings
 As you click on the icon, an Acknowledgement Window will appear on your screen,
indicating that your settings have been successfully saved.

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Figure 141 - Write Successful
 The above steps are to be performed everytime the user wants to change any of the
settings.
 If the user changes any setting from the front panel of the relay, and wants to see the
update in the software, click on the Refresh tab to view the updated values in the
software.
The further chapters explain each of the tools and settings along with the real-time
screenshots so as to simplify the user interface of the software.

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4.2 SETTINGS
This chapter directs the user so as to how to configure various settings, like device
configuration settings, protection setting parameters, communication settings, disturbance
record settings, & BI/BO & LED selection. The user can enter the Settings menu by clicking
icon. All of these settings can be viewed in the form of a pane on the left hand side of your
screen.
4.2.1 Disturbance Record Settings
The disturbance recorder can be used to record all the measured signals, i.e., currents,
voltages and the status information of digital inputs (DI) and digital outputs (DO) in
oscillographic manner. The recorder can be triggered by any start or trip signal from any
protection stage or by a digital input. The triggering signal is selected in the output matrix.
The recording can also be triggered manually. All recordings are time stamped. These
disturbance records can be downloaded & saved from ConAegis Relay Configuration
Software. This is a COMTRADE file format and is stored at a particular location according to
the path given by the user.
Figure 142 - Disturbance Record Settings
Disturbance Record: Enables / Disables the disturbance recording facility.

Pre- fault: This sets the trigger point as a percentage of the duration.
No. of samples per cycle: Required for data sampling
DR Triggering LED: The selected LED will give a blink on triggering of a DR.

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Clearing the DR: Erases all the previously stored disturbance records.
Permissible Values:
DIST. RECORDS : Enable / Disable

PRE-FAULT : 1% - 99%
SAMPLE RATE : 8 / 16 / 32 / Cycle
TRIG LED : NONE / LED 5 - 16
We also have the facility of providing disturbance record for pick up and trip conditions
of all the protection functions. These can be turned ON / OFF from the DR Trigger Settings.
Here, the user has to select pickup & trip signals for which the DR is to be generated & the
settings are to be saved by clicking on Write.

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Figure 143 - Disturbance Record Trigger Settings
Similarly, Disturbance Records can be also obtained on triggering of a particular BI.

This menu allows the user to dedicate the any of the available BIs to Disturbance Records.
Whenever the assigned BI will be active, the Disturbance Records will be generated. Clicking
on Write saves the settings.

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Figure 144 - DR Trigger BI Settings

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4.2.2 Configuration Settings
Configuration Menu allows the user to set the system parameters like type and ratings
of CT and VT, system frequency, ICT, Harmonic and Breaker control settings and the setting
groups for the protection parameters. The configuration submenu has the following settings
as shown in the figure.
Active Group: The total active and functional protection parameter settings are based on
the Active Group. Operation of the relay is based on the present Active Group.
System Frequency: This is the frequency on which relay operates.
View / Edit Group: The user can edit any group parameters irrespective of the Active
group set, by using this menu.
Trip Alert: This setting indicates the fault alert on the display. When Enabled, the
occurrence of a Trip will cause the relay to display the Fault Record screen & the only
way to leave this screen is by acknowledging the trip through the ESC key on the relay
front end.
Permissible Values:
ACTIVE GROUP : 1/2/3/4

SYSTEM FREQUENCY : 50Hz / 60Hz
VIEW / EDIT SETT GROUP : 1/2/3/4
TRIP ALERT : YES / NO

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4.2.2.1 Phase CT, Earth CT & VT Settings
This submenu gives the facility to configure the primary and secondary ratings of the
phase and earth CT, and the VT according to user‟s requirement. These settings can be
changed and updated by clicking on Write. The permissible values alongwith their range is
shown in the figure.
Figure 146 - Phase & Earth CT & VT Settings

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HV / LV / Phase / Earth / Primary & Secondary: These ratings can be configured as

per user‟s requirement.
VT Connection Type: We can change the VT connection type as PH-N, PH-PH.
VT Type: If we select the VT Type as PH-VT we can achieve all the protections
functions, but for NDR protection function, VT Type setting should be changed to NDR-
VT.
CT Type: This parameter allows user to operate the relay in either REF or EF mode.
Default, this relay supplied with inbuilt REF protection, but for the Ig protection
function, the setting should be changed to EF protection.
Auxiliary Protection Function: Back up protections like over current, Earth fault etc
will protect either HV or LV windings but not both.
Note: We cannot select the both protection functions at a time.
Permissible Values:
CT Settings:
HV-Phase CT Pri : 1A - 5000A (In steps of 1A)
HV-Phase CT Sec : 1A/5A
LV-Phase CT Pri : 1A - 5000A (In steps of 1A)
LV Phase CT Sec : 1A/5A
HV-Earth CT Pri : 1A - 5000A (In steps of 1A)
HV-Earth CT Sec : 1A/5A
LV-Earth CT Pri : 1A - 5000A (In steps of 1A)
LV-Earth CT Sec : 1A/5A
VT Settings:
VT Pri : 3.3kV-500kV (In steps of 0.1KV)
VT Sec : 40V – 120V (In steps of 0.1V)
VT Conn. Type : PH-N/PH-PH
VT Type : PH VT/NDR VT
CT Type : REF/EF
Aux. Prot. : HV/LV

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4.2.2.2 Configuration Settings
Logic: The logic file downloaded in the device will work only if this setting is enabled.
Protection & Setting Group on Binary Inputs (BIs): The enabling / disabling of the
protection functions and the setting group changes to be done on activation of a BI will
work only if this setting is enabled.
Measurement Scroll: The various windows in the Measurement menu keep scrolling
after a fixed time if this setting is enabled. If disabled, the window does not changed
unless changed from the front end.
Permissible Values:
LOGIC : Enable / Disable

PROT & SETGRP ON IP : Enable / Disable
MESR SCROL : Enable / Disable

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4.2.2.3 ICT Settings
Internal current multipliers are used to adjust the CT secondary currents to

accommodate for any mismatch between the winding 1 and winding 2 CT ratios. Internal
interposing current transformers (ICT) are used to correct the CT secondary current phase
relationships in line with any phase change introduced by the transformer connections. Note
that the choice of interposing CT vector group will modify the effective operating levels of
the protection due to the current distribution for the various fault conditions. Figure shows
various editable settings in this menu.
Figure 148 - ICT Settings
HV ICT Multiplier and LV ICT Multiplier: Sets the multiplying factor at HV and LV
side
HV ICT Connection and LV ICT Connection: Sets the current phase relationship
Permissible Values:
HV ICT Mult : 0.25-5(In steps of 0.01)

HV ICT Conn : Yy0/Yd1/Yy2/Yd3/Yy4/Yd5/Yy6/Yd7/Yy8/Yd9/Yy10/
Yd11/Ydy0/Ydy6
LV ICT Mult : 0.25-5(In steps of 0.01)
LV ICT Conn : Yy0/Yd1/Yy2/Yd3/Yy4/Yd5/Yy6/Yd7/Yy8/Yd9/Yy10/Yd11/
Ydy0/Ydy6

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4.2.2.4 Harmonics Blocking
This submenu helps to set threshold for tripping, in case of 2nd, 4th, and 5th harmonics.
Figure 149 - Harmonics Block Settings
If2>, If4>, If5> Set Value: Sets the pickup value for 2nd, 4th, & 5th harmonics
respectively.
If2>, If4>, If5> DT: Sets the delay after which tripping occurs.
Permissible Values:
If2> SET VALUE : 0.10 - 0.50 (In steps of 0.01)
If2> DT : 0.02 - 10.00S (In steps of 0.02)
If4> DT : 0.02 - 10.00S (In steps of 0.02)
If5> DT : 0.02 - 10.00S (In steps of 0.02)

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4.2.2.5 Trip / Close BO
BOs can be assigned for trip or close operations from the relay. These operations are
possible only when the setting CB Operation is Local.
Figure 150 - Trip / Close BO Settings
Trip BO: The assigned BO operates when trip signal is issued from the relay.
Close BO: The assigned BO operates when close signal is issued from the relay.
IRF BO: The assigned BO operates in case an LED glows due to some Internal Relay
Failure (IRF).
CB Operation: Sets the operation of Circuit Breaker.
Permissible Values:
TRIP BO : NONE / BO 5 / 6
CLOSE BO : NONE / BO 5 / 6
IRF BO : NONE / BO 1 - 6
CB Operation : Local / Remote

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4.2.2.6 Trip / Close BI
Similar to Trip / Close BOs, BIs can also be assigned for several operations from the
relay.
Figure 151 - Trip / Close BI Settings
CB OFF BI: This BI is used to check the CB OFF status coming from the switchgear.
CB ON BI: This BI is used to check the CB ON status coming from the switchgear.
TCS BI: The assigned BI is triggered when the trip circuit is healthy, else the assigned
LED & relay indicates bad circuit.
CCS BI: The assigned BI is triggered when the close circuit is healthy, else the assigned
LED & relay indicates bad circuit.
Remote BI Setting: This setting determines whether the operation of CB is remote based
on activation of BI.
Local BI Setting: This setting determines whether the operation of CB is local based on
activation of BI.

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Remote Trip: Whenever a selected BI in this setting is activated, it results in a remote

trip. This trip condition is time stamped & shown in the fault record menu.
Permissible Values:
CB OFF BI : None / Any of the max. available BIs

CB ON BI : None / Any of the max. available BIs
TCS BI : None / Any of the max. available BIs
CCS BI : None / Any of the max. available BIs
REMOTE BI : None / Any of the max. available BIs
LOCAL BI : None / Any of the max. available BIs
REMOTE TRIP BI : None / Any of the max. available BIs

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4.2.2.7 Hysteresis
This submenu configures the pickup and dropout values for IDMT and Instantaneous
Settings in case of hysteresis.
Figure 152 – Pickup-Reset Time Settings
IDMT Pickup: Sets the pickup value, i.e, alarm signal will be issued when the measured
IDMT Reset: Sets the dropout value, i.e, normal operation will resume when the
INST Pickup: Sets the pickup value, i.e, alarm signal will be issued when the measured
INST Reset: Sets the dropout value, i.e, normal operation will resume when the
Permissible Values:
IDMT PICKUP : 1.01 - 1.10

IDMT RESET : 0.90 - 0.99
INST PICKUP : 1.01 - 1.10
INST RESET : 0.90 - 0.99

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4.2.2.8 DI Debounce Settings
This submenu configures the pickup and dropout time for a DI to be valid.
Figure 153 - DI Debounce Settings
DI Debounce Pickup: Sets the minimum time for which the assigned DI should be
triggered so as to be considered as active.
DI Debounce Drop: Sets the minimum time for which the assigned DI should drop down
so as to be considered as inactive.
Permissible Values:
DI DBNC PICKUP : 10 – 100 ms
DI DBNC DROP : 10 – 100 ms

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4.2.3 Bias Differential Protection (87BD) & Bias Differential

High Set Protection (87HS)
The following figure shows UI for Bias Differential Protection Settings which allows
the user to configure various settings. Also the default / previously set value & the setting
range for each setting is given.
Figure 154 - Biased Differential
87BD Protection: Enables / Disables Bias Differential Protection Function.

87BD Pick up: Defines the minimum differential current required to operate the relay.
87BD Slope 1: Used to ensure protection stability in the presence of steady state errors.

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87BD Slope 1 Limit: Defines the border between the 1st and 2nd bias slopes.
87BD Slope 2: Used to modify the sensitivity of the differential algorithm at higher
current levels.
87BD DT Delay: Sets the time after which tripping occurs.
87BD If2>, 87BD If4>, 87BD If5: Harmonic bias is used to prevent relay operation
during magnetizing inrush current into one winding when the transformer is first
energized.
Similarly, the following figure shows UI for Bias Differential High Set Protection
Settings which allows the user to configure various settings. Also the default / previously set
value & the setting range for each setting is given.
Figure 155 - Biased Differential Highset
87HS Protection: Enables / Disables Highset Bias Differential Protection Function.

87HS Set Value: Defines the minimum differential current required to operate the relay.
87BD DT Delay: Sets the time after which tripping occurs.
87BD If2>, 87BD If4>, 87BD If5>: Harmonic bias is used to prevent relay operation
during magnetizing inrush current into one winding when the transformer is first
energized.

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4.2.3.1 Configuring LEDs & BOs:
After enabling a protection function the relay may generate alarm or trip signal based
on the set threshold value. Occurrence of such an event can be indicated by the LEDs. To
indicate the fault due to which alarming / tripping has occurred, the user can configure the
LEDs for a particular protection function according to his wish.
Out of the 16 LEDs provided on the relay, the first four LEDs are dedicated for Power,
Alarm, Trip, and Error respectively. So, the user can configure between LEDs 5 to 16.The
following steps guide on, how to configure the LEDs. The procedure is same for the other
protection functions as well. The LED configuration for pickup or trip in any of the phase can
be done from the Bias Differential LED Settings.
Figure 156 – Bias Differential LED Setting Step-1
The various LEDs can be assigned by clicking at the crosspoints of the matrix. For eg., in this
case, LED 5 is assigned to BD1 TRP, LED 6 is assigned to BD2 TRP, and so on.
After the LEDs have been assigned, click on Write. If the LEDs are configured from the
relay, click Refresh icon to update the settings in the software.

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Figure 157 - Bias Differential LED Setting Step-2

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To configure the BOs, follow the same procedure after you click on SW_BIBO submenu.
This configuration allows assigning any relay outputs for any fault Pick-up and trip condition.
Figure 158 - SwBI / BO Setting Configuration

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4.2.4 Restricted Earth Fault Protection (64H) (REF)
This protection is valid for both windings and both stages. The REF protection function
for HV side can be enabled by clicking on Enable after changing the auxiliary protection
setting. The following figure shows UI for REF Settings which allows the user to configure
various settings. Also the default / previously set value & the setting range for each setting is
given.
Figure 159 - Restricted Earth Fault Settings
HV 64H Protection: Enables / Disables Restricted Earth Fault Protection Function.

HV 64H Set Value: Sets the pick-up current level.
HV 64H DT Delay: Sets the time after which tripping occurs.
LV 64H Protection: Enables / Disables Restricted Earth Fault Protection Function.
LV 64H Set Value: Sets the pick-up current level.
LV 64H DT Delay: Sets the time after which tripping occurs.
The permissible values are same for the both windings and for both the stages. The BOs and
LEDs can be configured as given in subsection 4.2.3.1.

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4.2.5 Thermal Overload Protection (49)(THRM)
The thermal overload protection function for HV side can be enabled by clicking
Enable after changing the auxiliary protection setting. At this point of time, LV protection is
inactive. The thermal overload protection for LV side can be enabled by clicking on Enable
after changing the auxiliary protection setting. At this point of time, HV protection is
inactive. The following figure shows UI for Thermal Overload Settings which allows the user
to configure various settings. Also the default / previously set value & the setting range for
each setting is given.
Figure 160 - Thermal Overload Settings
HV Protection: Enables / Disables Thermal Overload Protection Function.

HV Set Value: Sets the pick-up current level.
HV T-Opr: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
LV Protection: Enables / Disables Thermal Overload Protection Function.

LV Set Value: Sets the pick-up current level.
LV T-Opr: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
The permissible values are same for the both windings. The BOs and LEDs can be configured
as given in subsection 4.2.3.1.

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4.2.6 Over Fluxing Protection (24) (OFLX)
The following figure shows UI for Over Flux Settings which allows the user to
configure various settings. Also the default / previously set value & the setting range for each
setting is given.
Figure 161 - Over Fluxing Settings
24 Protection: Enables / Disables Over Fluxing Protection Function.

24 Set Value: Sets the pick-up level.
24 Curve: Selects the required characteristics
24 TMS: Sets the Time Multiplier Setting value
24 DT Delay: Sets the time after which tripping occurs. An output is enabled after this
time elapses.
The BOs and LEDs can be configured as given in subsection 2.3.1.

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4.2.7 Over Current Protection (51) (3I>)
Overcurrent protection includes definite time and IDMT characteristics as per IEC and
IEEE standards. Optionally two stage over current elements are provided; each can be
selected to either winding 1 or winding 2. The over current protection function for HV side
can be enabled by clicking Enable after changing the auxiliary protection setting. At this
point of time, LV protection is inactive. Similarly, protection for LV side can be enabled by
clicking on Enable after changing the auxiliary protection setting. At this point of time, HV
protection is inactive. The following figure shows UI for Over Current IDMT Settings which
allows the user to configure various settings. Also the default / previously set value & the
setting range for each setting is given.
Figure 162 - Over Current Settings
51 Protection: Enables / Disables Over Current Protection Function.

51 Set Value: Sets the pick-up current level.
51 Curve: Selects the required time current characteristics
51 If2> ACT: Enables/ Disables tripping after 2nd harmonic
51 Reset DT: Sets the time for Reset DT Timer.
51 DT: Sets the time after which tripping occurs.
These values are same for the both windings and stages. The BOs and LEDs can be
configured as given in subsection 4.2.3.1.

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4.2.8 Instantaneous Over Current Protection (50) (3I>>)
The instantaneous over current protection function for HV side can be enabled by
clicking Enable after changing the auxiliary protection setting. At this point of time, LV
protection is inactive. Similarly, protection for LV side can be enabled by clicking on Enable
inactive. The following figure shows UI for Over Current INST Settings which allows the
user to configure various settings. Also the default / previously set value & the setting range
for each setting is given.
Figure 163 - Instantaneous Over Current Settings

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50 Protection: Enables / Disables Instantaneous Over Current Protection Function.

50 DT: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
50 If2> Action: Enables/ Disables tripping after 2nd harmonic.
These values are same for the both windings and for all stages also. The BOs and LEDs can
be configured as given in subsection 2.3.1.

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4.2.9 Measured Earth Fault Protection (51G) (Ig>)
Measured earth-fault protection includes definite time and IDMT characteristics as per
IEC and IEEE standards. Optionally two stage earth-fault elements are provided; each can be
selected to either winding 1 or winding 2. The measured earth fault protection function for
HV side can be enabled by clicking Enable after changing the auxiliary protection setting. At
this point of time, LV protection is inactive. Similarly, protection for LV side can be enabled
by clicking on Enable after changing the auxiliary protection setting. At this point of time,
HV protection is inactive. The following figure shows UI for Measured Earth-fault IDMT
Figure 164 - Measured Earth Fault Settings
51G Protection: Enables / Disables Measured Earth Fault Protection Function.

51G Set Value: Sets the pick-up current level.
51G Curve: Selects the required time current characteristics
51G TMS: Sets the Time Multiplier Setting value
51G If2> Action: Enables/ Disables tripping after 2nd harmonic
51G Reset DT Delay: Sets the time for Reset DT Timer.
51G DT Delay: Sets the time after which tripping occurs. An output is enabled after this
time elapses.
be configured as given in subsection 4.2.3.1.

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4.2.10 Instantaneous Measured Earth Fault Protection (50G)

(Ig>>)
The instantaneous measured earth fault protection function for HV side can be enabled
by clicking Enable after changing the auxiliary protection setting. At this point of time, LV
inactive. The following figure shows UI for Measured Earth-fault INST Settings which
Figure 165 - Instantaneous Measured Earth Fault Settings

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50G Protection: Enables / Disables Instantaneous Measured Earth Fault Protection

Function.
50G Set Value: Sets the pick-up current level.
50G DT: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
50G If2> Action: Enables/ Disables tripping after 2nd harmonic.

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4.2.11 Derived Earth Fault Protection (51N) (Io>)
Derived Earth-fault protection includes definite time and IDMT characteristics as per
IEC and IEEE standards. Optionally two stages of earth-fault elements are provided; each can
be selected to either winding 1 or winding 2. The derived earth fault protection function for
HV side can be enabled by clicking Enable after changing the auxiliary protection setting. At
this point of time, LV protection is inactive. Similarly, protection for LV side can be enabled
by clicking on Enable after changing the auxiliary protection setting. At this point of time,
HV protection is inactive. The following figure shows UI for Derived Earth-fault IDMT
Figure 166 - Derived Earth Fault Settings
51N Protection: Enables / Disables Derived Earth Fault Protection Function.

51N Set Value: Sets the pick-up current level.
51N Curve: Selects the required time current characteristics
51N TMS: Sets the Time Multiplier Setting value
51N If2> Action: Enables/ Disables tripping after 2nd harmonic
51N Reset DT Delay: Sets the time for Reset DT Timer.
51N DT Delay: Sets the time after which tripping occurs. An output is enabled after this
time elapses.

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4.2.12 Instantaneous Derived Earth Fault Protection (50N)

(Io>>)
The instantaneous derived fault protection function for HV side can be enabled by
inactive. The following figure shows UI for Derived Earth-fault INST Settings which allows
the user to configure various settings. Also the default / previously set value & the setting
range for each setting is given.
Figure 167 - Instantaneous Derived Earth Fault Settings

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50N Protection: Enables / Disables Instantaneous Derived Earth Fault Protection

Function.
50N Set Value: Sets the pick-up current level.
50N DT: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
50N If2> Action: Enables/ Disables tripping after 2nd harmonic.
These values are same for the both windings and for all stages also. The BOs and LEDs
can be configured as given in subsection 4.2.3.1.

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4.2.13 Negative Sequence Over Current Protection (46) (I2>)
Negative phase sequence overcurrent protection includes definite time and IDMT
characteristics as per IEC and IEEE standards. Optionally two instantaneous over current
elements are provided; each can be selected to either winding 1 or winding 2. The negative
sequence over current protection function for HV side can be enabled by clicking Enable
after changing the auxiliary protection setting. At this point of time, LV protection is inactive.
Similarly, protection for LV side can be enabled by clicking on Enable after changing the
auxiliary protection setting. At this point of time, HV protection is inactive. The following
figure shows UI for Negative phase sequence overcurrent IDMT Settings which allows the
user to configure various settings. Also the default / previously set value & the setting range
for each setting is given.
Figure 168 - Negative Sequence IDMT Over Current Settings
46 Protection: Enables / Disables Negative Sequence Over Current Protection Function.

46 Curve: Selects the required time current characteristics
46 Reset DT Delay: Sets the time for Reset DT Timer.
time elapses.

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These values are same for the both windings and for the all stages also. The BOs and
4.2.14 Instantaneous Negative Sequence Over Current

Protection (46) (I2>>)
The instantaneous negative sequence over current protection function for HV side can
be enabled by clicking Enable after changing the auxiliary protection setting. At this point of
time, LV protection is inactive. Similarly, protection for LV side can be enabled by clicking
on Enable after changing the auxiliary protection setting. At this point of time, HV protection
is inactive. The following figure shows UI for Negative phase sequence overcurrent INST
Figure 169 - Instantaneous Negative Sequence Over Current Settings

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46 Protection: Enables / Disables Instantaneous Negative Sequence Over Current

Protection Function.
time elapses.

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4.2.15 Under Current Protection (37) (UC)
Two instantaneous under current elements are provided; each can be selected to either
winding 1 or winding 2. The under current protection function for HV side can be enabled by
inactive. The following figure shows UI for both stages of under current Settings which
Figure 170 - Under Current Settings

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37 Protection: Enables / Disables Under Current Protection Function.

elapses.
37 Iguard: Sets the minimum current guard below which the operation is undesirable.

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4.2.16 Over Voltage Protection (59) (OV)
Over voltage protection can be selected to either winding 1 or winding 2.This protection
includes both DT/IDMT characteristics. The following figure shows UI for over voltage
IDMT & INST Settings which allows the user to configure various settings. Also the default /
previously set value & the setting range for each setting is given.
Figure 171 - Over Voltage Settings
Stage -1 Settings (3U> - IDMT)
59 Protection: Enables / Disables Over Voltage Protection Function.

59 Set Value: Sets the pick-up voltage level.
59 Curve: Selects the required time characteristics
elapses.

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Stage -2 Settings (3U>> - Instantaneous / High set)
59HS Protection: Enables / Disables Instantaneous Over Voltage Protection Function.

59HS Set Value: Sets the pick-up voltage level.
59HS DT: Sets the time after which tripping occurs.
The BOs and LEDs can be configured as given in subsection 4.2.3.1.

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4.2.17 Under Voltage Protection (27) (UV)
Under voltage protection includes both DT/IDMT characteristics. The following figure
shows UI for under voltage IDMT & INST Settings which allows the user to configure
various settings. Also the default / previously set value & the setting range for each setting is
given.
Figure 172 - Under Voltage Settings
Stage -1 Settings (3U< - IDMT)
27 Protection: Enables / Disables Under Voltage Protection Function.

27 Set Value: Sets the pick-up voltage level.
27 Curve: Selects the required time characteristics
27 UV Guard: Sets the minimum voltage below which the operation is undesirable.
elapses.

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Stage -2 Settings (3U<< - Instantaneous / High set)
27HS Protection: Enables / Disables Instantaneous Under Voltage Protection Function.

27HS Set Value: Sets the pick-up voltage level.
27HS DT: Sets the time after which tripping occurs. An output is enabled after this time
elapses.

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4.2.18 NDR Protection (59)
The following figure shows UI for both IDMT & INST stages of NDR Settings which
Figure 173 - NDR Protection
Stage -1 Settings (NDR - IDMT)
59N Protection: Enables / Disables IDMT NDR Protection Function.

59N Set Value: Sets the pick-up voltage level.
59N Curve: Selects the required time characteristics
59N TMS: Sets the Time Multiplier Setting value
59N Reset DT: Sets the delay for Reset DT Timer.
elapses.

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Stage -2 Settings (NDR - Instantaneous / High set)
59N Protection: Enables / Disables INST NDR Protection Function.

59N Set Value: Sets the pick-up voltage level.
elapses.

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4.2.19 Over Frequency Protection (81) (OF)
The following figure shows UI for Over Frequency Settings which allows the user to
setting is given.
Figure 174 - Over Frequency Protection
81 Protection: Enables / Disables Over Frequency Protection Function.

81 Set Value: Sets the frequency.
elapses.
The permissible values are same for the all stages The BOs and LEDs can be configured

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4.2.20 Under Frequency Protection (81) (UF)
The following figure shows UI for Under Frequency Settings which allows the user to
setting is given.
Figure 175 - Under Frequency Protection
81 Protection: Enables / Disables Under Frequency Protection Function.

81 Set Value: Sets the frequency.
elapses.
81 Guard Set: Sets a guard voltage below which operation is undesirable.
The permissible values are same for the all stages The BOs and LEDs can be configured

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4.2.21 Supervision Setting (SUPR)
The supervision settings include three supervisory protection functions, viz. breaker
failure protection, trip circuit supervision and close circuit supervision.
4.2.21.1 Breaker Failure Protection (50 BF)
The following figure shows UI for both the stages of Breaker Failure Settings which
Figure 176 – Supervision Settings
50BF-1 Protection: Enables / Disables Breaker Failure protection

50BF-1 OC: Sets the pick-up current level for over current stage.
50BF-1 EF: Sets the pick-up current level for earth fault stage.
50BF-1 DT: Sets the time after which tripping occurs. An output is enabled after this
time elapses.
50BF Mode: Sets pick-up mode.
These values are same for both the stages. The BOs and LEDs can be configured as given in
subsection 4.2.3.1.

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4.2.21.2 Trip Circuit Supervision (TCS) & Close Circuit Supervison

(CCS)
The following figure shows UI for TTC & CCS Settings which allows the user to
setting is given.
Figure 177 - TCS / CCS Settings
TCS / CCS Protection: Enables / Disables TCS / CCS failure protection

DT: Sets the time after which tripping occurs. An output is enabled after this time
elapses.
LED: Indicates TCS or CCS
BO 1 & BO 2: Can be assigned for TCS / CCS purpose.

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4.2.22 Communication Settings
The relay can be configured for various communication protocol settings as like
MODBUS, IEC 103 & IEC 61850. To view / edit communication settings, click on the
Communication in the tree structure on left hand side of your screen. Figure shows UI for
the settings for various communication protocols.
4.2.22.1 MODBUS & IEC 103 Protocol
The settings for MODBUS & IEC 103 protocol are similar.
Figure 178 - IEC 103 & MODBUS Settings
Protocol: Selects the required communication protocol out of the available options on the
rear communications port.
Baud Rate: Controls the communication speed between relay and master. Both, the relay
and master station must be set to the same speed.
Parity: Controls the parity format used in the data frames. Both the relay and master
station must be set to the same parity.

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Relay Address: Sets the unique address for the relay so that only one relay is accessed by
master software.
Period: Defines the measurement period.
Scaling: Selects the scaling factor
Figure 179 - IEC 61850 Settings
Protocol: Selects the required communication protocol out of the available options on
the rear communications port.
Operation: Enables / Disables IEC 61850 Communication.
Timeout: Duration of time waited, after receiving a select command and awaiting an
operate confirmation from the master.
Pulse Length: Sets the time for which output must be ON.
Control Model: Selects the required control model
Reset Server: This setting is required for purposes only, and is to be performed only
when CID file of the device is updated from CGL IED 61850 Tool.

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Figure 180 - IEC 61850 IP Settings
Server IP: Displays the unique network IP address that identifies the relay.
Net Mask: Displays the sub-network the relay is connected to.
Primary SNTP Server: Displays the IP address of the primary SNTP server.
Secondary SNTP Server: Displays the IP address of the secondary SNTP server. This
server is used as a back-up server, in case the primary SNTP server fails. Priority is
always given to the primary SNTP server, if both servers are available.
Time Zone: Selects the time zone with respect to GMT.

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4.2.23 Binary Input & Binary Output Settings (BIBO)
The relay has multiple Binary inputs & Binary outputs. This configuration allows
programming or assigning any relay output for any fault Pick-up and trip condition. The relay
outputs can be configured on Digital Inputs. Also, protection on binary inputs (BI) and virtual
inputs (VI) can be enabled. Figure shows the various settings available in BIBO menu.
Figure 181 - BI / BO Settings Menu
4.2.23.1 Configuring External BIs to BOs
If a user wishes to configure an external BI to operate any BO, this function can be
used. Fig. shows a matrix which allows the user to map any BI to any BO. Selecting the
crosspoint and changing the value from OFF to ON ensures this assignment. In this case, BO
1 has been assigned to BI 1, BO 2 has been assigned to BI 2 and so on. After the assignment
is done, click on Write to save these settings. An acknowledgement window Write
Successful will appear on the screen.

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Figure 182 - Configuring External BI/BO

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4.2.23.2 Configuring External BIs to LEDs
LEDs can be assigned to indicate the status of external BIs. Fig. 3.22-6 shows the Ext
BI-LED Setting which allows the user to configure any BI to any of the available LEDs.
Clicking on the required BI setting & selecting the LED ensures this assignment. In this case,
LED 5 has been assigned to BI 1, LED 6 has been assigned for BI 2 and so on. After the
assignment is done, click on Write to save these settings. A acknowledge window Write
Successful will appear on the screen.
Figure 183 - Configuring External BI – LED Setting

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4.2.23.3 Self / Hand Reset
This setting gives the resetting status of LEDs and BOs, whether to be configured as
hand reset or self reset. Clicking on the required BO or LED & selecting either of the options
ensures this assignment. In this case, BO 1 & 2, & LED 6 & 7 have been configured to be
hand reset, & the rest of the LEDs & BOs have been configured to be self reset. To save these
changes, click on Write. An acknowledgement window Write Successful will appear on the
screen.
Figure 184 - Self / Hand Reset Setting

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4.2.23.4 Protection on BI
This menu is used to operate any protection function based on an active BI. The
operation of a protection function can be enabled or disabled for an active BI. If None is
selected, the protection function can be only enabled from the relay front end. Fig. 3.22-4
shows a matrix which allows the user to configure any protection function to any of the
available BIs. Clicking on the required protection function & selecting Enable / Disable /
None ensures this assignment. In this case, IDMT Non-directional Overcurrent Protection
will be enabled when BI 1 is active, INST Non-directional Overcurrent Protection will be
disabled when BI 2 is active, IDMT Directional Overcurrent Protection will be enabled when
BI 3 is active, & INST Directional Overcurrent Protection will be disabled when BI 4 is
active. After the assignment is done, click on Write to save these settings. An
acknowledgement window Write Successful will appear on the screen.

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Figure 185 - Protection on BI Settings

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4.2.23.5 Setting Group on BI
This menu enables the user to assign a BI to a particular Setting Group. This means that
the various protection settings defined in a Setting Group can be enabled, simply on the
activation of the assigned BI. Any of the available BIs can be assigned to any of the available
setting groups. In the figure shown below, BI 1, 2, 3, 4 have been assigned to Setting Groups
1, 2, 3 & 4 respectively. If None is selected, the setting group can be only selected from the
relay front end. After the assignment is done, click on Write to save these settings. A
acknowledge window Write Successful will appear on the screen.
Figure 186 - Setting Group on BI Settings

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4.2.23.6 Protection on VI (Applicable to IEC 61850 compatible IEDs

only)
Similar to Protection on BI menu, this menu is used to operate any protection function
based on an active VI. The operation of a protection function can be enabled or disabled for
an active VI. If None is selected, the protection function can be only enabled from the relay
front end. Fig. 3.22-4 shows a matrix which allows the user to configure any protection
function to any of the available VIs. Clicking on the crosspoint ensures this assignment. In
this case, IDMT Non-directional Overcurrent Protection will be enabled when VI 1 is active,
INST Non-directional Overcurrent Protection will be disabled when VI 2 is active, IDMT
Directional Overcurrent Protection will be enabled when VI 3 is active, & INST Directional
Overcurrent Protection will be disabled when VI 4 is active. After the assignment is done,
click on Write to save these settings. An acknowledgement window Write Successful will
appear on the screen.

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Figure 187 - Protection on VI Settings

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4.2.23.7 Setting Group on VI (Applicable to IEC 61850 compatible IEDs

only)
Similar to the Setting Group on BI menu, this menu enables the user to assign a VI to
a particular Setting Group. This means that the various protection settings defined in a Setting
Group can be enabled, simply on the activation of the assigned VI. Any of the available VIs
can be assigned to any of the available setting groups. In the figure shown below, VI 1, 2, 3, 4
have been assigned to Setting Groups 1, 2, 3 & 4 respectively. If None is selected, the setting
group can be only selected from the relay front end. After the assignment is done, click on
Write to save these settings. A acknowledge window Write Successful will appear on the
screen.
Figure 188 - Setting Group on VI

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4.2.23.8 Protection on General Inputs (GIs)
Similar to Protection on BI Setting, this setting is used to operate any protection

function based on an active GI. The operation of a protection function can be enabled or
disabled for an active GI. If None is selected, the protection function can be only enabled
from the relay front end. Fig. 3.22-4 shows a matrix which allows the user to configure any
protection function to any of the GIs. Clicking on the required protection function and
selecting Enable / Disable / None ensures this assignment. In this case, IDMT Non-
directional Overcurrent Protection will be enabled when GI 1 is active & INST Non-
directional Overcurrent Protection will be disabled when GI 2 is active. After the assignment
is done, click on Write to save these settings. An acknowledgement window Write
Successful will appear on the screen. Here, the user must note that the logic for operation of
these inputs is to be designed in the user programmable Logic in the ConAegis Relay
Figure 189 - Protection on GI Settings

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4.2.23.9 Setting Group on General Inputs (GIs)
Similar to the Setting Group on BI setting, this setting enables the user to assign a GI
Setting Group can be enabled, simply on the activation of the assigned GI. GI can be assigned
to any of the available setting groups. In the figure shown below, GI 1 has been assigned to
Setting Group 1. If None is selected, the setting group can be only selected from the relay
front end. After the assignment is done, click on Write to save these settings. A acknowledge
window Write Successful will appear on the screen.
Figure 190 – Setting Group on GI

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4.2.24 Write All
The user can write / read all the settings to / from the device using this menu. If the user
wants to read all the settings from the device, click on Read All.
Figure 191 - Read All Settings
The user can now save this file to the desired location. Click on Save icon in the Tool
Bar. Choose the desired location and click on Save.

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Figure 192 - Save the Setting File
To write all the previously configured settings at a single time, click on Write All.
The user can also download a previously saved setting file in the device from this menu.
To open this setting file from the desired location, click Open icon in the Toolbar. Route to
the desired path and click Open to open the settings file. The next step is to click Write All
to download this file to the device. The device is now configured according to the settings in
the saved file.

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Figure 193 - Opening the Settings file

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Figure 194 - Updating Settings from the file
If none of the settings are changed after the device is connected to the software, and still
the user clicks on Write All, the default values get loaded in the relay.

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4.3 LOGIC
This section guides the user on developing a customized programmable logic, which can
be later downloaded in the relay. This menu can be viewed by clicking on Logic in the tree
structure at the left of your screen. The developed logic can be implemented in the relay only
when the user makes the LOGIC: Enable in Configuration Settings of the relay.
4.3.1 Overview
The motive behind the development of user-programmable logic is to permit the user to
configure any particular protection function as per their need to suit a typical application.
This logic can be developed using programmable logic gates or combinational & sequential
circuits. Logic gates can be programmed to perform a wide assortment of different logic
functions and can accept number of inputs. Input to the gates may be combination of the
status of BI inputs, output of the protection elements, e.g. protection alarms and trip signals,
and the mapping of BI- BO status. Output to the logic gates may be the LEDs and / or the
output contacts. The following sections guide the user on developing new logic as per one‟s
requirement.
4.3.1.1 The User Interface
When the user clicks on Logic Tab, ConAEGIS reads the existing relay logic and loads
the Logic software.
Figure 195 - Reading Relay Logic

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Logic Blocks Toolbar Workspace Window Workspace Properties
Status Window Comments Outline Window

Figure 196 - Main Window for Logic
Figure shows the main window of Logic software, which is divided into following parts.
 Toolbar: Provides various file handling and management tools along with their shortcuts
used for interfacing with the relay.
 Logic Blocks: Includes all the programmable logic gates, timers, flip-flops, comparators
and the outputs i.e. the LEDs, BOs and VOs.
 Workspace Window: The window where logic is to be developed.
 Workspace Properties: Shows information about the relay which is being configured,
including the type, model number, serial number, and the protection functions it provides.
It gives information about the logic blocks used in the design. Also, it gives the
percentage of the available memory used.
 Status Window: Displays the operation being performed in the software currently and
keeps updating itself continuously.
 Comments: The user can describe the developed logic or make some comments
regarding current logic under development in this window.
 Outline Window: Shows the design as a whole. Useful when zooming and panning.

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4.3.2 Building Programmable Logic
This chapter gives guidelines in stepwise manner to create, configure, and download the
logic to the relay.
4.3.2.1 Creating a New Logic File
 Figure shows a snapshot of the toolbar. To create a new file, Click New in the File menu.
The Workspace Window appears on the screen. The user can also import a previously
compiled logic file by clicking on Import, and further changes can be done to the same
file.
 The Status Window displays the message Logic Uploaded Successfully.
Figure 197 - Creating a New Logic File

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4.3.2.2 Selecting the Relay Type
 The Logic software detects the connected relay, its type, and model number, and displays
the same in Workspace Properties.
 If user selects some other relay model, it is not possible to create a transferable file and
the following warning is displayed on the screen. Also, the Status Window comes up
with the required relay model to be selected.
Figure 198 - Selecting the Relay Type
4.3.2.3 Placing the Logic Gates / Circuits
Logic software provides all the basic gates (AND, OR, NOT), universal gates (NAND,
NOR), and exclusive gates (EX-OR, EX-NOR) with a capability of accepting any number of
inputs. The maximum number of gates that can be added to a design is 64. Along with the
gates, combinational & sequential circuits like timers, comparators & flip-flops with
numerous configurations can also added to the design. The user may select and place any of
the available gates / circuit from the Logic Blocks window.
 To place a gate, select the required gate from the window, and the click on Workspace
Window.

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Figure 199 - Placing a Gate
 Number of inputs to a gate can be selected and added from Gate Properties. This
window shows the name and type of the gate, the number of inputs added, and description
if the user wants to mention it.
 The inputs to any gate may be pickup or trip signals of protection functions, software
inputs, binary inputs (BIs), virtual inputs (VIs), common inputs, general inputs, or even
commands like Trip / Close / Reset LED Status. To configure the inputs, select the gate to
which inputs are to be added, mark a tick on the required inputs, and the inputs blocks
will get connected to the gate.
 Virtual input data is divided into two fields:
o VI D: Virtual Input Data: This field represents the actual data value of the virtual
input.
o VI Q: Virtual Input Quality: This field represents the quality of the data. If the
intended data is received, the VI quality is termed as Good. If the intended data is not
received due to any mal-operation (communication failure, supply issues or data
corruption due to internal relay failure), the VI quality is termed as Bad.
 The Status Window is also updated as each input is connected.

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Figure 200 - Connecting the Inputs
 A single input AND gate can also be configured which can be used as a buffer.
4.3.2.4 Placing the Connectors
 Figure shows a NOT gate placed below the AND gate. To Connect these two gates, place
the mouse cursor near the AND gate output to observe a highlighted green box.
 Click in the highlighted box and drag the connector link until you observe another
highlighted green box near the input of NOT gate. Release when the box is highlighted.
The connection is made.
Figure 201 - Placing the Connectors
4.3.2.5 Placing the Outputs
 Output from any gate may be LED indicators, binary outputs (BOs), or virtual outputs
(VOs). To configure the outputs, click on Outputs in Logic Gates window and select
LED / BO / VO. The number of LEDs and BOs are available as per the type and
configuration of the relay.

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 Details about the LED can be seen in Output Properties. The Status Window shows the
current status.
Figure 202 - Placing the Outputs (LED)
 Similarly, a BO can also be added and configured.
 The outputs can have multiple input connections.
Figure 203 - Placing the Outputs (LED & BO)

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4.3.2.6 Compiling and Transferring Logic to Relay
 After the logic has been developed, the user can compile it to verify the correctness of the
logic. Click Compile in the Build Menu.
 If the logic is error free, the message Compilation Successful appears in Status
Window.
Figure 204 - Compilation Successful
 In case of errors in the logic, a Warning symbol flashes in the Workspace Window. A
message Compilation Failed appears in Status Window, with the cause of the error.
Figure 205 - Compilation Failed
 If the logic is error free, click Compile and Transfer in the Build menu to transfer the
logic file to the relay.
 The logic is recompiled, and the Status Window gives the confirmation that the logic file
has been transferred to the relay.
 To minimize data burden, the transferable file only stores the information about logic
diagram (input – outputs, logic gates, connectors), and does not contain any data about
the comments and the placement of the design. So, it is advisable to save the logic file.

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Figure 206 - Transferring the Logic File
4.3.2.7 Other Functions

4.3.2.7.1 Saving the Logic
 To save the developed logic to the system, click Save in the toolbar.
 The logic file is saved with a .logic extension at the user defined path.
Figure 207 - Saving the Logic File

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4.3.2.7.2 Importing & Exporting the Logic
 The functions Import and Export in the File menu of the Toolbar operate similar to the
Open and Save functions respectively.
 When the user develops logic and clicks on Export, a Ready to Transfer file with .tlogic
extension is generated. As mentioned above, the file gets directly compiled and can be
transferred to the relay.
Figure 208 - Export the Logic File
 Clicking on Import opens the existing Ready to Transfer file with .tlogic extension.
Changes can be made in this file and then be transferred to the relay. Select the file to be
imported and click Open.
Figure 209 - Import the Logic File
4.3.2.7.3 Zoom & Pan Tools
 In case of larger designs it may not be easy to get a detailed view of all the logic blocks.
To serve this purpose, zooming and panning tools have been provided.
 Zoom in and Zoom out setting is available in Toolbar, and panning can be done by
pressing Ctrl + Shift and drag.
 The Outline Window shows the full view of the developed logic.

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Figure 210 - Outline Window
 To erase the existing logic in the relay, clear the Workspace Window, and Compile and
Transfer this empty logic to the relay. The relay logic will be erased.

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4.3.3 Logic Gates & Blocks
The Logic software provides all the logic gates some combinational and sequential
logic blocks like timers, flip - flops & comparators which are fully configurable. Any of these
blocks can be selected by the user from the Logic Blocks window. The following subsections
give a brief description about each of the blocks:
4.3.3.1 Logic Gates

4.3.3.1.1 AND Gate
AND gates are used to form combinational expressions with Boolean variables. The
output of AND gate will be true / logical „1‟ only when all the inputs to the gate are true /
logic „1‟.
Figure 211 - AND Gate
The AND gate can have any number of inputs, which can be configured from the Gate
Properties window as shown above. This window shows the number of inputs connected to
the gate & gives the available options which can be given to the gate as inputs. An AND gate
with a single input acts as a buffer. The window also shows the percentage of memory
consumed by the AND gate, which is 3.10%.
4.3.3.1.2 OR Gate
OR gates are used to form combinational expressions with Boolean variables. The
output of OR gate will be true / logical „1‟ when any of the inputs to the gate are true / logic
„1‟.
Figure 212 - OR Gate
The OR gate can have any number of inputs, which can be configured from the Gate
the gate & gives the available options which can be given to the gate as inputs. The window
also shows the percentage of memory consumed by the OR gate, which is 3.10%.

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4.3.3.1.3 NOT Gate
NOT gates are used to form combinational expressions with Boolean variables. NOT
inverts the input signal.
Figure 213 - NOT Gate
The NOT gate can single input, which can be configured from the Gate Properties
window as shown above. This window gives the available options which can be given to the
gate as inputs. The window also shows the percentage of memory consumed by the NOT
gate, which is 3.10%.
4.3.3.1.4 XOR Gate
Exclusive OR / XOR gates are special function gates used to form combinational
expressions with Boolean variables. The output of XOR gate will be true / logical „1‟ if the
input signals are different and false / logical „0‟, if they are equal.
Figure 214 - XOR Gate
The XOR gate can have any number of inputs, which can be configured from the Gate
also shows the percentage of memory consumed by the XOR gate, which is 3.10%.

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4.3.3.1.5 XNOR Gate
Exclusive NOR / XNOR are special function gates used to form combinational
expressions with Boolean variables. The XNOR gate is nothing but a inverted XOR gate. The
output of XNOR gate will be true / logical „1‟ if the input signals are same and false / logical
„0‟, if they are different.
Figure 215 - XNOR Gate
The XNOR gate can have any number of inputs, which can be configured from the
Gate Properties window as shown above. This window shows the number of inputs
connected to the gate & gives the available options which can be given to the gate as inputs.
The window also shows the percentage of memory consumed by the XNOR gate, which is
3.10%.
4.3.3.1.6 NAND Gate
The universal NAND gates are used to form combinational expressions with Boolean
variables. The NAND gate is nothing but an inverted AND gate. The output of NAND gate
will be false / logical „0‟ only when all the inputs to the gate are true / logic „1‟.
Figure 216 - NAND Gate
The NAND gate can have any number of inputs, which can be configured from the
Gate Properties window as shown above. This window shows the number of inputs
connected to the gate & gives the available options which can be given to the gate as inputs.
The window also shows the percentage of memory consumed by the NAND gate, which is
3.10%.

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4.3.3.1.7 NOR Gate
The universal NOR gates are used to form combinational expressions with Boolean
variables. The NOR gate is nothing but an inverted OR gate. The output of NOR gate will be
true / logical „1‟ only when all the inputs to the gate are false / logic „0‟.
Figure 217 - NOR Gate
The NOR gate can have any number of inputs, which can be configured from the Gate
also shows the percentage of memory consumed by the NOR gate, which is 3.10%.

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4.3.3.2 Timers
The Timer Block is used to perform operations of a certain logic which can be
connected as an input or output to it. Logic software provides 4 types of timers which can be
configured to work on positive or negative edge as explained below:
4.3.3.2.1 Pulse Timer
The pulse timer function has a settable pulse time. Once the input is activated, the
output is set for a specific time duration using the Time setting, ranging from 0 to 2000
seconds in the Timer Properties window. This window also gives the available options
which can be given to the timer as an input, & percentage of memory consumed by the timer,
which is 1.50%. The pulse timer can be a positive edge triggered timer or a negative edge
triggered timer.
Figure 218 - Pulse Timers
The following figure shows timing diagram for both, positive and negative edge
triggered pulse timers, where the behavior of the timer (OUT) for positive / rising edge (IN-
R) & negative / falling edge (IN-F) can be observed. A brief description of 4 possible
scenarios is given below:
dt = pulse delay time
Figure 219 - Timing Diagram for Pulse Timers

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Case-I: If the input signal picks up at time t0, the pulse timer output OUT will be triggered at
the same rising / falling edge. Once this input is activated, the output is set for a specific
duration t0 + dt using the Time setting (eg. 5s). Even if the input goes low before the set DT
(eg. 2s), the pulse timer output will drop out only after completion of time t0 + dt, which is
5s.
Case-II: If the input signal picks up at time t1, the pulse timer output OUT will be triggered
at the same rising / falling edge. Once this input is activated, the output is set for a specific
duration t1 + dt using the Time setting (eg. 5s). But even if this input is retriggered before
the set DT (eg. at 2s), the pulse timer output will drop out only after completion of time t1 +
dt, which is 5s. This means that it will only consider the first rising / falling edge & will not
follow any retriggering of the input.
Case-III: If the input signal picks up at time t2, the pulse timer output OUT will be triggered
duration t2+ dt using the Time setting (eg. 5s). If this input continues to remain active even
after completion of the set DT (eg. till 7s), the pulse timer output will follow the input signal
till the time it remains high & drops out when the input signal drops out, i.e. after 7s.
Case-IV: If the input signal picks up at time t3, the pulse timer output OUT will be triggered
duration t3 + dt using the Time setting (eg. 5s). If this input is retriggered and continues to
remain active even after completion of the set DT (eg. till 7s), the pulse timer output will
follow the input signal, irrespective of the retriggering till the time it remains high & will
drop out when the input signal drops out, i.e. after 7s.

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4.3.3.2.2 Fixed Pulse Timer
The fixed pulse timer function has a settable pulse time. Once the input is activated, the
output is set for fixed time duration, irrespective of validity of the input signal. This time can
be decided using the Time setting, ranging from 0 to 2000 seconds in the Timer Properties
window. The window also gives the available options which can be given to the timer as an
input, & percentage of memory consumed by the timer, which is 1.50%. The fixed pulse
timer can be a positive edge triggered timer or a negative edge triggered timer.
Figure 220 - Fixed Pulse Timers
triggered fixed pulse timers, where the behavior of the timer (OUT) for positive / rising edge
(IN-R) & negative / falling edge (IN-F) can be observed. A brief description of 3 possible
Figure 221 - Timing Diagram for Fixed Pulse Timers
Case-I: If the input signal picks up at time t0, the fixed pulse timer output OUT will be
triggered at the same rising / falling edge. Once this input is activated, the output is set for a
fixed duration t0 + dt using the Time setting (eg. 5s). Even if the input goes low before the
set DT (eg. 2s), the fixed pulse timer output will drop out only after completion of time t0 +
dt, which is 5s.
Case-II: If the input signal picks up at time t1, the fixed pulse timer output OUT will be
fixed duration t1 + dt using the Time setting (eg. 5s). But even if this input is retriggered
before the set DT (eg. at 2s), the fixed pulse timer output will drop out only after completion

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of time t1 + dt, which is 5s. This means that it will only consider the first rising / falling edge
& will not follow any retriggering of the input.
Case-III: If the input signal picks up at time t2, the fixed pulse timer output OUT will be
fixed duration t2+ dt using the Time setting (eg. 5s). If this input continues to remain active
even after completion of the set DT (eg. till 7s), the fixed pulse timer output will drop out
after completion of time t2 + dt, which is 5s.

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4.3.3.2.3 Pulse Retrigger Timer
The pulse retrigger timer function has a settable pulse time. Once the input is activated,
the output is set for specific time duration. A unique feature of this timer is that it calculates
the DT from the instance retriggered input signal. The output signal remains high for a
specific time duration using the Time setting, ranging from 0 to 2000 seconds in the Timer
Properties window. This window also gives the available options which can be given to the
timer as an input, & percentage of memory consumed by the timer, which is 1.50%. The
pulse retrigger timer can be a positive edge triggered timer or a negative edge triggered timer.
Figure 222 - Pulse Retrigger Timers
triggered pulse retrigger timers, where the behavior of the timer (OUT) for positive / rising
edge (IN-R) & negative / falling edge (IN-F) can be observed. A brief description of 4
possible scenarios is given below:
dt = pulse delay time

Figure 223 - Timing Diagram for Pulse Retrigger Timers
Case-I: If the input signal picks up at time t0, the pulse timer output OUT will be triggered at
the same rising / falling edge. Once this input is activated, the output is set for a specific
duration t0 + dt using the Time setting (eg. 5s). Even if the input goes low before the set DT
(eg. 2s), the pulse retrigger timer output will drop out only after completion of time t0 + dt,
which is 5s.
Case-II: If the input signal picks up at time t1, the pulse timer output OUT will be triggered
duration t1 + dt using the Time setting (eg. 5s). If this input is retriggered before the set DT

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(eg. at 2s), the pulse retrigger timer will calculate the DT from the instance when the input
has retriggered, i.e. 2s, & the output will drop out only after completion of time 2s + dt,
which is 7s.
Case-III: If the input signal picks up at time t2, the pulse timer output OUT will be triggered
duration t2+ dt using the Time setting (eg. 5s). If this input continues to remain active even
after completion of the set DT (eg. till 7s), the pulse timer output will follow the input signal
till the time it remains high & drops out when the input signal drops out, i.e. after 7s.
Case-IV: If the input signal picks up at time t3, the pulse timer output OUT will be triggered
duration t3 + dt using the Time setting (eg. 5s). If this input is retriggered (at t4), and
continues to remain active even after completion of the set DT t4 +dt (eg. till 7s), the pulse
timer output will follow the input signal, irrespective of the retriggering till the time it
remains high & will drop out when the input signal drops out, i.e. after 7s.

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4.3.3.2.4 Delay-On Timer
The delay-on timer function has a settable pulse time. Once the input is activated, the
output is set after a delay of specific duration using the Time setting, ranging from 0 to 2000
seconds in the Timer Properties window. This window also gives the available options
which can be given to the timer as an input, & percentage of memory consumed by the timer,
which is 1.50%. The pulse timer can be a positive edge triggered timer or a negative edge
triggered timer.
Figure 224 - Delay-On Timers
triggered delay-on timers, where the behavior of the timer (OUT) for positive / rising edge
(IN-R) & negative / falling edge (IN-F) can be observed. A brief description of 3 possible
Figure 225 - Timing Diagram for Delay-On Timers
Case-I: If the input signal picks up at time t0, the delay-on timer output OUT will be
triggered after a delay of specific duration t0 + dt defined in the Time setting (eg. after 4s).
Once the output is set, it follows the input, i.e. it stays high as long as input is high & drops
out as the input drops out at t1 (eg. after 5s).
Case-II: The delay-on timer output does not respond to any glitch in the input signal. During
the duration t2 to t3, the timer output signal will remain low.

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Case-III: If the input signal picks up at time t4, the delay-on timer output OUT will be
triggered after a delay of specific duration t0 + dt defined in the Time setting (eg. after 4s).
Once the output is set, it follows the input, i.e. it stays high as long as input is high & drops
out as the input drops out at t (eg. after 8s).

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4.3.3.3 Set – Reset Flip-flop
This block is a simple SR flip-flop with a memory that can be set or that can reset an
output from the S or R inputs, respectively. The status of output Q is stored in the nonvolatile
memory. The percentage of memory consumed by the SR Flip-flop is shown in the Properties
Window, which is 1.65%. Figure shows logic block and truth table of SR flip-flop.
S R Q
0 0 0 (Previous State)
0 1 0
1 0 1
1 1 1
Figure 226 - SR Flip-flop: Logic Block & Truth Table
The inputs to the flip-flop may be pickup or trip signals of protection functions,
software inputs, binary inputs (BIs), virtual inputs (VIs), common inputs or general inputs.
On selection of a input signal, a Select Input window pops up. Here the user has to select
whether to configure the input signal as a Set(S) input or Reset(R) input.
Figure 227 - Select Input

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4.3.3.4 Comparators
Comparator is a combinational logic block that takes two quantities as input &
determines whether one number is greater than, less than or equal to the other. Logic software
provides 4 types of comparator, wherein, two measured quantities can be compared with each
other, or a measured quantity can be compared with a predefined value. The percentage of
memory consumed by the comparator is shown in the Properties Window, which is 1.65%.
The types of comparators are:
 Less than (<) Comparator: This comparator takes two quantities and determines the
smallest of them.
Figure 228 - < / > Comparators
 Greater than (>) Comparator: This comparator takes two quantities and determines the
largest of them.
 Less than or Equal to (≤) Comparator: This comparator takes two quantities and
determines if the first quantity is less than or equal to the second quantity.
Figure 229 - ≤ / ≥ Comparators
 Greater than or Equal to (≥) Comparator: This comparator takes two quantities and
determines if the first quantity is greater than or equal to the second quantity.
When two measured quantities are to be compared using any comparator, select the
setting Input v/s Input from Comparator Properties. On selection of input quantity, a
Select Input window pops up. Here the user has to select whether to configure the input
quantity as input A or input B. In this case, inputs to the comparator may be current, voltage,
energy or power quantities which can be compared with each other. Output of any
comparator may be LED indicators, binary outputs (BOs), or virtual outputs (VOs). The
following example shows comparison of Current IL1 with Current IL2. When IL1< IL2, LED
5 will glow.

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Figure 230 - Input v/s Input Comparison
When a measured quantity is to be compared with a Set Value using any comparator,
select the setting Value v/s Input from Comparator Properties. On selection of input
quantity, a Select Input window pops up. Here the user has to select whether to configure the
input quantity as input A or input B. In this case, one input to the comparator may be current,
voltage, energy or power quantities which will be compared with other input Value, which
can be set as per user‟s requirement. Output of any comparator may be LED indicators,
binary outputs (BOs), or virtual outputs (VOs). The following example shows comparison of
Current IL1 with Value, which is defined to be 1A in this case. When IL1 > 1A, LED 5 will
glow.

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Figure 231 - Value v/s Input Comparison

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4.3.4 Generic Inputs
The inputs to any logic block maybe pickup & trip signals of various protection
functions, BIs, VIs or GIs. Along with these inputs, some generic inputs have been provided
which can also be assigned as input to the gates. The set of generic inputs contain 8 special
purpose inputs and 8 completely user configurable inputs. Figure 16 shows a combination of
all.
Figure 232 - Generic Inputs
The 8 special purpose inputs are:
 Error: Error Signal due to some internal relay operation failure.
 General Pickup: Pickup in any of the protection function.
 General Trip: Trip in any of the protection function.
 CSWI Close: The Close BO in the device operates when this is given from SCADA and
in further configured in Logic.
 CSWI Trip: The Trip BO in the device operates when this is given from SCADA and in
further configured in Logic.

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 LED Reset: Operates the LED on Hand Reset.
 Local Position: Sets the operation of circuit breaker as local.
 Remote Position: Sets the operation of circuit breaker as remote.
Along with these inputs, 8 fully user configurable generic inputs are also available. In
the above figure, all of the generic inputs have been shown, outputs to which, may be a LED
or BO as per the type of input.

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4.3.5 Output Commands
The Outputs section in the Logic Gates menu also provides with five commands
which operate similarly as the relay.
4.3.5.1 Reset Relay
This command operates similar to the Self / Hand Reset feature in the relay, and can be
assigned to any of the BOs. The BO can be reset from the Logic software on triggering of
any of the inputs (Protection pickups, BIs, VIs). The status of all the outputs operating on
Hand Reset will be reset when the assigned input will be triggered. The figure shows that the
relay will be reset when BI 1 is triggered.
Figure 233 - Reset Relay
4.3.5.2 Reset LED
This command operates similar to the Self / Hand Reset feature in the relay, and can be
assigned to any of the LEDs. In case of a protection function, if an LED operates on Hand
Reset in the relay, it can be also reset from the Logic software on triggering of any of the
inputs (Protection pickups, BIs, VIs). The status of all the output operating on Hand Reset
will be reset when the assigned input will be triggered. The figure shows that the LED will be
reset when BI 1 is triggered.
Figure 234 - Reset Status

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4.3.5.3 Trip
This command operates similar to the Trip key on the front end of the relay. When the
Trip key is pressed on the relay, its assigned BO operates. The same can be done from the
Logic software on triggering of any of the inputs (Protection pickups, BIs, VIs). The assigned
BO for the trip function operates when the assigned input will be triggered. The figure shows
that relay will be trip when BI 1 will be triggered.
Figure 235 - Trip Command
4.3.5.4 Close
This command operates similar to the Close key on the front end of the relay. When the
Close key is pressed on the relay, its assigned BO operates. The same can be done from the
Logic software on triggering of any of the inputs (Protection pickups, BIs, VIs). The assigned
BO for the Close function operates when the assigned input will be triggered. The figure
shows that relay contacts will close when BI 1 will be triggered.
Figure 236 - Close Command

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4.3.5.5 DR Trigger
This command operates similar to the DR Trip Trigger and DR Pickup Trigger
function in the relay. When the DR triggering is kept ON for a trip or pickup instance of a
protection function, Disturbance Records are obtained on occurrence of these events. The
same can be done from the Logic software on triggering of any of the inputs (Protection
pickups, BIs, VIs). The DR is obtained for when the assigned input is triggered. The figure
shows that Disturbance Records will be obtained when VI D 31 & VI D 37 will be triggered.
Figure 237 - DR Trigger Command
4.3.5.6 Protection on GI
of any protection function based on an active GI. The user has to select Yes in PROT ON GI
setting in the device, and develop logic for the same in Logic software. In the given example
in figure 171, BIs have been used as triggering inputs for activation of GI. Consider GI 1 is
assigned to enable over current protection in the device. So, if BI 4 or BI 5 is triggered,
overcurrent protection will be enabled based on GI1.
Figure 238 - Protection on GI Command

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4.3.5.7 Setting Group on GI
Similar to the Setting Group on BI setting, this setting enables the user to assign a GIs
Setting Group can be enabled, simply on the activation of the assigned GI. Any of the GIs
can be assigned to any setting group. The user has to select Yes in SET. GRP ON GI setting
in the device, and develop logic for the same in Logic software. In the given example in
figure 172, BIs have been used as triggering inputs for activation of GI. Consider GI 1 is
assigned to activate Setting Group 1 in the device. So, if BI 4 or BI 5 is triggered, Setting
Group 1 will be the active group in the device based on GI1.
Figure 239 - Setting Group on GI Command

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4.4 GRAPHS
This chapter gives guidelines for downloading the disturbance records, which can be
further useful for fault analysis. This menu can be viewed by clicking on Graphs in the tree
structure at the left of your screen.
4.4.1 Downloading the Disturbance Records
The user can download & save the disturbance records from ConAegis Relay
Communication Software and plot the downloaded disturbance records in standard Comtrade
Player (Transwin). To download the records, the following procedure is to be followed:
Click on Disturbance Record in the tree structure at the left of your screen. Choose the
number of records to be downloaded and click Download DR.
Figure 240 - DR Menu
Figure 241 - Downloading the Disturbance Records
After the downloading is completed, the generated file can be saved by the user in
standard COMTRADE file format at the desired location.

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Figure 242 - Saving the DR file

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4.5 MEASUREMENTS
This chapter provides the details about various analog inputs injected in the relay. The
measured values can be viewed by clicking on Measurements in the tree structure at the left
of your screen. Measurements section displays three submenus, Current & Voltage, Power
& Date & Time.
4.5.1 Current Measurement
This menu displays measured values of Primary & Secondary, Phase & Earth currents,
Differential & Average currents in real-time. It also displays Measured ICT Currents &
Harmonic currents (2nd, 4th & 5th). To update the measured values, the user can click on Scan
Current Measurements.
Figure 243 - Current Measurements

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4.5.2 Voltage Measurement
This menu displays the measured Primary & Secondary voltages, To update the
measured values, the user can click on Scan Voltage Measurements.
Figure 244 - Voltage Measurements

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4.6 STATUS
This menu represents the status of all the protection functions if they have been enabled
or disabled in the device. Also the status of all the binary inputs and outputs is shown whether
they are ON or OFF. This status can be viewed by clicking on Status in the tree structure at
the left of your screen.
Figure 245 - Status Menu

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4.7 REPORTS
This chapter helps the user to know about tracking the fault records and event records,
which can be further useful for fault analysis. These records can be viewed by clicking on
Reports in the tree structure at the left of your screen.
4.7.1 Fault Records
Aegis Feeder Protection Relay stores the latest 10 faults occurred in the system. From
the figure, it can be seen that the fault record displays the trip count, type of the fault
occurred, various measured quantities in all the phases at the time of fault, & the date and
time at which fault has occurred. Click on Fault Records to observe the latest 10 faults.
The fault record can be cleared by clicking on Clear Record. The user must note that
clearing the fault record will also clear the event records.

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Figure 246 - Fault Records

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4.7.2 Event Records
Aegis Transformer Protection Relay stores the latest 500 events occurred in the system.
These events include occurrence of a fault, or change in the relay settings. The user may
download the event records ranging from 1 to 500. Click on Event Record to observe the
latest 500 events. The user may select the number of event records he wishes to download,
out of the events registered until that instant (eg. 4 in this case), and then click Download
Events.
Figure 247 - Event Records
The events records display the event number, the frame type, which is distinctive for
occurrence of an event (ASDU 1) and occurrence of a fault (ASDU 2), information related to
faults, the fault number, and the time at which fault has occurred.

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APPENDIX A – IDMT CURVES
Various characteristics IEC Curves for the Over Current protection as shown in below figure:
IEC - Very Inverse-time characteristic IEC- Standard Inverse-time characteristic
Figure 248 - IEC VI & SI Curves Characteristics

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IEC - Extremely Inverse-time characteristic IEC - Long Time Inverse-time characteristic
Figure 249 - IEC EI & LTI Curves Characteristics

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Various characteristics IEEE Curves for the Over Current protection as shown in below
figure:
Figure 250 - IEEE EI, MI & VI Curves Characteristics

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IEEE – Standard Inverse-time characteristic IAC – SI3, EI & VI Curve Characteristics
Figure 251 - IEEE SI Curve & IAC Curve Characteristics

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Appendix B – Curves in IEC 61850 Logical Nodes

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Value in IEC
61850 Logical Curve Characteristic Equation
Nodes
ANSI Extremely
1
Inverse
2 ANSI Very Inverse
3 ANSI Normal Inverse
ANSI Moderately
4
Inverse
5 ANSI Definite Time

Long Time Extremely
6
Inverse
Long Time Very
7
Inverse
8 Long Time Inverse
IEC Normal Inverse
9
(SI1)
10 IEC Very Inverse (VI)
11 IEC Inverse
12 IEC Extremely Inverse
IEC Short-Time
13
Inverse (SI3)
IEC Long-Time
14
Inverse
15 IEC Definite Time

16 Reserved

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33 Curve 1 (OV & NDR)
37 Curve 1 (UV)
38 Curve 2 (UV)
39 IAC Extremely Inverse
40 IAC Very Inverse
IAC Short-Time
41
Inverse (SI3)
42 RD
43 RI
44 IEEE Very Inverse
IEEE Extremely
45
Inverse
IEEE Short-Time
46
Inverse (SI3)

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47 Curve 1 (OF)(24)
Appendix C –Data Attributes in IEC 61850 Logical Nodes

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Sr. No. Function Logical Node IEC 61850 Name Attribute Type FC
1 A24H1PVPH1 A24H1PVPH1$ST$Beh$stVal BOOLEAN ST

2 A24H1PVPH1 A24H1PVPH1$ST$Beh$q Quality ST
3 A24H1PVPH1 A24H1PVPH1$ST$Beh$t TimeStamp ST
4 A24H1PVPH1 A24H1PVPH1$ST$Str$general BOOLEAN ST
5 A24H1PVPH1 A24H1PVPH1$ST$Str$dirGeneral Enum ST
6 A24H1PVPH1 A24H1PVPH1$ST$Str$q Quality ST
7 A24H1PVPH1 A24H1PVPH1$ST$Str$t TimeStamp ST
8 A24H1PVPH1 A24H1PVPH1$ST$Op$general BOOLEAN ST
9 A24H1PVPH1 A24H1PVPH1$ST$Op$q Quality ST
Over Fluxing Stage1
10 A24H1PVPH1 A24H1PVPH1$ST$Op$t TimeStamp ST

11 A24H1PVPH1 A24H1PVPH1$CF$Mod$ctlModel CtlModels CF
12 A24H1PVPH1 A24H1PVPH1$CF$OpDlTmms$minVal INT32 CF
13 A24H1PVPH1 A24H1PVPH1$CF$OpDlTmms$maxVal INT32 CF
14 A24H1PVPH1 A24H1PVPH1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
15 A24H1PVPH1 A24H1PVPH1$DC$NamPlt$vendor DC
STRING255
VISIBLE
16 A24H1PVPH1 A24H1PVPH1$DC$NamPlt$swRev DC
STRING255
VISIBLE
17 A24H1PVPH1 A24H1PVPH1$DC$NamPlt$d DC
STRING255
VISIBLE
18 A24H1PVPH1 A24H1PVPH1$DC$Str$d DC
STRING255
VISIBLE
19 A24H1PVPH1 A24H1PVPH1$DC$Op$d DC
STRING255
20 A24H1PVPH1 A24H1PVPH1$SP$VHzCrv$setCharact Enum SP
21 A24H1PVPH1 A24H1PVPH1$SP$OpDlTmms$setVal BOOLEAN SP
Fluxing
Stage2
22 A24H2PVPH1 A24H2PVPH1$ST$Beh$stVal BOOLEAN ST

Over
23 A24H2PVPH1 A24H2PVPH1$ST$Beh$q Quality ST

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24 A24H2PVPH1 A24H2PVPH1$ST$Beh$t TimeStamp ST

25 A24H2PVPH1 A24H2PVPH1$ST$Str$general BOOLEAN ST
26 A24H2PVPH1 A24H2PVPH1$ST$Str$dirGeneral Enum ST
27 A24H2PVPH1 A24H2PVPH1$ST$Str$q Quality ST
28 A24H2PVPH1 A24H2PVPH1$ST$Str$t TimeStamp ST
29 A24H2PVPH1 A24H2PVPH1$ST$Op$general BOOLEAN ST
30 A24H2PVPH1 A24H2PVPH1$ST$Op$q Quality ST
31 A24H2PVPH1 A24H2PVPH1$ST$Op$t TimeStamp ST
32 A24H2PVPH1 A24H2PVPH1$CF$Mod$ctlModel CtlModels CF
33 A24H2PVPH1 A24H2PVPH1$CF$OpDlTmms$minVal INT32 CF
34 A24H2PVPH1 A24H2PVPH1$CF$OpDlTmms$maxVal INT32 CF
35 A24H2PVPH1 A24H2PVPH1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
36 A24H2PVPH1 A24H2PVPH1$DC$NamPlt$vendor DC
STRING255
VISIBLE
37 A24H2PVPH1 A24H2PVPH1$DC$NamPlt$swRev DC
STRING255
VISIBLE
38 A24H2PVPH1 A24H2PVPH1$DC$NamPlt$d DC
STRING255
VISIBLE
39 A24H2PVPH1 A24H2PVPH1$DC$Str$d DC
STRING255
VISIBLE
40 A24H2PVPH1 A24H2PVPH1$DC$Op$d DC
STRING255
41 A24H2PVPH1 A24H2PVPH1$SP$VHzCrv$setCharact Enum SP
42 A24H2PVPH1 A24H2PVPH1$SP$OpDlTmms$setVal BOOLEAN SP
43 A27_PTUV1 A27_PTUV1$ST$Beh$stVal BOOLEAN ST
Under Voltage Stage1
44 A27_PTUV1 A27_PTUV1$ST$Beh$q Quality ST

45 A27_PTUV1 A27_PTUV1$ST$Beh$t TimeStamp ST
46 A27_PTUV1 A27_PTUV1$ST$Str$general BOOLEAN ST
47 A27_PTUV1 A27_PTUV1$ST$Str$dirGeneral Enum ST
48 A27_PTUV1 A27_PTUV1$ST$Str$q Quality ST

`
49 A27_PTUV1 A27_PTUV1$ST$Str$t TimeStamp ST

50 A27_PTUV1 A27_PTUV1$ST$Op$general BOOLEAN CF
51 A27_PTUV1 A27_PTUV1$ST$Op$q Quality CF
52 A27_PTUV1 A27_PTUV1$ST$Op$t TimeStamp CF
53 A27_PTUV1 A27_PTUV1$CF$Mod$ctlModel CtlModels CF
54 A27_PTUV1 A27_PTUV1$CF$OpDlTmms$minVal INT32 CF
55 A27_PTUV1 A27_PTUV1$CF$OpDlTmms$maxVal INT32 CF
56 A27_PTUV1 A27_PTUV1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
57 A27_PTUV1 A27_PTUV1$DC$NamPlt$vendor DC
STRING255
VISIBLE
58 A27_PTUV1 A27_PTUV1$DC$NamPlt$swRev DC
STRING255
VISIBLE
59 A27_PTUV1 A27_PTUV1$DC$NamPlt$d DC
STRING255
VISIBLE
60 A27_PTUV1 A27_PTUV1$DC$Str$d DC
STRING255
VISIBLE
61 A27_PTUV1 A27_PTUV1$DC$Op$d DC
STRING255
62 A27_PTUV1 A27_PTUV1$SP$TmVCrv$setCharact Enum SP
63 A27_PTUV1 A27_PTUV1$SP$OpDlTmms$setVal BOOLEAN SP
64 A27_PTUV2 A27_PTUV2$ST$Beh$stVal BOOLEAN ST
65 A27_PTUV2 A27_PTUV2$ST$Beh$q Quality ST
66 A27_PTUV2 A27_PTUV2$ST$Beh$t TimeStamp ST
Under Voltage Stage2
67 A27_PTUV2 A27_PTUV2$ST$Str$general BOOLEAN ST

68 A27_PTUV2 A27_PTUV2$ST$Str$dirGeneral Enum ST
69 A27_PTUV2 A27_PTUV2$ST$Str$q Quality ST
70 A27_PTUV2 A27_PTUV2$ST$Str$t TimeStamp ST
71 A27_PTUV2 A27_PTUV2$ST$Op$general BOOLEAN ST
72 A27_PTUV2 A27_PTUV2$ST$Op$q Quality ST
73 A27_PTUV2 A27_PTUV2$ST$Op$t TimeStamp ST

`
74 A27_PTUV2 A27_PTUV2$CF$Mod$ctlModel CtlModels CF

75 A27_PTUV2 A27_PTUV2$CF$OpDlTmms$minVal INT32 CF
76 A27_PTUV2 A27_PTUV2$CF$OpDlTmms$maxVal INT32 CF
77 A27_PTUV2 A27_PTUV2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
78 A27_PTUV2 A27_PTUV2$DC$NamPlt$vendor DC
STRING255
VISIBLE
79 A27_PTUV2 A27_PTUV2$DC$NamPlt$swRev DC
STRING255
VISIBLE
80 A27_PTUV2 A27_PTUV2$DC$NamPlt$d DC
STRING255
VISIBLE
81 A27_PTUV2 A27_PTUV2$DC$Str$d DC
STRING255
VISIBLE
82 A27_PTUV2 A27_PTUV2$DC$Op$d DC
STRING255
83 A27_PTUV2 A27_PTUV2$SP$OpDlTmms$setVal BOOLEAN SP
84 A37H1PTUC1 A37H1PTUC1$ST$Beh$stVal BOOLEAN ST
85 A37H1PTUC1 A37H1PTUC1$ST$Beh$q Quality ST
86 A37H1PTUC1 A37H1PTUC1$ST$Beh$t TimeStamp ST
87 A37H1PTUC1 A37H1PTUC1$ST$Str$general BOOLEAN ST
88 A37H1PTUC1 A37H1PTUC1$ST$Str$dirGeneral Enum ST
Under Current HV Stage1
89 A37H1PTUC1 A37H1PTUC1$ST$Str$phsA BOOLEAN ST

90 A37H1PTUC1 A37H1PTUC1$ST$Str$dirPhsA Enum ST
91 A37H1PTUC1 A37H1PTUC1$ST$Str$phsB BOOLEAN ST
92 A37H1PTUC1 A37H1PTUC1$ST$Str$dirPhsB Enum ST
93 A37H1PTUC1 A37H1PTUC1$ST$Str$phsC BOOLEAN ST
94 A37H1PTUC1 A37H1PTUC1$ST$Str$dirPhsC Enum ST
95 A37H1PTUC1 A37H1PTUC1$ST$Str$q Quality ST
96 A37H1PTUC1 A37H1PTUC1$ST$Str$t TimeStamp ST
97 A37H1PTUC1 A37H1PTUC1$ST$Op$general BOOLEAN ST
98 A37H1PTUC1 A37H1PTUC1$ST$Op$phsA BOOLEAN ST

`
99 A37H1PTUC1 A37H1PTUC1$ST$Op$phsB BOOLEAN ST

100 A37H1PTUC1 A37H1PTUC1$ST$Op$phsC BOOLEAN ST
101 A37H1PTUC1 A37H1PTUC1$ST$Op$q Quality ST
102 A37H1PTUC1 A37H1PTUC1$ST$Op$t TimeStamp ST
103 A37H1PTUC1 A37H1PTUC1$CF$Mod$ctlModel CtlModels CF
104 A37H1PTUC1 A37H1PTUC1$CF$OpDlTmms$minVal INT32 CF
105 A37H1PTUC1 A37H1PTUC1$CF$OpDlTmms$maxVal INT32 CF
106 A37H1PTUC1 A37H1PTUC1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
107 A37H1PTUC1 A37H1PTUC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
108 A37H1PTUC1 A37H1PTUC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
109 A37H1PTUC1 A37H1PTUC1$DC$NamPlt$d DC
STRING255
VISIBLE
110 A37H1PTUC1 A37H1PTUC1$DC$Str$d DC
STRING255
VISIBLE
111 A37H1PTUC1 A37H1PTUC1$DC$Op$d DC
STRING255
112 A37H1PTUC1 A37H1PTUC1$SP$OpDlTmms$setVal BOOLEAN SP
113 A37H2PTUC1 A37H2PTUC1$ST$Beh$stVal BOOLEAN ST
114 A37H2PTUC1 A37H2PTUC1$ST$Beh$q Quality ST
115 A37H2PTUC1 A37H2PTUC1$ST$Beh$t TimeStamp ST
Under Current HV Stage2
116 A37H2PTUC1 A37H2PTUC1$ST$Str$general BOOLEAN ST

117 A37H2PTUC1 A37H2PTUC1$ST$Str$dirGeneral Enum ST
118 A37H2PTUC1 A37H2PTUC1$ST$Str$phsA BOOLEAN ST
119 A37H2PTUC1 A37H2PTUC1$ST$Str$dirPhsA Enum CF
120 A37H2PTUC1 A37H2PTUC1$ST$Str$phsB BOOLEAN CF
121 A37H2PTUC1 A37H2PTUC1$ST$Str$dirPhsB Enum CF
122 A37H2PTUC1 A37H2PTUC1$ST$Str$phsC BOOLEAN CF
123 A37H2PTUC1 A37H2PTUC1$ST$Str$dirPhsC Enum CF

`
124 A37H2PTUC1 A37H2PTUC1$ST$Str$q Quality CF

125 A37H2PTUC1 A37H2PTUC1$ST$Str$t TimeStamp CF
126 A37H2PTUC1 A37H2PTUC1$ST$Op$general BOOLEAN DC
127 A37H2PTUC1 A37H2PTUC1$ST$Op$phsA BOOLEAN DC
128 A37H2PTUC1 A37H2PTUC1$ST$Op$phsB BOOLEAN DC
129 A37H2PTUC1 A37H2PTUC1$ST$Op$phsC BOOLEAN DC
130 A37H2PTUC1 A37H2PTUC1$ST$Op$q Quality DC
131 A37H2PTUC1 A37H2PTUC1$ST$Op$t TimeStamp DC
132 A37H2PTUC1 A37H2PTUC1$CF$Mod$ctlModel CtlModels SP
133 A37H2PTUC1 A37H2PTUC1$CF$OpDlTmms$minVal INT32 SP
134 A37H2PTUC1 A37H2PTUC1$CF$OpDlTmms$maxVal INT32 SP
135 A37H2PTUC1 A37H2PTUC1$CF$OpDlTmms$stepSize INT32U ST
VISIBLE
136 A37H2PTUC1 A37H2PTUC1$DC$NamPlt$vendor ST
STRING255
VISIBLE
137 A37H2PTUC1 A37H2PTUC1$DC$NamPlt$swRev ST
STRING255
VISIBLE
138 A37H2PTUC1 A37H2PTUC1$DC$NamPlt$d ST
STRING255
VISIBLE
139 A37H2PTUC1 A37H2PTUC1$DC$Str$d ST
STRING255
VISIBLE
140 A37H2PTUC1 A37H2PTUC1$DC$Op$d ST
STRING255
141 A37H2PTUC1 A37H2PTUC1$SP$OpDlTmms$setVal BOOLEAN SP
142 A37L1PTUC1 A37L1PTUC1$ST$Beh$stVal BOOLEAN ST
Under Current LV Stage1
143 A37L1PTUC1 A37L1PTUC1$ST$Beh$q Quality ST

144 A37L1PTUC1 A37L1PTUC1$ST$Beh$t TimeStamp ST
145 A37L1PTUC1 A37L1PTUC1$ST$Str$general BOOLEAN ST
146 A37L1PTUC1 A37L1PTUC1$ST$Str$dirGeneral Enum ST
147 A37L1PTUC1 A37L1PTUC1$ST$Str$phsA BOOLEAN ST
148 A37L1PTUC1 A37L1PTUC1$ST$Str$dirPhsA Enum ST

`
149 A37L1PTUC1 A37L1PTUC1$ST$Str$phsB BOOLEAN ST

150 A37L1PTUC1 A37L1PTUC1$ST$Str$dirPhsB Enum ST
151 A37L1PTUC1 A37L1PTUC1$ST$Str$phsC BOOLEAN ST
152 A37L1PTUC1 A37L1PTUC1$ST$Str$dirPhsC Enum ST
153 A37L1PTUC1 A37L1PTUC1$ST$Str$q Quality ST
154 A37L1PTUC1 A37L1PTUC1$ST$Str$t TimeStamp ST
155 A37L1PTUC1 A37L1PTUC1$ST$Op$general BOOLEAN ST
156 A37L1PTUC1 A37L1PTUC1$ST$Op$phsA BOOLEAN ST
157 A37L1PTUC1 A37L1PTUC1$ST$Op$phsB BOOLEAN ST
158 A37L1PTUC1 A37L1PTUC1$ST$Op$phsC BOOLEAN ST
159 A37L1PTUC1 A37L1PTUC1$ST$Op$q Quality ST
160 A37L1PTUC1 A37L1PTUC1$ST$Op$t TimeStamp ST
161 A37L1PTUC1 A37L1PTUC1$CF$Mod$ctlModel CtlModels CF
162 A37L1PTUC1 A37L1PTUC1$CF$OpDlTmms$minVal INT32 CF
163 A37L1PTUC1 A37L1PTUC1$CF$OpDlTmms$maxVal INT32 CF
164 A37L1PTUC1 A37L1PTUC1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
165 A37L1PTUC1 A37L1PTUC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
166 A37L1PTUC1 A37L1PTUC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
167 A37L1PTUC1 A37L1PTUC1$DC$NamPlt$d DC
STRING255
VISIBLE
168 A37L1PTUC1 A37L1PTUC1$DC$Str$d DC
STRING255
VISIBLE
169 A37L1PTUC1 A37L1PTUC1$DC$Op$d DC
STRING255
170 A37L1PTUC1 A37L1PTUC1$SP$OpDlTmms$setVal BOOLEAN SP
171 A37L1PTUC1 A37L2PTUC1$ST$Beh$stVal BOOLEAN ST

`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
Unde
rCur
Stag
VISIBLE
rent
LV
e2

STRING255

`

A37L2PTUC1 A37L2PTUC1$ST$Beh$stVal BOOLEAN ST
VISIBLE
STRING255
VISIBLE
STRING255

`
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
228 A46SH1PTOC2 A46SH1PTOC2$ST$Beh$q Quality ST
229 A46SH1PTOC2 A46SH1PTOC2$ST$Beh$t TimeStamp ST
230 A46SH1PTOC2 A46SH1PTOC2$ST$Str$general BOOLEAN ST
231 A46SH1PTOC2 A46SH1PTOC2$ST$Str$dirGeneral Enum ST
232 A46SH1PTOC2 A46SH1PTOC2$ST$Str$q Quality ST
233 A46SH1PTOC2 A46SH1PTOC2$ST$Str$t TimeStamp ST
234 A46SH1PTOC2 A46SH1PTOC2$ST$Op$general BOOLEAN ST
235 A46SH1PTOC2 A46SH1PTOC2$ST$Op$q Quality ST
NPS IDMT HV Stage1
236 A46SH1PTOC2 A46SH1PTOC2$ST$Op$t TimeStamp ST

237 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$ctlVal CO
238 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$origin$orCat Enum CO
239 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
240 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$ctlNum INT8U CO
241 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$T 6 CO
242 A46SH1PTOC2 A46SH1PTOC2$CO$Mod$Cancel$Test BOOLEAN CO
243 A46SH1PTOC2 A46SH1PTOC2$CF$Mod$ctlModel CtlModels CF
244 A46SH1PTOC2 A46SH1PTOC2$CF$OpDlTmms$minVal INT32 CF
245 A46SH1PTOC2 A46SH1PTOC2$CF$OpDlTmms$maxVal INT32 CF
246 A46SH1PTOC2 A46SH1PTOC2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
247 A46SH1PTOC2 A46SH1PTOC2$DC$NamPlt$vendor DC
STRING255
VISIBLE
248 A46SH1PTOC2 A46SH1PTOC2$DC$NamPlt$swRev DC
STRING255

`
VISIBLE
249 A46SH1PTOC2 A46SH1PTOC2$DC$NamPlt$d DC
STRING255
VISIBLE
250 A46SH1PTOC2 A46SH1PTOC2$DC$Str$d DC
STRING255
VISIBLE
251 A46SH1PTOC2 A46SH1PTOC2$DC$Op$d DC
STRING255
252 A46SH1PTOC2 A46SH1PTOC2$SP$OpDlTmms$setVal Enum SP
253 A46SH2PTOC1 A46SH2PTOC1$ST$Beh$stVal BOOLEAN ST
254 A46SH2PTOC1 A46SH2PTOC1$ST$Beh$q BOOLEAN ST
255 A46SH2PTOC1 A46SH2PTOC1$ST$Beh$t Quality ST
256 A46SH2PTOC1 A46SH2PTOC1$ST$Str$general TimeStamp ST
257 A46SH2PTOC1 A46SH2PTOC1$ST$Str$dirGeneral BOOLEAN ST
258 A46SH2PTOC1 A46SH2PTOC1$ST$Str$q Enum ST
259 A46SH2PTOC1 A46SH2PTOC1$ST$Str$t Quality ST
260 A46SH2PTOC1 A46SH2PTOC1$ST$Op$general TimeStamp ST
261 A46SH2PTOC1 A46SH2PTOC1$ST$Op$q BOOLEAN ST
NPS IDMT HV Stage2
262 A46SH2PTOC1 A46SH2PTOC1$ST$Op$t Quality ST

263 A46SH2PTOC1 A46SH2PTOC1$CO$Mod$Cancel$ctlVal TimeStamp CO
VISIBLE
STRING255
274 A46SH2PTOC1 A46SH2PTOC1$DC$NamPlt$swRev VISIBLE DC

`
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
278 A46SH2PTOC1 A46SH2PTOC1$SP$TmACrv$setCharact Enum SP
279 A46SH2PTOC1 A46SH2PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
280 A46SH2PTOC2 A46SH2PTOC2$ST$Beh$stVal BOOLEAN ST
281 A46SH2PTOC2 A46SH2PTOC2$ST$Beh$q Quality ST
282 A46SH2PTOC2 A46SH2PTOC2$ST$Beh$t TimeStamp ST
283 A46SH2PTOC2 A46SH2PTOC2$ST$Str$general BOOLEAN ST
284 A46SH2PTOC2 A46SH2PTOC2$ST$Str$dirGeneral Enum ST
285 A46SH2PTOC2 A46SH2PTOC2$ST$Str$q Quality ST
286 A46SH2PTOC2 A46SH2PTOC2$ST$Str$t TimeStamp ST
287 A46SH2PTOC2 A46SH2PTOC2$ST$Op$general BOOLEAN ST
288 A46SH2PTOC2 A46SH2PTOC2$ST$Op$q Quality ST
289 A46SH2PTOC2 A46SH2PTOC2$ST$Op$t TimeStamp ST
290 A46SH2PTOC2 A46SH2PTOC2$CO$Mod$Cancel$ctlVal CO

`
VISIBLE
STRING255
VISIBLE
301 A46SH2PTOC2 A46SH2PTOC2$DC$NamPlt$swRev DC
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
305 A46SH2PTOC2 A46SH2PTOC2$SP$OpDlTmms$setVal BOOLEAN SP
306 A46SL1PTOC1 A46SL1PTOC1$ST$Beh$stVal BOOLEAN ST
307 A46SL1PTOC1 A46SL1PTOC1$ST$Beh$q Quality ST
308 A46SL1PTOC1 A46SL1PTOC1$ST$Beh$t TimeStamp ST
309 A46SL1PTOC1 A46SL1PTOC1$ST$Str$general BOOLEAN ST
310 A46SL1PTOC1 A46SL1PTOC1$ST$Str$dirGeneral Enum ST
311 A46SL1PTOC1 A46SL1PTOC1$ST$Str$q Quality ST
312 A46SL1PTOC1 A46SL1PTOC1$ST$Str$t TimeStamp ST
NPS IDMT LV Stage1
313 A46SL1PTOC1 A46SL1PTOC1$ST$Op$general BOOLEAN ST

314 A46SL1PTOC1 A46SL1PTOC1$ST$Op$q Quality ST
315 A46SL1PTOC1 A46SL1PTOC1$ST$Op$t TimeStamp ST
316 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$ctlVal Enum CO
317 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
318 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
319 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
320 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$T 6 CO
321 A46SL1PTOC1 A46SL1PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
322 A46SL1PTOC1 A46SL1PTOC1$CF$Mod$ctlModel CtlModels CF
323 A46SL1PTOC1 A46SL1PTOC1$CF$OpDlTmms$minVal INT32 CF
324 A46SL1PTOC1 A46SL1PTOC1$CF$OpDlTmms$maxVal INT32 CF

`
325 A46SL1PTOC1 A46SL1PTOC1$CF$OpDlTmms$stepSize INT32U CF

VISIBLE
326 A46SL1PTOC1 A46SL1PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
327 A46SL1PTOC1 A46SL1PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
328 A46SL1PTOC1 A46SL1PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
329 A46SL1PTOC1 A46SL1PTOC1$DC$Str$d DC
STRING255
VISIBLE
330 A46SL1PTOC1 A46SL1PTOC1$DC$Op$d DC
STRING255
331 A46SL1PTOC1 A46SL1PTOC1$SP$TmACrv$setCharact Enum SP
332 A46SL1PTOC1 A46SL1PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
NPS INST LV Stage1

343 A46SL1PTOC2 A46SL1PTOC2$CO$Mod$Cancel$ctlVal CO

`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
NPS IDMT LV Stage2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
384 A46SL2PTOC1 A46SL2PTOC1$SP$TmACrv$setCharact Enum SP
NPS INST LV Stage2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
412 A49H1PTTR1 A49H1PTTR1$ST$Beh$stVal BOOLEAN ST
413 A49H1PTTR1 A49H1PTTR1$ST$Beh$q Quality ST
414 A49H1PTTR1 A49H1PTTR1$ST$Beh$t TimeStamp ST
415 A49H1PTTR1 A49H1PTTR1$ST$Str$general BOOLEAN ST
Thermal HV Stage1
416 A49H1PTTR1 A49H1PTTR1$ST$Str$dirGeneral Enum ST

417 A49H1PTTR1 A49H1PTTR1$ST$Str$phsA BOOLEAN ST
418 A49H1PTTR1 A49H1PTTR1$ST$Str$dirPhsA Enum ST
419 A49H1PTTR1 A49H1PTTR1$ST$Str$phsB BOOLEAN ST
420 A49H1PTTR1 A49H1PTTR1$ST$Str$dirPhsB Enum ST
421 A49H1PTTR1 A49H1PTTR1$ST$Str$phsC BOOLEAN ST
422 A49H1PTTR1 A49H1PTTR1$ST$Str$dirPhsC Enum ST
423 A49H1PTTR1 A49H1PTTR1$ST$Str$q Quality ST
424 A49H1PTTR1 A49H1PTTR1$ST$Str$t TimeStamp ST

`
425 A49H1PTTR1 A49H1PTTR1$ST$Op$general BOOLEAN ST

426 A49H1PTTR1 A49H1PTTR1$ST$Op$phsA BOOLEAN ST
427 A49H1PTTR1 A49H1PTTR1$ST$Op$phsB BOOLEAN ST
428 A49H1PTTR1 A49H1PTTR1$ST$Op$phsC BOOLEAN ST
429 A49H1PTTR1 A49H1PTTR1$ST$Op$q Quality ST
430 A49H1PTTR1 A49H1PTTR1$ST$Op$t TimeStamp ST
431 A49H1PTTR1 A49H1PTTR1$CF$Mod$ctlModel CtlModels CF
432 A49H1PTTR1 A49H1PTTR1$CF$OpDlTmms$minVal INT32 CF
433 A49H1PTTR1 A49H1PTTR1$CF$OpDlTmms$maxVal INT32 CF
434 A49H1PTTR1 A49H1PTTR1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
435 A49H1PTTR1 A49H1PTTR1$DC$NamPlt$vendor DC
STRING255
VISIBLE
436 A49H1PTTR1 A49H1PTTR1$DC$NamPlt$swRev DC
STRING255
VISIBLE
437 A49H1PTTR1 A49H1PTTR1$DC$NamPlt$d DC
STRING255
VISIBLE
438 A49H1PTTR1 A49H1PTTR1$DC$Str$d DC
STRING255
VISIBLE
439 A49H1PTTR1 A49H1PTTR1$DC$Op$d DC
STRING255
440 A49H1PTTR1 A49H1PTTR1$SP$OpDlTmms$setVal BOOLEAN SP
441 A49L1PTTR1 A49L1PTTR1$ST$Beh$stVal BOOLEAN ST
442 A49L1PTTR1 A49L1PTTR1$ST$Beh$q Quality ST
Thermal LV Stage1
443 A49L1PTTR1 A49L1PTTR1$ST$Beh$t TimeStamp ST

444 A49L1PTTR1 A49L1PTTR1$ST$Str$general BOOLEAN ST
445 A49L1PTTR1 A49L1PTTR1$ST$Str$dirGeneral Enum ST
446 A49L1PTTR1 A49L1PTTR1$ST$Str$phsA BOOLEAN ST
447 A49L1PTTR1 A49L1PTTR1$ST$Str$dirPhsA Enum ST
448 A49L1PTTR1 A49L1PTTR1$ST$Str$phsB BOOLEAN ST
449 A49L1PTTR1 A49L1PTTR1$ST$Str$dirPhsB Enum ST

`
450 A49L1PTTR1 A49L1PTTR1$ST$Str$phsC BOOLEAN ST

451 A49L1PTTR1 A49L1PTTR1$ST$Str$dirPhsC Enum ST
452 A49L1PTTR1 A49L1PTTR1$ST$Str$q Quality ST
453 A49L1PTTR1 A49L1PTTR1$ST$Str$t TimeStamp ST
454 A49L1PTTR1 A49L1PTTR1$ST$Op$general BOOLEAN ST
455 A49L1PTTR1 A49L1PTTR1$ST$Op$phsA BOOLEAN ST
456 A49L1PTTR1 A49L1PTTR1$ST$Op$phsB BOOLEAN ST
457 A49L1PTTR1 A49L1PTTR1$ST$Op$phsC BOOLEAN ST
458 A49L1PTTR1 A49L1PTTR1$ST$Op$q Quality ST
459 A49L1PTTR1 A49L1PTTR1$ST$Op$t TimeStamp ST
460 A49L1PTTR1 A49L1PTTR1$CF$Mod$ctlModel CtlModels CF
461 A49L1PTTR1 A49L1PTTR1$CF$OpDlTmms$minVal INT32 CF
462 A49L1PTTR1 A49L1PTTR1$CF$OpDlTmms$maxVal INT32 CF
463 A49L1PTTR1 A49L1PTTR1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
464 A49L1PTTR1 A49L1PTTR1$DC$NamPlt$vendor DC
STRING255
VISIBLE
465 A49L1PTTR1 A49L1PTTR1$DC$NamPlt$swRev DC
STRING255
VISIBLE
466 A49L1PTTR1 A49L1PTTR1$DC$NamPlt$d DC
STRING255
VISIBLE
467 A49L1PTTR1 A49L1PTTR1$DC$Str$d DC
STRING255
VISIBLE
468 A49L1PTTR1 A49L1PTTR1$DC$Op$d DC
STRING255
469 A49L1PTTR1 A49L1PTTR1$SP$OpDlTmms$setVal BOOLEAN SP
Breaker Fail Stage 1
470 A50BF_RBRF1 A50BF_RBRF1$ST$Beh$stVal BOOLEAN ST

471 A50BF_RBRF1 A50BF_RBRF1$ST$Beh$q Quality ST
472 A50BF_RBRF1 A50BF_RBRF1$ST$Beh$t TimeStamp ST
473 A50BF_RBRF1 A50BF_RBRF1$ST$OpEx$general BOOLEAN ST
474 A50BF_RBRF1 A50BF_RBRF1$ST$OpEx$q Quality ST

`
475 A50BF_RBRF1 A50BF_RBRF1$ST$OpEx$t TimeStamp ST

476 A50BF_RBRF1 A50BF_RBRF1$CF$Mod$ctlModel CtlModels CF
477 A50BF_RBRF1 A50BF_RBRF1$CF$FailTmms$minVal INT32 CF
478 A50BF_RBRF1 A50BF_RBRF1$CF$FailTmms$maxVal INT32 CF
479 A50BF_RBRF1 A50BF_RBRF1$CF$FailTmms$stepSize INT32U CF
VISIBLE
480 A50BF_RBRF1 A50BF_RBRF1$DC$NamPlt$vendor DC
STRING255
VISIBLE
481 A50BF_RBRF1 A50BF_RBRF1$DC$NamPlt$swRev DC
STRING255
VISIBLE
482 A50BF_RBRF1 A50BF_RBRF1$DC$NamPlt$d DC
STRING255
VISIBLE
483 A50BF_RBRF1 A50BF_RBRF1$DC$OpEx$d DC
STRING255
484 A50BF_RBRF1 A50BF_RBRF1$SP$FailTmms$setVal BOOLEAN SP
485 A50BF_RBRF2 A50BF_RBRF2$ST$Beh$stVal BOOLEAN ST
486 A50BF_RBRF2 A50BF_RBRF2$ST$Beh$q Quality ST
487 A50BF_RBRF2 A50BF_RBRF2$ST$Beh$t TimeStamp ST
488 A50BF_RBRF2 A50BF_RBRF2$ST$OpEx$general BOOLEAN ST
489 A50BF_RBRF2 A50BF_RBRF2$ST$OpEx$q Quality ST
Breaker Fail Stage 2
490 A50BF_RBRF2 A50BF_RBRF2$ST$OpEx$t TimeStamp ST

491 A50BF_RBRF2 A50BF_RBRF2$CF$Mod$ctlModel CtlModels CF
492 A50BF_RBRF2 A50BF_RBRF2$CF$FailTmms$minVal INT32 CF
493 A50BF_RBRF2 A50BF_RBRF2$CF$FailTmms$maxVal INT32 CF
494 A50BF_RBRF2 A50BF_RBRF2$CF$FailTmms$stepSize INT32U CF
VISIBLE
495 A50BF_RBRF2 A50BF_RBRF2$DC$NamPlt$vendor DC
STRING255
VISIBLE
496 A50BF_RBRF2 A50BF_RBRF2$DC$NamPlt$swRev DC
STRING255
VISIBLE
497 A50BF_RBRF2 A50BF_RBRF2$DC$NamPlt$d DC
STRING255
VISIBLE
498 A50BF_RBRF2 A50BF_RBRF2$DC$OpEx$d DC
STRING255

`
499 A50BF_RBRF2 A50BF_RBRF2$SP$FailTmms$setVal BOOLEAN SP

500 A50GH1PTOC2 A50GH1PTOC2$ST$Beh$stVal BOOLEAN ST
501 A50GH1PTOC2 A50GH1PTOC2$ST$Beh$q Quality ST
502 A50GH1PTOC2 A50GH1PTOC2$ST$Beh$t TimeStamp ST
503 A50GH1PTOC2 A50GH1PTOC2$ST$Str$general BOOLEAN ST
504 A50GH1PTOC2 A50GH1PTOC2$ST$Str$dirGeneral Enum ST
505 A50GH1PTOC2 A50GH1PTOC2$ST$Str$neut ST
506 A50GH1PTOC2 A50GH1PTOC2$ST$Str$dirNeut ST
507 A50GH1PTOC2 A50GH1PTOC2$ST$Str$q Quality ST
508 A50GH1PTOC2 A50GH1PTOC2$ST$Str$t TimeStamp ST
Measured EF HV INST Stage 1
509 A50GH1PTOC2 A50GH1PTOC2$ST$Op$general BOOLEAN ST
510 A50GH1PTOC2 A50GH1PTOC2$ST$Op$neut ST
511 A50GH1PTOC2 A50GH1PTOC2$ST$Op$q Quality ST
512 A50GH1PTOC2 A50GH1PTOC2$ST$Op$t TimeStamp ST
513 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$ctlVal CO
514 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$origin$orCat Enum CO
515 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
516 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$ctlNum INT8U CO
517 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$T 6 CO
518 A50GH1PTOC2 A50GH1PTOC2$CO$Mod$Cancel$Test BOOLEAN CO
519 A50GH1PTOC2 A50GH1PTOC2$CF$Mod$ctlModel CtlModels CF
520 A50GH1PTOC2 A50GH1PTOC2$CF$OpDlTmms$minVal INT32 CF
521 A50GH1PTOC2 A50GH1PTOC2$CF$OpDlTmms$maxVal INT32 CF
522 A50GH1PTOC2 A50GH1PTOC2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
523 A50GH1PTOC2 A50GH1PTOC2$DC$NamPlt$vendor DC
STRING255
VISIBLE
524 A50GH1PTOC2 A50GH1PTOC2$DC$NamPlt$swRev DC
STRING255

`
VISIBLE
525 A50GH1PTOC2 A50GH1PTOC2$DC$NamPlt$d DC
STRING255
VISIBLE
526 A50GH1PTOC2 A50GH1PTOC2$DC$Str$d DC
STRING255
VISIBLE
527 A50GH1PTOC2 A50GH1PTOC2$DC$Op$d DC
STRING256
528 A50GH1PTOC2 A50GH1PTOC2$SP$OpDlTmms$setVal BOOLEAN SP
529 A50GH1PTOC2 A50GH1PTOC2$SP$DirMod$setVal BOOLEAN SP
Measured EF HV INST Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
556 A50GH2PTOC2 A50GH2PTOC2$DC$Str$d DC
STRING255
VISIBLE
557 A50GH2PTOC2 A50GH2PTOC2$DC$Op$d DC
STRING256
560 A50GL1PTOC2 A50GL1PTOC2$ST$Beh$stVal BOOLEAN ST
561 A50GL1PTOC2 A50GL1PTOC2$ST$Beh$q Quality ST
562 A50GL1PTOC2 A50GL1PTOC2$ST$Beh$t TimeStamp ST
563 A50GL1PTOC2 A50GL1PTOC2$ST$Str$general BOOLEAN ST
564 A50GL1PTOC2 A50GL1PTOC2$ST$Str$dirGeneral Enum ST
565 A50GL1PTOC2 A50GL1PTOC2$ST$Str$neut ST
566 A50GL1PTOC2 A50GL1PTOC2$ST$Str$dirNeut ST
567 A50GL1PTOC2 A50GL1PTOC2$ST$Str$q Quality ST
568 A50GL1PTOC2 A50GL1PTOC2$ST$Str$t TimeStamp ST
569 A50GL1PTOC2 A50GL1PTOC2$ST$Op$general BOOLEAN ST
570 A50GL1PTOC2 A50GL1PTOC2$ST$Op$neut ST
571 A50GL1PTOC2 A50GL1PTOC2$ST$Op$q Quality ST
572 A50GL1PTOC2 A50GL1PTOC2$ST$Op$t TimeStamp ST
573 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$ctlVal CO
574 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$origin$orCat Enum CO
575 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO

`
576 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$ctlNum INT8U CO

577 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$T 6 CO
578 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$Test BOOLEAN CO
579 A50GL1PTOC2 A50GL1PTOC2$CF$Mod$ctlModel CtlModels CF
580 A50GL1PTOC2 A50GL1PTOC2$CF$OpDlTmms$minVal INT32 CF
581 A50GL1PTOC2 A50GL1PTOC2$CF$OpDlTmms$maxVal INT32 CF
582 A50GL1PTOC2 A50GL1PTOC2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
583 A50GL1PTOC2 A50GL1PTOC2$DC$NamPlt$vendor DC
STRING255
VISIBLE
584 A50GL1PTOC2 A50GL1PTOC2$DC$NamPlt$swRev DC
STRING255
VISIBLE
585 A50GL1PTOC2 A50GL1PTOC2$DC$NamPlt$d DC
STRING255
VISIBLE
586 A50GL1PTOC2 A50GL1PTOC2$DC$Str$d DC
STRING255
VISIBLE
587 A50GL1PTOC2 A50GL1PTOC2$DC$Op$d DC
STRING256
588 A50GL1PTOC2 A50GL1PTOC2$SP$OpDlTmms$setVal BOOLEAN SP
589 A50GL1PTOC2 A50GL1PTOC2$SP$DirMod$setVal BOOLEAN SP
Measured EF LV INST Stage 1


`

603 A50GL1PTOC2 A50GL1PTOC2$CO$Mod$Cancel$ctlVal CtlModels CO
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
Measured EF LV INST

Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
OC HV INST Stage
646 A50H1PIOC1 A50H1PIOC1$ST$Beh$stVal BOOLEAN ST

647 A50H1PIOC1 A50H1PIOC1$ST$Beh$q Quality ST
648 A50H1PIOC1 A50H1PIOC1$ST$Beh$t TimeStamp ST
1
649 A50H1PIOC1 A50H1PIOC1$ST$Str$general BOOLEAN ST

650 A50H1PIOC1 A50H1PIOC1$ST$Str$dirGeneral Enum ST

`
651 A50H1PIOC1 A50H1PIOC1$ST$Str$phsA BOOLEAN ST

652 A50H1PIOC1 A50H1PIOC1$ST$Str$dirPhsA Enum ST
653 A50H1PIOC1 A50H1PIOC1$ST$Str$phsB BOOLEAN ST
654 A50H1PIOC1 A50H1PIOC1$ST$Str$dirPhsB Enum ST
655 A50H1PIOC1 A50H1PIOC1$ST$Str$phsC BOOLEAN ST
656 A50H1PIOC1 A50H1PIOC1$ST$Str$dirPhsC Enum ST
657 A50H1PIOC1 A50H1PIOC1$ST$Str$q Quality ST
658 A50H1PIOC1 A50H1PIOC1$ST$Str$t TimeStamp ST
659 A50H1PIOC1 A50H1PIOC1$ST$Op$general BOOLEAN ST
660 A50H1PIOC1 A50H1PIOC1$ST$Op$phsA BOOLEAN ST
661 A50H1PIOC1 A50H1PIOC1$ST$Op$phsB BOOLEAN ST
662 A50H1PIOC1 A50H1PIOC1$ST$Op$phsC BOOLEAN ST
663 A50H1PIOC1 A50H1PIOC1$ST$Op$q Quality ST
664 A50H1PIOC1 A50H1PIOC1$ST$Op$t TimeStamp ST
665 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$ctlVal CO
666 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$origin$orCat Enum CO
667 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
668 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$ctlNum INT8U CO
669 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$T 6 CO
670 A50H1PIOC1 A50H1PIOC1$CO$Mod$Cancel$Test BOOLEAN CO
671 A50H1PIOC1 A50H1PIOC1$CF$Mod$ctlModel CtlModels CF
672 A50H1PIOC1 A50H1PIOC1$DC$NamPlt$vendor INT32 DC
673 A50H1PIOC1 A50H1PIOC1$DC$NamPlt$swRev INT32 DC
674 A50H1PIOC1 A50H1PIOC1$DC$NamPlt$d INT32U DC
VISIBLE
675 A50H1PIOC1 A50H1PIOC1$DC$Str$d DC
STRING255
VISIBLE
676 A50H1PIOC1 A50H1PIOC1$DC$Op$d DC
STRING255

`
VISIBLE
677 A50H2PIOC1 A50H2PIOC1$ST$Beh$stVal ST
STRING255
VISIBLE
678 A50H2PIOC1 A50H2PIOC1$ST$Beh$q ST
STRING255
VISIBLE
679 A50H2PIOC1 A50H2PIOC1$ST$Beh$t ST
STRING256
680 A50H2PIOC1 A50H2PIOC1$ST$Str$general BOOLEAN ST
681 A50H2PIOC1 A50H2PIOC1$ST$Str$dirGeneral Enum ST
682 A50H2PIOC1 A50H2PIOC1$ST$Str$phsA BOOLEAN ST
683 A50H2PIOC1 A50H2PIOC1$ST$Str$dirPhsA Enum ST
684 A50H2PIOC1 A50H2PIOC1$ST$Str$phsB BOOLEAN ST
685 A50H2PIOC1 A50H2PIOC1$ST$Str$dirPhsB Enum ST
686 A50H2PIOC1 A50H2PIOC1$ST$Str$phsC BOOLEAN ST
OC HV INST Stage 2
687 A50H2PIOC1 A50H2PIOC1$ST$Str$dirPhsC Enum ST

688 A50H2PIOC1 A50H2PIOC1$ST$Str$q Quality ST
689 A50H2PIOC1 A50H2PIOC1$ST$Str$t TimeStamp ST
690 A50H2PIOC1 A50H2PIOC1$ST$Op$general BOOLEAN ST
691 A50H2PIOC1 A50H2PIOC1$ST$Op$phsA BOOLEAN ST
692 A50H2PIOC1 A50H2PIOC1$ST$Op$phsB BOOLEAN ST
693 A50H2PIOC1 A50H2PIOC1$ST$Op$phsC BOOLEAN ST
694 A50H2PIOC1 A50H2PIOC1$ST$Op$q Quality ST
695 A50H2PIOC1 A50H2PIOC1$ST$Op$t TimeStamp ST
696 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$ctlVal CO
697 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$origin$orCat Enum CO
698 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
699 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$ctlNum INT8U CO
700 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$T 6 CO
701 A50H2PIOC1 A50H2PIOC1$CO$Mod$Cancel$Test BOOLEAN CO
702 A50H2PIOC1 A50H2PIOC1$CF$Mod$ctlModel CtlModels CF

`
VISIBLE
703 A50H2PIOC1 A50H2PIOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
704 A50H2PIOC1 A50H2PIOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
705 A50H2PIOC1 A50H2PIOC1$DC$NamPlt$d DC
STRING255
VISIBLE
706 A50H2PIOC1 A50H2PIOC1$DC$Str$d DC
STRING255
VISIBLE
707 A50H2PIOC1 A50H2PIOC1$DC$Op$d DC
STRING256
708 A50L1PIOC1 A50L1PIOC1$ST$Beh$stVal BOOLEAN ST
709 A50L1PIOC1 A50L1PIOC1$ST$Beh$q Quality ST
710 A50L1PIOC1 A50L1PIOC1$ST$Beh$t TimeStamp ST
711 A50L1PIOC1 A50L1PIOC1$ST$Str$general BOOLEAN ST
712 A50L1PIOC1 A50L1PIOC1$ST$Str$dirGeneral Enum ST
713 A50L1PIOC1 A50L1PIOC1$ST$Str$phsA BOOLEAN ST
714 A50L1PIOC1 A50L1PIOC1$ST$Str$dirPhsA Enum ST
715 A50L1PIOC1 A50L1PIOC1$ST$Str$phsB BOOLEAN ST
OC LV INST Stage 1
716 A50L1PIOC1 A50L1PIOC1$ST$Str$dirPhsB Enum ST

717 A50L1PIOC1 A50L1PIOC1$ST$Str$phsC BOOLEAN ST
718 A50L1PIOC1 A50L1PIOC1$ST$Str$dirPhsC Enum ST
719 A50L1PIOC1 A50L1PIOC1$ST$Str$q Quality ST
720 A50L1PIOC1 A50L1PIOC1$ST$Str$t TimeStamp ST
721 A50L1PIOC1 A50L1PIOC1$ST$Op$general BOOLEAN ST
722 A50L1PIOC1 A50L1PIOC1$ST$Op$phsA BOOLEAN ST
723 A50L1PIOC1 A50L1PIOC1$ST$Op$phsB BOOLEAN ST
724 A50L1PIOC1 A50L1PIOC1$ST$Op$phsC BOOLEAN ST
725 A50L1PIOC1 A50L1PIOC1$ST$Op$q Quality ST
726 A50L1PIOC1 A50L1PIOC1$ST$Op$t TimeStamp ST
727 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$ctlVal CO

`
728 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$origin$orCat Enum CO

729 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
730 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$ctlNum INT8U CO
731 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$T 6 CO
732 A50L1PIOC1 A50L1PIOC1$CO$Mod$Cancel$Test BOOLEAN CO
733 A50L1PIOC1 A50L1PIOC1$CF$Mod$ctlModel CtlModels CF
VISIBLE
734 A50L1PIOC1 A50L1PIOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
735 A50L1PIOC1 A50L1PIOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
736 A50L1PIOC1 A50L1PIOC1$DC$NamPlt$d DC
STRING255
VISIBLE
737 A50L1PIOC1 A50L1PIOC1$DC$Str$d DC
STRING255
VISIBLE
738 A50L1PIOC1 A50L1PIOC1$DC$Op$d DC
STRING256
739 A50L2PIOC1 A50L2PIOC1$ST$Beh$stVal BOOLEAN ST
740 A50L2PIOC1 A50L2PIOC1$ST$Beh$q Quality ST
741 A50L2PIOC1 A50L2PIOC1$ST$Beh$t TimeStamp ST
742 A50L2PIOC1 A50L2PIOC1$ST$Str$general BOOLEAN ST
743 A50L2PIOC1 A50L2PIOC1$ST$Str$dirGeneral Enum ST
OC LV INST Stage 2
744 A50L2PIOC1 A50L2PIOC1$ST$Str$phsA BOOLEAN ST

745 A50L2PIOC1 A50L2PIOC1$ST$Str$dirPhsA Enum ST
746 A50L2PIOC1 A50L2PIOC1$ST$Str$phsB BOOLEAN ST
747 A50L2PIOC1 A50L2PIOC1$ST$Str$dirPhsB Enum ST
748 A50L2PIOC1 A50L2PIOC1$ST$Str$phsC BOOLEAN ST
749 A50L2PIOC1 A50L2PIOC1$ST$Str$dirPhsC Enum ST
750 A50L2PIOC1 A50L2PIOC1$ST$Str$q Quality ST
751 A50L2PIOC1 A50L2PIOC1$ST$Str$t TimeStamp ST
752 A50L2PIOC1 A50L2PIOC1$ST$Op$general BOOLEAN ST

`
753 A50L2PIOC1 A50L2PIOC1$ST$Op$phsA BOOLEAN ST

754 A50L2PIOC1 A50L2PIOC1$ST$Op$phsB BOOLEAN ST
755 A50L2PIOC1 A50L2PIOC1$ST$Op$phsC BOOLEAN ST
756 A50L2PIOC1 A50L2PIOC1$ST$Op$q Quality ST
757 A50L2PIOC1 A50L2PIOC1$ST$Op$t TimeStamp ST
758 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$ctlVal CO
759 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$origin$orCat Enum CO
760 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
761 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$ctlNum INT8U CO
762 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$T 6 CO
763 A50L2PIOC1 A50L2PIOC1$CO$Mod$Cancel$Test BOOLEAN CO
764 A50L2PIOC1 A50L2PIOC1$CF$Mod$ctlModel CtlModels CF
VISIBLE
765 A50L2PIOC1 A50L2PIOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
766 A50L2PIOC1 A50L2PIOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
767 A50L2PIOC1 A50L2PIOC1$DC$NamPlt$d DC
STRING255
VISIBLE
768 A50L2PIOC1 A50L2PIOC1$DC$Str$d DC
STRING255
VISIBLE
769 A50L2PIOC1 A50L2PIOC1$DC$Op$d DC
STRING256
770 A50NH1PTOC2 A50NH1PTOC2$ST$Beh$stVal BOOLEAN ST
Derived EF HV INST Stage 1
771 A50NH1PTOC2 A50NH1PTOC2$ST$Beh$q Quality ST

772 A50NH1PTOC2 A50NH1PTOC2$ST$Beh$t TimeStamp ST
773 A50NH1PTOC2 A50NH1PTOC2$ST$Str$general BOOLEAN ST
774 A50NH1PTOC2 A50NH1PTOC2$ST$Str$dirGeneral Enum ST
775 A50NH1PTOC2 A50NH1PTOC2$ST$Str$neut ST
776 A50NH1PTOC2 A50NH1PTOC2$ST$Str$dirNeut ST
777 A50NH1PTOC2 A50NH1PTOC2$ST$Str$q Quality ST

`
778 A50NH1PTOC2 A50NH1PTOC2$ST$Str$t TimeStamp ST

779 A50NH1PTOC2 A50NH1PTOC2$ST$Op$general BOOLEAN ST
780 A50NH1PTOC2 A50NH1PTOC2$ST$Op$neut ST
781 A50NH1PTOC2 A50NH1PTOC2$ST$Op$q Quality ST
782 A50NH1PTOC2 A50NH1PTOC2$ST$Op$t TimeStamp ST
783 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$ctlVal CO
784 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$origin$orCat Enum CO
785 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
786 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$ctlNum INT8U CO
787 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$T 6 CO
788 A50NH1PTOC2 A50NH1PTOC2$CO$Mod$Cancel$Test BOOLEAN CO
789 A50NH1PTOC2 A50NH1PTOC2$CF$Mod$ctlModel CtlModels CF
790 A50NH1PTOC2 A50NH1PTOC2$CF$OpDlTmms$minVal INT32 CF
791 A50NH1PTOC2 A50NH1PTOC2$CF$OpDlTmms$maxVal INT32 CF
792 A50NH1PTOC2 A50NH1PTOC2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
793 A50NH1PTOC2 A50NH1PTOC2$DC$NamPlt$vendor DC
STRING255
VISIBLE
794 A50NH1PTOC2 A50NH1PTOC2$DC$NamPlt$swRev DC
STRING255
VISIBLE
795 A50NH1PTOC2 A50NH1PTOC2$DC$NamPlt$d DC
STRING255
VISIBLE
796 A50NH1PTOC2 A50NH1PTOC2$DC$Str$d DC
STRING255
VISIBLE
797 A50NH1PTOC2 A50NH1PTOC2$DC$Op$d DC
STRING256
798 A50NH1PTOC2 A50NH1PTOC2$SP$OpDlTmms$setVal BOOLEAN SP
799 A50NH1PTOC2 A50NH1PTOC2$SP$DirMod$setVal BOOLEAN SP
Derived EF

HV INST
Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256

`

830 A50NL1PTOC2 A50NL1PTOC2$ST$Beh$stVal BOOLEAN ST
831 A50NL1PTOC2 A50NL1PTOC2$ST$Beh$q Quality ST
832 A50NL1PTOC2 A50NL1PTOC2$ST$Beh$t TimeStamp ST
833 A50NL1PTOC2 A50NL1PTOC2$ST$Str$general BOOLEAN ST
834 A50NL1PTOC2 A50NL1PTOC2$ST$Str$dirGeneral Enum ST
835 A50NL1PTOC2 A50NL1PTOC2$ST$Str$neut ST
836 A50NL1PTOC2 A50NL1PTOC2$ST$Str$dirNeut ST
837 A50NL1PTOC2 A50NL1PTOC2$ST$Str$q Quality ST
838 A50NL1PTOC2 A50NL1PTOC2$ST$Str$t TimeStamp ST
Derived EF LV INST Stage 1
839 A50NL1PTOC2 A50NL1PTOC2$ST$Op$general BOOLEAN ST

840 A50NL1PTOC2 A50NL1PTOC2$ST$Op$neut ST
841 A50NL1PTOC2 A50NL1PTOC2$ST$Op$q Quality ST
842 A50NL1PTOC2 A50NL1PTOC2$ST$Op$t TimeStamp ST
843 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$ctlVal CO
844 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$origin$orCat Enum CO
845 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
846 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$ctlNum INT8U CO
847 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$T 6 CO
848 A50NL1PTOC2 A50NL1PTOC2$CO$Mod$Cancel$Test BOOLEAN CO
849 A50NL1PTOC2 A50NL1PTOC2$CF$Mod$ctlModel CtlModels CF
850 A50NL1PTOC2 A50NL1PTOC2$CF$OpDlTmms$minVal INT32 CF
851 A50NL1PTOC2 A50NL1PTOC2$CF$OpDlTmms$maxVal INT32 CF
852 A50NL1PTOC2 A50NL1PTOC2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
853 A50NL1PTOC2 A50NL1PTOC2$DC$NamPlt$vendor DC
STRING255

`
VISIBLE
854 A50NL1PTOC2 A50NL1PTOC2$DC$NamPlt$swRev DC
STRING255
VISIBLE
855 A50NL1PTOC2 A50NL1PTOC2$DC$NamPlt$d DC
STRING255
VISIBLE
856 A50NL1PTOC2 A50NL1PTOC2$DC$Str$d DC
STRING255
VISIBLE
857 A50NL1PTOC2 A50NL1PTOC2$DC$Op$d DC
STRING256
858 A50NL1PTOC2 A50NL1PTOC2$SP$OpDlTmms$setVal BOOLEAN SP
859 A50NL1PTOC2 A50NL1PTOC2$SP$DirMod$setVal BOOLEAN ST
Derived EF LV INST Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
889 A50NL2PTOC2 A50NL2PTOC2$SP$DirMod$setVal BOOLEAN SP
Measured EF HV IDMT Stage 1


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
916 A51GH1PTOC1 A51GH1PTOC1$SP$TmACrv$setCharact Enum SP
Measured EF HV IDMT Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
945 A51GH2PTOC1 A51GH2PTOC1$SP$TmACrv$setCharact Enum SP
Measured EF LV IDMT Stage 1


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
974 A51GL1PTOC1 A51GL1PTOC1$SP$TmACrv$setCharact Enum SP
Measured EF LV IDMT

Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
1003 A51GL2PTOC1 A51GL2PTOC1$SP$TmACrv$setCharact Enum SP
IDMT Stage
1006 A51H1PTOC1 A51H1PTOC1$ST$Beh$stVal BOOLEAN ST

OC HV
1007 A51H1PTOC1 A51H1PTOC1$ST$Beh$q Quality ST

1
1008 A51H1PTOC1 A51H1PTOC1$ST$Beh$t TimeStamp ST

`
1009 A51H1PTOC1 A51H1PTOC1$ST$Str$general BOOLEAN ST

1010 A51H1PTOC1 A51H1PTOC1$ST$Str$dirGeneral Enum ST
1011 A51H1PTOC1 A51H1PTOC1$ST$Str$phsA BOOLEAN ST
1012 A51H1PTOC1 A51H1PTOC1$ST$Str$dirPhsA Enum ST
1013 A51H1PTOC1 A51H1PTOC1$ST$Str$phsB BOOLEAN ST
1014 A51H1PTOC1 A51H1PTOC1$ST$Str$dirPhsB Enum ST
1015 A51H1PTOC1 A51H1PTOC1$ST$Str$phsC BOOLEAN ST
1016 A51H1PTOC1 A51H1PTOC1$ST$Str$dirPhsC Enum ST
1017 A51H1PTOC1 A51H1PTOC1$ST$Str$q Quality ST
1018 A51H1PTOC1 A51H1PTOC1$ST$Str$t TimeStamp ST
1019 A51H1PTOC1 A51H1PTOC1$ST$Op$general BOOLEAN ST
1020 A51H1PTOC1 A51H1PTOC1$ST$Op$phsA BOOLEAN ST
1021 A51H1PTOC1 A51H1PTOC1$ST$Op$phsB BOOLEAN ST
1022 A51H1PTOC1 A51H1PTOC1$ST$Op$phsC BOOLEAN ST
1023 A51H1PTOC1 A51H1PTOC1$ST$Op$q Quality ST
1024 A51H1PTOC1 A51H1PTOC1$ST$Op$t TimeStamp ST
1025 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$ctlVal CO
1026 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1027 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1028 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1029 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$T 6 CO
1030 A51H1PTOC1 A51H1PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1031 A51H1PTOC1 A51H1PTOC1$CF$Mod$ctlModel CtlModels CF
1032 A51H1PTOC1 A51H1PTOC1$CF$OpDlTmms$minVal INT32 CF
1033 A51H1PTOC1 A51H1PTOC1$CF$OpDlTmms$maxVal INT32 CF
1034 A51H1PTOC1 A51H1PTOC1$CF$OpDlTmms$stepSize INT32U CF
1035 A51H1PTOC1 A51H1PTOC1$DC$NamPlt$vendor VISIBLE DC

`
STRING255
VISIBLE
1036 A51H1PTOC1 A51H1PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1037 A51H1PTOC1 A51H1PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1038 A51H1PTOC1 A51H1PTOC1$DC$Str$d DC
STRING256
VISIBLE
1039 A51H1PTOC1 A51H1PTOC1$DC$Op$d DC
STRING257
1040 A51H1PTOC1 A51H1PTOC1$SP$TmACrv$setCharact Enum SP
1041 A51H1PTOC1 A51H1PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1042 A51H1PTOC1 A51H1PTOC1$SP$DirMod$setVal BOOLEAN SP
1043 A51H2PTOC1 A51H2PTOC1$ST$Beh$stVal BOOLEAN ST
1044 A51H2PTOC1 A51H2PTOC1$ST$Beh$q Quality ST
1045 A51H2PTOC1 A51H2PTOC1$ST$Beh$t TimeStamp ST
1046 A51H2PTOC1 A51H2PTOC1$ST$Str$general BOOLEAN ST
1047 A51H2PTOC1 A51H2PTOC1$ST$Str$dirGeneral Enum ST
1048 A51H2PTOC1 A51H2PTOC1$ST$Str$phsA BOOLEAN ST
1049 A51H2PTOC1 A51H2PTOC1$ST$Str$dirPhsA Enum ST
OC HV IDMT Stage 2
1050 A51H2PTOC1 A51H2PTOC1$ST$Str$phsB BOOLEAN ST

1051 A51H2PTOC1 A51H2PTOC1$ST$Str$dirPhsB Enum ST
1052 A51H2PTOC1 A51H2PTOC1$ST$Str$phsC BOOLEAN ST
1053 A51H2PTOC1 A51H2PTOC1$ST$Str$dirPhsC Enum ST
1054 A51H2PTOC1 A51H2PTOC1$ST$Str$q Quality ST
1055 A51H2PTOC1 A51H2PTOC1$ST$Str$t TimeStamp ST
1056 A51H2PTOC1 A51H2PTOC1$ST$Op$general BOOLEAN ST
1057 A51H2PTOC1 A51H2PTOC1$ST$Op$phsA BOOLEAN ST
1058 A51H2PTOC1 A51H2PTOC1$ST$Op$phsB BOOLEAN ST
1059 A51H2PTOC1 A51H2PTOC1$ST$Op$phsC BOOLEAN ST
1060 A51H2PTOC1 A51H2PTOC1$ST$Op$q Quality ST

`
1061 A51H2PTOC1 A51H2PTOC1$ST$Op$t TimeStamp ST

1062 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$ctlVal CO
1063 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1064 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1065 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1066 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$T 6 CO
1067 A51H2PTOC1 A51H2PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1068 A51H2PTOC1 A51H2PTOC1$CF$Mod$ctlModel CtlModels CF
1069 A51H2PTOC1 A51H2PTOC1$CF$OpDlTmms$minVal INT32 CF
1070 A51H2PTOC1 A51H2PTOC1$CF$OpDlTmms$maxVal INT32 CF
1071 A51H2PTOC1 A51H2PTOC1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1072 A51H2PTOC1 A51H2PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1073 A51H2PTOC1 A51H2PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1074 A51H2PTOC1 A51H2PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1075 A51H2PTOC1 A51H2PTOC1$DC$Str$d DC
STRING256
VISIBLE
1076 A51H2PTOC1 A51H2PTOC1$DC$Op$d DC
STRING257
1077 A51H2PTOC1 A51H2PTOC1$SP$TmACrv$setCharact Enum SP
1078 A51H2PTOC1 A51H2PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1079 A51H2PTOC1 A51H2PTOC1$SP$DirMod$setVal BOOLEAN SP
1080 A51L1PTOC1 A51L1PTOC1$ST$Beh$stVal BOOLEAN ST
OC LV IDMT Stage 1
1081 A51L1PTOC1 A51L1PTOC1$ST$Beh$q Quality ST

1082 A51L1PTOC1 A51L1PTOC1$ST$Beh$t TimeStamp ST
1083 A51L1PTOC1 A51L1PTOC1$ST$Str$general BOOLEAN ST
1084 A51L1PTOC1 A51L1PTOC1$ST$Str$dirGeneral Enum ST
1085 A51L1PTOC1 A51L1PTOC1$ST$Str$phsA BOOLEAN ST

`
1086 A51L1PTOC1 A51L1PTOC1$ST$Str$dirPhsA Enum ST

1087 A51L1PTOC1 A51L1PTOC1$ST$Str$phsB BOOLEAN ST
1088 A51L1PTOC1 A51L1PTOC1$ST$Str$dirPhsB Enum ST
1089 A51L1PTOC1 A51L1PTOC1$ST$Str$phsC BOOLEAN ST
1090 A51L1PTOC1 A51L1PTOC1$ST$Str$dirPhsC Enum ST
1091 A51L1PTOC1 A51L1PTOC1$ST$Str$q Quality ST
1092 A51L1PTOC1 A51L1PTOC1$ST$Str$t TimeStamp ST
1093 A51L1PTOC1 A51L1PTOC1$ST$Op$general BOOLEAN ST
1094 A51L1PTOC1 A51L1PTOC1$ST$Op$phsA BOOLEAN ST
1095 A51L1PTOC1 A51L1PTOC1$ST$Op$phsB BOOLEAN ST
1096 A51L1PTOC1 A51L1PTOC1$ST$Op$phsC BOOLEAN ST
1097 A51L1PTOC1 A51L1PTOC1$ST$Op$q Quality ST
1098 A51L1PTOC1 A51L1PTOC1$ST$Op$t TimeStamp ST
1099 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$ctlVal CO
1100 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1101 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1102 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1103 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$T 6 CO
1104 A51L1PTOC1 A51L1PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1105 A51L1PTOC1 A51L1PTOC1$CF$Mod$ctlModel CtlModels CF
1106 A51L1PTOC1 A51L1PTOC1$CF$OpDlTmms$minVal INT32 CF
1107 A51L1PTOC1 A51L1PTOC1$CF$OpDlTmms$maxVal INT32 CF
1108 A51L1PTOC1 A51L1PTOC1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1109 A51L1PTOC1 A51L1PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1110 A51L1PTOC1 A51L1PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1111 A51L1PTOC1 A51L1PTOC1$DC$NamPlt$d DC
STRING255

`
VISIBLE
1112 A51L1PTOC1 A51L1PTOC1$DC$Str$d DC
STRING256
VISIBLE
1113 A51L1PTOC1 A51L1PTOC1$DC$Op$d DC
STRING257
1114 A51L1PTOC1 A51L1PTOC1$SP$TmACrv$setCharact Enum SP
1115 A51L1PTOC1 A51L1PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1116 A51L1PTOC1 A51L1PTOC1$SP$DirMod$setVal BOOLEAN SP
1117 A51L2PTOC1 A51L2PTOC1$ST$Beh$stVal BOOLEAN ST
1118 A51L2PTOC1 A51L2PTOC1$ST$Beh$q Quality ST
1119 A51L2PTOC1 A51L2PTOC1$ST$Beh$t TimeStamp ST
1120 A51L2PTOC1 A51L2PTOC1$ST$Str$general BOOLEAN ST
1121 A51L2PTOC1 A51L2PTOC1$ST$Str$dirGeneral Enum ST
1122 A51L2PTOC1 A51L2PTOC1$ST$Str$phsA BOOLEAN ST
1123 A51L2PTOC1 A51L2PTOC1$ST$Str$dirPhsA Enum ST
1124 A51L2PTOC1 A51L2PTOC1$ST$Str$phsB BOOLEAN ST
OC LV IDMT Stage 2
1125 A51L2PTOC1 A51L2PTOC1$ST$Str$dirPhsB Enum ST

1126 A51L2PTOC1 A51L2PTOC1$ST$Str$phsC BOOLEAN ST
1127 A51L2PTOC1 A51L2PTOC1$ST$Str$dirPhsC Enum ST
1128 A51L2PTOC1 A51L2PTOC1$ST$Str$q Quality ST
1129 A51L2PTOC1 A51L2PTOC1$ST$Str$t TimeStamp ST
1130 A51L2PTOC1 A51L2PTOC1$ST$Op$general BOOLEAN ST
1131 A51L2PTOC1 A51L2PTOC1$ST$Op$phsA BOOLEAN ST
1132 A51L2PTOC1 A51L2PTOC1$ST$Op$phsB BOOLEAN ST
1133 A51L2PTOC1 A51L2PTOC1$ST$Op$phsC BOOLEAN ST
1134 A51L2PTOC1 A51L2PTOC1$ST$Op$q Quality ST
1135 A51L2PTOC1 A51L2PTOC1$ST$Op$t TimeStamp ST
1136 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$ctlVal CO
1137 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$origin$orCat Enum CO

`
1138 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO

1139 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1140 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$T 6 CO
1141 A51L2PTOC1 A51L2PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1142 A51L2PTOC1 A51L2PTOC1$CF$Mod$ctlModel CtlModels CF
1143 A51L2PTOC1 A51L2PTOC1$CF$OpDlTmms$minVal INT32 CF
1144 A51L2PTOC1 A51L2PTOC1$CF$OpDlTmms$maxVal INT32 CF
1145 A51L2PTOC1 A51L2PTOC1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1146 A51L2PTOC1 A51L2PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1147 A51L2PTOC1 A51L2PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1148 A51L2PTOC1 A51L2PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1149 A51L2PTOC1 A51L2PTOC1$DC$Str$d DC
STRING256
VISIBLE
1150 A51L2PTOC1 A51L2PTOC1$DC$Op$d DC
STRING257
1151 A51L2PTOC1 A51L2PTOC1$SP$TmACrv$setCharact Enum SP
1152 A51L2PTOC1 A51L2PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1153 A51L2PTOC1 A51L2PTOC1$SP$DirMod$setVal BOOLEAN SP
Derived EF HV IDMT Stage 1


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
VISIBLE
STRING257
1182 A51NH1PTOC1 A51NH1PTOC1$SP$TmACrv$setCharact Enum SP
Derived EF
HV IDMT

Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
VISIBLE
STRING257

`
1213 A51NH2PTOC1 A51NH2PTOC1$SP$TmACrv$setCharact Enum SP

Derived EF LV IDMT Stage 1

1239 A51NL1PTOC1 A51NL1PTOC1$DC$NamPlt$vendor VISIBLE DC

`
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
VISIBLE
STRING257
1244 A51NL1PTOC1 A51NL1PTOC1$SP$TmACrv$setCharact Enum SP
Derived EF LV IDMT Stage 2


`

VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING255
VISIBLE
STRING256
VISIBLE
STRING257
1275 A51NL2PTOC1 A51NL2PTOC1$SP$TmACrv$setCharact Enum SP
1278 A59N_PTOV1 A59N_PTOV1$ST$Beh$stVal BOOLEAN ST
1279 A59N_PTOV1 A59N_PTOV1$ST$Beh$q Quality ST
1280 A59N_PTOV1 A59N_PTOV1$ST$Beh$t TimeStamp ST
1281 A59N_PTOV1 A59N_PTOV1$ST$Str$general BOOLEAN ST
1282 A59N_PTOV1 A59N_PTOV1$ST$Str$dirGeneral Enum ST
NDR Stage 1
1283 A59N_PTOV1 A59N_PTOV1$ST$Str$neut ST

1284 A59N_PTOV1 A59N_PTOV1$ST$Str$dirNeut ST
1285 A59N_PTOV1 A59N_PTOV1$ST$Str$q Quality ST
1286 A59N_PTOV1 A59N_PTOV1$ST$Str$t TimeStamp ST
1287 A59N_PTOV1 A59N_PTOV1$ST$Op$general BOOLEAN ST
1288 A59N_PTOV1 A59N_PTOV1$ST$Op$neut ST
1289 A59N_PTOV1 A59N_PTOV1$ST$Op$q Quality ST

`
1290 A59N_PTOV1 A59N_PTOV1$ST$Op$t TimeStamp ST

1291 A59N_PTOV1 A59N_PTOV1$CF$Mod$ctlModel CtlModels CF
1292 A59N_PTOV1 A59N_PTOV1$CF$OpDlTmms$minVal INT32 CF
1293 A59N_PTOV1 A59N_PTOV1$CF$OpDlTmms$maxVal INT32 CF
1294 A59N_PTOV1 A59N_PTOV1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1295 A59N_PTOV1 A59N_PTOV1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1296 A59N_PTOV1 A59N_PTOV1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1297 A59N_PTOV1 A59N_PTOV1$DC$NamPlt$d DC
STRING255
VISIBLE
1298 A59N_PTOV1 A59N_PTOV1$DC$Str$d DC
STRING256
VISIBLE
1299 A59N_PTOV1 A59N_PTOV1$DC$Op$d DC
STRING257
1300 A59N_PTOV1 A59N_PTOV1$SP$TmVCrv$setCharact Enum SP
1301 A59N_PTOV1 A59N_PTOV1$SP$OpDlTmms$setVal BOOLEAN SP
1302 A59N_PTOV2 A59N_PTOV2$ST$Beh$stVal BOOLEAN ST
1303 A59N_PTOV2 A59N_PTOV2$ST$Beh$q Quality ST
1304 A59N_PTOV2 A59N_PTOV2$ST$Beh$t TimeStamp ST
1305 A59N_PTOV2 A59N_PTOV2$ST$Str$general BOOLEAN ST
1306 A59N_PTOV2 A59N_PTOV2$ST$Str$dirGeneral Enum ST
NDR Stage 2
1307 A59N_PTOV2 A59N_PTOV2$ST$Str$neut ST

1308 A59N_PTOV2 A59N_PTOV2$ST$Str$dirNeut ST
1309 A59N_PTOV2 A59N_PTOV2$ST$Str$q Quality ST
1310 A59N_PTOV2 A59N_PTOV2$ST$Str$t TimeStamp ST
1311 A59N_PTOV2 A59N_PTOV2$ST$Op$general BOOLEAN ST
1312 A59N_PTOV2 A59N_PTOV2$ST$Op$neut ST
1313 A59N_PTOV2 A59N_PTOV2$ST$Op$q Quality ST
1314 A59N_PTOV2 A59N_PTOV2$ST$Op$t TimeStamp ST

`
1315 A59N_PTOV2 A59N_PTOV2$CF$Mod$ctlModel CtlModels CF

1316 A59N_PTOV2 A59N_PTOV2$CF$OpDlTmms$minVal INT32 CF
1317 A59N_PTOV2 A59N_PTOV2$CF$OpDlTmms$maxVal INT32 CF
1318 A59N_PTOV2 A59N_PTOV2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1319 A59N_PTOV2 A59N_PTOV2$DC$NamPlt$vendor DC
STRING255
VISIBLE
1320 A59N_PTOV2 A59N_PTOV2$DC$NamPlt$swRev DC
STRING255
VISIBLE
1321 A59N_PTOV2 A59N_PTOV2$DC$NamPlt$d DC
STRING255
VISIBLE
1322 A59N_PTOV2 A59N_PTOV2$DC$Str$d DC
STRING256
VISIBLE
1323 A59N_PTOV2 A59N_PTOV2$DC$Op$d DC
STRING257
1324 A59N_PTOV2 A59N_PTOV2$SP$OpDlTmms$setVal BOOLEAN SP
1325 A59_PTOV1 A59_PTOV1$ST$Beh$stVal BOOLEAN ST
1326 A59_PTOV1 A59_PTOV1$ST$Beh$q Quality ST
1327 A59_PTOV1 A59_PTOV1$ST$Beh$t TimeStamp ST
1328 A59_PTOV1 A59_PTOV1$ST$Str$general BOOLEAN ST
1329 A59_PTOV1 A59_PTOV1$ST$Str$dirGeneral Enum ST
OverVoltage Stage 1
1330 A59_PTOV1 A59_PTOV1$ST$Str$q Quality ST

1331 A59_PTOV1 A59_PTOV1$ST$Str$t TimeStamp ST
1332 A59_PTOV1 A59_PTOV1$ST$Op$general BOOLEAN ST
1333 A59_PTOV1 A59_PTOV1$ST$Op$q Quality ST
1334 A59_PTOV1 A59_PTOV1$ST$Op$t TimeStamp ST
1335 A59_PTOV1 A59_PTOV1$CF$Mod$ctlModel CtlModels CF
1336 A59_PTOV1 A59_PTOV1$CF$OpDlTmms$minVal INT32 CF
1337 A59_PTOV1 A59_PTOV1$CF$OpDlTmms$maxVal INT32 CF
1338 A59_PTOV1 A59_PTOV1$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1339 A59_PTOV1 A59_PTOV1$DC$NamPlt$vendor DC
STRING255

`
VISIBLE
1340 A59_PTOV1 A59_PTOV1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1341 A59_PTOV1 A59_PTOV1$DC$NamPlt$d DC
STRING255
VISIBLE
1342 A59_PTOV1 A59_PTOV1$DC$Str$d DC
STRING256
VISIBLE
1343 A59_PTOV1 A59_PTOV1$DC$Op$d DC
STRING257
1344 A59_PTOV1 A59_PTOV1$SP$TmVCrv$setCharact Enum SP
1345 A59_PTOV1 A59_PTOV1$SP$OpDlTmms$setVal BOOLEAN SP
1346 A59_PTOV2 A59_PTOV2$ST$Beh$stVal BOOLEAN ST
1347 A59_PTOV2 A59_PTOV2$ST$Beh$q Quality ST
1348 A59_PTOV2 A59_PTOV2$ST$Beh$t TimeStamp ST
1349 A59_PTOV2 A59_PTOV2$ST$Str$general BOOLEAN ST
1350 A59_PTOV2 A59_PTOV2$ST$Str$dirGeneral Enum ST
1351 A59_PTOV2 A59_PTOV2$ST$Str$q Quality ST
1352 A59_PTOV2 A59_PTOV2$ST$Str$t TimeStamp ST
OverVoltage Stage 2
1353 A59_PTOV2 A59_PTOV2$ST$Op$general BOOLEAN ST

1354 A59_PTOV2 A59_PTOV2$ST$Op$q Quality ST
1355 A59_PTOV2 A59_PTOV2$ST$Op$t TimeStamp ST
1356 A59_PTOV2 A59_PTOV2$CF$Mod$ctlModel CtlModels CF
1357 A59_PTOV2 A59_PTOV2$CF$OpDlTmms$minVal INT32 CF
1358 A59_PTOV2 A59_PTOV2$CF$OpDlTmms$maxVal INT32 CF
1359 A59_PTOV2 A59_PTOV2$CF$OpDlTmms$stepSize INT32U CF
VISIBLE
1360 A59_PTOV2 A59_PTOV2$DC$NamPlt$vendor DC
STRING255
VISIBLE
1361 A59_PTOV2 A59_PTOV2$DC$NamPlt$swRev DC
STRING255
VISIBLE
1362 A59_PTOV2 A59_PTOV2$DC$NamPlt$d DC
STRING255
VISIBLE
1363 A59_PTOV2 A59_PTOV2$DC$Str$d DC
STRING256

`
VISIBLE
1364 A59_PTOV2 A59_PTOV2$DC$Op$d DC
STRING257
1365 A59_PTOV2 A59_PTOV2$SP$OpDlTmms$setVal BOOLEAN SP
1366 A64RH1PTOC1 A64RH1PTOC1$ST$Beh$stVal BOOLEAN ST
1367 A64RH1PTOC1 A64RH1PTOC1$ST$Beh$q Quality ST
1368 A64RH1PTOC1 A64RH1PTOC1$ST$Beh$t TimeStamp ST
1369 A64RH1PTOC1 A64RH1PTOC1$ST$Str$general BOOLEAN ST
1370 A64RH1PTOC1 A64RH1PTOC1$ST$Str$dirGeneral Enum ST
1371 A64RH1PTOC1 A64RH1PTOC1$ST$Str$neut ST
1372 A64RH1PTOC1 A64RH1PTOC1$ST$Str$dirNeut ST
1373 A64RH1PTOC1 A64RH1PTOC1$ST$Str$q Quality ST
1374 A64RH1PTOC1 A64RH1PTOC1$ST$Str$t TimeStamp ST
1375 A64RH1PTOC1 A64RH1PTOC1$ST$Op$general BOOLEAN ST
1376 A64RH1PTOC1 A64RH1PTOC1$ST$Op$neut ST
REF HV Stage 1
1377 A64RH1PTOC1 A64RH1PTOC1$ST$Op$q Quality ST

1378 A64RH1PTOC1 A64RH1PTOC1$ST$Op$t TimeStamp ST
1379 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$ctlVal CO
1380 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1381 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1382 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1383 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$T 6 CO
1384 A64RH1PTOC1 A64RH1PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1385 A64RH1PTOC1 A64RH1PTOC1$CF$Mod$ctlModel CtlModels CF
1386 A64RH1PTOC1 A64RH1PTOC1$CF$OpDlTmms$minVal INT32 CF
1387 A64RH1PTOC1 A64RH1PTOC1$CF$OpDlTmms$maxVal INT32 CF
VISIBLE
1388 A64RH1PTOC1 A64RH1PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1389 A64RH1PTOC1 A64RH1PTOC1$DC$NamPlt$swRev DC
STRING255

`
VISIBLE
1390 A64RH1PTOC1 A64RH1PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1391 A64RH1PTOC1 A64RH1PTOC1$DC$Str$d DC
STRING256
VISIBLE
1392 A64RH1PTOC1 A64RH1PTOC1$DC$Op$d DC
STRING257
1393 A64RH1PTOC1 A64RH1PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1394 A64RH1PTOC1 A64RH1PTOC1$SP$DirMod$setVal BOOLEAN SP
1395 A64RH2PTOC1 A64RH2PTOC1$ST$Beh$stVal BOOLEAN ST
1396 A64RH2PTOC1 A64RH2PTOC1$ST$Beh$q Quality ST
1397 A64RH2PTOC1 A64RH2PTOC1$ST$Beh$t TimeStamp ST
1398 A64RH2PTOC1 A64RH2PTOC1$ST$Str$general BOOLEAN ST
1399 A64RH2PTOC1 A64RH2PTOC1$ST$Str$dirGeneral Enum ST
1400 A64RH2PTOC1 A64RH2PTOC1$ST$Str$neut ST
1401 A64RH2PTOC1 A64RH2PTOC1$ST$Str$dirNeut ST
1402 A64RH2PTOC1 A64RH2PTOC1$ST$Str$q Quality ST
1403 A64RH2PTOC1 A64RH2PTOC1$ST$Str$t TimeStamp ST
REF HV Stage 2
1404 A64RH2PTOC1 A64RH2PTOC1$ST$Op$general BOOLEAN ST

1405 A64RH2PTOC1 A64RH2PTOC1$ST$Op$neut ST
1406 A64RH2PTOC1 A64RH2PTOC1$ST$Op$q Quality ST
1407 A64RH2PTOC1 A64RH2PTOC1$ST$Op$t TimeStamp ST
1408 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$ctlVal CO
1409 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1410 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1411 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1412 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$T 6 CO
1413 A64RH2PTOC1 A64RH2PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1414 A64RH2PTOC1 A64RH2PTOC1$CF$Mod$ctlModel CtlModels CF
1415 A64RH2PTOC1 A64RH2PTOC1$CF$OpDlTmms$minVal INT32 CF

`
1416 A64RH2PTOC1 A64RH2PTOC1$CF$OpDlTmms$maxVal INT32 CF

VISIBLE
1417 A64RH2PTOC1 A64RH2PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1418 A64RH2PTOC1 A64RH2PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1419 A64RH2PTOC1 A64RH2PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1420 A64RH2PTOC1 A64RH2PTOC1$DC$Str$d DC
STRING256
VISIBLE
1421 A64RH2PTOC1 A64RH2PTOC1$DC$Op$d DC
STRING257
1422 A64RH2PTOC1 A64RH2PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1423 A64RH2PTOC1 A64RH2PTOC1$SP$DirMod$setVal BOOLEAN SP
1424 A64RL1PTOC1 A64RL1PTOC1$ST$Beh$stVal BOOLEAN ST
1425 A64RL1PTOC1 A64RL1PTOC1$ST$Beh$q Quality ST
1426 A64RL1PTOC1 A64RL1PTOC1$ST$Beh$t TimeStamp ST
1427 A64RL1PTOC1 A64RL1PTOC1$ST$Str$general BOOLEAN ST
1428 A64RL1PTOC1 A64RL1PTOC1$ST$Str$dirGeneral Enum ST
1429 A64RL1PTOC1 A64RL1PTOC1$ST$Str$neut 2 ST
1430 A64RL1PTOC1 A64RL1PTOC1$ST$Str$dirNeut 2 ST
REF LV Stage 1
1431 A64RL1PTOC1 A64RL1PTOC1$ST$Str$q Quality ST

1432 A64RL1PTOC1 A64RL1PTOC1$ST$Str$t TimeStamp ST
1433 A64RL1PTOC1 A64RL1PTOC1$ST$Op$general BOOLEAN ST
1434 A64RL1PTOC1 A64RL1PTOC1$ST$Op$neut ST
1435 A64RL1PTOC1 A64RL1PTOC1$ST$Op$q Quality ST
1436 A64RL1PTOC1 A64RL1PTOC1$ST$Op$t TimeStamp ST
1437 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$ctlVal CO
1438 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1439 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1440 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$ctlNum INT8U CO

`
1441 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$T 6 CO

1442 A64RL1PTOC1 A64RL1PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1443 A64RL1PTOC1 A64RL1PTOC1$CF$Mod$ctlModel CtlModels CF
1444 A64RL1PTOC1 A64RL1PTOC1$CF$OpDlTmms$minVal INT32 CF
1445 A64RL1PTOC1 A64RL1PTOC1$CF$OpDlTmms$maxVal INT32 CF
VISIBLE
1446 A64RL1PTOC1 A64RL1PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1447 A64RL1PTOC1 A64RL1PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1448 A64RL1PTOC1 A64RL1PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1449 A64RL1PTOC1 A64RL1PTOC1$DC$Str$d DC
STRING256
VISIBLE
1450 A64RL1PTOC1 A64RL1PTOC1$DC$Op$d DC
STRING257
1451 A64RL1PTOC1 A64RL1PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1452 A64RL1PTOC1 A64RL1PTOC1$SP$DirMod$setVal BOOLEAN SP
1453 A64RL2PTOC1 A64RL2PTOC1$ST$Beh$stVal BOOLEAN ST
1454 A64RL2PTOC1 A64RL2PTOC1$ST$Beh$q Quality ST
1455 A64RL2PTOC1 A64RL2PTOC1$ST$Beh$t TimeStamp ST
1456 A64RL2PTOC1 A64RL2PTOC1$ST$Str$general BOOLEAN ST
1457 A64RL2PTOC1 A64RL2PTOC1$ST$Str$dirGeneral Enum ST
REF LV Stage 2
1458 A64RL2PTOC1 A64RL2PTOC1$ST$Str$neut ST

1459 A64RL2PTOC1 A64RL2PTOC1$ST$Str$dirNeut ST
1460 A64RL2PTOC1 A64RL2PTOC1$ST$Str$q Quality ST
1461 A64RL2PTOC1 A64RL2PTOC1$ST$Str$t TimeStamp ST
1462 A64RL2PTOC1 A64RL2PTOC1$ST$Op$general BOOLEAN ST
1463 A64RL2PTOC1 A64RL2PTOC1$ST$Op$neut ST
1464 A64RL2PTOC1 A64RL2PTOC1$ST$Op$q Quality ST
1465 A64RL2PTOC1 A64RL2PTOC1$ST$Op$t TimeStamp ST

`
1466 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$ctlVal CO

1467 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$origin$orCat Enum CO
1468 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1469 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$ctlNum INT8U CO
1470 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$T 6 CO
1471 A64RL2PTOC1 A64RL2PTOC1$CO$Mod$Cancel$Test BOOLEAN CO
1472 A64RL2PTOC1 A64RL2PTOC1$CF$Mod$ctlModel CtlModels CF
1473 A64RL2PTOC1 A64RL2PTOC1$CF$OpDlTmms$minVal INT32 CF
1474 A64RL2PTOC1 A64RL2PTOC1$CF$OpDlTmms$maxVal INT32 CF
VISIBLE
1475 A64RL2PTOC1 A64RL2PTOC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1476 A64RL2PTOC1 A64RL2PTOC1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1477 A64RL2PTOC1 A64RL2PTOC1$DC$NamPlt$d DC
STRING255
VISIBLE
1478 A64RL2PTOC1 A64RL2PTOC1$DC$Str$d DC
STRING256
VISIBLE
1479 A64RL2PTOC1 A64RL2PTOC1$DC$Op$d DC
STRING257
1480 A64RL2PTOC1 A64RL2PTOC1$SP$OpDlTmms$setVal BOOLEAN SP
1481 A64RL2PTOC1 A64RL2PTOC1$SP$DirMod$setVal BOOLEAN SP
1482 A87HSPDIF2 A87HSPDIF2$ST$Beh$stVal BOOLEAN ST
1483 A87HSPDIF2 A87HSPDIF2$ST$Beh$q Quality ST
1484 A87HSPDIF2 A87HSPDIF2$ST$Beh$t TimeStamp ST
Differential Hiset
1485 A87HSPDIF2 A87HSPDIF2$ST$Str$general BOOLEAN ST

1486 A87HSPDIF2 A87HSPDIF2$ST$Str$dirGeneral Enum ST
1487 A87HSPDIF2 A87HSPDIF2$ST$Str$phsA BOOLEAN ST
1488 A87HSPDIF2 A87HSPDIF2$ST$Str$dirPhsA Enum ST
1489 A87HSPDIF2 A87HSPDIF2$ST$Str$phsB BOOLEAN ST
1490 A87HSPDIF2 A87HSPDIF2$ST$Str$dirPhsB Enum ST

`
1491 A87HSPDIF2 A87HSPDIF2$ST$Str$phsC BOOLEAN ST

1492 A87HSPDIF2 A87HSPDIF2$ST$Str$dirPhsC Enum ST
1493 A87HSPDIF2 A87HSPDIF2$ST$Str$q Quality ST
1494 A87HSPDIF2 A87HSPDIF2$ST$Str$t TimeStamp ST
1495 A87HSPDIF2 A87HSPDIF2$ST$Op$general BOOLEAN ST
1496 A87HSPDIF2 A87HSPDIF2$ST$Op$phsA BOOLEAN ST
1497 A87HSPDIF2 A87HSPDIF2$ST$Op$phsB BOOLEAN ST
1498 A87HSPDIF2 A87HSPDIF2$ST$Op$phsC BOOLEAN ST
1499 A87HSPDIF2 A87HSPDIF2$ST$Op$q Quality ST
1500 A87HSPDIF2 A87HSPDIF2$ST$Op$t TimeStamp ST
1501 A87HSPDIF2 A87HSPDIF2$CF$Mod$ctlModel CtlModels CF
1502 A87HSPDIF2 A87HSPDIF2$CF$HiSet$minVal INT32 CF
1503 A87HSPDIF2 A87HSPDIF2$CF$HiSet$maxVal INT32 CF
1504 A87HSPDIF2 A87HSPDIF2$CF$HiSet$stepSize INT32U CF
1505 A87HSPDIF2 A87HSPDIF2$CF$RstMod$minVal INT32 CF
1506 A87HSPDIF2 A87HSPDIF2$CF$RstMod$maxVal INT32 CF
1507 A87HSPDIF2 A87HSPDIF2$CF$RstMod$stepSize INT32U CF
VISIBLE
1508 A87HSPDIF2 A87HSPDIF2$DC$NamPlt$vendor DC
STRING255
VISIBLE
1509 A87HSPDIF2 A87HSPDIF2$DC$NamPlt$swRev DC
STRING255
VISIBLE
1510 A87HSPDIF2 A87HSPDIF2$DC$NamPlt$d DC
STRING255
VISIBLE
1511 A87HSPDIF2 A87HSPDIF2$DC$Str$d DC
STRING256
VISIBLE
1512 A87HSPDIF2 A87HSPDIF2$DC$Op$d DC
STRING257
1513 A87HSPDIF2 A87HSPDIF2$SP$HiSet$setVal BOOLEAN SP
1514 A87HSPDIF2 A87HSPDIF2$SP$RstMod$setVal BOOLEAN SP
ntia
Diff
Bia
sed
ere
1515 A87_PDIF1 A87_PDIF1$ST$Beh$stVal BOOLEAN ST

l

`
1516 A87_PDIF1 A87_PDIF1$ST$Beh$q Quality ST

1517 A87_PDIF1 A87_PDIF1$ST$Beh$t TimeStamp ST
1518 A87_PDIF1 A87_PDIF1$ST$Str$general BOOLEAN ST
1519 A87_PDIF1 A87_PDIF1$ST$Str$dirGeneral Enum ST
1520 A87_PDIF1 A87_PDIF1$ST$Str$phsA BOOLEAN ST
1521 A87_PDIF1 A87_PDIF1$ST$Str$dirPhsA Enum ST
1522 A87_PDIF1 A87_PDIF1$ST$Str$phsB BOOLEAN ST
1523 A87_PDIF1 A87_PDIF1$ST$Str$dirPhsB Enum ST
1524 A87_PDIF1 A87_PDIF1$ST$Str$phsC BOOLEAN ST
1525 A87_PDIF1 A87_PDIF1$ST$Str$dirPhsC Enum ST
1526 A87_PDIF1 A87_PDIF1$ST$Str$q Quality ST
1527 A87_PDIF1 A87_PDIF1$ST$Str$t TimeStamp ST
1528 A87_PDIF1 A87_PDIF1$ST$Op$general BOOLEAN ST
1529 A87_PDIF1 A87_PDIF1$ST$Op$phsA BOOLEAN ST
1530 A87_PDIF1 A87_PDIF1$ST$Op$phsB BOOLEAN ST
1531 A87_PDIF1 A87_PDIF1$ST$Op$phsC BOOLEAN ST
1532 A87_PDIF1 A87_PDIF1$ST$Op$q Quality ST
1533 A87_PDIF1 A87_PDIF1$ST$Op$t TimeStamp ST
1534 A87_PDIF1 A87_PDIF1$CF$Mod$ctlModel CtlModels CF
1535 A87_PDIF1 A87_PDIF1$CF$LoSet$minVal INT32 CF
1536 A87_PDIF1 A87_PDIF1$CF$LoSet$maxVal INT32 CF
1537 A87_PDIF1 A87_PDIF1$CF$LoSet$stepSize INT32U CF
1538 A87_PDIF1 A87_PDIF1$CF$RstMod$minVal INT32 CF
1539 A87_PDIF1 A87_PDIF1$CF$RstMod$maxVal INT32 CF
1540 A87_PDIF1 A87_PDIF1$CF$RstMod$stepSize INT32U CF
VISIBLE
1541 A87_PDIF1 A87_PDIF1$DC$NamPlt$vendor DC
STRING255

`
VISIBLE
1542 A87_PDIF1 A87_PDIF1$DC$NamPlt$swRev DC
STRING255
VISIBLE
1543 A87_PDIF1 A87_PDIF1$DC$NamPlt$d DC
STRING255
VISIBLE
1544 A87_PDIF1 A87_PDIF1$DC$Str$d DC
STRING256
VISIBLE
1545 A87_PDIF1 A87_PDIF1$DC$Op$d DC
STRING257
1546 A87_PDIF1 A87_PDIF1$SP$LoSet$setVal BOOLEAN SP
1547 A87_PDIF1 A87_PDIF1$SP$RstMod$setVal BOOLEAN SP
1548 CB_XCBR1 CB_XCBR1$ST$Beh$stVal BOOLEAN ST
1549 CB_XCBR1 CB_XCBR1$ST$Beh$q Quality ST
1550 CB_XCBR1 CB_XCBR1$ST$Beh$t TimeStamp ST
1551 CB_XCBR1 CB_XCBR1$ST$Loc$stVal BOOLEAN ST
1552 CB_XCBR1 CB_XCBR1$ST$Loc$q Quality ST
1553 CB_XCBR1 CB_XCBR1$ST$Loc$t TimeStamp ST
1554 CB_XCBR1 CB_XCBR1$ST$OpCnt$stVal BOOLEAN ST
1555 CB_XCBR1 CB_XCBR1$ST$OpCnt$q Quality ST
Breaker Control
1556 CB_XCBR1 CB_XCBR1$ST$OpCnt$t TimeStamp ST

1557 CB_XCBR1 CB_XCBR1$ST$Pos$stVal BOOLEAN ST
1558 CB_XCBR1 CB_XCBR1$ST$Pos$q Quality ST
1559 CB_XCBR1 CB_XCBR1$ST$Pos$t TimeStamp ST
1560 CB_XCBR1 CB_XCBR1$ST$BlkOpn$stVal BOOLEAN ST
1561 CB_XCBR1 CB_XCBR1$ST$BlkOpn$q Quality ST
1562 CB_XCBR1 CB_XCBR1$ST$BlkOpn$t TimeStamp ST
1563 CB_XCBR1 CB_XCBR1$ST$BlkCls$stVal BOOLEAN ST
1564 CB_XCBR1 CB_XCBR1$ST$BlkCls$q Quality ST
1565 CB_XCBR1 CB_XCBR1$ST$BlkCls$t TimeStamp ST
1566 CB_XCBR1 CB_XCBR1$ST$CBOpCap$stVal BOOLEAN ST
1567 CB_XCBR1 CB_XCBR1$ST$CBOpCap$q Quality ST

`
1568 CB_XCBR1 CB_XCBR1$ST$CBOpCap$t TimeStamp ST

1569 CB_XCBR1 CB_XCBR1$CF$Mod$ctlModel CtlModels CF
1570 CB_XCBR1 CB_XCBR1$CF$Pos$ctlModel CtlModels CF
1571 CB_XCBR1 CB_XCBR1$CF$BlkOpn$ctlModel CtlModels CF
1572 CB_XCBR1 CB_XCBR1$CF$BlkCls$ctlModel CtlModels CF
VISIBLE
1573 CB_XCBR1 CB_XCBR1$DC$NamPlt$vendor DC
STRING257
VISIBLE
1574 CB_XCBR1 CB_XCBR1$DC$NamPlt$swRev DC
STRING258
VISIBLE
1575 CB_XCBR1 CB_XCBR1$DC$NamPlt$d DC
STRING259
1576 CSWI1 CSWI1$ST$Beh$stVal BOOLEAN ST
1577 CSWI1 CSWI1$ST$Beh$q Quality ST
1578 CSWI1 CSWI1$ST$Beh$t TimeStamp ST
1579 CSWI1 CSWI1$ST$Pos$stVal BOOLEAN ST
1580 CSWI1 CSWI1$ST$Pos$q Quality ST
1581 CSWI1 CSWI1$ST$Pos$t TimeStamp ST
1582 CSWI1 CSWI1$ST$Pos$stSeld ST
Switch Control
1583 CSWI1 CSWI1$ST$OpOpn$general BOOLEAN ST

1584 CSWI1 CSWI1$ST$OpOpn$q Quality ST
1585 CSWI1 CSWI1$ST$OpOpn$t TimeStamp ST
1586 CSWI1 CSWI1$ST$OpCls$general BOOLEAN ST
1587 CSWI1 CSWI1$ST$OpCls$q Quality ST
1588 CSWI1 CSWI1$ST$OpCls$t TimeStamp ST
1589 CSWI1 CSWI1$CO$Mod$Cancel$ctlVal CO
1590 CSWI1 CSWI1$CO$Mod$Cancel$origin$orCat Enum CO
1591 CSWI1 CSWI1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1592 CSWI1 CSWI1$CO$Mod$Cancel$ctlNum INT8U CO
1593 CSWI1 CSWI1$CO$Mod$Cancel$T 6 CO

`
1594 CSWI1 CSWI1$CO$Mod$Cancel$Test BOOLEAN CO

1595 CSWI1 CSWI1$CO$Pos$SBOw$ctlVal CO
1596 CSWI1 CSWI1$CO$Pos$SBOw$origin$orCat Enum CO
1597 CSWI1 CSWI1$CO$Pos$SBOw$origin$orIdent OCTET STRING64 CO
1598 CSWI1 CSWI1$CO$Pos$SBOw$ctlNum INT8U CO
1599 CSWI1 CSWI1$CO$Pos$SBOw$T 6 CO
1600 CSWI1 CSWI1$CO$Pos$SBOw$Test BOOLEAN CO
1601 CSWI1 CSWI1$CO$Pos$SBOw$Check CO
1602 CSWI1 CSWI1$CO$Pos$Oper$ctlVal CO
1603 CSWI1 CSWI1$CO$Pos$Oper$origin$orCat Enum CO
1604 CSWI1 CSWI1$CO$Pos$Oper$origin$orIdent OCTET STRING64 CO
1605 CSWI1 CSWI1$CO$Pos$Oper$ctlNum INT8U CO
1606 CSWI1 CSWI1$CO$Pos$Oper$T 6 CO
1607 CSWI1 CSWI1$CO$Pos$Oper$Test BOOLEAN CO
1608 CSWI1 CSWI1$CO$Pos$Oper$Check CO
1609 CSWI1 CSWI1$CO$Pos$Cancel$ctlVal CO
1610 CSWI1 CSWI1$CO$Pos$Cancel$origin$orCat Enum CO
1611 CSWI1 CSWI1$CO$Pos$Cancel$origin$orIdent OCTET STRING64 CO
1612 CSWI1 CSWI1$CO$Pos$Cancel$ctlNum INT8U CO
1613 CSWI1 CSWI1$CO$Pos$Cancel$T 6 CO
1614 CSWI1 CSWI1$CO$Pos$Cancel$Test BOOLEAN CO
1615 CSWI1 CSWI1$CF$Mod$ctlModel CtlModels CF
1616 CSWI1 CSWI1$CF$Pos$pulseConfig$cmdQual CF
1617 CSWI1 CSWI1$CF$Pos$pulseConfig$onDur CF
1618 CSWI1 CSWI1$CF$Pos$pulseConfig$offDur CF
1619 CSWI1 CSWI1$CF$Pos$pulseConfig$numPls CF
1620 CSWI1 CSWI1$CF$Pos$ctlModel CtlModels CF

`
1621 CSWI1 CSWI1$CF$Pos$sboTimeout CF

VISIBLE
1622 CSWI1 CSWI1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1623 CSWI1 CSWI1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1624 CSWI1 CSWI1$DC$NamPlt$d DC
STRING257
1625 DISts_GGIO1 DISts_GGIO1$ST$Beh$stVal BOOLEAN ST
1626 DISts_GGIO1 DISts_GGIO1$ST$Beh$q Quality ST
1627 DISts_GGIO1 DISts_GGIO1$ST$Beh$t TimeStamp ST
1628 DISts_GGIO1 DISts_GGIO1$ST$SPCSO1$stVal BOOLEAN ST
1629 DISts_GGIO1 DISts_GGIO1$ST$SPCSO1$q Quality ST
1630 DISts_GGIO1 DISts_GGIO1$ST$SPCSO1$t TimeStamp ST
Digital Input


`

1652 DISts_GGIO1 DISts_GGIO1$CF$Mod$ctlModel BOOLEAN ST
1653 DISts_GGIO1 DISts_GGIO1$CF$SPCSO1$ctlModel CtlModels CF
VISIBLE
1661 DISts_GGIO1 DISts_GGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1662 DISts_GGIO1 DISts_GGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1663 DISts_GGIO1 DISts_GGIO1$DC$NamPlt$d DC
STRING257
1664 DOSts_GGIO1 DOSts_GGIO1$ST$Beh$stVal BOOLEAN ST
1665 DOSts_GGIO1 DOSts_GGIO1$ST$Beh$q Quality ST
1666 DOSts_GGIO1 DOSts_GGIO1$ST$Beh$t TimeStamp ST
Digital Output
1667 DOSts_GGIO1 DOSts_GGIO1$ST$SPCSO1$q Quality ST

1668 DOSts_GGIO1 DOSts_GGIO1$ST$SPCSO1$stVal BOOLEAN ST
1669 DOSts_GGIO1 DOSts_GGIO1$ST$SPCSO1$t TimeStamp ST

`

1691 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$ctlVal CO
1692 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$origin$orCat Enum CO
1693 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$origin$orIdent OCTET STRING64 CO
1694 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$ctlNum INT8U CO
1695 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$T 6 CO
1696 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$Test BOOLEAN CO
1697 DOSts_GGIO1 DOSts_GGIO1$CO$SPCSO1$Oper$Check CO

`


`

1747 DOSts_GGIO1 DOSts_GGIO1$CF$Mod$ctlModel CtlModels CF
1748 DOSts_GGIO1 DOSts_GGIO1$CF$SPCSO1$ctlModel CtlModels CF

`

VISIBLE
1756 DOSts_GGIO1 DOSts_GGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1757 DOSts_GGIO1 DOSts_GGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1758 DOSts_GGIO1 DOSts_GGIO1$DC$NamPlt$d DC
STRING257
1759 Gen_PTRC1 Gen_PTRC1$ST$Beh$stVal BOOLEAN ST
1760 Gen_PTRC1 Gen_PTRC1$ST$Beh$q Quality ST
1761 Gen_PTRC1 Gen_PTRC1$ST$Beh$t TimeStamp ST
1762 Gen_PTRC1 Gen_PTRC1$ST$Tr$general BOOLEAN ST
General Trip
1763 Gen_PTRC1 Gen_PTRC1$ST$Tr$q Quality ST
1764 Gen_PTRC1 Gen_PTRC1$ST$Tr$t TimeStamp ST
1765 Gen_PTRC1 Gen_PTRC1$CF$Mod$ctlModel CtlModels CF
VISIBLE
1766 Gen_PTRC1 Gen_PTRC1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1767 Gen_PTRC1 Gen_PTRC1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1768 Gen_PTRC1 Gen_PTRC1$DC$NamPlt$d DC
STRING257
1769 LED_GGIO1 LED_GGIO1$ST$Beh$stVal BOOLEAN ST
1770 LED_GGIO1 LED_GGIO1$ST$Beh$q Quality ST
1771 LED_GGIO1 LED_GGIO1$ST$Beh$t TimeStamp ST
1772 LED_GGIO1 LED_GGIO1$ST$SPCSO1$stVal BOOLEAN ST
1773 LED_GGIO1 LED_GGIO1$ST$SPCSO1$q Quality ST
Led
1774 LED_GGIO1 LED_GGIO1$ST$SPCSO1$t TimeStamp ST


`


`

1820 LED_GGIO1 LED_GGIO1$CF$Mod$ctlModel CtlModels CF
1821 LED_GGIO1 LED_GGIO1$CF$SPCSO1$ctlModel CtlModels CF

`

VISIBLE
1837 LED_GGIO1 LED_GGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1838 LED_GGIO1 LED_GGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1839 LED_GGIO1 LED_GGIO1$DC$NamPlt$d DC
STRING257
1840 LLN0 LLN0$ST$Beh$stVal BOOLEAN ST
1841 LLN0 LLN0$ST$Beh$q Quality ST
1842 LLN0 LLN0$ST$Beh$t TimeStamp ST
1843 LLN0 LLN0$ST$LEDRs$stVal BOOLEAN ST
1844 LLN0 LLN0$ST$LEDRs$q Quality ST
1845 LLN0 LLN0$ST$LEDRs$t TimeStamp ST
1846 LLN0 LLN0$CO$Mod$Cancel$ctlVal CO
Logical Node Zero Name
1847 LLN0 LLN0$CO$Mod$Cancel$origin$orCat Enum CO

1848 LLN0 LLN0$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1849 LLN0 LLN0$CO$Mod$Cancel$ctlNum INT8U CO
1850 LLN0 LLN0$CO$Mod$Cancel$T 6 CO
1851 LLN0 LLN0$CO$Mod$Cancel$Test BOOLEAN CO
1852 LLN0 LLN0$CO$LEDRs$Cancel$ctlVal CO
1853 LLN0 LLN0$CO$LEDRs$Cancel$origin$orCat Enum CO
1854 LLN0 LLN0$CO$LEDRs$Cancel$origin$orIdent OCTET STRING64 CO
1855 LLN0 LLN0$CO$LEDRs$Cancel$ctlNum INT8U CO
1856 LLN0 LLN0$CO$LEDRs$Cancel$T 6 CO
1857 LLN0 LLN0$CO$LEDRs$Cancel$Test BOOLEAN CO
1858 LLN0 LLN0$CO$LEDRs$Oper$ctlVal CO

`
1859 LLN0 LLN0$CO$LEDRs$Oper$origin$orCat Enum CO

1860 LLN0 LLN0$CO$LEDRs$Oper$origin$orIdent OCTET STRING64 CO
1861 LLN0 LLN0$CO$LEDRs$Oper$ctlNum INT8U CO
1862 LLN0 LLN0$CO$LEDRs$Oper$T 6 CO
1863 LLN0 LLN0$CO$LEDRs$Oper$Test BOOLEAN CO
1864 LLN0 LLN0$CO$LEDRs$Oper$Check CO
1865 LLN0 LLN0$CF$Mod$ctlModel CTlModels CF
1866 LLN0 LLN0$CF$LEDRs$ctlModel CTlModels CF
VISIBLE
1867 LLN0 LLN0$DC$NamPlt$vendor DC
STRING255
VISIBLE
1868 LLN0 LLN0$DC$NamPlt$swRev DC
STRING256
VISIBLE
1869 LLN0 LLN0$DC$NamPlt$d DC
STRING257
VISIBLE
1870 LLN0 LLN0$DC$NamPlt$configRev DC
STRING258
1871 LLN0 LLN0$GO$gcb3$GoEna 1 GO
1872 LLN0 LLN0$GO$gcb3$GoID 5 GO
1873 LLN0 LLN0$GO$gcb3$DatSet 5 GO
1874 LLN0 LLN0$GO$gcb3$ConfRev 3 GO
1875 LLN0 LLN0$GO$gcb3$NdsCom 1 GO
1881 LPHD1 LPHD1$ST$PhyHealth$stVal BOOLEAN ST
Physical Dev Info Name
1882 LPHD1 LPHD1$ST$PhyHealth$q Quality ST

1883 LPHD1 LPHD1$ST$PhyHealth$t TimeStamp ST
1884 LPHD1 LPHD1$ST$Proxy$stVal BOOLEAN ST
1885 LPHD1 LPHD1$ST$Proxy$q Quality ST
1886 LPHD1 LPHD1$ST$Proxy$t TimeStamp ST
VISIBLE
1887 LPHD1 LPHD1$DC$PhyNam$vendor DC
STRING255
ntia
Diff
ran
asu
Me
ere
ds
1888 MesrMDIF1 MesrMDIF1$MX$OpARem$phsA$cVal$mag$f MX

l

`
1889 MesrMDIF1 MesrMDIF1$MX$OpARem$phsA$q Quality MX

1890 MesrMDIF1 MesrMDIF1$MX$OpARem$phsA$t TimeStamp MX
1891 MesrMDIF1 MesrMDIF1$MX$OpARem$phsB$cVal$mag$f MX
1892 MesrMDIF1 MesrMDIF1$MX$OpARem$phsB$q Quality MX
1893 MesrMDIF1 MesrMDIF1$MX$OpARem$phsB$t TimeStamp MX
1894 MesrMDIF1 MesrMDIF1$MX$OpARem$phsC$cVal$mag$f MX
1895 MesrMDIF1 MesrMDIF1$MX$OpARem$phsC$q Quality MX
1896 MesrMDIF1 MesrMDIF1$MX$OpARem$phsC$t TimeStamp MX
1897 MesrMDIF1 MesrMDIF1$ST$Beh$stVal BOOLEAN ST
1898 MesrMDIF1 MesrMDIF1$ST$Beh$q Quality ST
1899 MesrMDIF1 MesrMDIF1$ST$Beh$t TimeStamp ST
1900 MesrMDIF1 MesrMDIF1$CF$Mod$ctlModel CTlModels CF
VISIBLE
1901 MesrMDIF1 MesrMDIF1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1902 MesrMDIF1 MesrMDIF1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1903 MesrMDIF1 MesrMDIF1$DC$NamPlt$d DC
STRING257
1904 MesrMMXU1 MesrMMXU1$MX$Hz$mag$f MX
1905 MesrMMXU1 MesrMMXU1$MX$Hz$q Quality MX
1906 MesrMMXU1 MesrMMXU1$MX$Hz$t TimeStamp MX
HV Measurement Name
1907 MesrMMXU1 MesrMMXU1$MX$PhV$phsA$cVal$mag$f MX

1908 MesrMMXU1 MesrMMXU1$MX$PhV$phsA$q Quality MX
1909 MesrMMXU1 MesrMMXU1$MX$PhV$phsA$t TimeStamp MX
1910 MesrMMXU1 MesrMMXU1$MX$A$phsA$cVal$mag$f MX
1911 MesrMMXU1 MesrMMXU1$MX$A$phsA$q Quality MX
1912 MesrMMXU1 MesrMMXU1$MX$A$phsA$t TimeStamp MX
1913 MesrMMXU1 MesrMMXU1$MX$A$phsB$cVal$mag$f MX
1914 MesrMMXU1 MesrMMXU1$MX$A$phsB$q Quality MX

`
1915 MesrMMXU1 MesrMMXU1$MX$A$phsB$t TimeStamp MX

1916 MesrMMXU1 MesrMMXU1$MX$A$phsC$cVal$mag$f MX
1917 MesrMMXU1 MesrMMXU1$MX$A$phsC$q Quality MX
1918 MesrMMXU1 MesrMMXU1$MX$A$phsC$t TimeStamp MX
1919 MesrMMXU1 MesrMMXU1$MX$A$neut$cVal$mag$f MX
1920 MesrMMXU1 MesrMMXU1$MX$A$neut$q Quality MX
1921 MesrMMXU1 MesrMMXU1$MX$A$neut$t TimeStamp MX
1922 MesrMMXU1 MesrMMXU1$ST$Mod$stVal BOOLEAN ST
1923 MesrMMXU1 MesrMMXU1$ST$Mod$q Quality ST
1924 MesrMMXU1 MesrMMXU1$ST$Mod$t TimeStamp ST
1925 MesrMMXU1 MesrMMXU1$ST$Beh$q Quality ST
1926 MesrMMXU1 MesrMMXU1$ST$Beh$t TimeStamp ST
1927 MesrMMXU1 MesrMMXU1$ST$Health$stVal BOOLEAN ST
1928 MesrMMXU1 MesrMMXU1$ST$Health$q Quality ST
1929 MesrMMXU1 MesrMMXU1$ST$Health$t TimeStamp ST
1930 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$ctlVal CO
1931 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$origin$orCat Enum CO
1932 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1933 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$ctlNum INT8U CO
1934 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$T 6 CO
1935 MesrMMXU1 MesrMMXU1$CO$Mod$Cancel$Test BOOLEAN CO
1936 MesrMMXU1 MesrMMXU1$CF$Mod$ctlModel CTlModels CF
VISIBLE
1937 MesrMMXU1 MesrMMXU1$DC$NamPlt$vendor DC
STRING255
VISIBLE
1938 MesrMMXU1 MesrMMXU1$DC$NamPlt$swRev DC
STRING256
VISIBLE
1939 MesrMMXU1 MesrMMXU1$DC$NamPlt$d DC
STRING257
rem
asu
Me
LV
ent
me
Na
1940 MesrMMXU2 MesrMMXU2$MX$Hz$mag$f MX

`
1941 MesrMMXU2 MesrMMXU2$MX$Hz$q Quality MX

1942 MesrMMXU2 MesrMMXU2$MX$Hz$t TimeStamp MX
1943 MesrMMXU2 MesrMMXU2$MX$PhV$phsA$cVal$mag$f MX
1944 MesrMMXU2 MesrMMXU2$MX$PhV$phsA$q Quality MX
1945 MesrMMXU2 MesrMMXU2$MX$PhV$phsA$t TimeStamp MX
1946 MesrMMXU2 MesrMMXU2$MX$A$phsA$cVal$mag$f MX
1947 MesrMMXU2 MesrMMXU2$MX$A$phsA$q Quality MX
1948 MesrMMXU2 MesrMMXU2$MX$A$phsA$t TimeStamp MX
1949 MesrMMXU2 MesrMMXU2$MX$A$phsB$cVal$mag$f MX
1950 MesrMMXU2 MesrMMXU2$MX$A$phsB$q Quality MX
1951 MesrMMXU2 MesrMMXU2$MX$A$phsB$t TimeStamp MX
1952 MesrMMXU2 MesrMMXU2$MX$A$phsC$cVal$mag$f MX
1953 MesrMMXU2 MesrMMXU2$MX$A$phsC$q Quality MX
1954 MesrMMXU2 MesrMMXU2$MX$A$phsC$t TimeStamp MX
1955 MesrMMXU2 MesrMMXU2$MX$A$neut$cVal$mag$f MX
1956 MesrMMXU2 MesrMMXU2$MX$A$neut$q Quality MX
1957 MesrMMXU2 MesrMMXU2$MX$A$neut$t TimeStamp MX
1958 MesrMMXU2 MesrMMXU2$ST$Beh$stVal BOOLEAN ST
1959 MesrMMXU2 MesrMMXU2$ST$Beh$q Quality ST
1960 MesrMMXU2 MesrMMXU2$ST$Beh$t TimeStamp ST
1961 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$ctlVal CO
1962 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$origin$orCat Enum CO
1963 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$origin$orIdent OCTET STRING64 CO
1964 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$ctlNum INT8U CO
1965 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$T 6 CO
1966 MesrMMXU2 MesrMMXU2$CO$Mod$Cancel$Test BOOLEAN CO
1967 MesrMMXU2 MesrMMXU2$CF$Mod$ctlModel CTlModels CF

`
VISIBLE
1968 MesrMMXU2 MesrMMXU2$DC$NamPlt$vendor DC
STRING255
VISIBLE
1969 MesrMMXU2 MesrMMXU2$DC$NamPlt$swRev DC
STRING256
VISIBLE
1970 MesrMMXU2 MesrMMXU2$DC$NamPlt$d DC
STRING257
1971 SPC_GGIO1 SPC_GGIO1$ST$Beh$stVal BOOLEAN ST
1972 SPC_GGIO1 SPC_GGIO1$ST$Beh$q Quality ST
1973 SPC_GGIO1 SPC_GGIO1$ST$Beh$t TimeStamp ST
1974 SPC_GGIO1 SPC_GGIO1$ST$SPCSO1$q Quality ST
1975 SPC_GGIO1 SPC_GGIO1$ST$SPCSO1$stVal BOOLEAN ST
1976 SPC_GGIO1 SPC_GGIO1$ST$SPCSO1$t TimeStamp ST
Scada Inputs


`

1998 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$ctlVal CO
1999 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$origin$orCat Enum CO
2000 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$origin$orIdent OCTET STRING64 CO
2001 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$ctlNum INT8U CO
2002 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$T 6 CO
2003 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$Test BOOLEAN CO
2004 SPC_GGIO1 SPC_GGIO1$CO$SPCSO1$Oper$Check CO

`


`

2054 SPC_GGIO1 SPC_GGIO1$CF$Mod$ctlModel CTlModels CF
2055 SPC_GGIO1 SPC_GGIO1$CF$SPCSO1$ctlModel CTlModels CF
VISIBLE
2063 SPC_GGIO1 SPC_GGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
2064 SPC_GGIO1 SPC_GGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
2065 SPC_GGIO1 SPC_GGIO1$DC$NamPlt$d DC
STRING257
2066 VirtIPGGIO1 VirtIPGGIO1$ST$Beh$stVal BOOLEAN ST
2067 VirtIPGGIO1 VirtIPGGIO1$ST$Beh$q Quality ST
2068 VirtIPGGIO1 VirtIPGGIO1$ST$Beh$t TimeStamp ST
Virtual Input
2069 VirtIPGGIO1 VirtIPGGIO1$ST$SPCSO1$stVal BOOLEAN ST

2070 VirtIPGGIO1 VirtIPGGIO1$ST$SPCSO1$q Quality ST
2071 VirtIPGGIO1 VirtIPGGIO1$ST$SPCSO1$t TimeStamp ST

`


`


`


`


`


`


`

2261 VirtIPGGIO1 VirtIPGGIO1$CF$Mod$ctlModel CtlModels CF
2262 VirtIPGGIO1 VirtIPGGIO1$CF$SPCSO1$ctlModel CtlModels CF

`


`


`

VISIBLE
2326 VirtIPGGIO1 VirtIPGGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
2327 VirtIPGGIO1 VirtIPGGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
2328 VirtIPGGIO1 VirtIPGGIO1$DC$NamPlt$d DC
STRING257
2329 VirtOPGGIO1 VirtOPGGIO1$ST$Beh$stVal BOOLEAN ST
2330 VirtOPGGIO1 VirtOPGGIO1$ST$Beh$q Quality ST
2331 VirtOPGGIO1 VirtOPGGIO1$ST$Beh$t TimeStamp ST
2332 VirtOPGGIO1 VirtOPGGIO1$ST$SPCSO1$stVal BOOLEAN ST
2333 VirtOPGGIO1 VirtOPGGIO1$ST$SPCSO1$q Quality ST
Virtual Output
2334 VirtOPGGIO1 VirtOPGGIO1$ST$SPCSO1$t TimeStamp ST


`


`


`


`


`


`


`

2524 VirtOPGGIO1 VirtOPGGIO1$CF$Mod$ctlModel CtlModels CF
2525 VirtOPGGIO1 VirtOPGGIO1$CF$SPCSO1$ctlModel CtlModels CF

`


`


`

VISIBLE
2589 VirtOPGGIO1 VirtOPGGIO1$DC$NamPlt$vendor DC
STRING255
VISIBLE
2590 VirtOPGGIO1 VirtOPGGIO1$DC$NamPlt$swRev DC
STRING256
VISIBLE
2591 VirtOPGGIO1 VirtOPGGIO1$DC$NamPlt$d DC
STRING257

`
Crompton Greaves Ltd.

Power Systems: M. V. Switchgear Division (S2)
A-3, MIDC, Ambad, Nasik - 422010. India.
Tel.: +91 253 2382271 to 75
Email: [email protected]
Visit us at: www.cgglobal.com

`
Registered Office
CG House, 6th Floor, Dr.Annie Besant Road, Worli, Mumbai-400 030
Doc. No.: Aegis-TA-1.001

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`

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

If this is your first CG Protection Relay, we hope it is the beginning of a long

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

Crompton Greaves Limited

MV Switchgear Division (S2)

Phone : (00 91 253) 2382271-75

Fax : (00 91 253) 2381247

@ Copyright 2011 by Crompton Greaves Ltd.

CROMPTON GREAVES LIMITED

@ Copyright 2010 by Crompton Greaves Ltd.

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

1.4.2 Test & Environmental Conditions ................................................................................................ 81

CROMPTON GREAVES LIMITED

4.1.4 Connecting Relay with the Software .......................................................................................... 280

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

Figure 117 - New Dataset ................................................................................................................................... 236

CROMPTON GREAVES LIMITED

Figure 177 - TCS / CCS Settings ........................................................................................................................ 337

CROMPTON GREAVES LIMITED

Figure 237 - DR Trigger Command ................................................................................................................... 388

CROMPTON GREAVES LIMITED

Table 1 - Relay Features ......................................................................................................................................... 5

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

Abbreviations & Symbols

3I> IDMT OC Protection

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED

CROMPTON GREAVES LIMITED PAGE 1

This section describes the overall functioning of CG Aegis Series Transformer

 Relay Settings & Navigation of each menu

 Connections & Wiring Diagram

 Dimensions of the relay

CROMPTON GREAVES LIMITED PAGE 2

Figure 1 - Architecture of Numerical Protection Relay

CROMPTON GREAVES LIMITED PAGE 3

CROMPTON GREAVES LIMITED PAGE 4

1.1.2 Relay Features

ANSI No. FUNCTION NAME

CROMPTON GREAVES LIMITED PAGE 5

1.1.3 Health & Safety

The information in the Safety Section of the equipment documentation is intended to

When electrical equipment is in operation, dangerous voltages will be present in certain

Qualified personnel are individuals who

1.1.3.1 Installing, Commissioning & Servicing

Personnel undertaking installation, commissioning or servicing work for this equipment

CROMPTON GREAVES LIMITED PAGE 6

The equipment documentation should be consulted before installing, commissioning or

Terminals exposed during installation, commissioning and maintenance may present a

Removal of equipment front panel/cover

Equipment operations conditions

CROMPTON GREAVES LIMITED PAGE 7

Current Transformer Circuits