Dlca NOTES
Dlca NOTES
ORGANIZATIONAL DECISION:
STRUCTURE FUNCTION
the way in which components Function is what each part does
relate to each other within the structure.
Data processing
Data storage
Input
Output
Communication
Control
STRUCTURE:
1. TOP LEVEL:
CPU: The computer's control center for data processing.
Main memory: Temporarily stores data for execution.
I/O: Manages data transfer between the computer and external devices.
System interconnection: communication between CPU, memory, and I/O, often through a
system bus.
2. THE CPU
For example:
An operating system that allows a single user to perform only one task at a
Functions like printing a document etc can be performed only one at a time.
Examples include MS-DOS etc.
Disadvantage was Underutilization of resources
Pipelining
• Input
• Control
• ALU
• Registers
• Memory
• Output
Stored-program concept:
Concept to store both instructions and data in one place, making things simpler.
Early computers needed switches and cables to work, but today's computers use one memory
for everything.
CLOCK CYCLE:
The von Neumann bottleneck slows down data transfer between the CPU and memory, limiting
processing speed.
In recent years, while processor speeds have risen, memory improvements have focused on
storing more data in less space, causing processors to wait for data from memory
Making a faster processor often result in more idle time due to the transfer rate bottleneck.
Solution:
MEMORY HIERARCHY
Hard Disk: Used for permanent storage due to its non-volatile nature.
RAM: Executable memory for running software, also known as Primary or Main Memory.
Cache Memory: Speeds up processing by storing recent/frequent instructions and data for quick
access.
Register(s): These are very fast small memories inside theCPU. These are of two types
TYPES OF REGISTERS:
Dedicated Registers: For the exclusive use of CU and cannot be accessed by the user
General Purpose Registers: These are used by programmers for storing data, addresses and
transitional& final results.
Fetch Cycle:
The computer loads the instruction's code into IR and its location into MAR.
The instruction can come from the IBR or memory, passing through MBR, IBR, IR, and MAR.
Decode Cycle:
Once the opcode is in the IR. Control unit interprets the opcode.
Execution Cycle:
Computer's control unit tells ALU what to do, like move data or do a calculation, by sending the
right signals.
IAS instruction set contains 21 instructions. Can be grouped into the following categories:
Data Transfer Instructions: move data between memory and ALU registers.
Arithmetic: operations performed by the ALU.
Unconditional Branch: These instructions make the computer jump to a different part of the
program without considering any conditions.
Conditional Branch: These instructions make the computer decide whether to jump to a
different part of the program based on specific conditions.
Address Modify Instructions: let the computer calculate new addresses using the ALU and put
them into instructions stored in memory, making it very flexible.
IAS REGISTERS
PROGRAMMING:
A FIVE-STEP PROCEDURE: