Computer Aided Design For Vlsi

COMPUTER AIDED DESIGN
FOR VLSI
1. (a) Synthesis:
Synthesis is the process of combining simpler components or elements to create a
unified and more complex whole. In electronics, it often refers to generating a logic
circuit or design from a high-level description.
(b) Simulated Annealing:

Simulated Annealing is a probabilistic optimization algorithm inspired by
metallurgical annealing. It finds approximate solutions by iteratively exploring a
solution space, allowing both uphill and downhill moves, with decreasing probability
for accepting worse solutions over time.
(c) Hardware Abstract Model:

A Hardware Abstract Model (HAM) is a representation that abstracts hardware
details, providing a higher-level understanding of behavior and structure. It simplifies
the description of hardware systems without focusing on specific implementations.
(d) Compilation:
Compilation is the translation of high-level programming code into machine code or
intermediate code using a compiler. It involves multiple stages, including analysis and
optimization, resulting in an executable file or code that can be run on a computer.
2. Flow Chart in CAD:
Creating a flow chart for Very Large Scale Integration (VLSI) design in Computer-Aided
Design (CAD) involves illustrating the various stages and steps involved in the design
process.
VLSI Design Flow Chart in CAD:
Start: Begin the flow chart with the "Start" symbol.
Specification: Specify the design requirements and constraints. Use a rectangle to represent
this step.
Conceptualization: Conceptualize the design, considering high-level architecture and

functionality. Use a rectangle for this step.
RTL Design: Perform Register-Transfer Level (RTL) design to describe the digital circuit's
behavior. This involves creating an abstract representation of the digital logic. Use a
rectangle for this step.
Functional Simulation: Simulate the RTL design to ensure it meets functional requirements.
Use a rectangle for this step.
Synthesis: Use synthesis tools to convert the RTL code into a netlist, specifying the logic
gates and their interconnections. Represent this step with a rectangle.
Floor Planning: Plan the physical layout of the chip, considering the placement of functional
blocks and I/O pads. Use a rectangle for this step.
Place and Route: Place the logical elements onto the chip and route the interconnections.
Physical Verification: Perform physical verification to check for design rule violations and
ensure the layout meets manufacturing requirements. Use a rectangle for this step.
Timing Analysis: Analyze the timing characteristics of the design to ensure proper
functionality and performance. Use a rectangle for this step.
Gate-Level Simulation: Simulate the gate-level net list to verify the design's functionality at
a lower abstraction level. Use a rectangle for this step.
Design Verification: Verify the entire design using various tests and simulations to ensure it
meets specifications. Use a rectangle for this step.
Final Net list: Generate the final net list that will be used for manufacturing. Use a rectangle
for this step.
Mask Generation: Generate the masks needed for the semiconductor manufacturing process.
Fabrication: Begin the fabrication process to manufacture the integrated circuit. Use a
rectangle for this step.
Testing: Test the fabricated chips to ensure they meet quality and functionality standards.
End: End the flow chart with the "End" symbol.
3. BDD and OBDD:

BDD (Binary Decision Diagram):
Definition: A Binary Decision Diagram (BDD) is a directed acyclic graph (DAG)
representation of a Boolean function. It is a compact way to express and manipulate Boolean
expressions.
Nodes: BDDs consist of nodes, where each node represents a decision variable (Boolean
variable) and has two outgoing edges corresponding to the variable's values (0 and 1).
Compact Representation: BDDs provide a compact representation of Boolean functions,

enabling efficient manipulation and analysis of logic circuits.
Variable Order: The efficiency of BDDs depends on the order in which variables are
chosen. Different variable orders can result in different-sized BDDs for the same function.
OBDD (Ordered Binary Decision Diagram):

Definition: An Ordered Binary Decision Diagram (OBDD) is a type of BDD where the
variables have a fixed, predetermined order. This order is crucial for maintaining the
canonical form of the BDD.
Canonical Form: OBDDs have a canonical form, meaning that there is a unique
representation for each Boolean function. This canonical form allows for efficient
comparison and manipulation of BDDs.
Reduced Size: Because of the fixed variable order, OBDDs often have a reduced size
compared to generic BDDs. This reduction in size contributes to more efficient storage and
manipulation.
Efficient Operations: OBDDs support efficient operations such as conjunction, disjunction,

and negation of Boolean functions. These operations are crucial in symbolic model checking
and formal verification.
4. Scheduling In CAD for VLSI:
In CAD for VLSI, scheduling involves planning and organizing tasks in the design process.
This includes allocating resources, determining task order, and managing timelines
efficiently. Key aspects include task allocation, resource management, parallel processing,
dependency analysis, tool integration, critical path analysis, and contingency planning.
Efficient scheduling is crucial for optimizing design processes and meeting project deadlines.
Key Aspects of Scheduling in CAD for VLSI:

 Task Allocation: Assign design activities such as RTL design, synthesis, layout, and
testing to team members based on expertise.
 Resource Management: Efficiently allocate computational resources, like servers, for
different stages of the VLSI design flow.
 Timeline Planning: Establish realistic timelines for each design stage, considering
project deadlines and dependencies.
 Critical Path Analysis: Identify and optimize the critical path, the sequence of tasks
determining the overall project duration.
 Quality Assurance and Contingency: Allocate time for testing, verification, and
incorporate contingency plans to address unforeseen challenges.
5. Sequencing Diagrams in CAD for VLSI:

In the context of CAD (Computer-Aided Design) for VLSI (Very Large Scale Integration),
sequencing diagrams typically refer to the chronological representation of different steps or
processes involved in the design flow. These diagrams illustrate the order in which various
design activities occur during the creation of integrated circuits.
 RTL Design and Simulation: Begin with Register-Transfer Level (RTL) design,
describing digital logic using HDLs. Simulate to ensure functionality.
 Synthesis and Floor Planning: Synthesize the design into a netlist and perform floor
planning to determine physical layout and block placement.
 Place and Route: Execute place and route processes, positioning logic elements on the
chip and establishing interconnections.
 Verification and Timing Analysis: Verify the design through gate-level simulation and
comprehensive testing. Conduct timing analysis for performance assessment.
 Manufacturing and Testing: Proceed to mask generation, fabrication, and testing to
ensure the quality and functionality of the manufactured integrated circuit.

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COMPUTER AIDED DESIGN

(b) Simulated Annealing:

(c) Hardware Abstract Model:

VLSI Design Flow Chart in CAD:

Start: Begin the flow chart with the "Start" symbol.

Conceptualization: Conceptualize the design, considering high-level architecture and

End: End the flow chart with the "End" symbol.

3. BDD and OBDD:

Compact Representation: BDDs provide a compact representation of Boolean functions,

OBDD (Ordered Binary Decision Diagram):

Efficient Operations: OBDDs support efficient operations such as conjunction, disjunction,

Key Aspects of Scheduling in CAD for VLSI:

5. Sequencing Diagrams in CAD for VLSI:

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