2023 4th International Conference on Signal Processing and Communication (ICSPC) | 23-24 March 2023 | Karunya Institute of Technology

and Sciences, Coimbatore, India.

Functional Verification of SPI Protocol using UVM

based on AMBA Architecture for Flash Memory
Applications
Shaila C K G Manoj
2023 4th International Conference on Signal Processing and Communication (ICSPC) | 979-8-3503-0077-2/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICSPC57692.2023.10125890

Department of Electronics and communication Department of Electronics and communication

Karunya Institute of Technology and Science (KITS) Karunya Institute of Technology and Science (KITS)
Coimbatore, India Coimbatore, India
shailac@karunya.edu.in manojpillai@karunya.edu

Divya P.S. Vijila. M

Department of Mathematics Department of Mathematics
Karunya Institute of Technology and Science (KITS) Karunya Institute of Technology and Science (KITS)
Coimbatore, India Coimbatore, India
divya_deepam@karunya.edu vijilamoses@karunya.edu

Abstract—Effective verification of circuit designs is required protocol data transfer is between the slave and master.[4]. Before
because integrated circuit designs keep growing, and hence the attempting to transmit again, a device that is transmitting data must
process of verification is becoming major challenging and read the incoming data. The devices always exchange data with one
prolonging action. Hence, there is a need for a robust testbench another. A device acts as both transmitter and receiver. [3]. Between
hierarchy that contains essential common control components the devices the data exchange is done by clock line namely SCK,
which are widely transformable and can be simply extended to which is controlled by the master device.
models. One architecture that implements architectures for The UVM Class Library, the units are provided to create test
testbench in verification environments along coverage with CRT environments and verification components(reusable), is used to
is the Hierarchy of Universal Verification Methodology (UVM) model the entire architecture in this research project. [5,6].
(Limited Random Test). According to the verification strategy The bus protocol and the specifications, which is more suited to
developed following a thorough analysis of the SPI protocol reusing IP, must be followed in the development of IP. Applications
specifications, the current work is appropriately focused on the for the AMBA bus abound on system chips built around the ARM
SPI Single Master and Multiple Slave protocol based on UVM processor. Additionally, the ARM processor holds a dominant share
verification. The UVM test bench targets on bringing forth in the embedded sector. As a result, the AMBA bus protocol enjoys
random vectors that are fed to a DUT (Design Under Test) or widespread acceptance both domestically and internationally and is
SPI module and compares them with the output secured by a the industry standard for on-chip bus architecture. Hence, the
scoreboard. This procedure helps to validate SPI functionality. creation of communication protocols using AMBA bus has
The SPI interface has flexible bandwidth and frequency and can significant current and future utility. SPI is a communication
give and take data from multiple slaves and powerful APB SPI protocol that is frequently used in the AMBA bus architecture and
controllers. An SPI device is difficult to manage over the AMBA has a variety of benefits, including user friendly, resource
bus because it is usually attached to the main data bus of the conservation, dependability, and stability. To make sure it can be
system, such as the AMBA APB bus interface core. In the field used for IP reuse, this research created the SPI protocol and
of embedded systems, flash memory has gained its significance. performed front-end design and functional verification on it.
This paper describes how an analog FPGA-based SPI FLASH
memory system can be used in various applications by taking
advantage of its features such as parallelism, reconfiguration,
fast real-time and high speed.

Keywords— SPI, APB, AMBA, UVM, Flash Memory, System

Verilog.

I. INTRODUCTION
The majority of the SOC is made up of various peripherals,
including registers, memories, digital to analogue converters, and
others. As a result, data transmission and reception between the
various connected peripherals inside the SOC are required. Often
used most popular serial interface for intra and inter-chip normal
speed data transfers is serial peripheral interface (SPI). It is utilised
to transfer data between a processor and various hardware Fig. 1:SoC for Flash Memory
components, such as external memory, data conversion circuits, etc.
[1]. SPI is usually referred to as a "little" interface communication Due to its less power consumption, low pin count, high speed,
in the world of protocols. It's critical to keep in mind each protocol's increased capacity, low cost, and lack of data loss after a power
goal. Meanwhile communication between low to medium speed data outage, FLASH memory is utilized in many applications in
exchange with on board peripherals is good using SPI. embedded sector. The widespread use of SPI+FLASH in many
Communication with outside world and data transfer inside the fields has exposed a number of issues. For instance, even though
system is done using Ethernet, USB, and SATA. [2], [3]. In SPI FLASH works quickly in bigger data volumes, instructions and

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311
timing of Flash are complicated, and repeatedly rewriting in small
volumes of data is not simple or flexible. Applications which
involve high-speed data transmission clearly benefit from the
FPGA's high integration and flexibility, low power consumption,
good speed, and real-time performance. The most common remedy
is to apply an FPGA to oversee the SPI+FLASH memory system.
This involves using the FPGA as the controller to control the
SPI+FLASH and perform various operations like reading, erasing
and writing of FLASH while also receiving commands from the host
computer.

The rest of this paper is structured as follows. Section II gives a brief

overview of SPI, Section III describes the research
methodology/verification platform, Section IV deals with AMBA
architecture, Section V gives an idea about SPI Flash Memory, Fig. 2. SPI single master communicating with multiple slaves
Section VI shows the simulation results. Finally, in Section VII
The logic signal lines, Master Out Slave In (MOSI), Master in Slave
deals with performance and discussions.
Out (MISO), Serial Clock (SCLK), and Slave Select (SS), are part
of the SPI bus interface during data transmission (SS). For creating
II. SERIAL PERIPHERAL INTERFACE a synchronised transfer between the master and slave, use Master
Out Slave In (MOSI). Additionally, it is in charge of the uni- or bi-
The serial peripheral interface's control and data signals govern how directional transmission of data from the master to the slave. The
information is communicated between master and slave devices in four signals are as follows:
SPI. There are two different kinds of control signals: a clock signal
and either slave select (SS) or chip select (CS) (SCLK). There are • Master in Slave out (MISO)
two data signals: master output slave input (MOSI) and master input
• Master out Slave in (MOSI)
slave output (MISO). Depending on the clock polarity (CPOL) and
clock phase, the chip-select line's selects, the respected slave, and • Slave Select (SS)
the data will read or write when it is active low (CPHA). When the • Serial Clock (SCLK)
chip select signal is high, the clock signal writes and reads the data
addresses from the clock pulses. Through MOSI and MISO signals, The function of each port is given below:
data is sent from the master to the slave and from the slave to the Master Out Slave In (MOSI) - It is in charge of master to slave
master. Data can be transferred in four different ways using clock data transmission in a single direction.
polarity and clock phase. Table 1 represents the SPI Modes with Master in Slave Out (MISO) - A unidirectional signal line, the
clock polarity. MOSI is set up as an output line in a slave unit and an input signal
in a master device.
Table 1. MODES OF SPI
Slave Select – The slave device is chosen using the slave select
signal, which also serves as a signal to select chip. It is an active low
MODE Clock Polarity Clock Phase signal that needs to remain low throughout the transmission.
(CPOL) (CPHA) Serial Clock (SCLK) - The output MOSI and input MISO signal
lines are synchronised for data transfer using the serial clock line.
0 0 0 The SPI master and slave are further designed in accordance with
the data layout and control lines, and the transaction is initialised in
1 0 1
8,16,and 32 bit widths.
2 1 0 Features of SPI:
1. Full duplex communication.
3 1 1
2.Better and Higher output than I2C (integrated Interface circuit).
3. During bit transferring, bit size is not limited.
One master device and multiple slave devices are both compatible 4. Better and Simple hardware interface.
with the SPI bus. If only one slave unit is being utilized, the Slave 5. Low Power requirement.
Select pin could potentially be down to zero. We can infer from the
Fig 2 that until full-duplex communication is possible, data can be III. SPI BUS VERIFICATION PLATFORM
transferred to multiple slaves by proper selection of slave selection The DUT and test case are typically instantiated by UVM-based
signal. By using other logics or discrete input/output pins, the master verification platforms to make the connection between the DUT and
produces signals for the slave selection. The edges of the clock test case. Test cases of many kinds will use varying configurations
signal that are used to drive and sample the data are determined by and input stimuli to cover various test scenarios while maintaining
two parameters known as clock polarity (CPOL) and clock phase the same verification environment. As a result, the simulator will
(CPHA). Since there are two possible states for each of the two firmly incorporate the test case during the simulation regression and
parameters, there are four possible combinations that cannot be compiles only the static verification environment once. The layered
made. UVM verification architecture is shown in Fig.3. The structure of
the environment houses the scoreboard, reference model, adapter,
agent, and other components, while the layout of the agent houses
the sequencer, driver, and monitor. To reflect the encapsulation
features of object-oriented languages, the components of same
transactions are grouped together by the agent. The sending of input
stimuli or sequence is controlled by the sequencer. The
transformation of the register signal to the bus signal is the
responsibility of the adapter. Although they do not create content,
the driver and the monitor are in charge of its conversion. For the

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312
ease of engineers to control, the driver can convert transaction level bridge ought to act as a slave device for both. The bridge becomes
stimuli to signal level stimuli that the DUT can recognize, whereas more than just a simple location for data exchange as a result of these
the DUT line output is converted to transaction level data by the problems. It should have a sophisticated control system with
monitor that is easy to understand. The ideal value of the information memory units and an error-handling system. Such a construction
or data is represented by outcome of the reference model. The does, however, allow for a reduction in processor usage when it
scoreboard compares the two data which are transmitted from the comes to the link to external devices. The structure shown in Fig.3
monitor which obtains the actual value of data. The APB bus contributes four major activities:
transmits the signal to APB master agent, which is typically the • control,
master device also acts as input agent. The DUT is paired with an • data storage,
output agent known as SPI, one of which is a slave device and the • synchronization,
other a master device. • serialization.
It is necessary to use "first in, first out" (FIFO) buffers. The two
FIFO memories receive signal transmissions in memory words of
the user's chosen length. The memory address is automatically
increased after each read/write cycle. The system clock synchronises
the quick APB transmission, whereas the much slower SPI
transmission may have a different clock period. The system clock
and SCK are synchronised by the edge detector in order to avoid
mis-detecting the data and finds the edges at the nSS line, which are
critical for the auto-incremented memory. The knowledge is saved
in memory words. The serializer and de-serializer enable the
serialisation of parallel data from memory for SPI transmission or
reception. Control is handled by the control unit communicated to
Fig. 3. Bus verification platform for SPI the address decoder. It finds the selection of a bridge, keeps track of
data flow, alerts the user to faults, resets the bridge, and sends
transmission acknowledgement. Data overflow and reading of a
IV. AMBA ARCHITECTURE vacant FIFO is prevented by control unit. A specified input word can
Architecture of APB/SPI bridge is shown in Fig. 3. The APB bus read the status register, which is automatically updated to reflect any
relies on parallel transmission and needs a large data bus (Fig.4), exception, if one occurs. By writing the right value to the right
usually with 32 bits for the data read bus (PRDATA) and 32 bits for register, the reset could be both hard (hardware) and soft (software).
the data write bus (PWDATA). The device address bus (PADDR)
and the protocol-specified signals clock (PCLK), slave select
V. SPI FLASH MEMORY
(PSEL), write (PWRITE), write/read enable (PENABLE), and
acknowledge are additionally necessary (PREADY). The High-performance non-volatile memory, also known as FLASH
transmission and system clock are in sync. memory, is a type of memory system that merge the privileges of
RAM and ROM, transfers data fast, and maintains data when power
is lost for an extended period of time, much like a hard drive. The
main distinction between FLASH and EEPROM is that each unit are
erased using FLASH, whereas bytes are erased using EEPROM.
There are also differences in the addressing schemes and the storage
unit's structural design. EEPROM is often used as data storage
which is nonvolatile than FLASH because of its simpler circuit
structure, lower cost, and smaller chip area per unit of capacity.
FLASH is therefore well suited for storing programs. The two most
popular non-flash memory technologies are NOR and NAND. Using
a memory block a permanent memory called FLASH can be reset
and reprogrammed. At all time, erasing data ought be completed
before writing, because FLASH writing can only be done on deleted
or deleted cells. While erase operations in NAND memory are fairly
simple, erase operations in NOR mode require all bits in the target
block to be reset to zero first. [7].
The FLASH chip the MX25L3206E shown in Fig 5 was selected
for this study. It has 64 Blocks, each of which is composed of 16
Sectors. Each section has 12 memory addresses, and every block can
be individually erased. Up to 64k bytes of data can be stored in each
block and every section up to 4k bytes of data. If the instructions are
followed, each Block can be completely erased. Figure 4 below
Fig. 4. The Architecture of APB/SPI bridge displays the serial flash memory block diagram. There are two
output modes: one with 33554432x1 bits and the other with
Depending on the number of peripherals, the SPI only has 3 to 4 16777216x2 bits. The SPI protocol is compatible with both SPI0 and
wires: master out slave in (MOSI), slave select (nSS), serial clock SPI3 method of operation, and the voltage at which it operates for
(SCK), and master in slave out (MISO). Because SPI transmission erasing, reading, and writing data on this chip is -2.7 to 3.6 volts.
rarely exceeds 1 Mbit/s, it is significantly slower than APB but much The region that is protected from page programming and erasure
more useful for external devices. instructions is identified by the block storage protection function
The Advanced Peripheral Bus/Serial Peripheral Interface bridge using the bp3-bp0 state bit. This chip can transfer data via a three-
needs to be "unseen" to both the Central Processing Unit and the wire bus thanks to the SPI interface and a software protocol that
peripheral. In addition, SPI is very much slower than APB, for includes a Serial Clock Input (SCLK), Serial data (SI) and Serial
asynchronous communication between CPU and a peripheral, the data Outputs (SO). The CS input enables serialization of the device.

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313
During bidirectional output read mode, the Serial Input and Serial
Output signals of the chip become SIO0 and SIO1 pins for
communication. Status registers are built into the chip to provide
practical user interfaces for users and to indicate the status of the
chip. A read status register instruction can find out whether a page
program command or an erase command has been executed by
looking up the WIP bit. During the off state of the device, it is in
standby mode with high CS.
Status register will be checked to make sure that the device is ready
for the operation. The memory enters standby mode when
unauthorized instruction is received to the device. It stays in standby
mode till correct command is inputted to the device. Access to
memory array is neglected when a write status register operation is
in progress.

Fig. 7. RTL Module for the AMBA Architecture

The RTL Module for the AMBA Architecture for the SPI
is represented in the Fig 7 for the Flash memory applications.
Synthesis report for the AMBA Architecture is given in the Table 2.

Table 2: RTL Synthesis report

Parameters AMBA Register Control SPI

Bank Logic Master-
Slave
No. of Slices 54 out of 106 out of 121 out of 13 out of
4567 3232 6776 7165
(1.18%) (0.03%) (0.02%) (0.002%)
No. of input 76 out of 128 out of 224 out of 56 out of
LUT 7657 7299 7167 7882
Fig. 5. Block Diagram of Serial Flash Memory (0.99%) (0.02%) (0.03%) (0.007%)
No. of 10 out of 236 out of 152 out of 37 out of
bounded IOBs 7156 8773 131 121 24%
VI. SIMULATION RESULTS (0.14%) (0.03%) (1.16%) (0.31%)
Number of 1 out of 8 1 out of 8 1 out of 8 1 out of 8
This part offers information on simulation outcomes of the current GCLK (12.5%) (12.5%) (12.5%) (12.5%)
Single Master Multiple Slave Design Under Test (DUT). For
efficient performance in a tight space, the DUT is connected to the
generator module, interface module and control and display
modules. Using the EDA-Playground tool, the simulation is carried 50
AMBA
out following the integration phase. Additionally, UVM 45
methodology-based DUT verification gives out result using the Register Bank

EDA-Playground tool along with the mentor questa 2021.3 and 40 Control Logic
Percentage of Utilization

synopsys VCS 2021.09 simulator tools. The simulation of the the 35 SPI Master-Slave
UVM shown in the Fig 6. 30

25

20

15

10

0
No. of Slices No. of input LUT No. of bounded IOBs Number of GCLK
Parameters

Fig. 8. Utilization percentage of the AMBA architectures

A utilization resource of the AMBA architectures of SPI modeling

Fig. 6. UVM Simulation Result for AMBA Architecture for flash memory is shown in the Fig 8.

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314
 VII. CONCLUSION [17] PallaviPolsani, V. Priyanka B., Y. Padma Sai, “Design & Verification
of Serial Peripheral Interface (SPI) Protocol”, International Journal of
Recent Technology and Engineering (IJRTE) ISSN: 2277-3878,
In this study, System Verilog is used to create a UVM environment Volume-8 Issue-6, March 2020
for the SPI protocol. Full duplex serial communication between a [18] Deepika, Jayanthi K Murthy “Interrupt Enabled Priority Based Master
single master and multiple slave modules can be verified and Slave Communication using SPI Protocol”, International Journal of
validated by using test bench. The AMBA architecture, which Innovative Technology and Exploring Engineering (IJITEE), ISSN:
connects the APB and SPI protocols, is also covered in this essay. 2278-3075, Volume-9 Issue-9, July 2020
SPI is used in real-time, high-speed applications, and can interface [19] N.Venkateswara Rao, PV Chandrika, Abhishek Kumar and Sowmya
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