Embedded Low-Power

Embedded System
Application
4190.303C
Laboratory

2010 Spring Semester

Serial Communication
ELPL

Naehyuck Chang
Dept. of EECS/CSE
Seoul National University
[email protected]
Introduction to System-on-Chip
i4040 - the first-generation microprocessor
Very low density even for a complete microprocessor core
Too expensive glue logic implementation when TTL is used
Companion chips

4008/4009 standard memory and I/O interface set

4040 4-bit Central Processor Unit with 60 instructions
4101 256 x 4 RAM
4201 clock generator
4265 programmable general purpose I/O device
4269 programmable keyboard display device
4289 standard memory interface
4308 1024-bit mask programmable ROM and four 4-bit I/O Ports
4316/2316 2048-bit ROM
4702/1702 2048-bit Erasable and Electrically Reprogrammable MOS ROM (Static)

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Introduction to System-on-Chip
Companion chips continued until 16-bit microprocessors became popular
Z80 CPU, SIO, PIO, etc.
Microcontrollers
16-bit or 32-bit microprocessor cores
Enough transistor density to accommodate other necessary peripherals

ARM920T™ Microprocessor Core

• AHB to IP Bus Interfaces (AIPIs)
• External Interface Module (EIM)
• SDRAM Controller (SDRAMC)
• DPLL Clock and Power Control Module
• Three Universal Asynchronous Receiver/Transmitters (UART 1, 2, and 3)
• Two Serial Peripheral Interfaces (SPI1 and SPI2)
• Two General-Purpose 32-bit Counters/Timers
• Watchdog Timer
• Real-Time Clock/Sampling Timer (RTC)
• LCD Controller (LCDC)
• Pulse-Width Modulation (PWM) Module
• Universal Serial Bus (USB) Device
• Multimedia Card and Secure Digital (MMC/SD) Host Controller Module
• Memory Stick® Host Controller (MSHC)
• Direct Memory Access Controller (DMAC)
• Two Synchronous Serial Interfaces and an Inter-IC Sound
(SSI1 and SSI2/I2S) Module
• Inter-IC (I2C) Bus Module
• Video Port

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Introduction to System-on-Chip
System-on-chip (SoC) or system-on-a-chip
Integrating all components of a computer or other electronic system into a single chip
Microcontrollers usually have limited on-chip memory
Typical specifications
One microcontroller, microprocessor or DSP core(s)
Multiple-core systems are called MPSoC
Memory blocks including a selection of ROM, RAM, EEPROM and Flash
Timing sources including oscillators and phase-locked loops
Peripherals including counter-timers, real-time timers and power-on reset generators
External interfaces including industry standards such as USB, FireWire, Ethernet, USART, SPI, etc.
Analog interfaces including ADCs and DACs
Voltage regulators and power management circuits
Peripherals actually differentiate the value of an SoC

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Introduction to System-on-Chip
How to promote a microprocessor?
ARM-based microcontroller products
What makes the designer select a particular ARM-based microcontroller?

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Introduction to System-on-Chip
Device selection points
Not only the CPU core is important!  CAN
 Flash (Bytes)
 Ethernet MAC
Key to success for Core-A  SRAM (Bytes)
 RTC/RTT
 Cache Memory (Bytes)
 ADC Channels
 LCD Controller
 DAC Channels
 Image Sensor Interface
 Peripheral DMA
 External Bus Interface Channels
 SDRAM Interface  Max. Clock Speed (MHz)
 MMU/MPU  PWM Controller
 AES Engine (Bits)  I/O Pins number
 Triple DES Engine (Bits)  I/O Voltage Domain (V)
 USB Host Controller  High Current Pads
 USB Device Controller  16-bit Timers
 Enhanced USART  Power-On-Reset
 USART/DBGU  Brown Out Detection
 SPI  On-chip RC Oscillator
 TWI  Crystal Oscillator/PLL
http://www.st.com/mcu/files/mcu/1208848572.pdf  SSC  Period Interval Timer
 MCI  Watchdog Timer

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Introduction to System-on-Chip
There is a big gap between the component development and system development
Developers often consider solution support more importantly than the performance of the
microprocessor core
System design solution is a bridge across a death valley

System design solution

Component Commercial
development system
products

Death Valley

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Serial Communication
Communication
Data transmission between two different domains
On-chip-, on-board, in system, or inter system communications
Parallel communication
Transmit and receive a byte or word data simultaneously with parallel links such as a printer port
Serial communication
Parallel data → serialize → transmit → parallelize → parallel data
Better for long distance communication
Low wire cost
Low signal conditioning cost
Speed penalty for serial transmission → overcome by high bit rate

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Serial Communication
Transmit bits in a single channel
Simplex (one way)
Half-duplex (one direction at a time)
Full-duplex (two way)
A sequence of bits – packet or character
ASCII code – 7 bits for 128 characters (alphabet, numerical, and control)
Start, stop, and parity bits
Binary code - not necessarily be 8 bit multiple
Fixed length or variable length

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Principle of Operation

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Synchronous Communication

Synchronized!

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Synchronous Communication

Local clock

Local clock

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Synchronous Communication
Synchronous communication
Use of the same clock is not feasible
Direct transmission of the clock signal is not practical
Send clock information with data
Complex encoding but high bit rate
DC balance

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Synchronous Communication
Synchronous communication
Use of the same clock is not feasible
Direct transmission of the clock signal is not practical
Send clock information with data
Complex encoding but high bit rate
DC balance

Long packet is feasible

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Asynchronous Serial Communication - UART
Asynchronous communication
Use of lock clocks for both ends
Local clocks are not synchronized → eventually skewed
Oversampling and re-synchronization with start and stop bit information
Simple encoding but slow bit rate → start and stop for every 8 bits
Universal asynchronous receiver/transmitter
General purpose
Baud rate
Generally 57600 bps, 115200 bps
Up to ~10 Mbps

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Asynchronous Serial Communication - UART
Asynchronous communication
Use of lock clocks for both ends
Local clocks are not synchronized → eventually skewed
Oversampling and re-synchronization with start and stop bit information
Simple encoding but slow bit rate → start and stop for every 8 bits
Universal asynchronous receiver/transmitter
General purpose
Baud rate
Generally 57600 bps, 115200 bps
Start Stop
Up to ~10 Mbps Short packet

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General UART Definitions
Bit time
The period of time required to serially transmit or receive 1 bit of data (1 cycle of the baud rate
frequency)
Start bit
The bit time of a logic 0 that indicates the beginning of a data frame
A start bit begins with a 1-to-0 transition, and is preceded by at least 1 bit time of logic 1
Stop bit
1 bit time of logic 1 that indicates the end of a data frame
BREAK
A frame in which all of the data bits, including the stop bit, is logic 0
This type of frame is usually sent to signal the end of a message or the beginning of a new
message

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General UART Definitions
Frame
A start bit followed by a specified number of data or information bits and terminated by a stop bit
The most common frame format is 1 start bit followed by 8 data bits (least significant bit first) and
terminated by 1 stop bit
An additional stop bit and a parity bit also can be included
Framing error
An error condition that occurs when the stop bit of a received frame is missing
Usually when the frame boundaries in the received bit stream are not synchronized with the
receiver bit counter
Framing errors can go undetected if a data bit in the expected stop bit time happens to be a logic
1
A framing error is always present on the receiver side when the transmitter is sending BREAKs
However, when the UART is programmed to expect 2 stop bits and only the first stop bit is
received, this is not a framing error by definition

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General UART Definitions
Parity error
An error condition that occurs when the calculated parity of the received data bits in a frame does
not match the parity bit received on the RXD input
Parity error is calculated only after an entire frame is received
Overrun error
An error condition that occurs when the latest character received is ignored to prevent overwriting
a character already present in the UART receive buffer (RxFIFO)
An overrun error indicates that the software reading the buffer (RxFIFO) is not keeping up with the
actual reception of characters on the RXD input

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UART Architecture
Functional block diagram
Serializer
CPU interface
From the perspective of CPU, the whole module is a memory which can be read (Rx) and written (Tx) with
control registers
Each registers are assigned with a fixed address in a on-chip bus address space
Baud rate generator
Provides clocks for Rx/Tx modules
Generates a high frequency up-sampling clock Interrupt
for the Rx module Control
FIFOs and interrupt control
CPU cannot keep polling the availability of
shift registers Control Baud Rate
Registers Generator

CPU Rx
Rx FIFO
Interface Shift Reg.

Tx
Tx FIFO
Shift Reg.

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UART Architecture

HOST 1 Interrupt
Control

Control Baud Rate

Registers Generator

CPU CPU Rx FIFO Rx

Interface Shift Reg.

Tx FIFO Tx
Shift Reg.

HOST 2 Interrupt
Control

Control Baud Rate

Registers Generator

CPU CPU Rx FIFO Rx

Interface Shift Reg.

Tx FIFO Tx
Shift Reg.

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Terminal and Terminal Emulator
Dummy terminal
Terminal emulator

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DTE and DCE
Data terminal equipment
Data circuit-terminating equipment

Crossover cable

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EIA RS232
International standard for serial communication
Connection and signal characteristics
Data terminal equipment and data communication equipment
Logic 1 (marking)
-3 V to -25 V with respect to signal ground
Logic 0 (spacing)
+3 V to +25 V
Not assigned
between -3 V and +3 V
(a transition region)

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TTL – RS232C Level Conversion
Most UARTs’ signals are TTL, LVTTL, CMOS, LVCMOS, etc.
Level converters are mandatory
Old-fashioned TTL to RS232 level converter
LM1488 and LM1489

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TTL – RS232C Level Conversion
Modern TTL to RS232 level converters
Built-in DC-DC converters

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Modem (Modulation and Demodulation)
Square wave unnecessarily has high-frequency components for communication

PAM

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Modem Control Signals
Flow control (handshaking) signals to avoid buffer overflow or lock-up

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Simplified Asynchronous Serial Communication
Three-wire connection
Null-modem or crossover cable
Connect two DTEs whose connectors are the same
Connects the TxD (transmit data) on one end with the RxD (receive data) on the other end

(DTE)
GND

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Single-ended and Differential Data Transmission
Single-ended methods are often inadequate
High data rates
Long distances in real world environments
Different ground level
Differential data transmission (balanced differential signal) offers superior performance in
most applications

Single ended Differential

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Single-ended and Differential Data Transmission
RS232, RS422 and RS485

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Single-ended and Differential Data Transmission
Modern high-speed duplex TTL to RS485 driver
Common-mode rejection ratio (CMRR)

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Single-ended and Differential Data Transmission
Serial communication physical layer specifications

SPECIFICATIONS RS232 RS423 RS422 RS485

SINGLE SINGLE
Mode of Operation DIFFERENTIAL DIFFERENTIAL
-ENDED -ENDED

Total Number of Drivers and Receivers on One Line (One driver active at 1 DRIVER 1 DRIVER 1 DRIVER 32 DRIVER
a time for RS485 networks) 1 RECVR 10 RECVR 10 RECVR 32 RECVR
Maximum Cable Length 50 FT. 4000 FT. 4000 FT. 4000 FT.
Maximum Data Rate (40ft. - 4000ft. for RS422/RS485) 20kb/s 100kb/s 10Mb/s-100Kb/s 10Mb/s-100Kb/s
Maximum Driver Output Voltage +/-25V +/-6V -0.25V to +6V -7V to +12V
+/-5V to
Driver Output Signal Level (Loaded Min.) Loaded +/-3.6V +/-2.0V +/-1.5V
+/-15V
Driver Output Signal Level (Unloaded Max) Unloaded +/-25V +/-6V +/-6V +/-6V
Driver Load Impedance (Ohms) 3k to 7k >=450 100 54
Max. Driver Current in High Z State Power On N/A N/A N/A +/-100uA
+/-6mA
Max. Driver Current in High Z State Power Off +/-100uA +/-100uA +/-100uA
@ +/-2v
Slew Rate (Max.) 30V/uS Adjustable N/A N/A
Receiver Input Voltage Range +/-15V +/-12V -10V to +10V -7V to +12V
Receiver Input Sensitivity +/-3V +/-200mV +/-200mV +/-200mV
Receiver Input Resistance (Ohms), (1 Standard Load for RS485) 3k to 7k 4k min. 4k min. >=12k

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Application
Modem
Dummy terminal for development
Converter to other communication protocols (LAN, Bluetooth, etc.)
Simple sensors
ex) Issys methanol sensor

ex) Low resolution camera

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Embedded Low-Power

Embedded System
Application
4190.303C
Laboratory

2010 Spring Semester

I2C Bus
ELPL

Naehyuck Chang
Dept. of EECS/CSE
Seoul National University
[email protected]
Basic Characteristics
Two-wired communication
SDA and SCL
I2C is for on-board communication so the ground is shared
Multi-master
Multiple masters allowed with collision detection and arbitration
Operate as either a transmitter or receiver, depending on the function of the device
Devices can also be considered as masters or slaves when performing data transfers
Speeds
100 kbps (standard mode)
400 kbps (fast mode)
3.4 Mbps (high-speed mode)
8-bit oriented data transfer
Addressing
7-bit or 10-bit unique addresses

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Basic Characteristics
Device count limit
No logical limit
Maximum capacitance of 400 pF

Example of an I2C-bus configuration using two microcontrollers

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 Philips Semiconductors

Basic Terminology
The I2C-bus specification

Summary of basic terminology

Table 1 Definition of I2C-bus terminology 1) Suppose microcontroller A wa
microcontroller B:
TERM DESCRIPTION
• microcontroller A (master), ad
Transmitter The device which sends data to the (slave)
bus
• microcontroller A (master-tran
Receiver The device which receives data from microcontroller B (slave- rece
the bus
• microcontroller A terminates t
Master The device which initiates a transfer,
generates clock signals and 2) If microcontroller A wants to r
terminates a transfer microcontroller B:
Slave The device addressed by a master • microcontroller A (master) add
Multi-master More than one master can attempt to (slave)
control the bus at the same time • microcontroller A (master- rec
without corrupting the message microcontroller B (slave- trans
Arbitration Procedure to ensure that, if more • microcontroller A terminates t
than one master simultaneously tries
Even in this case, the master (mi
to control the bus, only one is allowed
the timing and terminates the tra
to do so and the winning message is
not corrupted The possibility of connecting mo
Synchronization Procedure to synchronize the clock microcontroller to the I2C-bus m
signals of two or more devices master could try to initiate a data
To avoid the chaos that might en
an arbitration procedure has bee
The I2C-bus is a multi-master bus. This means that more procedure relies on the wired-AN
than one device capable of controlling the bus can be
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connected to it. As masters are usually micro-controllers,
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interfaces Laboratory
I2C Electrical Specification
Open-drain buses

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 onductors
Bit Transfer
C-busData
specification
validity
The data on the SDA line must be stable during the HIGH period of the clock
The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is
LOW

idth
SDA

SCL

data line change

stable; of data
data valid allowed MBC621

Fig.4 Bit transfer on the I2C-bus.

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T and STOP conditions The bus stays busy if a repeated START (
A HIGH to LOW transition on the SDA line while SCL is represent both the START and repeated START
HIGH is one such unique case. This situation indicates a conditions, unless Sr is particularly relevant.
Bit Transfer
START condition.
Detection of START and STOP conditions by devices
A LOW to HIGH transition on the SDA line while SCL is connected to the bus is easy if they incorporate the
HIGH defines a STOP condition. necessary interfacing hardware. However,
START and STOP conditions microcontrollers with no such interface have to sample t
START and STOP conditions are always generated by the
Start condition SDA line at least twice per clock period to sense the
master. The bus is considered to be busy after the START
A HIGH to LOW transition on the SDA line while SCL is HIGH
transition.
condition. The bus is considered to be free again a certain
time after theStop
STOP condition
condition. This bus free situation is
specified in Section 15.to HIGH transition on the SDA line while SCL is HIGH
A LOW
START and STOP conditions are always generated by the master.
The bus is considered to be busy after the START condition. The bus is considered to be free again
a certain time after the STOP condition.

handbook, full pagewidth

SDA SDA

SCL SCL
S P

START condition STOP condition

MBC622

Fig.5 START and STOP conditions.

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Transferring Data
Acknowledge
Data transfer with acknowledge is obligatory
Philips Semiconductors
The acknowledge-related clock pulse is generated by the master
The transmitter releases the SDA line (HIGH) during the acknowledge clock pulse
The IThe receiver
2C-bus must pull down the SDA line during the acknowledge clock pulse so that it remains
specification
stable LOW during the HIGH period of this clock pulse

handbook, full pagewidth

DATA OUTPUT
BY TRANSMITTER

not acknowledge
DATA OUTPUT
BY RECEIVER

acknowledge

SCL FROM
1 2 8 9
MASTER
S
clock pulse for
START acknowledgement
condition
MBC602

Fig.7 Acknowledge on the I2C-bus.

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acknowledge-related clock pulse is generated by the an acknowledge on the last byte that was clocked out of
master. The transmitter releases the SDA line (HIGH) the slave. The slave-transmitter must release the data line

Transferring Data
during the acknowledge clock pulse. to allow the master to generate a STOP or repeated
START condition.
The receiver must pull down the SDA line during the
acknowledge clock pulse so that it remains stable LOW
Data transfer diagram

handbook, full pagewidth P

SDA

MSB acknowledgement acknowledgement Sr

signal from slave signal from receiver

byte complete,
interrupt within slave

clock line held low while

interrupts are serviced

SCL S Sr
or 1 2 7 8 9 1 2 3-8 9 or
Sr P
ACK ACK
START or STOP or
repeated START Slave hold the SLK low during the interrupt processing repeated START
condition condition
MSC608

Fig.6 Data transfer on the I2C-bus.

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Transferring Data
Byte format
Every byte put on the SDA line must be 8-bits long
The number of bytes that can be transmitted per transfer is unrestricted
Each byte has to be followed by an acknowledge bit
Data is transferred with the most significant bit (MSB) first

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Arbitration
Arbitration
If the bus is not busy (after STOP condition), any master can initiate a transfer
Arbitration process required when more than one master try to initiate a transfer at the same time
Logic ‘0’ has higher priority over logic ‘1’ in open-drain bus (wired AND)
If any device pulls down the bus, it is pulled down
When a master pulls up the bus, it checks if the bus is really pulled up
If not, it is occupied by some other devices, so the master releases the bus
A transfer to a lower address device has a higher priority
No information is lost during arbitration process

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tions 10 and 14). If the masters are each trying not affect the data transfer initiated by the winn
Arbitration
Arbitration procedure of two masters

gewidth master 1 loses arbitration

DATA 1 SDA
DATA
1

DATA
2

SDA

SCL

S MSC609

Fig.9 Arbitration procedure

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 Sr = repeated START condition at this point.

7-Bit Addressing
MBC607

The addressing procedure for the I2C-bus determines which slave will be selected by the
master format.
Combined
The first byte after the START condition
Definition of bits in the first byte
The first seven bits of the first byte make up the slave address
When an address is sent, each device in a system compares the first seven bits after the START
condition with its address
If they match, the device considers itself addressed by the master as a slave-receiver or slave-
transmitter, depending on the R/Wbit
t the
es
ption MSB
handbook, halfpage LSB

ices. R/W
ory,
n be slave address
MBC608

ken. Fig.14 The first byte after the START procedure.

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7-Bit Addressing
The I2C-bus specification
Definition of bits in the first byte

Table 2 Definition of bits in the first byte

SLAVE
R/W BIT DESCRIPTION
ADDRESS
0 0 0 0
0000 000 0 General call address
firs
0000 000 1 START byte(1) (general
0000 001 X CBUS address(2)
0000 010 X Reserved for different bus
format(3) F
0000 011 X Reserved for future purposes
0000 1XX X Hs-mode master code
When bit B i
1111 1XX X Reserved for future purposes definition:
1111 0XX X 10-bit slave addressing
• 00000110
Notes of slave ad
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1. No device is allowed to acknowledge at the reception
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general ca
byte or prepare another byte to be transmitted. Slaves can

Formats with 7-Bit Addresses

A complete data transfer

handbook, full pagewidth

SDA

SCL 1–7 8 9 1–7 8 9 1–7 8 9

S P

START ADDRESS R/W ACK DATA ACK DATA ACK STOP

condition condition
MBC604

Fig.10 A complete data transfer.

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 format (see Fig.13). During a change of
ithin a transfer, the START condition and the 4. I2C-bus compatible devices must res
ess Formats withbut7-Bit
are both repeated, with theAddresses
R/W bit on receipt of a START or repeated S
f a master receiver sends a repeated START such that they all anticipate the send
t has previously sent a not-acknowledge
A master-transmitter (A).
addressing a slave receiver with address, even if these START cond
a 7-bit address
Master is a transmitter positioned according to the proper fo
Slaver is a receiver 5. A START condition immediately follo
Transfer direction is not changed condition (void message) is an illega

width A/A
S SLAVE ADDRESS R/W A DATA A DATA P

data transferred
'0' (write) (n bytes + acknowledge)

from master to slave

A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
from slave to master
S = START condition
MBC605 P = STOP condition

Fig.11 A master-transmitter addressing a slave receiver with a 7-bit address.

The transfer direction is not changed.
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 A = acknowledge (SDA LOW)
A = not acknowledge (SDA HIGH)
from slave to master

Formats with 7-Bit Addresses

S = START condition
MBC605
P = STOP condition

Fig.11
A master A master-transmitter
reads addressing
a slave immediately after thea first
slavebyte
receiver with a 7-bit address.
The transfer direction is not changed.
At the moment of the first acknowledge
The master-transmitter becomes a master-receiver
The slave-receiver becomes a slave-transmitter
This first acknowledge is still generated by the slave
The STOP condition is generated by the master

, full pagewidth 1
S SLAVE ADDRESS R/W A DATA A DATA A P

data transferred
MBC606 (read) (n bytes + acknowledge)

Fig.12 A master reads a slave immediately after the first byte.

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e I2C-bus specification
Formats with 7-Bit Addresses
Combined format

ull pagewidth

S SLAVE ADDRESS R/W A DATA A/A Sr SLAVE ADDRESS R/W A DATA A/A P

(n bytes (n bytes
+ ack.) * + ack.) *
read or write
read or write direction
of transfer
may change
* not shaded because Sr = repeated START condition at this point.
transfer direction of
data and acknowledge bits MBC607
depends on R/W bits.

Fig.13 Combined format.

BIT ADDRESSING
dressing procedure for the I2C-bus is such that the
e after the START condition usually determines
lave will be selected by the master. The exception 50 MSB
handbook, halfpage ELPL Embedded Low-Power
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LSB

eneral call’ address which can address all devices.

10-Bit Addressing
If 7 bits are not enough to identify devices, 10-bit addressing is used
Since I2C is 8-bit oriented, 10-bit address is transfered using 2 frames
Last 3 bits of the first frame and 7 bits of the second frame is combined into 10-bit
address
First frame start with 11110

First frame 1 1 1 1 0 A0 A1 A2

Second frame A3 A4 A5 A6 A7 A8 A9 R/W

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Clock Synchronization
All masters generate their own clock on the SCL line to transfer messages on the I2C-bus
Clock synchronization is performed using the wired-AND connection of I2C interfaces to
the SCL line
A synchronized SCL clock is generated with its LOW period determined by the device with
the longest clock LOW period
A HIGH period determined by the one with the shortest clock HIGH period

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Embedded Low-Power

Embedded System
Application
4190.303C
Laboratory

2010 Spring Semester

SPI Bus
ELPL

Naehyuck Chang
Dept. of EECS/CSE
Seoul National University
[email protected]
Basic Characteristics
SPI - Serial Peripheral Interface Bus
De facto standard
No unique specification or protocol defined
Many variants exist
Full duplex communication
Single master, single slave without chip-enable signals
Multi slave available with multiple chip-enable signals
Daisy-chain available with single chip-enable signal

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Basic Characteristics
SPI - Serial Peripheral Interface Bus
Complete protocol flexibility for the bits transferred
Not limited to 8-bit words
Arbitrary choice of message size, content, and purpose
Extremely simple hardware interface
Typically lower power requirements than I²C due to less circuitry (including pull-ups)
No arbitration or associated failure modes
Slaves use the master's clock, and do not need precision oscillators
Transceivers are not needed
Logic-level on-board communication
No electrical specification
No formal specification on logic level or input capacitance
General digital signals can be used, but all participating devices should match or have tolerance

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Signals
The SPI bus specifies four logic signals (4-wire)
SCLK (SCK)
Serial Clock (output from master)
MOSI/SIMO (SDI, DI, SI)
Master Output, Slave Input (output from master)
MISO/SOMI (SDO, DO, SO)
Master Input, Slave Output (output from slave)
SS (nCS, CS, nSS, STE)
Slave Select (active low; output from master)

SPI is an on-chip bus and shares GND

3-wire variant
Replace MOSI and MISO with a single data line SISO (Slave In/Slave out)

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Note: I2C, SPI and 3-Wire Naming Convention
Some venders call SPI as 3-wire as well

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3-Wire Single Byte Protocol
3-wire protocol

3-wire command byte

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Basic Characteristics
Disadvantages of SPI
Requires more pins on IC packages than I²C, even in the "3-Wire" variant
No in-band addressing; out-of-band chip select signals are required on shared busses
In-band addressing: addressing (selecting device) signals share data bus
Out-of-band addressing: addressing (selecting device) signals are separated from data bus
No hardware flow control
Sender cannot check READY status of the receiver
No slave acknowledgment
Sender cannot confirm a successful data transmission
Multi-master busses are rare and awkward, and are usually limited to a single slave
Without a formal standard, validating conformance is not possible (de facto standard)
Only handles short distances compared with RS232, RS485, or CAN

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Operation
Data Transmission
The master enables the chip select pin for the desired device
During each SPI clock cycle, a full duplex data transmission occurs
The master sends a bit on the MOSI line; the slave reads it from that same line
The slave sends a bit on the MISO line; the master reads it from that same line
Word size (number of bits) should be pre-defined identically between master and slave before
transmission

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Operation
No standard protocol defined
Master and slave should agree in advance on
word size (8, 16, 32, ...)
bit ordering (MSB or LSB first)
clock polarity
clock phase
Usually, microprocessor can be configured for various slave devices by configuring SPI control
registers
For example, in TMS470 SPI controller has 3 control registers
SPICTRL1: clock speed, word size
SPICTRL2: clock polarity, phase
SPICTRL3: DMA, interrupt

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Operation
Clock polarity and phase
Clock polarity
Clock low when idle
Clock high when idle
Clock phase
Read data on rising edge and change on falling edge
Read data on falling edge and change on rising edge
Four combinations are available, and should be pre-defined between master and salve

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Operation
Clock polarity and phase
Polarity low; Phase rising edge

Polarity low; Phase falling edge

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Operation
Clock polarity and phase
Polarity high; Phase rising edge

Polarity high; Phase falling edge

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Operation
Independent slave SPI configuration
Each slave communicates with the master in a 1-to-1 manner
Each slave is enabled one by one
Master needs as many enable pins as the number of slaves

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Operation
Daisy chain SPI configuration
Some products with SPI bus are designed to be capable of being connected in a daisy chain
configuration
The SPI port of each slave is designed to send out during the second group of clock pulses an
exact copy of what it received during the first group of clock pulses
All slaves are enabled all the time
Master needs only one enable pin

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Application
Applications of SPI and I2C are overlapped widely
Sensors
ex) Temperature sensor and accelerometer

Register read/write
ex) CMOS camera module

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Application
Serial memory devices
Small non-volatile memory devices use a serial interface
ex) Serial EEPROM, flash memory

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Application
Simple ICs
ADCs, ADCs, and potentiometers
ex) Texas Instruments ADC interface
Parallel interface: 197 devices
Serial SPI interface: 248 devices
Serial I2C interface: 14 devices

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