Processor Architecture

ARM
Difference Between Computer Architecture & Computer
Organization

Computer Architecture: Defines the end user

view of computer like Addressing modes
available, Instruction set, User Registers,
Exceptions, Aborts, are part of architecture

Computer Organization: User invisible

implementations of architecture like Pipeline
structure, Transparent Caches, Memory
management units (table walking H/W,
Translation look aside Buffers), Memory
protection units
What is Processor

• A general purpose processor is finite state

machine, which executes instructions
stored in memory.
The state of the processor is defined by
the value held in the memory location
together with the values held in certain
registers.
Complex Instruction Set Computers (CISC)

Driving Force:
Slower secondary memories
Earlier Trend to bridge semantic gap using complex
instructions*.
Characteristics/Peculiarities of CISC:
-- Processor control Unit is using micro code ROM,
-- Instructions take more than one clock cycles.
-- Abundant Memory addressing modes
available.
*Compiler bridges the semantic gap between HLL & low level language.
Reduced Instruction Set Computers( RISC)
Instruction Usage
• Driving Force:
Data Movement 43%
Dynamic Instruction Usage
Control Flow 23%
Pecularities:
-- Hard wired Instruction decode logic
Arithmetic 15%
-- Pipelined execution Operations
-- Single cycle execution comparison 13%
--Load Store architecture
-- Several general Purpose registers & Logical 5%
large cache Operations
-- Delayed jump Other 1%
Advantages of RISC

• Smaller Die Size

• A short Development time
• Low power consumption
• Higher clock rates

Drawbacks of RISC
• Poor code density compared to CISC*
• They Don’t execute x86 code.
*ARM have THUMB mode for compact code generation
ARM Introduction

• Advanced RISC Machine, designed by Acorn Computer

Systems Ltd. In 1980s Based on Berkeley RISC I & II
concepts.
-- A load store architecture
-- Fixed 32 bit length instructions
-- 3 address instruction formats.

• Features rejected from Original RISC concept:

– Register Windows
– Delayed Branch
– Single cycle execution of all Instructions
ARM Introduction Cont..
• Version 1: Obsolete
-- Basic data processing instructions
-- Byte word & multiple word load store
-- Branch, Branch & link instructions
-- A S/W interrupt for OS support

• Version 2: Obsolete
-- MAC instructions for DSP operations
-- Coprocessor support
-- More banked registers for FIQ (Fast Int. Request)
-- Atomic load store instructions added.

• Version 3: Obsolete
-- Extended the design to 32 bit address range architecture
-- CPSR & SPSR are added, leading to add new instructions to access these
registers
ARM Introduction Cont..

• Version 4: In force
-- Half word load store instruction added
-- Instructions to load & sign extend byte & half word added.
-- Thumb concept for optimal code density
-- New privileged access mode which uses user mode registers.
-- Undefined S/W interrupt provision made

• Version 5: In force
-- Improvement in ARM THUMB mode interworking
-- added count leading zero instructions for efficient integer divide
-- Adds S/W break point Instructions
Naming convention
• The string ‘ARM’ is concatenated
• The next letter instruction set version ex. ARM7/ARM9
• The ‘T’ reads for THUMB mode support of that core.
• The ‘M’ letter stands for support for Long Multiply instruction support
-- These can do 32x32  64 muliplication & 32x32+64 64 Multiply
accumulate operations.
• The ‘E’ letter stands for enhanced performance of ARM processors for DSP
algorithms.
-- several new MAC instructions to operate on 16 bit data also add & sub
instructions acting on saturated signed arithmatics. Also support cache
preload instructions
• The letter ‘I’ stands for built in support for embedded on chip ICE-RT logic
for debuggin.
• The ‘D’ stands for on chip Debug channel to interface with target debugger.
• So The ARM7TDMI will read as  ARM processor Version 7 having T:
THUMB extension, D: On chip Debugger, ‘M’: Long multiply supported,
‘I’: Built in embedded ICE-RT logic
*processor Core Version is somehing Diff.
Registers

• Total 37 registers each 32 bit wide

• 31 GPR & 6 status register.
• Registers are in partially overlapped fashion, each time only R0-R15
registers are visible.

• The Registers are grouped as

– R0 – R7 Unbaked registers
– R8-R14 Banked registers
– R14 & R13 have six banked registers one each exception mode
– R15 is used as Program counter
• R13 is used as Stack pointer
• R14 is used as Link register used to hold subroutine return address
or return address of an exception.
• R15 is used as Program counter
Processor Modes

• Supports seven operating modes

– User Normal Program execution mode
– FIQ  High speed data Transfer or channel process
– IRQ  Used for general purpose interrupt handling
– Supervisory  A protected mode for OS
– Abort  Implements virtual memory and/or memory protection
– Undefined  Supports S/W emulation of H/W coprocessor
– System  Runs privileged OS tasks.

• Mode change can be made under S/W control or can be caused by

external interrupts or exception processing.
• Most Application program executes in the User mode, & they can not
access protected system resources.
• All privileged modes are entered by respective exceptions.
• System mode is only privileged mode which is not entered by any
exception, shares the same registers that of
Program status register

The Current Program Status Register (CPSR) is accessible in all

processor modes. It contains condition code flags, Interrupt disable bits and
current processor status.
The value of CPSR is saved in Saved Program Status Register
(SPSR) when any exception occurs.
Program status register cont..

• N Bit: Negative Flag, is set to bit 31 of result, N=1 for negative number & N=0
for positive or zero.

• Z Bit: Zero flag, Indicates equal result in compare, or result of previous

instruction is zero

• C Bit: Carry flag, Reflects resultant borrow in Sub instruction (unsigned

underflow) or used in long additions, also the compare instruction affect the C
flag, Shift instructions can also change the Carry bit status.

• V Bit: Overflow flag, used in signed add/sub to indicate the overflow. (All
operands & result in twos’ compliment form)

• Q Bit: This flag is used to indicate the overflow or saturation occurred in some
of the DSP related instructions.
Program status register cont..

• I Bit: 0= IRQ interrupts enabled

1= IRQ interrupt disabled

• F Bit: 0= FIQ interrupt is enabled

1= FIQ interrupt is disabled

• T Bit: 0= ARM mode execution

1 = Thumb mode execution

• M4-M0 Bits: These bits are used to determine the mode in which the
processor operates.

• Other bits are reserved & S/W should not modify these bits, to maintain
future compatibility.
Program status register cont..
Exceptions
• ARM supports Seven types of exceptions.
• Exception vector address can be moved from normal address range
0x00000000 to 0x0000001C & at the bottom of 32 bit address space
0xFFFF0000-0xFFFF001C The H/W config I/P selects normal or High vector
Exception handling

• Entering The Exception:

– Preserve the address of next instruction in the appropriate link
register
– Copies the CPSR into the SPSR
– Forces the CPSR bits to the appropriate value
– Forces the PC to fetch the next instruction from predefined
exception vector.
– It may also set the I flag so as to avoid unnecessary nesting of
interrupts.

• If the processor is in THUMB mode at the time of

exception then it enters in the ARM state automatically &
loads the intrrupt vector address.
Exception handling cont…

• Action on leaving interrupt:

– On completing the exception, moves link register to PC
(some times minus offset depending on type of exception)
– Copies the SPSR to CPSR
– Clears the INT disable flag, if any were set at the time of
entry.

• Explicit entry in THUMB mode is not needed if exception

had occurred in Thumb mode, as restoring the CPSR from
SPSR does that automatically & sets the T bit appropriately
to the value it was set before exception.
Exception handling cont…
• Reset:
– When reset input is asserted, ARM processor immediately stops the
execution of the current instruction.

• Actions after Reset is deasserted

– R14_svc = undefined
– SPSR_svc = undefined
– CPSR[4:0] = 0b10011; enter in supervisory State
– CPSR[5] = 0 enter in ARM state
– CPSR[6] = 1 Disable FIQ interrupt
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored address 0x0000 or 0xFFFF0000

• After reset ARM processor starts execution in supervisory mode

with all interrupts disabled
Exception handling cont…
• Undefined Instruction Exception:
– If an attempt is made to execute an instruction that is undefined.
– If executes a coprocessor instruction and no coprocessor responds
• It can be used for the S/W emulation of coprocessor that do not
have physical coprocessor.

• Actions on Undefined Instruction exception

– R14_und = address of Inst. Next to undefined instr.
– SPSR_und = CPSR
– CPSR[4:0] = 0b11011; enter in Undefined exc. State
– CPSR[5] = 0 enter in ARM state
– Jump to vectored address

• To return from Undefined Inst. Exception

– CPSR = SPSR_und
– PC = R14_und
Exception handling cont…
• Software Interrupt (SWI)
– Processor enters in supervisory state after executing SWI to
request particular supervisory function.

• Actions on SWI
– R14_svc = address of Inst. Next to SWI
– SPSR_svc = CPSR
– CPSR[4:0] = 0b10011; enter in SWI exc. State
– CPSR[5] = 0 enter in ARM state
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored location

• To return from exception

– Restore CPSR from SPSR_svc
– Restore PC from R14_svc
Exception handling cont…

• Interrupt Request (IRQ)

– It is generated by asserting IRQ signal to the processor.
– It has a lower priority & is masked out when FIQ occurs.
– IRQ is disabled when I bit in CPSR is set.

• Actions on IRQ exception

– R14_irq = address of next Inst to execute + 4
– SPSR_irq = CPSR
– CPSR[4:0] = 0b10010; enter in IRQ State
– CPSR[5] = 0 enter in ARM state
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored location

• To return from exception

– Restore CPSR from SPSR_irq
– Restore PC from (R14_irq – 4) & return to execute aborted Inst.
Exception handling cont…
• Fast Interrupt Request (FIQ) exception
– FIQ is generated by asserting the FIQ input on the processor. It is
designed to support the data transfer or channel process, & have
sufficient private registers to remove need for register saving in an
application.
– This exception is disabled when FIQ bit in CPSR is set.

• Actions on FIQ exception

– R14_fiq = address of next Inst to execute + 4
– SPSR_fiq = CPSR
– CPSR[4:0] = 0b10001; enter in FIQ State
– CPSR[5] = 0 enter in ARM state
– CPSR[6] = 1 Disable FIQ interrupt
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored location

• To return from exception

– Restore CPSR from SPSR_fiq
– Restore PC from (R14_fiq – 4) & return to execute aborted Inst.
Exception handling cont…
• Prefetch Abort (Insruction fetch memory abort) :
– It is signaled by the memory sub system. Activating abort in response
to any prefetch marks that instruction as invalid.
– In ARMv5 & above Abort can also be generated by executing BKPT
instruction

• Actions on prefetch abort

– R14_abt = address of aborted Inst. + 4
– SPSR_abt = CPSR
– CPSR[4:0] = 0b10111; enter in Abort. State
– CPSR[5] = 0 enter in ARM state
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored location

• To return from exception

– Restore CPSR from SPSR_svc
– Restore PC from (R14_svc – 4) & return to execute aborted Inst.
Exception handling cont…
• Data Abort (Data Access memory abort):
– It is signaled by memory system .
– Activating abort in response to load or store marks data
invalid. Data abort exception occurs before any exception
occurs or next instruction is executed.

• Actions on Data abort

– R14_abt = address of aborted Inst. + 8
– SPSR_abt = CPSR
– CPSR[4:0] = 0b10111; enter in Abort. State
– CPSR[5] = 0 enter in ARM state
– CPSR[7] = 1 Disable normal interrupt
– Jump to vectored location

• To return from exception

– Restore CPSR from SPSR_svc
– Restore PC from (R14_svc – 8) & return to execute aborted Inst.
Exception handling cont…

• Exception Priorities
• Undefined instruction &
SWI can no occur at the
same time so they have
the same priority.
• Also the data abort
handle have higher
priority than the FIQ this
ensures that data abort
are resolved before the
FIQ compleates
Memory & Memory mapped I/O
• If certain rules in memory mapped I/O are broken then
– It might make memory system implementation difficult
– Might cause difficulty in porting system
– Standard S/W (compiler/Linker/Assemblers) might not work with rule
breaking system

• Basic Rules
– ARM architecture considers the address space as 2^30 32 bit flat
address space, with Word aligned boundary
– Address Calculations are performed by normally Integer arithmetic, so
that if any overflow or underflow occurs, the address simply wraps
around
– Most branches are relative (addr_of_curr_inst) + 8 + offset so if any
overflow or underflow occurs results are unpredictable.
– Always match the H/W endianness select I/P with the memory mapped
I/O’s endianness. (by default ARM is configured for little endian format)
– If memory system is configured for one type of access & actual memory
is configured for other type of access then only word access can be
relied on, other half word & byte access would have unpredictable
results
Memory & Memory mapped I/O

• Unaligned Instruction fetches, i.e. writing address not aligned to

word boundary in ARM state can result in unpredictable results.

• Memory mapped I/O differs from normal memory, so always keep

memory mapped I/O locations as uncached & unbuffered.
Endianness