VHDL code for counters with testbench - FPGA4student.com https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-tes...

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VHDL code for counters with testbench

Last time, several 4-bit counters including up counter, down counter and up-down Join 18,000+ Followers
counter are implemented in Verilog. Verilog code for the counters is presented.
In this VHDL project, the counters are implemented in VHDL. The testbench VHDL code for the
FPGA4STUDENT
counters is also presented together with the simulation waveform.
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library IEEE; designed and implemented
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entity UP_COUNTER is the 4-digit seven-segment display on
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Port ( clk: in std_logic; -- clock input controller will be ...
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter Verilog code for counter
with testbench
); In this project, Verilog code
end UP_COUNTER; for counters with testbench
will be presented including
up counter, down counter, up-down
architecture Behavioral of UP_COUNTER is counter, and r...
signal counter_up: std_logic_vector(3 downto 0);
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-- up counter
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using Verilog from reading an input
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if(reset='1') then
counter_up <= x"0"; VHDL code for Seven-
Segment Display on Basys
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counter_up <= counter_up + x"1"; Last time , I wrote a full
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control the 4-digit 7-segment display on
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Basys 3 FPGA. A full Verilog code for
end process; displayi...
counter <= counter_up;
VHDL code for Arithmetic
Logic Unit (ALU)
end Behavioral; Arithmetic Logic Unit ( ALU
Testbench VHDL code for the up-counter: ) is one of the most
important digital logic
library IEEE; components in CPUs. It normally
executes logic and arithmetic op...
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: Testbench VHDL code for up counter
entity tb_counters is
end tb_counters;

architecture Behavioral of tb_counters is

component UP_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter

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VHDL code for counters with testbench - FPGA4student.com https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-tes...

);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);

begin
dut: UP_COUNTER port map (clk => clk, reset=>reset, counter => counter);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process;
end Behavioral;

Simulation waveform:

VHDL code for down counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for down counter
entity DOWN_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end DOWN_COUNTER;

architecture Behavioral of DOWN_COUNTER is

signal counter_down: std_logic_vector(3 downto 0);
begin
-- down counter
process(clk)
begin
if(rising_edge(clk)) then
if(reset='1') then
counter_down <= x"F";
else
counter_down <= counter_down - x"1";
end if;
end if;
end process;
counter <= counter_down;

end Behavioral;
Testbench VHDL code for the down counter:

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VHDL code for counters with testbench - FPGA4student.com https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-tes...

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: Testbench VHDL code for down counter
entity tb_counters is
end tb_counters;

architecture Behavioral of tb_counters is

component DOWN_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end component;
signal reset,clk: std_logic;
signal counter:std_logic_vector(3 downto 0);

begin
dut: DOWN_COUNTER port map (clk => clk, reset=>reset, counter => counter);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
wait for 20 ns;
reset <= '0';
wait;
end process;
end Behavioral;
Simulation waveform:

VHDL code for the up-down counter:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: VHDL code for up-down counter
entity UPDOWN_COUNTER is
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
up_down: in std_logic; -- up or down
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end UPDOWN_COUNTER;

architecture Behavioral of UPDOWN_COUNTER is

signal counter_updown: std_logic_vector(3 downto 0);
begin
-- down counter
process(clk)

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VHDL code for counters with testbench - FPGA4student.com https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-tes...

begin
if(rising_edge(clk)) then
if(reset='1') then
counter_updown <= x"0";
elsif(up_down='1') then
counter_updown <= counter_updown - x"1"; -- count down
else
counter_updown <= counter_updown + x"1"; -- count up
end if;
end if;
end process;
counter <= counter_updown;

end Behavioral;
Testbench VHDL code for the up-down counter:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- FPGA projects using Verilog code VHDL code
-- fpga4student.com: FPGA projects, Verilog projects, VHDL projects
-- VHDL project: VHDL code for counters with testbench
-- VHDL project: Testbench VHDL code for up-down counter
entity tb_counters is
end tb_counters;

architecture Behavioral of tb_counters is

component UPDOWN_COUNTER
Port ( clk: in std_logic; -- clock input
reset: in std_logic; -- reset input
up_down: in std_logic;
counter: out std_logic_vector(3 downto 0) -- output 4-bit counter
);
end component;
signal reset,clk,up_down: std_logic;
signal counter:std_logic_vector(3 downto 0);

begin
dut: UPDOWN_COUNTER port map (clk => clk, reset=>reset, up_down => up_down, counter => counter);
-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
reset <= '1';
up_down <= '0';
wait for 20 ns;
reset <= '0';
wait for 300 ns;
up_down <= '1';
wait;
end process;
end Behavioral;
Simulation waveform:

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VHDL code for counters with testbench - FPGA4student.com https://www.fpga4student.com/2017/06/vhdl-code-for-counters-with-tes...

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1 comment:

Unknown February 15, 2020 at 2:32 AM

VHDL CODE for 2- bit counter
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