LT3751

High Voltage Capacitor

Charger Controller with Regulation
FEATURES DESCRIPTION
nn Charges Any Size Capacitor The LT®3751 is a high input voltage capable flyback con-
nn Low Noise Output in Voltage Regulation Mode troller designed to rapidly charge a large capacitor to a
nn Stable Operation Under a No-Load Condition user-adjustable high target voltage set by the transformer
nn Integrated 2A MOSFET Gate Driver with Rail-to-Rail turns ratio and three external resistors. Optionally, a feed-
Operation for VCC ≤ 8V back pin can be used to provide a low noise high voltage
nn Selectable 5.6V or 10.5V Internal Gate Drive regulated output.
Voltage Clamp The LT3751 has an integrated rail-to-rail MOSFET gate
nn User-Selectable Over/Undervoltage Detect
driver that allows for efficient operation down to 4.75V.
nn Easily Adjustable Output Voltage
A low 106mV differential current sense threshold volt-
nn Primary or Secondary Side Output Voltage Sense
age accurately limits the peak switch current. Added pro-
nn Wide Input V
CC Voltage Range (5V to 24V) tection is provided via user-selectable overvoltage and
nn Available in 20-Pin QFN 4mm × 5mm and 20-Lead
undervoltage lockouts for both VCC and VTRANS. A typical
TSSOP Packages application can charge a 1000µF capacitor to 500V in less
than one second.
APPLICATIONS The CHARGE pin is used to initiate a new charge cycle
nn High Voltage Regulated Supply and provides ON/OFF control. The DONE pin indicates
nn High Voltage Capacitor Charger when the capacitor has reached its programmed value and
nn Professional Photoflash Systems the part has stopped charging. The FAULT pin indicates
nn Emergency Strobe when the LT3751 has shut down due to either VCC or
nn Security/Inventory Control Systems VTRANS voltage exceeding the user-programmed supply
nn Detonators tolerances.
All registered trademarks and trademarks are the property of their respective owners. Protected
by U.S. Patents including 6518733 and 6636021.

TYPICAL APPLICATION
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

T1
Load Regulation and Efficiency
D1
VTRANS 1:10 500V 500 90
24V + 330µF 10µF
0 TO 150mA
×2 40.2k ×2 • +
100µF
• 498 84
RVTRANS 18.2k 0.47µF
OUTPUT VOLTAGE (V)

OFF ON CHARGE RDCM

CLAMP 40.2k
EFFICIENCY (%)

RVOUT 496 78
VCC VCC LT3751
24V
10µF HVGATE
TO DONE
MICRO FAULT LVGATE VCC
CSP 494 72
374k
UVLO1 6mΩ
VTRANS 475k
OVLO1 CSN 715k
374k 492 66
UVLO2
VCC 475k FB OUTPUT VOLTAGE
OVLO2 EFFICIENCY
1.74k
GND RBG 10nF 490 60
0 50 100 150
732Ω
LOAD CURRENT (mA)
3751 TA01b
3751 TA01a

3751fd

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LT3751
ABSOLUTE MAXIMUM RATINGS (Note 1)

VCC, CHARGE, CLAMP...............................................24V Current into RVOUT Pin......................................... ±10mA

DONE, FAULT.............................................................24V Current into RDCM Pin......................................... ±10mA
LVGATE (Note 8)........................................................24V Current into UVLO1 Pin........................................... ±1mA
VCC – LVGATE..............................................................8V Current into UVLO2 Pin.......................................... ±1mA
HVGATE.................................................................Note 9 Current into OVLO1 Pin........................................... ±1mA
RBG, CSP, CSN............................................................2V Current into OVLO2 Pin........................................... ±1mA
FB ...............................................................................5V Maximum Junction Temperature........................... 125°C
Current into DONE Pin............................................ ±1mA Operating Temperature Range (Note 2).. –40°C to 125°C
Current into FAULT Pin............................................ ±1mA Storage Temperature Range................... –65°C to 150°C
Current into RV TRANS Pin....................................... ±1mA

PIN CONFIGURATION
TOP VIEW
TOP VIEW

RVTRANS
UVLO1

RDCM
RVTRANS 1 20 RDCM

NC
UVLO1 2 19 NC 20 19 18 17
OVLO1 3 18 RVOUT OVLO1 1 16 RVOUT
UVLO2 4 17 NC UVLO2 2 15 NC
OVLO2 5 16 RBG OVLO2 3 14 RBG
21 21
FAULT 6 15 HVGATE FAULT 4 13 HVGATE
DONE 7 14 LVGATE DONE 5 12 LVGATE
CHARGE 8 13 VCC CHARGE 6 11 VCC

CLAMP 9 12 CSP 7 8 9 10
FB 10 11 CSN
CLAMP
FB
CSN
CSP
FE PACKAGE
20-LEAD PLASTIC TSSOP
UFD PACKAGE
TJMAX = 125°C, θJA = 38°C/W 20-PIN (4mm × 5mm) PLASTIC QFN
EXPOSED PAD (PIN 21) IS GND, MUST BE SOLDERED TO PCB TJMAX = 125°C, θJA = 43°C/W
EXPOSED PAD (PIN 21) IS GND, MUST BE TIED TO PCB

ORDER INFORMATION http://www.linear.com/product/LT3751#orderinfo

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3751EFE#PBF LT3751EFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751IFE#PBF LT3751IFE#TRPBF LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751EUFD#PBF LT3751EUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LT3751IUFD#PBF LT3751IUFD#TRPBF 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LEAD BASED FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LT3751EFE LT3751EFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751IFE LT3751IFE#TR LT3751FE 20-Lead Plastic TSSOP –40°C to 125°C
LT3751EUFD LT3751EUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
LT3751IUFD LT3751IUFD#TR 3751 20-Pin (4mm × 5mm) Plastic QFN –40°C to 125°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/. Some packages are available in 500 unit reels through
designated sales channels with #TRMPBF suffix.
3751fd

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 LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCC Voltage l 4.75 24 V
RVTRANS Voltage (Note 3) l 4.75 65 V
VCC Quiescent Current Not Switching, CHARGE = 5V 5.5 8 mA
Not Switching, CHARGE = 0.3V 0 1 µA
RVTRANS, RDCM Quiescent Current (Note 4)
Not Switching, CHARGE = 5V l 35 40 45 µA
Not Switching, CHARGE = 0.3V 0 1 µA
RVOUT Quiescent Current (Note 4)
Not Switching, CHARGE = 5V l 42 47 52 µA
Not Switching, CHARGE = 0.3V 0 1 µA
UVLO1, UVLO2, OVLO1, OVLO2 Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 55 V
RVTRANS, RVOUT, RDCM Clamp Voltage Measured at 1mA into Pin, CHARGE = 0V 60 V
CHARGE Pin Current CHARGE = 24V 425 µA
CHARGE = 5V 60 µA
CHARGE = 0V 1 µA
CHARGE Minimum Enable Voltage l 1.5 V
CHARGE Maximum Disable Voltage IVCC ≤ 1µA l 0.3 V
Minimum CHARGE Pin Low Time 20 μs
One-Shot Clock Period l 32 38 44 μs
VOUT Comparator Trip Voltage Measured at RBG Pin l 0.955 0.98 1.005 V
VOUT Comparator Overdrive 2µs Pulse Width, 20 40 mV
RVTRANS, RVOUT = 25kΩ
RBG = 0.83kΩ
DCM Comparator Trip Voltage Measured as VDRAIN – VTRANS, RDCM = 25kΩ, VCC = 4.75V 350 600 900 mV
(Note 5)
Current Limit Comparator Trip Voltage FB Pin = 0V l 100 106 112 mV
FB Pin = 1.3V l 7 11 15 mV
FB Pin Bias Current Current Sourced from FB Pin, Measured at FB Pin Voltage 64 300 nA
FB Pin Voltage (Note 6) l 1.19 1.22 1.25 V
FB Pin Charge Mode Threshold 1.12 1.16 1.2 V
FB Pin Charge Mode Hysteresis (Note 7) 55 mV
FB Pin Overvoltage Mode Threshold 1.29 1.34 1.38 V
FB Pin Overvoltage Hysteresis 60 mV
DONE Output Signal High 100kΩ to 5V 5 V
DONE Output Signal Low 100kΩ to 5V 40 200 mV
DONE Leakage Current DONE = 5V 5 200 nA
FAULT Output Signal High 100kΩ to 5V 5 V
FAULT Output Signal Low 100kΩ to 5V 40 200 mV
FAULT Leakage Current FAULT = 5V 5 200 nA
UVLO1 Pin Current UVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA
UVLO2 Pin Current UVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA
OVLO1 Pin Current OVLO1 Pin Voltage = 1.24V l 48.5 50 51.5 μA
OVLO2 Pin Current OVLO2 Pin Voltage = 1.24V l 48.5 50 51.5 μA

3751fd

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LT3751
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are TA = 25°C. VCC = CHARGE = 5V, CLAMP = 0V, unless otherwise noted. Individual
25kΩ resistors tied from 5V VTRANS supply to RVTRANS, RVOUT, RDCM, unless otherwise noted. (Note 2)
PARAMETER CONDITIONS MIN TYP MAX UNITS
UVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V
UVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V
OVLO1 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V
OVLO2 Threshold Measured from Pin to GND l 1.195 1.225 1.255 V
Gate Minimum High Time 0.7 μs
Gate Peak Pull-Up Current VCC = 5V, LVGATE Active 2.0 A
VCC = 12V, LVGATE Inactive 1.5 A
Gate Peak Pull-Down Current VCC = 5V, LVGATE Active 1.2 A
VCC = 12V, LVGATE Inactive 1.5 A
Gate Rise Time 10% → 90%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active 40 ns
VCC = 12V, LVGATE Inactive 55 ns
Gate Fall Time 90% → 10%, CGATE = 3.3nF (Note 8)
VCC = 5V, LVGATE Active 30 ns
VCC = 12V, LVGATE Inactive 30 ns
Gate High Voltage (Note 8):
VCC = 5V, LVGATE Active 4.98 5 V
VCC = 12V, LVGATE Inactive 10 10.5 11.5 V
VCC = 12V, LVGATE Inactive, CLAMP Pin = 5V 5 5.6 6.5 V
VCC = 24V, LVGATE Inactive 10 10.5 11.5 V
Gate Turn-Off Propagation Delay CGATE = 3.3nF 180 ns
25mV Overdrive Applied to CSP Pin
Gate Voltage Overshoot 500 mV
CLAMP Pin Threshold 1.6 V

Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Refer to Block Diagram for VTRANS and VDRAIN definitions.
may cause permanent damage to the device. Exposure to any Absolute Note 6: Low noise regulation of the output voltage requires a resistive
Maximum Rating condition for extended periods may affect device voltage divider from output voltage to FB pin. FB pin should not be
reliability and lifetime. grounded in this configuration. Refer to the Typical Application diagram for
Note 2: The LT3751E is guaranteed to meet performance specifications proper FB pin configuration.
from 0°C to 125°C junction temperature. Specifications over the –40°C Note 7: The feedback pin has built-in hysteresis that defines the boundary
to 125°C operating junction temperature range are assured by design between charge-only mode and low noise regulation mode.
characterization and correlation with statistical process controls. The Note 8: LVGATE should be used in parallel with HVGATE when VCC is less
LT3751I is guaranteed over the full –40°C to 125°C operating junction than or equal to 8V (LVGATE active). When not in use, LVGATE should be
temperature range. tied to VCC (LVGATE inactive).
Note 3: A 60V internal clamp is connected to RVTRANS, RDCM, RVOUT, Note 9: Do not apply a positive or negative voltage or current source to
UVLO1, UVLO2, OVLO1 and OVLO2. Resistors should be used such that HVGATE, otherwise permanent damage may occur.
the pin currents do not exceed the Absolute Maximum Ratings.
Note 4: Currents will increase as pin voltages are taken higher than the
internal clamp voltage.

3751fd

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 LT3751
TYPICAL PERFORMANCE CHARACTERISTICS

VCC Pin Current VTRANS Supply Current CHARGE Pin Current

7 150 450
RVTRANS, RVOUT, RDCM = 25k
6 145 VCC, CHARGE = 5V 400
IVTRANS = IRVTRANS + IRVOUT + IRDCM
350
140

IVTRANS CURRENT (µA)

5
PIN CURRENT (mA)

300

CURRENT (µA)
135
4 250
130
3 200
125
150
2
120
100
1 –40°C –40°C –40°C
25°C 115 25°C 50 25°C
125°C 125°C 125°C
0 110 0
0 4 8 12 16 20 24 0 10 20 30 40 50 60 0 4 8 12 16 20 24
PIN VOLTAGE (V) PIN VOLTAGE (V) PIN VOLTAGE (V)
3751 G01 3751 G02 3751 G03

CHARGE Pin Minimum CHARGE Pin Maximum

Enable Voltage Disable Voltage DONE, FAULT Pin Voltage Low
1.3 1.2 400
VCC = 5V
VCC = 12V 350
1.2 1.1 VCC = 24V 1mA SINK
300
CHARGE PIN VOLTAGE (V)

CHARGE PIN VOLTAGE (V)

PIN LOW VOLTAGE (mV)

1.1 1.0
250
1.0 0.9
200
0.9 0.8
150
0.8 0.7
100
VCC = 5V 100µA SINK
0.7 0.6 50
VCC = 12V
VCC = 24V 10µA SINK
0.6 0.5 0
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G04 3751 G05 3751 G06

VOUT Comparator Trip Voltage UVLO1 Trip Voltage UVLO1 Trip Current
30.8 1.236 50.5
RVTRANS, RVOUT = 25.5k (RTOL = 1%)
RBG = 833Ω 50.4
30.4 1.234
VDRAIN – VTRANS VOLTAGE (V)

UVLO1 PIN CURRENT (µA)

50.3
UVLO1 PIN VOLTAGE (V)

30.0 1.232
50.2

29.6 1.230 50.1

50.0
29.2 1.228
49.9
28.8 VTRANS = 5V 1.226 VCC = 5V VCC = 5V
VTRANS = 12V VTRANS = 48V VCC = 12V 49.8 VCC = 12V
VTRANS = 24V VTRANS = 72V VCC = 24V VCC = 24V
28.4 1.224 49.7
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G07 3751 G08 3751 G09

3751fd

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LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
Current Comparator Trip Voltage Current Comparator Minimum
(Charge Mode) Trip Voltage (Regulation Mode) FB Pin Voltage
109.0 13.0 1.223
VTH = VCSP – VCSN VTH = VCSP – VCSN
12.8 FB = 1.3V
12.6
108.5 1.222
12.4

FB PIN VOLTAGE (V)

VTH VOLTAGE (mV)

VTH VOLTAGE (mV)

12.2
108.0 12.0 1.221

11.8
11.6
107.5 1.220
VCC = 5V 11.4 VCC = 5V VCC = 5V
VCC = 12V VCC = 12V VCC = 12V
11.2 VCC = 24V
VCC = 24V VCC = 24V
107.0 11.0 1.219
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G10 3751 G11 3751 G12

FB Pin Regulation FB Pin Regulation

FB Pin Bias Current Mode Threshold Mode Hysteresis
100 1.168 60
MEASURED AT FB PIN VOLTAGE VCC = 5V
VCC = 12V VCC = 12V
90 VCC = 24V
58
SOURCED PIN CURRENT (nA)

1.164
FB PIN VOLTAGE (V)

80
HYSTERESIS (mV)
56
70 1.160
54
60
1.156
VCC = 5V 52
50
VCC = 12V
VCC = 24V
40 1.152 50
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G13 3751 G14 3751 G15

FB Pin Overvoltage Mode FB Pin Overvoltage

Threshold Voltage Mode Hysteresis CLAMP Pin Threshold
1.356 61.0 1.9
VCC = 5V VCC = 12V
VCC = 12V VCC = 24V
1.354 VCC = 24V
60.6 1.8
CLAMP PIN VOLTAGE (V)
FB PIN VOLTAGE (V)

1.352
HYSTERESIS (mV)

60.2 1.7
1.350
59.8 1.6
1.348

59.4 VCC = 5V 1.5

1.346
VCC = 12V
VCC = 24V
1.344 59.0 1.4
–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 0 40 80 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G16 3751 G17 3751 G18

3751fd

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 LT3751
TYPICAL PERFORMANCE CHARACTERISTICS
DCM Trip Voltage (VDRAIN – VTRANS),
HVGATE Pin Clamp Voltage HVGATE Pin Clamp Voltage RVTRANS = RDCM = 25kΩ
11.0 5.70 0.64
VCC = 24V VCC = 12V VTRANS = 5V
CLAMP = 0V CLAMP = 12V VTRANS = 12V
10.9 VTRANS = 24V
0.62
5.65 VTRANS = 48V
HVGATE PIN VOLTAGE (V)

HVGATE PIN VOLTAGE (V)

DCM TRIP VOLTAGE (V)

10.8
0.60
10.7 5.60
0.58
10.6
5.55
0.56
10.5

10.4 5.50 0.54

–40 –20 0 20 40 60 80 100 120 –40 –20 0 20 40 60 80 100 120 –40 0 40 80 120
TEMPERATURE (°C) TEMPERATURE (°C) TEMPERATURE (°C)
3751 G19 3751 G20 3751 G21

PIN FUNCTIONS (TSSOP/QFN)

RVTRANS (Pin 1/Pin 19): Transformer Supply Sense Pin. UVLO2 (Pin 4/Pin 2): VCC Undervoltage Lockout Pin.
Connect a resistor between the RVTRANS pin and the Senses when VCC drops below:
VTRANS supply. Refer to Table 2 for proper sizing of the
RVTRANS resistor. The minimum operation voltage for VUVLO2 = 1.225 + 50µA • RUVLO2
VTRANS is 4.75V.
and trips the FAULT latch low, disabling switching. After
UVLO1 (Pin 2/Pin 20): VTRANS Undervoltage Lockout Pin.
Senses when VTRANS drops below: VCC rises above VUVLO2, toggling the CHARGE pin reac-
tivates switching.
VUVLO1 = 1.225 + 50µA • RUVLO1 OVLO2 (Pin 5/Pin 3): VCC Overvoltage Lockout Pin.
Senses when VCC rises above:
and trips the FAULT latch low, disabling switching. After
VOVLO2 = 1.225 + 50µA • R OVLO2
VTRANS rises above VUVLO1, toggling the CHARGE pin
reactivates switching.
and trips the FAULT latch low, disabling switching. After
OVLO1 (Pin 3/Pin 1): VTRANS Overvoltage Lockout Pin.
VCC drops below VOVLO2, toggling the CHARGE pin reac-
Senses when VTRANS rises above:
tivates switching.
VOVLO1 = 1.225 + 50µA • R OVLO1 FAULT (Pin 6/Pin 4): Open Collector Indication Pin. When
either VTRANS or VCC exceeds the user-selected voltage
and trips the FAULT latch low, disabling switching. After range, or an internal UVLO condition occurs, a transistor
VTRANS drops below VOVLO1, toggling the CHARGE pin turns on. The part will stop switching. This pin needs a
reactivates switching. proper pull-up resistor or current source.

3751fd

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LT3751
PIN FUNCTIONS
DONE (Pin 7/ Pin 5): Open Collector Indication Pin. When LVGATE (Pin 14/Pin 12): Low Voltage Gate Pin. Connect
the target output voltage (charge mode) is reached or the the NMOS gate terminal to this pin when operating VCC
FAULT pin goes low, a transistor turns on. This pin needs below 8V. The internal gate driver will drive the voltage to
a proper pull-up resistor or current source. the VCC rail. When operating VCC higher than 8V, tie this
CHARGE (Pin 8/Pin 6): Charge Pin. Initiates a new charge pin directly to VCC.
cycle (charge mode) or enables the part (regulation mode) HVGATE (Pin 15/Pin 13): High Voltage Gate Pin. Connect
when driven higher than 1.5V. Bring this pin below 0.3V NMOS gate terminal to this pin for all VCC operating volt-
to discontinue charging and put the part into shutdown. ages. Internal gate driver will drive the voltage to within
Turn-on ramp rates should be between 10ns to 10ms. VCC – 2V during each switch cycle.
CHARGE pin should not be directly ramped with VCC or RBG (Pin 16/Pin 14): Bias Generation Pin. Generates
LT3751 may not properly initialize. a bias current set by 0.98V/RBG. Select RBG to achieve
CLAMP (Pin 9/Pin 7): Internal Clamp Voltage Selection desired resistance for RDCM, RVOUT, and RVTRANS.
Pin. Tie this pin to VCC to activate the internal 5.6V gate NC (Pins 17, 19/Pins 15, 18): No Connection.
driver clamp. Tie this pin to ground to activate the internal
10.5V gate driver clamp. RVOUT (Pin 18/Pin 16): Output Voltage Sense Pin.
Develops a current proportional to the output capacitor
FB (Pin 10/Pin 8): Feedback Regulation Pin. Use this pin voltage. Connect a resistor between this pin and the drain
to achieve low noise voltage regulation. FB is internally of NMOS such that:
regulated to 1.22V when a resistive divider is tied from
this pin to the output. FB pin should not float. Tie FB pin ⎛ RV ⎞
VOUT = 0.98 • N • ⎜ OUT ⎟ − VDIODE
to either a resistor divider or ground. ⎝ RBG ⎠
CSN (Pin 11/Pin 9): Negative Current Sense Pin. Senses when RVOUT is set equal to RVTRANS, otherwise:
external NMOS source current. Connect to local RSENSE
⎡ RV ⎛ RV ⎞⎤
ground connection for proper Kelvin sensing. The current VOUT = N • ⎢0.98 • OUT + VTRANS ⎜ OUT − 1
⎟⎥
limit is set by 106mV/RSENSE. ⎣ RBG ⎝ RVTRANS ⎠⎦
CSP (Pin 12/Pin 10): Positive Current Sense Pin. Senses − VDIODE
NMOS source current. Connect the NMOS source terminal
and the current sense resistor to this pin. The current where VDIODE = forward voltage drop of diode D1 (refer
limit is fixed at 106mV/RSENSE in charge mode. The cur- to the Block Diagram).
rent limit can be reduced to a minimum 11mV/RSENSE in RDCM (Pin 20/Pin 17): Discontinuous Mode Sense Pin.
regulation mode. Senses when the external NMOS drain is equal to 20µA •
VCC (Pin 13/Pin 11): Input Supply Pin. Must be locally RDCM + VTRANS and initiates the next switch cycle. Place
bypassed with high grade (X5R or better) ceramic capaci- a resistor equal to 0.45 times the resistor on the RVTRANS
tor. The minimum operating voltage for VCC is 4.75V. pin between this pin and VDRAIN.
GND (Pin 21/Pin 21): Ground. Tie directly to local ground
plane.

3751fd

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 LT3751
BLOCK DIAGRAM
T1 D1
VTRANS 1:10 VOUT
12V + • 450V

SECONDARY
PRIMARY
47µF RVTRANS 10µF
×2 40.2k +
COUT
VOUT RVTRANS •
CHARGE COMPARATOR – 0.98V
REFERENCE 60V
OFF ON
START-UP RVOUT
OTLO RVOUT
ONE-SHOT 40.2k
VCC +
VCC MASTER DIFF. AMP
12V LATCH COMPARATOR 60V
100k DONE DCM WITH
10µF
S R COMPARATOR INTERNAL RDCM
– 60V CLAMPS RDCM 18.2k
Q Q ENABLE
GATE DCM
100k DRIVER ONE-SHOT 60V
+ 1.22V
FAULT REFERENCE
VDRAIN
S R FAULT VCC
Q Q LATCH 26kHz ONE-SHOT
CLOCK
HVGATE
GATE DRIVE
INTERNAL S Q M1
CIRCUITRY
UVLO R Q
3.8V + SWITCH
LATCH
CLAMP
VCC –
VCC
RUVLO1
191k UVLO1 LVGATE
VTRANS – RESET VCC
55V CLK AUXILIARY
COUNT
+ +
COUNTER 162mV
ROVLO1
240k OVLO1 – +–
+
26kHz
55V ONE-SHOT MAIN CSP
CLOCK +
– RSENSE
UVLO/OVLO 106mV CSN 12mΩ
RUVLO2 COMPARATORS – +–
191k UVLO2
VCC –
TIMING AND PEAK
55V CURRENT CONTROL 11mV TO 106mV
TO CHARGE MODULATION
+ ONE-SHOT 26kHz ERROR
1.22V
ONE-SHOT AMP + REFERENCE
ROVLO2 CLOCK
240k OVLO2 A1
+
–
55V
+
–

RFBH
– 3.65M
DIE FB
TO VOUT 160ºC MODE
COMPARATOR TEMP
1.22V CONTROL
REFERENCE 10nF RFBL
GND RBG 10k
3751 BD
RBG
1.33k

3751fd

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LT3751
OPERATION
The LT3751 can be used as either a fast, efficient high ILPRI
voltage capacitor charger controller or as a high voltage, VTRANS – VDS(ON)
IPK
low noise voltage regulator. The FB pin voltage determines LPRI

one of the three primary modes: charge mode, low noise

regulation, or no-load operation (see Figure 1).
FB PIN
VOLTAGE ILSEC

NO-LOAD
OPERATION
VOUT + VDIODE
1.34V IPK
LSEC
N
REGULATION

1.16V
CHARGE VPRI VTRANS – VDS(ON)
MODE
0.0V

3751 F01

Figure 1. FB Pin Modes

CHARGE MODE –(VOUT + VDIODE)

N
When the FB pin voltage is below 1.16V, the LT3751 acts
VSEC
as a rapid capacitor charger. The charging operation has VOUT + VDIODE
four basic states for charge mode steady-state operation
(see Figure 2).

1. Start-Up
The first switching cycle is initiated approximately 2µs
after the CHARGE pin is raised high. During this phase, –N (VTRANS – VDS(ON))

the start-up one-shot enables the master latch turning

on the external NMOS and beginning the first switching V
VTRANS + OUT
+ VDIODE
VDRAIN N
cycle. After start-up, the master latch will remain in the
VTRANS
switching-enable state until the target output voltage is
reached or a fault condition occurs.
The LT3751 utilizes circuitry to protect against trans- VDS(ON) VDS(ON)
former primary current entering a runaway condition and
remains in start-up mode until the DCM comparator has
3751 F02

1. 2. 3.
enough headroom. Refer to the Start-Up Protection sec- PRIMARY-SIDE
CHARGING
SECONDARY
ENERGY TRANSFER
DISCONTINUOUS
MODE
tion for more detail. AND OUTPUT DETECTION
DETECTION

2. Primary-Side Charging
When the NMOS switch latch is set, and depending on the Figure 2. Idealized Charging Waveforms
use of LVGATE, the gate driver rapidly charges the gate
pin to VCC – 2V in high voltage applications or directly to
VCC in low voltage applications (refer to the Application

3751fd

10 For more information www.linear.com/LT3751

 LT3751
OPERATION
Information section for proper use of LVGATE). With the comparator sets the NMOS switch latch and a new switch
gate driver output high, the external NMOS turns on, cycle begins. Steps 2-4 continue until the target output
forcing VTRANS – VDS(ON) across the primary winding. voltage is reached.
Consequently, current in the primary coil rises linearly at
a rate (VTRANS – VDS(ON))/LPRI. The input voltage is mir- Start-Up Protection
rored on the secondary winding –N • (VTRANS – VDS(ON)) The LT3751 at start-up, when the output voltage is very
which reverse-biases the diode and prevents current flow low (or shorted), usually does not have enough VDRAIN
in the secondary winding. Thus, energy is stored in the node voltage to trip the DCM comparator. The part in start-
core of the transformer. up mode uses the internal 26kHz clock and an auxiliary
current comparator. Figure 3 shows a simplified block
3. Secondary Energy Transfer diagram of the start-up circuitry.
When current limit is reached, the current limit compara-
tor resets the NMOS switch latch and the device enters the FROM AUXILIARY
CURRENT INCREMENT
third phase of operation, secondary energy transfer. The COMPARATOR
COUNTER 1
–
energy stored in the transformer core forward-biases the FROM DCM
COMPARATOR
RESET
SWITCH
diode and current flows into the output capacitor. During LATCH
FROM CLK INCREMENT +
this time, the output voltage (neglecting the diode drop)
is reflected back to the primary coil. If the target output COUNTER 2
FROM GATE
voltage is reached, the VOUT comparator resets the master DRIVER ON
RESET
3751 F03
latch and the DONE pin goes low. Otherwise, the device
enters the next phase of operation. Figure 3. Start-Up Protection Circuitry

4. Discontinuous Mode Detection Toggling the CHARGE pin always generates a start-up
one-shot to turn on the external switch, initiating the
During secondary energy transfer to the output capacitor,
charging process. After the start-up one-shot, the LT3751
(VOUT + VDIODE)/N will appear across the primary wind-
waits for either the DCM comparator to generate a one-
ing. A transformer with no energy cannot support a DC
shot or the output of the start-up protection circuitry
voltage, so the voltage across the primary will decay to
going high, which ever comes first. If the switch drain
zero. In other words, the drain of the NMOS will ring
node, VDRAIN, is below the DCM comparator threshold
down from VTRANS + (VOUT + VDIODE)/N to VTRANS. When
(see Entering Normal Boundary Mode), the DCM compar-
the drain voltage falls to VTRANS + 20µA • RDCM, the DCM
ator will never fire and the start-up circuitry is dominant.
V

VTH1 VTH2

VDRAIN

VOUT

DCM
1-SHOT
t
START-UP BOUNDARY-MODE BELOW VTH2
(DCM THRESHOLD = VTH1) (DCM THRESHOLD = VTH2) (WAIT FOR TIME-OUT)
3751 F04

Figure 4. DCM Comparator Thresholds

3751fd

For more information www.linear.com/LT3751 11

LT3751
OPERATION
At very low output voltages, the boundary-mode switch- and indicates that the energy in the secondary winding
ing cycle period increases significantly such that the has depleted. For this to happen, VDRAIN must exceed
energy stored in the transformer core is not depleted VTRANS + ΔVDRAIN prior to its negative edge; otherwise,
before the next clock cycle. In this situation, the clock the DCM comparator will not generate a one-shot to initi-
may initiate another switching cycle before the secondary ate the next switching cycle. The part would remain stuck
winding current reaches zero and cause the LT3751 to in this state indefinitely; however, the LT3751 uses the
enter continuous-mode conduction. Normally, this is not start-up protection circuitry to jumpstart switching if the
a problem; however, if the secondary energy transfer time DCM comparator does not generate a one-shot after a
is much longer than the CLK period, significant primary maximum time-out of 500µs.
current overshoot can occur. This is due to the non-zero
Figure 4 shows a typical VDRAIN node waveform with a
starting point of the primary current when the switch
test circuit voltage clamp applied to the output. VTH1 is the
turns on and the finite speed of the current comparator.
start-up threshold and is set internally by forcing IOFFSET
The LT3751 startup circuitry adds an auxiliary current to 40μA. Once the first DCM one-shot is initiated, the
comparator with a trip level 50% higher than the nomi- mode latch is set to boundary-mode. The mode latch then
nal trip level. Every time the auxiliary current comparator sets the clock count to maximum (500µs) and lowers the
trips, the required clock count between switching cycles is DCM comparator threshold to VTH2 (IOFFSET = 20μA). This
incremented by one. This allows more time for secondary provides needed hysteresis between start-up mode and
energy transfer. boundary-mode operation.
Counter 1 in Figure 3 is set to its maximum count when
the first DCM comparator one-shot is generated. If no LOW NOISE REGULATION
DCM one-shot is initiated in normal boundary-mode oper- Low noise voltage regulation can be achieved by adding
ation during a maximum count of approximately 500µs, a resistive divider from the output node to the LT3751 FB
the LT3751 re-enters start-up mode and the count is pin. At start-up (FB pin below 1.16V), the LT3751 enters
returned to zero. the charge mode to rapidly charge the output capacitor.
Note that Counter 1 is initialized to zero at start-up. Once the FB pin is within the threshold range of 1.16V
Thus, the output of the startup circuitry will go high after to 1.34V, the part enters into low noise regulation. The
one clock cycle. Counter 2 is reset when the gate driver switching methodology in regulation mimics that used
goes high. This repeats until either the auxiliary cur- in the capacitor charging mode, but with the addition of
rent comparator increments the required clock count or peak current and duty cycle control techniques. Figure 5
until VDRAIN is high enough to sustain normal operation shows the steady state operation for both regulation tech-
described in steps 2 through 4 in the previous section. niques. Figure 6 shows how both techniques are com-
bined to provide stable, low noise operation over a wide
Entering Normal Boundary Mode load and supply range.
The LT3751 has two DCM comparator thresholds that During heavy load conditions, the LT3751 sets the peak
are dependent on what mode the part is in, either start- primary current to its maximum value, 106mV/RSENSE
up mode or normal boundary-mode, and the state of the and sets the maximum duty cycle to approximately 95%.
mode latch. For boundary-mode switching, the LT3751 This allows for maximum power delivery. At very light
requires the DCM sense voltage (VDRAIN) to exceed loads, the opposite occurs, and the LT3751 reduces the
VTRANS by the ΔDCM comparator threshold, ΔVDRAIN: peak primary current to approximately one tenth its maxi-
ΔVDRAIN = (40µA + IOFFSET) • RDCM – 40µA • RVTRANS mum value while modulating the duty cycle below 10%.
The LT3751 controls moderate loads with a combination
where IOFFSET is mode dependent. The DCM one-shot sig- of peak current mode control and duty cycle control.
nal is negative edge triggered by the switch node, VDRAIN,
3751fd

12 For more information www.linear.com/LT3751

 LT3751
OPERATION

CHARGE MODE LIGHT LOAD OPERATION

26kHz 26kHz
ONE-SHOT ONE-SHOT
CLK ... CLK ...
...
SWITCH MAXIMUM
ENABLE NO BLANKING SWITCH DUTY CYCLE DUTY CYCLE
PEAK CURRENT ...
ENABLE CONTROL CONTROL
FORCED
BLANKING
IPRI ... IPRI
...

t t
tPER ≈ 38µs

HEAVY LOAD OPERATION NO-LOAD OPERATION

26kHz
26kHz ONE-SHOT
ONE-SHOT ...
... CLK
CLK
110%
... VOUT, NOM
SWITCH PEAK CURRENT
ENABLE CONTROL VOUT ...
FORCED 105%
BLANKING VOUT, NOM
IPRI ... 1/10TH IPK ...
IPRI
t t
tPER ≈ 38µs
3751 F05

Figure 5. Modes of Operation (Steady State)

ILIM( ) DUTY CYCLE ( )

IMAX
95%

NO-LOAD
OPERATION

1/10 10%
IMAX
LOAD
0 LIGHT LOAD MODERATE HEAVY LOAD CHARGE CURRENT
LOAD MODE
3751 F06

Figure 6. Regulation Technique

3751fd

For more information www.linear.com/LT3751 13

LT3751
OPERATION
Periodic Refresh Light Load Operation
When the LT3751 enters regulation, the internal circuitry The LT3751 uses duty cycle control to drastically reduce
deactivates switching when the internal one-shot clock audible noise in both the transformer (mechanical) and
is high. The clock operates at a 1/20th duty cycle with a the ceramic capacitors (piezoelectric effects). Internal
minimum blank time of 1.5µs. This reset pulse is timed to control circuitry forces a one-shot condition at a periodic
drastically reduce switching frequency content within the rate greater than 20kHz and out of the audio spectrum.
audio spectrum and is active during all loading conditions. The regulation loop then determines the number of pulses
Each reset pulse guarantees at least one energy cycle. A that are required to maintain the correct output voltage.
minimum load is required to prevent the LT3751 from Figure 5 shows the use of duty-cycle control.
entering no-load operation.
No-Load Operation
Heavy Load Operation The LT3751 can remain in low noise regulation at very low
The LT3751 enters peak current mode control at higher loading conditions. Below a certain load current threshold
output load conditions. The control loop maximizes the (Light Load Operation), the output voltage would continue
number of switch cycles between each reset pulse. Since to increase and a runaway condition could occur. This is
the control scheme operates in boundary mode, the reso- due to the periodic one-shot forced by the periodic refresh
nant boundary-mode period changes with varying peak circuitry. By design, the LT3751 has built-in overvoltage
primary current: protection associated with the FB pin.
⎡ 1 N ⎤ When the FB pin voltage exceeds 1.34V (±20mV), the
Period = IPK • L PRI • ⎢ + ⎥
⎣ VTRANS VOUT ⎦ LT3751 enters no-load operation. No-load operation does
not reset with the one-shot clock. Instead, the pulse train
and the power output is proportional to the peak primary is completely load-dependent. These bursts are asynchro-
current: nous and can contain long periods of inactivity. This allows
1 / 2 • IPK regulation at a no-load condition but with the increase of
POUT = audible noise and voltage ripple. Note that when operating
⎡ 1 N ⎤
⎢ + ⎥ with no-load, the output voltage will increase 10% above
⎣ VTRANS VOUT ⎦ the nominal output voltage.
Noise becomes an issue at very low load currents. The
LT3751 remedies this problem by setting the lower peak
current limit to one tenth the maximum level and begins
to employ duty-cycle control.

3751fd

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 LT3751
APPLICATIONS INFORMATION
The LT3751 charger controller can be optimized for either 100
P = 20 WATTS
capacitor charging only or low noise regulation applica- 90 P = 50 WATTS
P = 100 WATTS
tions. Several equations are provided to aid in the design 80

process. 70
60

VTRANS (V)
Safety Warning 50
40
Large capacitors charged to high voltage can deliver a 30
lethal amount of energy if handled improperly. It is partic- 20
ularly important to observe appropriate safety measures 10
when designing the LT3751 into applications. First, cre- 0
1 10 100
ate a discharge circuit that allows the designer to safely PEAK PRIMARY CURRENT (A)
discharge the output capacitor. Second, adequately space 3751 F07

high voltage nodes from adjacent traces to satisfy printed Figure 7. Maximum Power Output
circuit board voltage breakdown requirements.
Selecting Transformer Turns Ratio
Selecting Operating Mode
The transformer ratio, N, should be selected based on
Tie the FB pin to GND to operate the LT3751 as a capacitor the input and output voltages. Smaller N values equate
charger. In this mode, the LT3751 charges the output at to faster charge times and larger available output power.
peak primary current in boundary mode operation. This Note that drastically reducing N below the VOUT/VTRANS
constitutes maximum power delivery and yields the fast- ratio will increase the flyback voltage on the drain of the
est charge times. Power delivery is halted once the output NMOS and increase the current through the output diode.
reaches the desired output voltage set by the RVOUT and The ratio, N, should not be drastically increased either,
RBG pins. due to the increased capacitance, N2 • CSEC, reflected to
Tie a resistor divider from the FB pin to VOUT and GND the primary. A good choice is to select N equal to VOUT/
to operate the LT3751 as a low noise voltage regulator VTRANS.
(refer to Low Noise regulation section for proper design VOUT
N≤
procedures). The LT3751 operates as a voltage regulator VTRANS
using both peak current and duty cycle modulation to
vary output current during different loading conditions. Choosing Capacitor Charger IPK

Selecting Component Parameters When operating the LT3751 as capacitor charger, choose
IPK based on the required capacitor charge time, tCHARGE,
Most designs start with the initial selection of VTRANS, and the initial design inputs.
VOUT, COUT, and either charge time, tCHARGE, (capacitor
charger) or POUT,MAX (regulator). These design inputs IPK =
( 2 • N • VTRANS + VOUT ) • COUT • VOUT
are then used to select the transformer ratio, N, the peak Efficiency • VTRANS • ( tCHARGE − t d )
primary current, IPK, and the primary inductance, LPRI.
The converter efficiency varies over the output voltage
Figure 7 can be used as a rough guide for maximum
range. The IPK equation is based on the average efficiency
power output for a given VTRANS and IPK.
over the entire charging period. Several factors can cause
the charge time to increase. Efficiency is the most domi-
nant factor and is mainly affected by the transformer
winding resistance, core losses, leakage inductance, and
transistor RDS. Most applications have overall efficiencies
above 70%.
3751fd

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LT3751
APPLICATIONS INFORMATION
The total propagation delay, td, is the second most domi- Transformer Design
nant factor that affects efficiency and is the summation of The transformer’s primary inductance, LPRI, is determined
gate driver on-off propagation delays and the discharge by the desired VOUT and previously calculated N and IPK
time associated with the secondary winding capacitance. parameters. Use the following equation to select LPRI:
There are two effective methods to reduce the total propa-
gation delay. First, reduce the total capacitance on the 3µs • VOUT
L PRI =
secondary winding, most notably the diode capacitance. IPK • N
Second, reduce the total required NMOS gate charge.
Figure 8 shows the effect of large secondary capacitance. The previous equation guarantees that the VOUT com-
parator has enough time to sense the flyback waveform
The energy stored in the secondary winding capacitance and trip the DONE pin latch. Operating VOUT significantly
is ½ • CSEC • VOUT 2. This energy is reflected to the primary higher than that used to calculate LPRI could result in a
when the diode stops forward conduction. If the reflected runaway condition and overcharge the output capacitor.
capacitance is greater than the total NMOS drain capaci-
tance, the drain of the NMOS power switch goes negative The LPRI equation is adequate for most regulator applica-
and its intrinsic body diode conducts. It takes some time tions. Note that if both IPK and N are increased signifi-
for this energy to be dissipated and thus adds to the total cantly for a given VTRANS and VOUT, the maximum IPK will
propagation delay. not be reached within the refresh clock period. This will
result in a lower than expected maximum output power.
To prevent this from occurring, maintain the condition in
VDRAIN
the following equation.
38µs
L PRI <
ISEC ⎡ 1 N ⎤
NO SEC. IPK • ⎢ + ⎥
CAPACITANCE ⎣ VTRANS VOUT ⎦
IPRI
The upper constraint on LPRI can be reduced by increas-
SEC. DISCHARGE
t ing VTRANS and starting the design process over. The best
3751 F08
regulation occurs when operating the boundary-mode
Figure 8. Effect of Secondary Winding Capacitance frequency above 100kHz (refer to Operation section for
boundary-mode definition).
Choosing Regulator Maximum IPK Figure 9 defines the maximum boundary-mode switching
frequency when operating at a desired output power level
The IPK parameter in regulation mode is calculated based
and is normalized to LPRI/POUT (μH/Watt). The relation-
on the desired maximum output power instead of charge
ship of output power, boundary-mode frequency, IPK, and
time like that in a capacitor charger application.
primary inductance can be used as a guide throughout
POUT(AVG) ⎛ 1 N ⎞ the design process.
IPK = 2 • •⎜ + ⎟
Efficiency ⎝ VTRANS VOUT ⎠

Note that the LT3751 regulation scheme varies the peak

current based on the output load current. The maximum
IPK is only reached during charge mode or during heavy
load conditions where output power is maximized.

3751fd

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 LT3751
APPLICATIONS INFORMATION
Table 1. Recommended Transformers
MANUFACTURER PART NUMBER SIZE L × W × H (mm) MAXIMUM IPRI (A) LPRI (µH) TURNS RATIO (PRI:SEC)
Coilcraft DA2033-AL 17.4 × 24.1 × 10.2 5 10 1:10
www.coilcraft.com DA2034-AL 20.6 × 30 × 11.3 10 10 1:10
GA3459-BL 32.65 × 26.75 × 14 20 5 1:10
GA3460-BL 32.65 × 26.75 × 14 50 2.5 1:10
HA4060-AL 34.29 × 26.75 × 14 2 300 1:3
HA3994-AL 34.29 × 28.75 × 14 5 7.5 2:1:3:3*
Würth Elektronik/Midcom 750032051 28.7 × 22 × 11.4 5 10 1:10
www.we-online.com 750032052 28.7 × 22 × 11.4 10 10 1:10
750310349 36.5 × 42 × 23 20 5 1:10
750310355 36.5 × 42 × 23 50 2.5 1:10
Sumida C8117 23 × 18.6 × 10.8 5 10 1:10
www.sumida.com C8119 32.2 × 27 × 14 10 10 1:10
PS07-299 32.5 × 26.5 × 13.5 20 5 1:10
PS07-300 32.5 × 26.5 × 13.5 50 2.5 1:10
TDK DCT15EFD-U44S003 22.5 × 16.5 × 8.5 5 10 1:10
www.tdk.com DCT20EFD-U32S003 30 × 22 × 12 10 10 1:10
DCT25EFD-U27S005 27.5 × 33 × 15.5 20 5 1:10
*Transformer has three secondaries where the ratio is designated as PRI:SEC1:SEC2:SEC3

RVTRANS, RVOUT and RDCM Selection

10.000
fMAX = 50kHz
fMAX = 100kHz RVTRANS sets the common-mode reference voltage for
fMAX = 200kHz
both the DCM comparator and VOUT comparator. Select
1.000
RVTRANS from Table 2 based on the transformer supply
LPRI/WATT (µH/WATT)

voltage range, VTRANS, and the maximum trip voltage,

0.100 ∆VDRAIN (VDRAIN-VTRANS).
The RVTRANS pin is connected to an internal 40µA current
0.010 source. Pin current increases as the pin voltage is taken
higher than the internal 60V Zener clamp. The LT3751 can
0.001 operate from VTRANS greater than the 60V internal Zener
1 10 100
PEAK PRIMARY CURRENT (A)
clamps by limiting the RVTRANS pin current to 250µA.
Operating VTRANS above 200V requires the use of resis-
3751 F09

Figure 9. Maximum Switching Frequency tor dividers. Two applications are presented that operate

Table 2. Suggested RVTRANS, RVOUT, and RDCM Values

VTRANS Range ∆VDRAIN RANGE RVTRANS RVOUT RDCM
(V) (V) (kΩ) (kΩ) (kΩ)
4.75 to 55 0 to 5 5.11 5.11 2.32
2.5 to 50 25.5 25.5 11.5
4.75 to 60
5 to 80 40.2 40.2 18.2
8 to 80 8 to 160 80.6 80.6 36.5

VTRANS − 55V VTRANS − 55V

80 to 200 2mA • RVOUT 0.86 • RVTRANS
0.25 0.25

>200 Resistor Divider Dependent Use Resistor Divider Use Resistor Divider Use Resistor Divider

3751fd

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LT3751
APPLICATIONS INFORMATION
with VTRANS between 100V and 400V (refer to Typical RVOUT from Table 2 meets this criterion. Use the following
Applications section). Consult applications engineering equation to size RBG (VTRANS ≤ 80V):
for applications with VTRANS operating above 400V.
⎛ RVOUT ⎞
RVOUT is required for capacitor charger applications but RBG = 0.98 •N • ⎜⎜ ⎟⎟
may be removed for regulator applications. Note that the ⎝ VOUT,TRIP + VDIODE ⎠
VOUT comparator can be used as secondary protection
for regulator applications. If the VOUT comparator is used Tie RBG pin to ground when not using the VOUT compara-
for protection, design VOUT,TRIP 15% to 20% higher than tor. Consult applications engineering for calculating RBG
the regulation voltage. Tie the RVOUT pin to ground when when operating VTRANS above 80V.
RVOUT resistor is removed.
NMOS Switch Selection
RDCM needs to be properly sized in relation to RVTRANS.
Improper selection of RDCM can lead to undesired switch- Choose an external NMOS power switch with minimal
ing operation at low output voltages. Use Table 2 to size gate charge and on-resistance that satisfies current limit
RDCM. and voltage break-down requirements. The gate is nomi-
nally driven to VCC – 2V during each charge cycle. Ensure
Parasitic capacitance on RVTRANS , RVOUT, and RDCM that this does not exceed the maximum gate to source
should be minimized. Capacitances on these nodes slow voltage rating of the NMOS but enhances the channel
down the response times of the VOUT and DCM com- enough to minimize the on-resistance.
parators. Keep the distance between the resistor and
pin short. It is recommended to remove all ground and Similarly, the maximum drain-source voltage rating of
power planes underneath these pins and their respective the NMOS must exceed VTRANS + VOUT/N or the magni-
components (refer to the recommended board layout at tude of the leakage inductance spike, whichever is greater.
the end of this section). The maximum instantaneous drain current rating must
exceed selected current limit. Because the switching
RBG Selection period decreases with output voltage, the average current
though the NMOS is greatest when the output is nearly
RBG sets the trip current (0.98/RBG) and is directly related
charged and is given by:
to the selection of RVOUT. The best accuracy is achieved
IPK • VOUT(PK)
with a trip current between 100µA and 2mA. Choosing IAVG,M =
2(VOUT(PK) + N • VTRANS )

See Table 3 for recommended external NMOS transistors.

Table 3. Recommended NMOS Transistors
MANUFACTURER PART NUMBER ID (A) VDS(MAX) (V) RDS(ON) (mΩ) QG(TOT) (nC) PACKAGE
Fairchild Semiconductor FDS2582 4.1 150 66 11 SO-8
www.fairchildsemi.com FQB19N20L 21 200 140 27 D2PAK
FQP34N20L 31 200 75 55 TO-220
FQD12N20L 12 200 280 16 DPAK
FQB4N80 3.9 800 3600 19 D2PAK
On Semiconductor MTD6N15T4G 6 150 300 15 DPAK
www.onsemi.com NTD12N10T4G 12 100 165 14 DPAK
NTB30N20T4G 30 200 81 75 D2PAK
NTB52N10T4G 52 100 30 72 D2PAK
Vishay Si7820DN 2.6 200 240 12.1 1212-8
www.vishay.com Si7818DN 3.4 150 135 20 1212-8
SUP33N20-60P 33 200 60 53 TO-220

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 LT3751
APPLICATIONS INFORMATION
Table 4. Recommended Output Diodes
MANUFACTURER PART NUMBER IF(AV) (A) VRRM (V) TRR (ns) PACKAGE
Central Semiconductor CMR1U-10M 1 1000 100 SMA
www.centralsemi.com CMSH2-60M 2 60 SMA
CMSH5-40 5 40 SMC
Fairchild Semiconductor ES3J 3 600 35 SMC
www.fairchildsemi.com ES1G 1 400 35 SMA
ES1J 1 600 35 SMA
On Semiconductor MURS360 3 600 75 SMC
www.onsemi.com MURA260 2 600 75 SMA
MURA160 1 600 75 SMA
Vishay USB260 2 600 30 SMB
www.vishay.com US1G 1 400 50 SMA
US1M 1 1000 75 SMA
GURB5H60 5 600 30 D2PAK

Gate Driver Operation The average diode current is also a function of the output
voltage.
The LT3751 gate driver has an internal, selectable 10.5V
or 5.6V clamp with up to 2A current capability (using IPK • VTRANS
IAVG =
LVGATE). For 10.5V operation, tie CLAMP pin to ground, 2 • (VOUT + N • VTRANS )
and for 5.6V operation, tie the CLAMP pin to the VCC pin.
Choose a clamp voltage that does not exceed the NMOS The highest average diode current occurs at low output
manufacturer’s maximum VGS ratings. The 5.6V clamp voltages and decreases as the output voltage increases.
can also be used to reduce LT3751 power dissipation Reverse recovery time, reverse bias leakage and junction
and increase efficiency when using logic-level FETs. The capacitance should also be considered. All affect the over-
typical gate driver overshoot voltage is 0.5V above the all charging efficiency. Excessive diode reverse recovery
clamp voltage. times can cause appreciable discharging of the output
capacitor, thereby increasing charge time. Choose a diode
The LT3751’s gate driver also incorporates a PMOS pull- with a reverse recovery time of less than 100ns. Diode
up device via the LVGATE pin. The PMOS pull-up driver leakage current under high reverse bias bleeds the output
should only be used for VCC applications of 8V or below. capacitor of charge and increases charge time. Choose a
Operating LVGATE with VCC above 8V will cause perma- diode that has minimal reverse bias leakage current. Diode
nent damage to the part. LVGATE is active when tied to junction capacitance is reflected back to the primary, and
HVGATE and allows rail-to-rail gate driver operation. This energy is lost during the NMOS intrinsic diode conduction.
is especially useful for low VCC applications, allowing bet- Choose a diode with minimal junction capacitance. Table 4
ter NMOS drive capability. It also provides the fastest rise recommends several output diodes for various output
times, given the larger 2A current capability verses 1.5A voltages that have adequate reverse recovery times.
when using only HVGATE.
Setting Current Limit
Output Diode Selection
Placing a sense resistor from the positive sense pin, CSP,
The output diode(s) are selected based on the maximum to the negative sense pin, CSN, sets the maximum peak
repetitive reverse voltage (VRRM) and the average for- switch current. The maximum current limit is nominally
ward current (IF(AV)). The output diode’s VRRM should 106mV/RSENSE. The power rating of the current sense
exceed VOUT + N • VTRANS. The output diode’s IF(AV) resistor must exceed:
should exceed IPK /2N, the average short-circuit current. 2
I • R SENSE ⎛ VOUT(PK) ⎞
PRSENSE ≥ PK ⎜
⎜V
⎟
⎟
3 ⎝ OUT(PK) + N • VTRANS ⎠
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LT3751
APPLICATIONS INFORMATION
Additionally, there is approximately a 180ns propaga- Under/Overvoltage Lockout
tion delay from the time that peak current limit is The LT3751 provides user-programmable under and
detected to when the gate transitions to the low state. overvoltage lockouts for both VCC and VTRANS. Use the
This delay increases the peak current limit by (VTRANS) equations in the Pin Functions section for proper selection
(180ns)/LPRI. of resistor values. When under/overvoltage lockout com-
Sense resistor inductance (LRSENSE) is another source of parators are tripped, the master latch is disabled, power
current limit error. LRSENSE creates an input offset voltage delivery is halted, and the FAULT pin goes low.
(VOS) to the current comparator and causes the current
Adequate supply bulk capacitors should be used to reduce
comparator to trip early. VOS can be calculated as:
power supply voltage ripple that could cause false tripping
⎛L ⎞ during normal switching operation. Additional filtering
VOS = VTRANS • ⎜ RSENSE ⎟ may be required due to the high input impedance of the
⎝ L PRIMARY ⎠
under/overvoltage lockout pins to prevent false tripping.
The change in current limit becomes VOS /RSENSE. The Individual capacitors ranging from 100pF to 1nF may be
error is more significant for applications using large di/ placed between each of the UVLO1, UVLO2, OVLO1 and
dt ratios in the transformer primary. It is recommended to OVLO2 pins and ground. Disable the undervoltage lock-
use very low inductance (< 2nH) sense resistors. Several outs by directly connecting the UVLO1 and UVLO2 pins
resistors can be placed in parallel to help reduce the to VCC. Disable the overvoltage lockouts by directly con-
inductance. necting the OVLO1 and OVLO2 pins to ground.
Care should also be taken in placement of the sense lines. The LT3751 provides internal Zener clamping diodes to
The negative return line, CSN, must be a dedicated trace protect itself in shutdown when VTRANS is operated above
to the low side resistor terminal. Haphazardly routing the 55V. Supply voltages should only be applied to UVLO1,
CSN connection to the ground plane can cause inaccurate UVLO2, OVLO1 and OVLO2 with series resistance such
current limit and can also cause an undesirable discon- that the Absolute Maximum pin currents are not exceeded.
tinuous charging profile. Pin current can be calculated using:
V − 55V
DONE and FAULT Pin Design IPIN = APPLIED
R SERIES
Both the DONE and FAULT pins require proper pull-up
resistors or current sources. Limit pin current to 1mA Note that in shutdown, RVTRANS, RVOUT, RDCM, UVLO1,
into either of these pins. 100kΩ pull-up resistors are rec- UVLO2, OVLO1 and OVLO2 currents increase significantly
ommended for most applications. Both the DONE and when operating VTRANS above the Zener clamp voltages
FAULT pins are latched in the low output state. Resetting and are inversely proportional to the external series pin
either latch requires the CHARGE pin to be toggled. A fault resistances.
condition will also cause the DONE pin to go low. A third,
non-latching condition occurs during startup when the NMOS Snubber Design
CHARGE pin is driven high. During this start-up condi- The transformer leakage inductance causes a parasitic
tion, both the DONE and FAULT pins will go low for several voltage spike on the drain of the power NMOS switch dur-
micro seconds. This indicates the internal rails are still ing the turn-off transition. Transformer leakage inductance
ramping to their proper levels. External RC filters may be effects become more apparent at high peak primary cur-
added to both indication pins to remove start-up indica- rents. The worst-case magnitude of the voltage spike is
tion. Time constants for the RC filter should be between determined by the energy stored in the leakage inductance
5µs to 20µs. and the total capacitance on the VDRAIN node.

3751fd

20 For more information www.linear.com/LT3751

 LT3751
APPLICATIONS INFORMATION
2
LOW NOISE REGULATION
L LEAK • IPK
VD,LEAK = The LT3751 has the option to provide a low noise regu-
C VDRAIN
lated output voltage when using a resistive voltage divider
Two problems can arise from large VD,LEAK. First, the from the output node to the FB pin. Refer to the Selecting
magnitude of the spike may require an NMOS with an Component Parameters section to design the transformer,
unnecessarily high V(BR)DSS which equates to a larger NMOS power switch, output diode, and sense resistor.
RDS(ON). Secondly, the VDRAIN node will ring—possibly Use the following equations to select the feedback resis-
below ground—causing false tripping of the DCM com- tor values based on the power dissipation and desired
parator or damage to the NMOS switch (see Figure 11). output voltage:
Both issues can be remedied using a snubber. If leakage 2
inductance causes issues, it is recommended to use a RC RFBH
( V − 1.22 )
= OUT ; Top Feedback Resistor
snubber in parallel with the primary winding, as shown PD
in Figure 10. Size CSNUB and RSNUB based on the desired ⎛ 1.22 ⎞
leakage spike voltage, known leakage inductance, and an RFBL = ⎜ ⎟ • RFBH ; Bottom Feedback Resistor
⎝ VOUT − 1.22 ⎠
RC time constant less than 1µs. Otherwise, the leakage
voltage spike can cause false tripping of the VOUT com- RFBH, depending on output voltage and type used, may
parator and stop charging prematurely. require several smaller values placed in series. This will
reduce the risk of arcing and damage to the feedback
Figure 11 shows the effect of the RC snubber resulting in resistors. Consult the manufacturer’s rated voltage speci-
a lower voltage spike and faster settling time. fication for safe operation of the feedback resistors.
The LT3751 has a minimum periodic refresh frequency
• limit of 23kHz. This drastically reduces switching fre-
RSNUB LPRI quency components in the audio spectrum. The LT3751
•
can operate with no-load, but the regulation scheme
CSNUB
switches to no-load operation and audible noise and
LLEAK
output voltage ripple increase. This can be avoided by
operating with a minimum load current.
CVDRAIN
Minimum Load Current
3751 F11
Periodic refresh circuitry requires an average minimum
Figure 10. RC Snubber Circuit load current to avoid entering no-load operation. Usually,
the feedback resistors should be adequate to provide this
minimum load current.
VDRAIN
(WITHOUT 2
SNUBBER) L • I • 23kHz
0V
ILOAD(MIN) ≥ PRI PK
100 • VOUT
NMOS DIODE
VDRAIN
(WITH
CONDUCTS
IPK is the peak primary current at maximum power deliv-
SNUBBER)
0V
ery. The LT3751 will enter no-load operation if the mini-
IPRI
mum load current is not met. No-load operation will pre-
vent the application from entering a runaway condition;
3751 F12
however, the output voltage will increase 10% over the
nominal regulated voltage.
Figure 11. Effects of RC Snubber
3751fd

For more information www.linear.com/LT3751 21

LT3751
APPLICATIONS INFORMATION
Large Signal Stability Small Signal Stability
Large signal stability can be an issue when audible noise The LT3751’s error amplifier is internally compensated to
is a concern. Figure 12 shows that the problem originates increase its operating range but requires the converter’s
from the one-shot clock and the output voltage ripple. output node to be the dominant pole. Small signal stability
The load must be constrained such that the output volt- constraints become more prevalent during heavy load-
age ripple does not exceed the regulation range of the ing conditions where the dominant output pole moves
error amplifier within one clock period (approximately to higher frequency and closer to the internal feedback
6mV referred to the FB pin). poles and zeros. The feedback loop requires the output
pole frequency to remain below 200Hz to guarantee small
The output capacitance should be increased if oscillations
signal stability. This allows smaller RLOAD values than the
occur or audible noise is present. Use Figure 13 to deter-
large signal constraint. Thus, small signal issues should
mine the maximum load for a given output capacitance to
not arise if the large signal constraint is met.
maintain low audible noise operation. A small capacitor
can also be added from the FB pin to ground to lower the Board Layout
ripple injected into FB pin.
The high voltage operation of the LT3751 demands care-
LOAD
DROOP ful attention to the board layout, observing the following
VOUT
points:
1. Minimize the area of the high voltage end of the sec-
ondary winding.
IPRI
2. Provide sufficient spacing for all high voltage nodes
(NMOS drain, VOUT and secondary winding of the
26kHz
ONE-SHOT transformer) in order to meet the breakdown voltage
CLK
requirements.
3751 F13

3. Keep the electrical path formed by CVTRANS, the primary

Figure 12. Voltage Ripple Stability Constraint of T1, and the drain of the NMOS as short as possible.
Increasing the length of this path effectively increases
30 the leakage inductance of T1, potentially resulting in an
VOUT = 150V
VOUT = 300V overvoltage condition on the drain of the NMOS.
25 VOUT = 600V
4. Reduce the total node capacitance on the RVOUT and
20 RDCM pins by removing any ground or power planes
COUT, MIN (µF)

underneath the RDCM and RVOUT pads and traces.

15
Parasitic capacitance can cause unwanted behavior
10 on these pins.
5 5. Thermal vias should be added underneath the Exposed
Pad, Pin 21, to enhance the LT3751’s thermal perfor-
0
0 50 100 150 200 mance. These vias should go directly to a large area of
OUTPUT POWER (W)
3751 F14
ground plane.
6. Isolated applications require galvanic separation of the
Figure 13. COUT(MIN) vs Output Power
output-side ground and primary-side ground. Adequate
spacing between both ground planes is needed to meet
voltage safety requirements.
3751fd

22 For more information www.linear.com/LT3751

 POWER
POWER
GND RETURN
GND CVTRANS1 CVTRANS2 CVTRANS3 CVTRANS4

+ +
REMOVE COPPER
FROM ALL SUB-LAYERS
(SEE ITEM 4)
RVTRANS

RUVLO1
VTRANS
T1
RDCM 1:N
ROVLO1

20 19 18 17
RVOUT
RUVLO2
APPLICATIONS INFORMATION

1 16 • •
ROVLO2
2

PRIMARY
15 SECONDARY
RBG ANALOG
3 14 GND
RFAULT LT3751
VCC 4 13

5 12
ANALOG VCC
RDONE GND VIAS CVCC POWER
6 11
GND
ANALOG M1
CHARGE GND

For more information www.linear.com/LT3751

7 8 9 10
RSENSE DVOUT CVOUT1 CVOUT2
+

SINGLE
CFB
POINT
ANALOG GND
GND RFBL
VOUT

POWER
RFBH3 GND RETURN RFBH2 RFBH1

3751 F15

Figure 14. QFN Package Recommended Board Layout (Not to Scale)

23
3751fd
LT3751
24
LT3751

VTRANS
CVTRANS1 CVTRANS2 DVOUT
CVTRANS3 CVTRANS4
+ + T1 VOUT
1:N
RVTRANS
REMOVE COPPER
FROM ALL SUB-LAYERS
POWER (SEE ITEM 4)
GND
POWER
RUVLO1 GND RETURN

ANALOG RDCM
GND
ROVLO1 •
RVOUT

PRIMARY
1 20 •
SECONDARY
APPLICATIONS INFORMATION

2 19 CVOUT1 CVOUT2
RUVLO2
3 18 +
RBG
4 17 ANALOG
5 16 GND
ROVLO2 LT3751
6 15
7 14
VCC
RFAULT 8 13 RFBH1
CVCC
9 12
10 11

For more information www.linear.com/LT3751

RDONE M1

RSENSE RFBH2
ANALOG
VCC CFB GND

RFBL POWER
CHARGE GND RETURN

3751 F16

Figure 15. TSSOP Package Recommended Board Layout (Not to Scale)

3751fd
 LT3751
TYPICAL APPLICATIONS
42A Capacitor Charger

DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

T1** D1 D2***
VTRANS 1:10 VOUT * M1, M2 REQUIRES PROPER
12V TO 24V + C3 R6 C2 500V HEATSINK/THERMAL DISSIPATION
1000µF 40.2k 10µF • TO MEET MANUFACTURER’S SPECIFICATIONS
×3 + C4 ** THERMAL DISSIPATION OF T1 WILL LIMIT
RVTRANS • 1200µF THE CHARGE/DISCHARGE DUTY CYCLE OF C4
OFF ON CHARGE R7, 18.2k
CLAMP RDCM *** D2 MAY BE OMITTED FOR OUTPUT
VCC VOLTAGE OPERATION BELOW 300V
VCC LT3751 R8, 40.2k 4.7nF
12V TO 24V
C1 RVOUT Y-RATED
R10, 100k
10µF
DONE
R11, 100k HVGATE M1, M2*
FAULT LVGATE VCC
R1, 191k CSP C1: 25V X5R OR X7R CERAMIC CAPACITOR
UVLO1 C2: 25V X5R OR X7R CERAMIC CAPACITOR
R5
VTRANS C3: 25V ELECTROLYTIC
R2, 475k 2.5mΩ
OVLO1 CSN C4: HITACHI FX22L122Y 1200µF, 550V ELECTROLYTIC
R3, 191k OR: CORNELL DUBILIER DCMC192T550CE2B 1900µF, 550V ELECTROLYTIC
UVLO2 FB D1, D2: VISHAY GURB5H60 600V, 5A ULTRAFAST RECTIFIER
VCC M1, M2: 2 PARALLEL VISHAY SUP33N20-60P 200V, 33A NMOS
R4, 475k
OVLO2 R1 THRU R4, R6 THRU R11: USE 1% 0805 RESISTORS
R5: USE 2 PARALLEL 5mΩ IRC LR SERIES 2512 RESISTORS
GND RBG T1: COILCRAFT GA3460-BL 50A SURACE MOUNT TRANSFORMER
3751 TA02
R9
FOR ANY VOUT VOLTAGE BETWEEN
787Ω
50V AND 500V SELECT R9 ACCORDING TO:

⎛ 40.2kΩ ⎞
R9 = 0.98 • N • ⎜⎜ ⎟⎟
⎝ VOUT + VDIODE ⎠

Efficiency Output Capacitor Charge Times Charging Waveform

85 1200
VOUT = 500V, VTRANS = 24V VOUT = 500V
VOUT = 500V, VTRANS = 12V VTRANS = 24V
VOUT = 300V, VTRANS = 24V C4 = 1200µF
VOUT = 300V, VTRANS = 12V
80 VOUT = 100V,
CHARGE TIME (ms)

800 VTRANS = 24V

EFFICIENCY (%)

VOUT = 100V,
VTRANS = 12V
75 VOUT
100V/DIV
400
70 AVERAGE
INPUT
VTRANS = 12V CURRENT
VTRANS = 24V 5A/DIV
65 0
50 150 250 350 450 200 400 600 800 1000 1200 100ms/DIV
3751 TA02d

OUTPUT VOLTAGE (V) OUTPUT CAPACITANCE (µF)

3751 TA02b 3751 TA02c

3751fd

For more information www.linear.com/LT3751 25

LT3751
TYPICAL APPLICATIONS
High Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

T1* D1
VTRANS 1:10 VOUT
5V TO 24V + C3 C2
100V TO 500V
R6 • C5
680µF 5× 2.2µF
40.2k + 0.47µF * M1 AND T1 REQUIRE PROPER
C4*** HEATSINK/THERMAL DISSIPATION
• 100µF TO MEET MANUFACTURER’S SPECIFICATIONS
RVTRANS R7, 18.2k
OFF ON CHARGE RDCM
** DEPENDING ON DESIRED OUTPUT VOLTAGES,
CLAMP
R10 MUST BE SPLIT INTO MULTIPLE RESISTORS,
LT3751 R8, 40.2k TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION.
VCC VCC RVOUT
5V TO 24V
C1 *** C4 MUST BE SIZED TO MEET LARGE SIGNAL
10µF TO DONE
STABILITY CRITERIA DESCRIBED IN THE
MICRO HVGATE M1*
VCC APPLICATIONS INFORMATION SECTION
FAULT LVGATE
R1, 69.8k CSP
UVLO1 R5 C1: 25V X5R OR X7R CERAMIC
VTRANS 6mΩ
R2, 475k C2: 25V X5R OR X7R CERAMIC
OVLO1 CSN C3: 25V ELECTROLYTIC
R10**
R3, 69.8k C5: TDK CKG57NX7R2J474M
UVLO2 D1: VISHAY US1M 1000V
VCC R4, 475k FB M1: FAIRCHILD FQP34N20L
OVLO2 C6 R1 THRU R4, R6 THRU R9, R11: USE 1% 0805
R11
GND RBG 10nF R5: IRC LR SERIES 2512 RESISTORS
3751 TA04
R10: USE 200V 1206 RESISTOR(S)
T1: COILCRAFT GA3459-AL
R9

Suggested Component Values Steady-State Operation with

IOUT(MAX) (mA) IOUT(MAX) (mA) 1.1mA Load Current
VOUT AT VTRANS = 5V, AT VTRANS = 24V, R9 R11 R10
VOUT
(V) 5% VOUT DEFLECTION 5% VOUT DEFLECTION (kΩ) (kΩ) (kΩ) AC COUPLED
100 180 270 3.32 0.383 30.9 2V/DIV

200 110 315 1.65 0.768 124 VDRAIN

50V/DIV
300 75 245 1.10 1.13 274
IPRI
400 55 200 0.825 1.54 499 10A/DIV
500† 40 170 Tie to GND 1.74 715 3751 TA03b

† Transformer primary inductance limits V 10µs/DIV

OUT comparator operation to VOUT = 400VMAX. RVOUT
and RBG should be tied to ground when operating VOUT above 400V.

Steady-State Operation with

Efficiency (VOUT = 500V) Load Regulation (VOUT = 500V) 100mA Load Current
90 515
VTRANS = 24V VOUT
COUPLED
85 2V/DIV
VTRANS = 12V 510
VDRAIN
OUTPUT VOLTAGE (V)

80 VTRANS = 24V 50V/DIV

EFFICIENCY (%)

75 505 IPRI
10A/DIV
VTRANS = 5V
70 VTRANS = 12V 3751 TA03e
10µs/DIV
500
65
VTRANS = 5V
60 495
0 50 100 150 200 0 50 100 150 200
ILOAD (mA) ILOAD (mA)
3751 TA03c 3751 TA03d
3751fd

26 For more information www.linear.com/LT3751

 LT3751
TYPICAL APPLICATIONS
1.6A High Input Voltage, Isolated Capacitor Charger

DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

VTRANS F1, 1A T1* D1 D2

100V TO 1:3 VOUT * T1 REQUIRES PROPER THERMAL MANAGEMENT
400VDC + C3 R6 C2
50V TO 500V TO ACHIEVE DESIRED OUTPUT POWER LEVELS
47µF 625k 2.2µF • + C4 ** M1 REQUIRES PROPER HEAT SINK/THERMAL
×5 220µF
R7, 96.2k DISSIPATION TO MEET MANUFACTURER’S
• SPECIFICATIONS
R8
RVTRANS 417k
C5 FOR ANY OUTPUT VOLTAGE BETWEEN 50V
OFF ON CHARGE RDCM
0.47µF TO 500V, SET R12 GIVEN BY:
CLAMP R9
LT3751 67.3k 0.98
VCC R10 R12 =
VCC 208k VOUT,TRIP
10V TO 24V 4.7nF
C1 RVOUT Y-RATED + 40µA • 2
10µF TO DONE R11 3 • R10
MICRO 32.1k R5
FAULT C1: 25V X5R OR X7R CERAMIC
20Ω C2: 630V X5R OR X7R CERAMIC
R1, 1.5M HVGATE M1**
UVLO1 C3: 450V ILLINOIS CAP 476CKE450MQW
VTRANS LVGATE VCC C4: 50V TO 500V ELECTROLYTIC
R2, 9M FB
OVLO1 C5: TDK CKG57NX7R2J474M
R3, 154k CSP D1, D2: VISHAY US1M 1000V
UVLO2 R13 F1: BUSSMANN PCB-1-R
VCC R4, 475k 68mΩ M1: FAIRCHILD FQB4N80
OVLO2 CSN R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
R3 THRU R5, R9, R12: 0805 RESISTORS, 1%
GND RBG
R6, R10: 3 X 1206 RESISTORS IN SERIES, 0.1%
3751 TA04a
R7, R11: 0805 RESISTORS, 0.1%
R12 R8: 3 X 1206 RESISTORS IN SERIES, 1%
R13: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL

Output Trip Voltage

and Charge Time
(VOUT = 500V, COUT = 220µF) Efficiency Charging Waveform
530 1000 100
VOUT = 500V
VTRANS = 300V
95
VOUT = 12V
VIN = 100V
520 850
90
CHARGE TIME (ms)

EFFICIENCY (%)

VIN = 250V
VOUT,TRIP (V)

VOUT,TRIP
85
510 700 VOUT
VIN = 400V
80 100V/DIV
CHARGE TIME AVERAGE
75 INPUT
500 550
CURRENT
70 200mA/DIV
CHARGE
490 400 65 10V/DIV
100 200 300 400 50 150 250 350 450 100ms/DIV
3751 TA04d

INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

3751 TA04b 3751 TA04c

3751fd

For more information www.linear.com/LT3751 27

LT3751
TYPICAL APPLICATIONS
High Input Voltage, High Output Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

T1* VOUT
VTRANS F1, 1A D1 D2
1:3 100V TO 500V
100V TO
400VDC + C3 C2
* T1 REQUIRES PROPER THERMAL MANAGEMENT
R6, 625k TO ACHIEVE DESIRED OUTPUT POWER LEVELS
47µF 2.2µF • C4
+
R7, 97.6k ×5 100µF ** M1 REQUIRES PROPER HEAT SINK/THERMAL
• DISSIPATION TO MEET MANUFACTURER’S
RVTRANS R8, 417k SPECIFICATIONS
C5
OFF ON CHARGE RDCM 0.47µF
CLAMP R9 *** DEPENDING ON DESIRED OUTPUT VOLTAGE,
VCC LT3751 67.3k R10 MUST BE SPLIT INTO MULTIPLE RESISTORS
10V TO VCC RVOUT TO MEET MANUFACTURER’S VOLTAGE SPECIFICATION
24V C1
10µF TO DONE R5, 20Ω C1: 25V X5R OR X7R CERAMIC
MICRO HVGATE M1** C2: 630V X5R OR X7R CERAMIC
FAULT LVGATE VCC C3: 450V ILLINOIS CAP 476CKE450MQW
R1, 1.5M CSP C4: 50V TO 500V ELECTROLYTIC
UVLO1 R12 C5: TDK CKG57NX7R2J474M
VTRANS 68mΩ
R2, 9M C6: 6.3V X5R OR X7R CERAMIC
OVLO1 CSN D1, D2: VISHAY US1M 1000V
R10***
R3, 154k F1: BUSSMANN PCB-1-R
UVLO2 M1: FAIRCHILD FQB4N80
VCC R4, 475k FB R1, R2: 2 X 1206 RESISTORS IN SERIES, 1%
OVLO2 C6 R3 THRU R5, R7, R9, R11: 0805 RESISTORS, 1%
R11
GND RBG 10nF R6, R8: 3 X 1206 RESISTORS IN SERIES, 1%
3751 TA05a
R10: 1206 RESISTOR(S), 1%
R12: IRC LR SERIES 1206 RESISTOR, 1%
T1: COILCRAFT HA4060-AL

Suggested Component Values

IOUT(MAX) (mA) IOUT(MAX) (mA)
VOUT AT VTRANS = 100V, AT VTRANS = 400V, R10 R11
(V) 1% VOUT DEFLECTION 1% VOUT DEFLECTION (kΩ) (kΩ)
100 55 130 30.9 0.383
200 110 150 124 0.768
300 95 175 274 1.13
400 80 130 499 1.54
500 65 140 715 1.74

Steady-State Operation with

Efficiency Line Regulation 50mA Load Current
90 398
VIN = 200V
VIN = 100V
VOUT = 400V
80 VIN = 250V
IOUT = 10mA
VDRAIN
OUTPUT VOLTAGE (V)

397 100V/DIV
EFFICIENCY (%)

70 IOUT = 25mA

VIN = 400V
60
396 IOUT = 50mA
IPRI
50 2A/DIV

40 395
0 25 50 75 100 200 300 400 10µs/DIV
3751 TA05d

OUTPUT CURRENT (mA) 3751 TA05b

INPUT VOLTAGE (V) 3751 TA05c

3751fd

28 For more information www.linear.com/LT3751

 LT3751
TYPICAL APPLICATIONS
Isolated 282V Voltage Regulator
DANGER HIGH VOLTAGE! OPERATION BY HIGH VOLTAGE TRAINED PERSONNEL ONLY

D2 R2, 10Ω ISOLATION BOUNDARY

T1
•
Npb
VTRANS
VTRANS F1, 2A D5
100V TO VOUT
200VDC R1 + C3 R3 C4
282V
• + 225mA
49.9k 22µF 210k 1µF C6 C7
M1 ×2 ×2 D3 Np Ns
R4 0.1µF 400µF
RVTRANS 105k •
C1 OFF ON CHARGE RDCM
CLAMP R5 R16
100pF 210k D4 249k
V LT3751 RV
CC OUT
Nsb
C1, C8: 16V COG CERAMIC D1 C2 R15 U2
C2: 16V X5R OR X74 CERAMIC 1µF TO DONE HVGATE M2 • 5.11Ω D6 R17
C3: 350V ELECTROLYTIC MICRO C5 221k
FAULT LVGATE VCC VIN COMP C8
C4: 250V X5R OR X7R CERAMIC 0.01µF
R9, 2.7M 22nF
C5, C6, C11, C12: 630V X5R OR X7R CERAMIC C9
UVLO1 CSP LT4430 R19
C7: 350V ELECTROLYTIC VTRANS 3.3µF
C9, C10: 25V X5R OR X7R CERAMIC R10, 4.3M 3.16k
R6 GND FB
F1: 250V, 2A FUSE OVLO1
40mΩ
R1: 2010 RESISTOR, 1% R11, 84.5k C10 R18
R2, R3, R6, R16, R17: 1206 RESISTORS, 1% UVLO2 CSN 0.47µF 1k
R4, R5: TWO 1206 RESISTORS IN SERIES, 1% VCC R12, 442k OC
R7 THRU R12, R15 THRU R20: 0805 RESISTORS, 1% OVLO2 FB U1 D7
R7 VCC OPTO
D1: 12V ZENER GND RBG
D2: VISHAY MURS140 475Ω R20
3751 TA06a
D3: VISHAY P6KE200A R8 274Ω
D4: VISHAY MURS160 2.49k
D5: STMICROELECTRONICS STTH112A
D6: VISHAY BAT54 T1: TDK SRW24LQ
D7: NXP SEMICONDUCTORS BAS516 (Np:Ns:Npb:Nsb = 1:2:0.08:0.08)
M1: VISHAY IRF830 U1: NEC PS2801-1
M2: STMICROELECTRONICS STB11NM60FD U2: LINEAR TECHNOLOGY LT4430 4.7nF
Y RATED

Steady-State Operation with

Load Regulation Efficiency 7.1mA Load Current
0.50 100
63W OUTPUT
48W OUTPUT
95 25W OUTPUT
VDRAIN
OUTPUT VOLTAGE ERROR (V)

0.25 100V/DIV
90
EFFICIENCY (%)

0 85 IPRIMARY
2A/DIV
80 3751 TA06d
20µs/DIV
–0.25
75
Steady-State Operation with
–0.50 70 225mA Load Current
0 50 100 150 200 250 100 120 140 160 180 200
IOUT (mA) INPUT VOLTAGE (V)
3751 TA06c
3751 TA06b

VDRAIN
100V/DIV

IPRIMARY
2A/DIV
3751 TA06e
20µs/DIV
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For more information www.linear.com/LT3751 29

LT3751
TYPICAL APPLICATIONS
Wide Input Voltage Range, 15 Watt, Triple Output Voltage Regulator
T1
2:1:3:3
(P1:S1:S2:S3) D1
VIN VOUT3
5V TO 24V + C2 R5 C3 C7 + +15V
1000µF
• C4 R12
25.5k 10µF 10µF 470µF 4.99k
S3
×2
RVTRANS
OFF ON CHARGE
R6 D2
CLAMP
11.5k VOUT2
VCC RDCM C8 C5 –15V
R13
C1
P1 S2 10µF + 470µF 4.99k
10µF LT3751 R7
R1, 100k 25.5k • •
DONE RVOUT
R2, 100k D3
M1 VOUT1
FAULT + +5V
C9 C6
R3, 66.5k HVGATE • 100µF
C1, C3: 25V X5R OR X7R CERAMIC UVLO1 LVGATE VCC S1 100µF
C2: 25V SANYO 25ME1000AX CSP ×2
R4, 464k
C4, C5: 35V SANYO 35ME470AX OVLO1 R11
C6: 10V KEMET T520D107M010ASE055 25mΩ
C7, C8: 16V CERAMIC, TDK C4532X7R1E106M UVLO2 CSN R9
C9: 6.3V CERAMIC, TDK C4532X5R0J107M 309Ω
D1, D2: CENTRAL SEMI CMSH2-60M OVLO2 FB
D3: CENTRAL SEM1 CMSH5-40 GND RBG R10
M1: FAIRCHILD FQD12N20L 100Ω
R1 THRU R10, R12, R13: 0805 RESISTOR, 1% R8
R11: 1206 RESISTOR, 1% 2.21k 3751 TA07a

T1: COILCRAFT HA3994-AL, 2:1:3:3 (P1:S1:S2:S3)

Maximum Output Conditions

VCC POUT(MAX) IOUT(MAX)* (mA)
(V) (W) VOUT1 VOUT2 VOUT3
5 6.5 750 300 300
12 10 1750 300 300
24 13 2500 300 300
*All other output currents set to 0mA

Cross Regulation Cross Regulation Efficiency

(IVOUT1 = 100mA) (IVOUT1 = 500mA) (IVOUT1 = 500mA)
20 26 90

VIN = 24V
24 85
VIN = 5V
VIN = 12V
22 80
–VOUT2, VOUT3 (V)

18
–VOUT2, VOUT3 (V)

VIN = 24V
EFFICIENCY (%)

VIN = 5V VIN = 24V

20 75
VIN = 12V
16 18 VIN = 12V 70
VIN = 5V
16 65

14 14 60
1 10 100 1000 1 10 100 1000 0 200 400 600 800
–IVOUT2, IVOUT3** (mA) –IVOUT2, IVOUT3** (mA) –IVOUT2 + IVOUT3 (mA)
3751 TA07b 3751 TA07c 3751 TA07d

**SOURCE/SINK IDENTICAL CURRENTS FROM BOTH VOUT2 AND VOUT3, RESPECTIVELY

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30 For more information www.linear.com/LT3751

 LT3751
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings.

FE Package
20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1663 Rev L)
Exposed Pad Variation CB

6.40 – 6.60* DETAIL A

3.86 (.252 – .260)
(.152) 3.86 0.60
(.152) (.024)
REF
20 1918 17 16 15 14 13 12 11
0.28
(.011)
REF
6.60 ±0.10 DETAIL A IS THE PART OF
2.74
THE LEAD FRAME FEATURE
4.50 ±0.10 (.108) DETAIL A 6.40 FOR REFERENCE ONLY
SEE NOTE 4 2.74 (.252)
NO MEASUREMENT PURPOSE
(.108) BSC
0.45 ±0.05

1.05 ±0.10

0.65 BSC
RECOMMENDED SOLDER PAD LAYOUT 1 2 3 4 5 6 7 8 9 10
1.20
4.30 – 4.50* (.047)
(.169 – .177) 0.25 MAX
REF
0° – 8°

0.65
0.09 – 0.20 0.50 – 0.75 (.0256) 0.05 – 0.15
(.0035 – .0079) (.020 – .030) BSC (.002 – .006)
0.195 – 0.30
FE20 (CB) TSSOP REV L 0117
(.0077 – .0118)
TYP
NOTE:
1. CONTROLLING DIMENSION: MILLIMETERS 4. RECOMMENDED MINIMUM PCB METAL SIZE
MILLIMETERS FOR EXPOSED PAD ATTACHMENT
2. DIMENSIONS ARE IN
(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH
3. DRAWING NOT TO SCALE SHALL NOT EXCEED 0.150mm (.006") PER SIDE

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For more information www.linear.com/LT3751 31

LT3751
PACKAGE DESCRIPTION
Please refer to http://www.linear.com/product/LT3751#packaging for the most recent package drawings.

UFD
UFD Package
Package
20-Lead
20-Pin Plastic QFN (4mm××5mm)
QFN (4mm 5mm)
(Reference
(ReferenceLTC
LTCDWG
DWG ## 05-08-1711 RevB)
05-08-1711 Rev B)

0.70 ±0.05

2.65 ±0.05
4.50 ±0.05 1.50 REF
3.10 ±0.05
3.65 ±0.05

PACKAGE OUTLINE

0.25 ±0.05
0.50 BSC
2.50 REF
4.10 ±0.05
5.50 ±0.05
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED PIN 1 NOTCH
R = 0.20 OR
0.75 ±0.05 1.50 REF C = 0.35
4.00 ±0.10 R = 0.05 TYP
(2 SIDES) 19 20

0.40 ±0.10
PIN 1
TOP MARK
(NOTE 6)
1
2

5.00 ±0.10
2.50 REF
(2 SIDES)

3.65 ±0.10

2.65 ±0.10

(UFD20) QFN 0506 REV B

0.200 REF R = 0.115 0.25 ±0.05

0.00 – 0.05 TYP 0.50 BSC
BOTTOM VIEW—EXPOSED PAD

NOTE:
1. DRAWING PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WXXX-X).
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE

3751fd

32 For more information www.linear.com/LT3751

 LT3751
REVISION HISTORY (Revision history begins at Rev B)

REV DATE DESCRIPTION PAGE NUMBER

B 5/10 Updated FAULT (Pin 6/Pin 4) description in Pin Functions 7
Updated DONE (Pin 7/Pin 5) description in Pin Functions 8
Updated Block Diagram 9
Revised Applications Information section 17, 18
Revised Typical Applications illustration 30
C 6/12 Revised Applications Information section 20
Corrected Schematic R8 value from 3.40k to 2.21k 30
Updated FE package drawing 31
D 12/17 Revised Absolute Maximum storage temperature range upper limit from 125°C to 150°C. 2

3751fd

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications
For more
subject to change without notice. No license information
is granted www.linear.com/LT3751
by implication or otherwise under any patent or patent rights of Analog Devices. 33
LT3751
TYPICAL APPLICATION
300V Regulated Power Supply

T1
D1
VTRANS 1:10 VOUT
24V + C3 R6
C2 300V
2.2µF • + 0mA TO 270mA
680µF 40.2k C4
×5
20µF
RVTRANS R7 •
OFF ON CHARGE 18.2k
CLAMP RDCM
RVOUT
VCC
VCC
24V
C1 M1 R8*
TO DONE HVGATE
10µF VCC 274k
MICRO FAULT LVGATE
R1 CSP
432k
UVLO1 R5
VTRANS R2 6mΩ * DEPENDING ON DESIRED OUTPUT
LT3751 VOLTAGE, R8 MUST BE SPLIT
475k
OVLO1 CSN INTO MULTIPLE RESISTORS TO
R3 MEET MANUFACTURER’S VOLTAGE
432k SPECIFICATION.
UVLO2 FB
VCC R4 C5
475k R9 10nF
OVLO2 1.13k

GND RBG
3751 TA08

C1: 25V X5R OR X7R CERAMIC CAPACITOR M1: FAIRCHILD FQP34N20L

C2: 25V X5R OR X7R CERAMIC CAPACITOR R1 THROUGH R4: USE 1% 0805 RESISTORS
C3: 25V ELECTROLYTIC R5: IRC LR SERIES 2512 RESISTOR
C4: 330V RUBYCON PHOTOFLASH CAPACITOR T1: SUMIDA PS07-299, 20A TRANSFORMER
D1: VISHAY US1M 1000V

RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC3225 150mA Supercapacitor Charger VIN: 2.75V to 5.5V, Charges Two Supercapacitors in Series to 4.8V or 5.3V
LT3420/LT3420-1 1.4A/1A, Photoflash Capacitor Charger Charges 220µF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V, ISD < 1µA,
with Automatic Top-Off 10-Lead MS Package
LT3468/LT3468-1/ 1.4A, 1A, 0.7A, Photoflash Capacitor Charger VIN: 2.5V to 16V, Charge Time: 4.6 Seconds for LT3468 (0V to 320V, 100µF,
LT3468-2 VIN = 3.6V), ISD < 1µA, ThinSOT Package
LT3484-0/LT3484-1/ 1.4A, 0.7A, 1A Photoflash Capacitor Charger VIN: 1.8V to 16V, Charge Time: 4.6 Seconds for LT3484-0 (0V to 320V, 100µF,
LT3484-2 VIN = 3.6V), ISD < 1µA, 2mm × 3mm 6-Lead DFN Package
LT3485-0/LT3485-1/ 1.4A, 0.7A, 1A, 2A Photoflash Capacitor VIN: 1.8V to 10V, Charge Time: 3.7 Seconds for LT3485-0 (0V to 320V, 100µF,
LT3485-2/LT3485-3 Charger with Output Voltage Monitor and VIN = 3.6V), ISD < 1µA, 3mm × 3mm 10-Lead DFN Package
Integrated IGBT
LT3585-0/LT3585-1/ 1.2A, 0.55A, 0.85A, 1.7A Photoflash VIN: 1.5V to 16V, Charge Time: 3.3 Seconds for LT3585-3 (0V to 320V, 100µF,
LT3585-2/LT3585-3 Capacitor Charger with Adjustable Input VIN = 3.6V), ISD < 1µA, 3mm × 2mm DFN-10 Package
Current and IGBT Drivers
LT3750 Capacitor Charger Controller VIN: 3V to 24V, Charge Time: 300ms for (0V to 300V, 100µF) MSOP-10 Package

3751fd

34
LT 1217 REV D • PRINTED IN USA
www.linear.com/LT3751
For more information www.linear.com/LT3751  ANALOG DEVICES, INC. 2017