Study on Spurious Suppression Behavior

of Fractional-N and DDS Based PLL Synthesizers

2023 International Conference on Microwave and Millimeter Wave Technology (ICMMT) | 979-8-3503-3887-4/23/$31.00 ©2023 IEEE | DOI: 10.1109/ICMMT58241.2023.10277622

with Fine Frequency Resolution

Shiqi Jiang, Yuwei Zhang, Jinping Xu*
State Key Laboratory of Millimeter Waves, Southeast University
Nanjing 210096, China E-mail: [email protected]

Abstract-A comparison study on spurious suppression worthwhile to quantitatively investigate the amplitude and
behavior of fractional-N and direct digital synthesizer (DDS) location of the spurious in frequency synthesizer [7].
based phase-locked loop (PLL) Synthesizers is reported in this
paper. It is well-known that a fractional-N synthesizer with delta- In this paper, the spurious of fractional-N and DDS based
sigma modulator (DSM) suffers serious problem of integer PLL frequency synthesis are measured and compared. The
boundary spurious and fractional spurious. A hybrid scheme of experiment shows the effectiveness of hybrid frequency
DDS and integer-division PLL is an effective way to alleviate this synthesizer scheme in suppressing the proximal spurious.
problem in the development of frequency sweeping synthesizers
with high frequency resolution. To quantitatively evaluate the II. DESIGN SCHEMES OF FREQUENCY SYNTHESIZERS
improvement of the spurious suppression of the DDS based PLL
to fractional-N synthesizer, a comparison study of the two schemes Two different frequency synthesizer schemes are designed to
of the frequency synthesizers has been carried. ADI’s HMC778 compare their performance of spurious suppression. The first
was adopted to generate form the fractional-N PLL, by adjusting one is a fractional-N PLL frequency synthesizer with ultra-fine
the frequency ratio of the fractional divider in the chip, a fine- frequency step. Fractional division generates integer boundary
resolution sweeping frequency source working in X-band was spurious and fractional spurious that are difficult to suppress.
implemented. A hybrid frequency synthesizer scheme, where
HMC778’s internal VCO is combined with ADI’s DDS AD9910 as The second one is a DDS based PLL frequency synthesizer, the
the reference source to the integer frequency division PLL, is DDS generates fine step frequencies and the PLL's dividing
adopted. In this way, the expected signal with ultra-fine frequency ratio is set to an integer. The hybrid frequency synthesizer
step size can be delivered from the DDS and multiplied by the fixed scheme suppresses both types of spurious, effectively.
integer frequency division ratio to the same frequencies of the A. Fractional-N PLL Frequency Synthesizer
fractional-N PLL. The two frequency synthesizers are measured
and compared in regard to spurious suppression behavior. The In this subsection, the details of fractional-N PLL frequency
fabricated hybrid frequency synthesizer avoids the integer synthesizer are described. As shown in Fig.1, the designed
boundary spurious and fractional spurious caused by fractional frequency synthesizer consists of a phase and frequency
frequency ratio, which basically has 39dB better integer boundary discriminator (PFD), a charge pump (CP), a loop filter, a VCO
spurious suppression at the frequency from 9.9 to 10.7GHz. and a fractional-N frequency divider. The frequency
Simultaneously, it is observed that the noise floor is improved by
5dB in 200KHz bandwidth. The results of this work are valuable synthesizer is fulfilled with a commercially chip HMC778
to balance system complexity and spurious suppression delivered by ADI.
requirement in practical applications.
Keywords-spurious suppression, fractional-N PLL, hybrid
frequency synthesizer, fine frequency resolution
I. INTRODUCTION
Frequency synthesizer systems are widely used in wireless
communication, electronic countermeasures and measurement
instruments [1]. As a core component of modern practical
electronic systems, frequency synthesizer has the Figure 1. Block diagram of fractional-N PLL frequency synthesizer
characteristics of low phase noise [2], low spurious [3], wide The input reference signal of the fractional-N PLL frequency
bandwidth [4], small step [5] and high degree of integration [6]. synthesizer is a fixed frequency signal, and fine steps are
When the step frequency of the frequency sweeping source is achieved by changing the value of frequency division ratio.
required as low as Hz order, the spurious of fractional-N When the frequency division ratio is set to a fractional one, it
frequency synthesizer mainly include integer boundary alternates between two consecutive integers N and N+1, and a
spurious and fractional spurious. Much of the spurious multiple bit digital accumulator is utilized to control the
components appear in the desired frequency band, and usually sequence of the two-division ratio. In each control cycle, the
they are unable to be filtered out by loop filter. Therefore, it is divider has 2 − K times N divisions and K times (N+1)
k

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divisions. Under this condition, the division frequency ratio can B. DDS-based PLL Frequency Synthesizer
be calculated by:

(2k − K )  N + K  ( N + 1) K
N frac = =N+ k (1)
2k 2

where k is the bits of the digital accumulator, and K is

determined by the frequency to be generated.
Fractional-N PLL synthesizers have the advantage of
Figure 3. Block diagram of hybrid frequency synthesizer
generating fine resolution frequency signal, but it also brings
the problem of serious spurious. Due to the phase errors that As shown in Fig.3, the main difference between this scheme
generated by the periodic variation of the fractional division and the fractional-N PLL scheme in Fig.2 is that the fixed
frequency ratio, fractional spurious are caused by the periodic reference frequency is replaced by a DDS with ultra-fine
jitter of the VCO tuning voltage. To improve the spurious frequency step. Meanwhile, PLL's dividing ratio is set to a fixed
suppression caused by fractional dividers, DSM breaks the integer instead of variable fractional. Therefore, the fine-
periodic variation of the division ratio by oversampling resolution DDS based PLL frequency synthesizer avoids
technique and spreads the fractional spurious into a wider integer boundary spurious and fractional spurious when
frequency band, which is generally integrated in fractional-N stepping at fine frequencies. Moreover, the out-of-band
PLL. spurious of the DDS output signal can be filtered out by the
In addition, the frequencies output from VCO are not the loop filter of the PLL.
integral multiple of the PFD frequency in fractional mode.
Intermodulation between the N-divide frequency and (N+1)- III. MEASUREMENT AND ANALYSIS
divide frequency will lead to integer boundary spurious. When To compare the spurious of fractional-N PLL frequency
VCO frequency is very close to the integral multiple of PD synthesizer and DDS based PLL frequency synthesizer, the
frequency, integer boundary spurious becomes more and more spectral characteristics of the output signal are measured at
strong in amplitude. The diagram of integer boundary spurious fixed frequency points within the range of frequency sweeping.
is shown in Fig.2 and the spurious’ offset frequency to the To reduce the effect of extraneous variables, both frequency
center frequency can be calculated as: synthesis schemes use a 100 MHz crystal (OXLN50D-S-HP-V)
as the external reference signal, the fractional-N PLL frequency
 = m  ( fVCO − n  f PFD ) (2) synthesizer is fulfilled with HMC778. The hybrid frequency
synthesizer scheme is adopted, where HMC778’s internal VCO
where m is the order of integer boundary spurious and n is the is combined with ADI’s DDS AD9910 as the reference source
integer division ratio. to the integer frequency division PLL. Similarly, AD9910 is
used as the reference source to the fractional frequency division
PLL in the fractional-N PLL frequency synthesizer. The
measurement setup of the frequency synthesizer is presented in
Fig.4.

Figure 2. Diagram of integer boundary spurious

The fractional-N PLL frequency synthesizer possesses

several advantages such as: miniaturized structure, low power
consumption and low cost. However, its fractional frequency
division scheme characteristics and DSM limitations do not
make it suitable for high resolution frequency sweeping source
systems due to its serious fractional spurious. Therefore, a
Figure 4. Measurement setup of the frequency synthesizer
hybrid frequency synthesizer based on PLL and DDS is adopted
to alleviate this problem. In our experiment, setting for the Fractional-N PLL
frequency synthesizer scheme is as follows: DDS output
frequency is set to be 130MHz, the fractional division

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frequency ratio of is set to be 82.0006308. According to IV. CONCLUSION
Equation 2, the calculation results are:  = 20KHz . The 1st to Two kinds of frequency synthesizer’s spurious suppression
4th order integer boundary spurious with a frequency spacing are measured and compared. The fractional-N and DDS-based
of  , which is about 20KHz, are uniformly distributed on both PLL frequency synthesizers are implemented by ADI’s
sides of the output signal at 10660.082MHz. The worst integer HMC778 and ADI’s AD9910. In the case of fine-resolution
boundary spurious suppression is only 28dBc over 200KHz frequency sweeping source, the hybrid frequency synthesize
bandwidth. At the same frequency bandwidth, the noise floor is scheme avoids integer boundary spurious and fractional
-80dBm. As the measured results shown in Fig.5(a). spurious that may appear in fractional-N PLL synthesizer. The
The setting for the hybrid frequency synthesizer based on measured results show that the hybrid synthesizer, compared
PLL and DDS scheme is as follows: DDS output frequency is with the fractional-N synthesizer, basically has 39dB better
set to be 130.0001 MHz, the integer division frequency ratio of integer boundary spurious suppression from 9.9 to 10.7GHz. It
the PLL is 82. The integer boundary spurious will not exist. The is observed that the noise floor is improved by 5dB in 200KHz
spurious suppression is better than 67dBc over 200KHz bandwidth. In the applications of wide band frequency
bandwidth. At the same frequency bandwidth, the noise floor is sweeping source with fine frequency resolution, the fractional-
-85dBm, which is 5dBc lower than Fractional-N PLL frequency N PLL frequency synthesizer is more suitable with low
synthesizer scheme. As the measured results shown in Fig.5(b). requirements for spurious suppression with minimized size, and
the DDS-based PLL frequency synthesizer has a significant
spurious suppression at the expense of system complexity.

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(a) (b)
Figure 6. Frequency spectrums of (a) fractional-N PLL frequency synthesizer
and (b) DDS-based PLL frequency synthesizer over 9.95 to 10.65GHz

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