Dte Notes

PRAVIN PATIL COLLEGE OF DIPLOMA
ENGINEERING AND TECHNOLOGY
SUBJECT – DIGITAL TECHNIQUES

( 22320 )
CLASS – CO3IA/B/ EJ3I
MRS. PRACHI KALPANDE
1-1
Chapter 1
NUMBER SYSTEM AND CODES
6 Hours
8 Marks
Basics of Digital Techniques
Modern digital computers, mobile communication systems, Internet etc.

have become part and parcel of society nowadays. This has become possible
basically due to Integrated Circuits (ICs). The operation of computers,
communications systems etc. is based on digital techniques.
Digital Signal and Digital Systems

The signals which are continuous and can have any value in a limited
range are called analog signals. A sample analog signal is shown in figure 1.1.
Figure 1.1: Sample analog signal

Electronic circuits used for processing analog signals are called as analog
circuits and the systems build for this kind of operation are called as analog
systems. One of the examples of analog system is electronic amplifier.
On the other hand, the signals which are discrete and can have only two
discrete levels or values are called digital signals. A sample digital signal is
shown in figure 1.2.
Figure 1.2: Sample digital signal

The two levels in a digital signal can be represented using the terms
HIGH and LOW. HIGH level can also be represented as ON or value ‘1’.
Similarly, LOW level can be represented as OFF or value ‘0’.
Electronic circuits used for processing digital signals are called as digital
circuits and the systems build for this kind of operation are called as digital
systems. One of the examples of digital system is electronic calculator.
1-2
Positive and Negative Logic
In digital systems there are two states – one for representing value ‘1’ and
other for representing value ‘0’ (as a binary variable can have value either 0 or
1). These states are represented by two different voltage levels (or sometimes
current levels).
If logic state ‘1’ is represented by a higher voltage level (or current level)
and logic state ‘0’ is represented by a lower voltage level (or current level), it is
called as positive logic system. E.g. If 0V and +5V are the two voltage levels
and +5V is used for representing ‘1’ and 0V is used for representing ‘0’, this is a
positive logic system.
5V
HIGH
3.5 V
1V
LOW
0V
Figure 1.3: Positive Logic
If logic state ‘0’ is represented by a higher voltage level (or current level)
and logic state ‘1’ is represented by a lower voltage level (or current level), it is
called as negative logic system. E.g. If 0V and +5V are the two voltage levels
and +5V is used for representing ‘0’ and 0V is used for representing ‘1’, this is a
negative logic system.
5V
LOW
3.5 V
1V
HIGH
0V
Figure 1.4: Negative Logic
Advantages of Digital Systems

- In digital systems devices generally operate in one of the two states only
i.e. ON and OFF. It results in simple operations.
- There are only few basic operations those can be learnt easily.
- Large number of ICs is available.
- Effect of fluctuations and noise is less.
- Digital systems have capability of memory.
- Digital systems can be easily controlled through computer software.
1-3
- They are less expensive.
- They are more reliable.
- They are easy to design.
- They have higher accuracy.
Disadvantages of Digital Systems

- Even if digital system has so many advantages, real world is analog. All
the real world signals (like velocity, acceleration, temperature, light,
sound, electric and magnetic field etc.) are analog.
- The real world analog signals need to be digitized.
- If a single piece of digital data is missed, large block of data may change
completely.
- Digital communication requires more bandwidth than analog
communication.
- Digital systems are prone to sampling errors.
Applications of Digital Systems

- Digital Audio
- Digital Photography
- Audio and speech processing
- Image processing
- Biomedical signal processing
- Archaeology
- Cell phones
- Fingerprint Processing
- Face detection
- Rolling display
- Industrial automation
Logic Families
For producing different types of digital integrated circuits (ICs) different

circuit configurations or approaches are used. Each such fundamental approach
is called logic family. Different logic functions may be fabricated in the form of
IC with same approach. i.e. Same logic family may have different logic
functions. All the ICs in same logic family have same characteristics. That’s why
digital ICs belonging to same logic family are compatible with each other.
1-4
Characteristics of logic families (or
Characteristics of digital ICs)
There is variety of logic families. Selection of a logic

family for an application depends on its characteristics. For a
real-time application immediate response is required. In such
application logic family with high speed of operation should be
selected.
Important characteristics of logic families are,
- Speed of operation
- Power dissipation
- Figure of merit
- Current and voltage parameters
- Fan-out
- Fan-in
- Noise immunity
- Power supply requirements
- Operating temperature
Speed of operation
It is desirable that a digital IC should have high speed of operation. Speed
of operation of a circuit is specified in terms of propagation delay time (i.e. lesser
the propagation delay time → higher the speed of operation).
There are two delay times.
𝑡𝑝𝐻𝐿→ Delay time when output goes from HIGH state to LOW state
𝑡𝑝𝐿𝐻→ Delay time when output goes from LOW state to HIGH state
Propagation delay time is computed as the average of these two delay
times as,
𝑡𝑝𝐻𝐿 + 𝑡𝑝𝐿𝐻
𝑡𝑝 =
2
1-5
The two delay times are computed by finding the time difference 50%
voltage levels of input and output waveforms as shown in figure 1.5.
Figure 1.5: Computation of tpLH and tpHL

The propagation delay between input and output must be as low as
possible.
tpLH tpHL
Power Dissipation
For operation of every electronic circuit, certain amount of electric power is
required. Out of supplied power, some power gets dissipated in electronic
circuits. This is due to wastage of power across electronic components. i.e.
Power dissipation is nothing but wastage of power across electronic
components or devices within a circuit. Power dissipation of a circuit is
expressed in terms of milliwatt (mW).
If power dissipation for a circuit is less, the circuit requires less power to
be supplied to it. So, power dissipation should be as less as possible
Figure of Merit
It is always desirable for an electronic circuit to have less power
dissipation (for reducing power requirements). But when power dissipation is
reduced in an electronic circuit, its speed of operation also gets reduced (In other
words, propagation delay gets increased).
As per above discussion, there is a trade-off between power dissipation
and speed of operation (which is denoted in terms of propagation delay). So,
instead of the two parameters speed of operation and power dissipation, a single
parameter called figure of merit is used for comparison of logic families. Figure
of merit is a product of propagation delay and power dissipation.
𝐹𝑖𝑔𝑢𝑟𝑒𝑜𝑓𝑚𝑒𝑟𝑖𝑡 = 𝑝𝑟𝑜𝑝𝑎𝑔𝑎𝑡𝑖𝑜𝑛𝑑𝑒𝑙𝑎𝑦 × 𝑝𝑜𝑤𝑒𝑟𝑑𝑖𝑠𝑠𝑖𝑝𝑎𝑡𝑖𝑜𝑛
Figure of merit is measured in terms of Pico-Joules (𝑛𝑠 × 𝑚𝑊 = 𝑝𝐽)
Current and Voltage Parameters

These parameters define minimum and maximum limits of current and
voltage for input and output of a logic family.
VIH (HIGH level Input Voltage) : It is the minimum input voltage
corresponding to logic ‘1’ state.
VIL (LOW level Input Voltage) : It is the maximum input voltage
1-6
VOH (HIGH level Output Voltage) : It is the minimum output voltage
VOL (LOW level Output Voltage) : It is the maximum output voltage
IIH (HIGH level Input Current) : It is the minimum input current
IIL (LOW level Input Current) : It is the maximum input current
IOH (HIGH level Output Current) : It is the minimum output current
This current is also called as
source current.
IOL (LOW level Output Current) : It is the maximum output current
This current is also called as sink
current.
Fan–out
Generally, output of one logic gate feeds input to several other gates.
Practically, it is not possible to drive unlimited number of logic gates from
output of a single logic gate.
Fan–out is the maximum number of similar gates that can be driven by a
logic gate. As shown in figure 1.6, if the driver gate is capable of driving at the
most N gates, fan–out of the driver gate is N.
If we try to drive more than N gates, current supply required to drive the
gates may become lesser than the minimum requirement (in case of HIGH
state) or current sink by the driver gate may become greater than its sink
capacity (in case of LOW state).
1-7
Fan–in
Fan–in is the number of inputs to a gate. For a two-input gate,

fan–in is 2 and for a 3-input gate, fan–in is 3 and so on.
Noise Immunity
Unwanted signal is called as noise. Stray electric or magnetic fields may
induce noise in the input to the digital circuits. Due to noise, input voltage may
drop below VIH or may rise above VIL. Both the circumstances will result in
undesired operations of the digital circuit.
Every circuit should have ability to tolerate the noise signal. This ability
of tolerating noise signal is called as noise immunity. Measure of noise
immunity is called as noise margin. The noise margin at logic ‘1’ state and
logic ‘0’ state are computed as,
Logic ‘1’ state noise margin: ∆1 = 𝑉𝑂𝐻 − 𝑉𝐼𝐻
Logic ‘0’ state noise margin: ∆0 = 𝑉𝑂𝐿 − 𝑉𝐼𝐿
Power Supply Requirements

Every electronic circuit requires certain supply voltage to operate. The
required supply voltage and power should be as less as possible.
Operating Temperature
Operating temperature is range of temperature in which an IC functions
properly. An IC is selected for a specific application depending on its operating
temperature. Generally the range of operating temperature is within −550𝐶 to
+1250𝐶.
Classification of Logic Families

Entire range of digital ICs is fabricated using either bipolar devices or
MOS devices or a combination of the two.
Different logic families falling in the first category are called bipolar
families. These families include diode logic (DL), resistor–transistor logic (RTL),
diode–transistor logic (DTL), transistor–transistor logic (TTL), emitter–coupled
logic (ECL), also known as current mode logic (CML), and integrated injection
logic (I2L).
The logic families that use MOS devices are known as MOS families.
These families include PMOS family (using P-channel MOSFETs), the NMOS
family (using N-channel MOSFETs) and the CMOS family (using both N- and P-
channel devices).
The Bi-MOS logic family uses both bipolar and MOS devices.
1-8
Logic Families
Bi-MOS Logic
Bipolar Families MOS Families
Family
Resistor
Diode Logic (DL) Transistor Logic PMOS Family NMOS Family
(RTL)
Transistor
Diode Transistor
Transistor CMOS Family
Logic (DTL)
Logic (TTL)
Emitter Integrated
Coupled Logic Injection Logic
(ECL) (I2L)
Figure 1.7: Classification of Logic Families

Logic families that are currently in widespread use include TTL, CMOS,
ECL, NMOS and Bi-CMOS.
Transistor–Transistor Logic (TTL) Family

Transistor is the basic element of this logic family. Transistor operates in
either cut-off region or saturation region. TTL Family has number of subfamilies
including standard TTL, low-power TTL, high-power TTL, low-power Schottky
TTL, Schottky TTL, advanced low-power Schottky TTL, fast TTL etc. The ICs
belonging to TTL family are designated as,
74 or 54 : Standard TTL
74L or 54L : Low-power TTL
74H or 54H : High-power TTL
74LS or 54LS : Low-power Schottky TTL
74S or 54S : Schottky TTL
74ALS or 54ALS : Advanced Low-power Schottky TTL
74F or 54F : Fast TTL
Characteristic parameters and features of the standard TTL family of
devices include the following:
VIL=0.8 V
VIH=2 V
IIH=40 µA
1-9
IIL=1.6 mA
VOH=2.4 V
VOL=0.4 V
IOH=400 µA
IOL=16 mA
1-10
propagation delay
= 22ns (max.) for LOW-to-HIGH transition at the output
= 15ns (max.) for HIGH- to-LOW output transition
worst-case noise margin=0.4V
fan-out=10
operating temperature range
=0°C to 70°C (74- series)
=−55°C to +125°C (54-series)
speed–power product=100pJ
Emitter–Coupled Logic (ECL) Family

Currently, popular sub-families of ECL include MECL-III (also called the
MC 1600 series), the MECL-10K series, the MECL-10H series and the MECL-
10E series.
Characteristic parameters and features of the MECL-III family of devices
include the following:
gate propagation delay=1ns
output edge speed =1ns
(indicative of the rise and fall time of output transition)
power dissipation per gate = 50mW
speed–power product = 60pJ
input voltage=0–VEE (VEE is the negative supply voltage)
negative power supply range (for VCC=0)=−5.1V to −5.3 V
continuous output source current (max.)=40mA
surge output source current (max.) = 80mA
operating temperature range=−30°C to +85°C.
Complementary Metal Oxide Semiconductor (CMOS) Family

This logic family uses both P-channel and N-channel MOSFETs. Popular
CMOS sub-families include 4000A, 4000B, 4000UB, 54/74C, 54/74HC,
54/74/HCT, 54/74AC and 54/74ACT families (The 54/74 sub-families are pin-
compatible with 54/74 TTL series logic functions).
Characteristic features of 4000B and 4000UB CMOS devices are as
follows:
VIH (buffered devices)
=3.5V (for VDD=5V)
=7.0 V (for VDD =10 V)
=11.0V (for VDD =15V)
VIH (unbuffered devices)
=4.0V (for VDD = 5V)
=8.0 V (for VDD =10V)
=12.5V (for VDD =15V)
IIH=1.0µA
IIL=1.0µA
IOH =0.2mA (for VDD =5V)
=0.5mA (for VDD =10V)
IOL =0.52mA (for VDD =5V)
=1.3mA (for VDD = 10V)
1-11
VIL (buffered devices) =1.5V (for VDD =5V)
=3.0V (for VDD = 10V)
=4.0V (for VDD = 15V)
VIL (unbuffered devices) =1.0V (for VDD =5V)
=2.0V (for VDD = 10V)
=2.5V (for VDD =15V)
VOH =4.95V (for VDD =5V)
=9.95V (for VDD =10V)
=14.95V (for VDD =15V)
VOL=0.05V
VDD =3– 15V
propagation delay (buffered devices) =150ns (for VDD =5V)
=65ns (for VDD =10V)
propagation delay (unbuffered devices)=60ns (for VDD =5V)
noise margin (buffered devices) =1.0V (for VDD =5V)
=2.0V (for VDD =10V)
=2.5V (for VDD = 15V)
noise margin (unbuffered devices) =0.5V (for VDD =5V)
=1.0V(for VDD =10V)
=1.5V(for VDD =15V)
Output transition time (for VDD =5Vand CL=50pF)
=100ns (buffered devices)
=50–100ns (for unbuffered devices)
power dissipation per gate (for f =100kHz)=0.1mW
speed–power product (for f =100kHz)=5pJ
Number System
Number system is one of the most important and basic topic in digital
electronics. It is important to understand a number system as it helps in
understanding how data is represented before processing it in digital system.
Important characteristics of number systems are:
- Independent digits used (radix or base).
- Place value of different digits.
- Maximum numbers that can be represented using given number of
digits.
In a number system there is an ordered set of symbols (digits) with rules

defined for performing arithmetic operations like addition, subtraction,
multiplication etc.
(𝑁)𝑏 = 𝑑𝑛−1𝑑𝑛−2 … 𝑑𝑖 … 𝑑2𝑑1𝑑0 . 𝑑−1𝑑−2 … 𝑑−𝑓 … 𝑑−𝑚+1𝑑−𝑚
Integer part Radix Point Fractional part

1-12
Where,
N → A number
b → Base or radix of the number system
n → Number of digits in Integer part
m → Number of digits in Fractional part
𝑑𝑛−1 → Most Significant Digit (MSD)
𝑑−𝑚 → Least Significant Digit (LSD)
Each digit (i.e. 𝑑𝑖 and 𝑑−𝑓) must be within the range from 0 to b–1
including the boundaries.
Decimal Number System

Base of decimal number system is 10. It is also called as radix-10 number
system. In this number system, 10 independent digits are used. They are:
012345678 9
All the numbers are represented using these digits only. One can
represent whole numbers as well as fractional numbers (requires additional
period symbol. i,e, ‘.’) using these digits. Some examples are given below.
149 39754 22361803 11
23.67333 100.001 .75 10.50
The place values of different digits in a decimal number are 10 0, 101, 102,
103 and so on. Value (also called as magnitude) of a decimal number can be
expressed as sum of multiplication of each digit by its place value. An example is
shown below.
(39754)10 = 4 × 100 + 5 × 101 + 7 × 102 + 9 × 103 + 3 × 104
4 × 1 + 5 × 10 + 7 × 100 + 9 × 1000 + 3 × 10000
4 + 50 + 700 + 9000 + 30000
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒39754
For fractional part, place values of different digits are 10 -1, 10-2, 10-3, 10-4
and so on. An example is shown below.
(10.50)10 = 1 × 101 + 0 × 100 + 5 × 10−1 + 0 × 10−2
1 × 10 + 0 × 1 + 5 × 0.1 + 0 × 0.01
10 + 0 + 0.5 + 0
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒10.5
Binary Number System

Base of binary number system is 2. It is also called as radix-2 number
system. In this number system, 2 independent digits are used.
They are:
0 1
All the numbers are represented using these digits only. Generally, a
digit in binary number system is called as bit (i.e. binary digit). One can
110 0 101110 1
1-13
101.1010 1.001 .100 1110.10
The place values of different digits in a binary number are 2 0, 21, 22, 23
and so on. Value (also called as magnitude) of a binary number can be expressed
as sum of multiplication of each bit by its place value. An example is shown
below.
(10110)2 = 0 × 20 + 1 × 21 + 1 × 22 + 0 × 23 + 1 × 24
0 × 1 + 1 × 2 + 1 × 4 + 0 × 8 + 1 × 16
0 + 2 + 4 + 0 + 16
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒 22
For fractional part, place values of different bits are 2 -1, 2-2, 2-3, 2-4 and so
on. An example is shown below.
(10.01)2 = 1 × 21 + 0 × 20 + 0 × 2−1 + 1 × 2−2
1 × 2 + 0 × 1 + 0 × 0.5 + 1 × 0.25
2 + 0 + 0 + 0.25
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒 2.25
Some important units in binary number system along with their
meanings are shown in table 1.1.
Table 1.1: Units in Binary number system

Unit Meaning
Bit Single binary digit (0 or 1)
Nibble Group of 4 bits
Byte Group of 8 bits
Word Number of bits that can be processed by a computer at a time. It may
vary from one computer to another. Generally it equals to 1 byte, 2
bytes, 4 bytes or even larger.
Advantages of Binary Number System

Binary number system is simplest possible number system.
Logic operations are backbone of any digital computer. Logic operations
are nothing but operations that deal with TRUE (‘1’) and FALSE (‘0’). So, in
digital computers, binary number system is most prominently used number
system.
As data is represented using 0’s and 1’s, basic electronic devices used in
implementation of hardware can easily handle the data (by considering OFF for
‘0’ and ON for ‘1’).
As data is represented using 0’s and 1’s, circuits required for performing
arithmetic operations like addition, subtraction etc can be easily designed.
Octal Number System

Base of octal number system is 8. It is also called as radix-8 number
system. In this number system, 8 independent digits are used. They are:
0123456 7
1-14
146 32754 22361203 11
23.67333 100.001 .75 10.50
The place values of different digits in a decimal number are 8 0, 81, 82, 83
and so on. Value (also called as magnitude) of a octalal number can be expressed
as sum of multiplication of each digit by its place value. An example is shown
below.
(32754)8 = 4 × 80 + 5 × 81 + 7 × 82 + 2 × 83 + 3 × 84
4 × 1 + 5 × 8 + 7 × 64 + 2 × 512 + 3 × 4096
4 + 40 + 448 + 1024 + 12288
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒 13804
For fractional part, place values of different digits are 8 -1, 8-2, 8-3, 8-4 and
so on. An example is shown below.
(10.50)8 = 1 × 81 + 0 × 80 + 5 × 8−1 + 0 × 8−2
1 × 8 + 0 × 1 + 5 × 0.125 + 0 × 0.0625
8 + 0 + 0.625 + 0
Hexadecimal Number System

Base of hexadecimal number system is 16. It is also called as radix-16
number system. In this number system, 16 independent digits are used. They
are:
0 1 2 3 4 5 6 7 8 9 A B C D E F
Values of additional digits are,
Digit Value Digit Value
A 10 B 11
C 12 D 13
E 14 F 15
149 F1AB 22C 1D3
23.67333 1E.001 .A5 10.50
The place values of different digits in a decimal number are 160, 161, 162,
163and so on. Value (also called as magnitude) of a hexadecimal number can be
expressed as sum of multiplication of each digit by its place value. An example is
shown below.
(𝐹1𝐴𝐵)16 = 𝐵 × 160 + 𝐴 × 161 + 1 × 162 + 𝐹 × 163
11 × 1 + 10 × 16 + 1 × 256 + 15 × 4096
11 + 160 + 256 + 61440
𝐷𝑒𝑐𝑖𝑚𝑎𝑙𝑣𝑎𝑙𝑢𝑒61867
For fractional part, place values of different digits are 16 -1, 16-2, 16-3, 16-4
and so on. An example is shown below.
(10.50)16 = 1 × 161 + 0 × 160 + 5 × 16−1 + 0 × 16−2
1 × 16 + 0 × 1 + 5 × 0.0625 + 0 × 0.00390625
1-15
16 + 0 + 0.3125 + 0
Advantages of Hexadecimal Number System

As already discussed previously, binary number system is used for
representing data in digital computers. Hexadecimal number system, on the
other hand, provides compact way of representing large binary numbers. A
value 250 can be represented in binary number system as 11111001. This is a
big number. It can be represented in very compact form in hexadecimal number
system as F9.
Due to compact representation of large binary numbers they can be easily
understood and handled.
Conversion of Number Systems

A number represented using one number system can be converted into its
equivalent number in any other number system. i.e. a number can be easily
converted from one number system to another. The original number and the
output of conversion are equivalent of each other. Processes used for converting
a number from one number system to another number system are discussed
below.
Binary to Decimal conversion

Decimal equivalent of a binary number can be found by adding sum of
multiplication of each bit by its place value.
Example 1:
(111010)2 = 1 × 25 + 1 × 24 + 1 × 23 + 0 × 22 + 1 × 21 + 0 × 20
1 × 32 + 1 × 16 + 1 × 8 + 0 × 4 + 1 × 2 + 0 × 1
32 + 16 + 8 + 0 + 2 + 0
(58)10
Example 2:
(1101.01)2 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 + 0 × 2−1 + 1 × 2−2
1 × 8 + 1 × 4 + 0 × 2 + 1 × 1 + 0 × 0.5 + 1 × 0.25
8 + 4 + 0 + 1 + 0 + 0.25
(13.25)10
Octal to Decimal conversion

Decimal equivalent of octal number can be found by adding sum of
multiplication of each bit by its place value.
Example 1:
(6251)8 = 6 × 83 + 2 × 82 + 5 × 81 + 1 × 80
=6 × 512 + 2 × 64 + 5 × 8 + 1 × 1
=3072 + 128 + 40 + 1
=(3241)10
1-16
Example 2:
(37.40)8 = 3 × 81 + 7 × 80 + 4 × 8−1 + 0 × 8−2
=3 × 8 + 7 × 1 + 4 × 0.125 + 0 × 0.0625
=24 + 7 + 0.5 + 0
=(31.5)10
Hexadecimal to Decimal conversion

Decimal equivalent of a hexadecimal number can be found by adding sum
of multiplication of each bit by its place value.
Example 1:
(20𝐴𝐵)16 = 20 × 163 + 0 × 162 + 𝐴 × 161 + 𝐵 × 160
=20 × 4096 + 0 × 256 + 10 × 16 + 11 × 1
=81920 + 0 + 160 + 11
=(82091)10
Example 2:
(𝐷𝐶. 61)16 = 𝐷 × 161 + 𝐶 × 160 + 6 × 16−1 + 1 × 16−2
=13 × 16 + 12 × 1 + 6 × 0.0625 + 1 × 0.00390625
=208 + 12 + 0.375 + 0.00390625
=(220.37890625)10
Decimal to Binary conversion

While converting Decimal number into its binary equivalent, the
conversion process for integer part and fraction part are different. So, these
parts must be separated first.
For integer part, decimal number is successively divided by 2 (which is
base or radix of binary number system) until the quotient becomes zero and the
remainders are recorded in each step. The number formed by writing
remainders in reverse order is the binary equivalent of integer part.
For fractional part, it is successively multiplied by 2 (which is base or
radix of binary number system) until result of multiplication is 0 and the carries
are recorded in each step. The number formed by writing carries in forward
order is the binary equivalent of fractional part. If we are not getting the result
of multiplication as zero after multiple iterations, we may stop the process after
getting desired number of bits.
Example 1:
(293.52)10 = (? )2
As a first step, the number should be separated in integer part and
fractional parts as,
(293.52)10 = (293)10 + (0.52)10
1-17
Converting the integer part (293)10:
Divisor Dividend Remainder
2 293 --
2 146 1
2 73 0
2 36 1
2 18 0
2 9 0
2 4 1
2 2 0
2 1 0
-- 0 1
(293)10 = (100100101)2
Converting the fractional part (0.52)10:
Fraction Multiplier Result Carry
.52 2 .04 1
.04 2 .08 0
.08 2 .16 0
.16 2 .32 0
.32 2 .64 0
.64 2 .28 1
.28 2 .56 0
.56 2 .12 1
. .
. .
. .
(0.52)10 = (. 10000101)2
Therefore,
(293.52)10 = (100100101.10000101)2
Example 2:
(63.25)10 = (? )2
(63.25)10 = (63)10 + (0.25)10
2 63 --
2 31 1
2 15 1
2 7 1
2 3 1
2 1 1
-- 0 1
1-18
(63)10 = (111111)2
.25 2 .5 0
.5 2 .0 1
(0.25)10 = (. 01)2
Therefore,
(63.25)10 = (111111.01)2
Decimal to Octal conversion

While converting Decimal number into its octal equivalent, the conversion
process for integer part and fraction part are different. So, these parts must be
separated first.
base or radix of octal number system) until the quotient becomes zero and the
remainders are recorded in each step. The number formed by writing
remainders in reverse order is the octal equivalent of integer part.
radix of octal number system) until result of multiplication is 0 and the carries
are recorded in each step. The number formed by writing carries in forward
order is the octal equivalent of fractional part. If we are not getting the result of
multiplication as zero after multiple iterations, we may stop the process after
getting desired number of octal digits.
Example 1:
(293.52)10 = (? )8
(293.52)10 = (293)10 + (0.52)10
8 293 --
8 36 5
8 4 4
-- 0 4
(293)10 = (445)2
1-19
.52 8 .16 4
.16 8 .28 1
.28 8 .24 2
.24 8 .92 1
.92 8 .36 7
.36 8 .88 2
.88 8 .04 7
.04 8 .32 0
. .
. .
(0.52)10 = (. 41217270)2
Therefore,
(293.52)10 = (445.41217270)2
Example 2:
(63.25)10 = (? )8
(63.25)10 = (63)10 + (0.25)10
8 63 --
8 7 7
-- 0 7
(63)10 = (77)8
.25 8 .0 2
(0.25)10 = (. 2)8
Therefore,
(63.25)10 = (77.2)8
Decimal to Hexadecimal conversion

While converting Decimal number into its hexadecimal equivalent, the
conversion process for integer part and fraction part are different. So, these
parts must be separated first.
base or radix of hexadecimal number system) until the quotient becomes zero
and the remainders are recorded in each step. The number formed by writing
remainders in reverse order is the hexadecimal equivalent of integer part.
1-20
radix of hexadecimal number system) until result of multiplication is 0 and the
carries are recorded in each step. The number formed by writing carries in
forward order is the hexadecimal equivalent of fractional part. If we are not
getting the result of multiplication as zero after multiple iterations, we may stop
the process after getting desired number of octal digits.
Example 1:
(293.52)10 = (? )16
(293.52)10 = (293)10 + (0.52)10

16 293 --
16 18 5
16 1 2
-- 0 1
(293)10 = (125)16
.52 16 .32 8
.32 16 .12 5
.12 16 .92 1
.92 16 .72 14(E)
.72 16 .52 11(B)
.52 16 .32 8
.32 16 .12 5
Results will be repeated
(0.52)10 = (. 851𝐸𝐵)16
Therefore,
(293.52)10 = (125.851𝐸𝐵)16
Example 2:
(63.25)10 = (? )16
(63.25)10 = (63)10 + (0.25)10
16 63 --
16 3 15(F)
-- 0 3
(63)10 = (3𝐹)16
1-21
.25 16 .0 4
(0.25)10 = (. 4)16
Therefore,
(63.25)10 = (3𝐹. 4)16
Octal to Binary and Binary to Octal conversion

While converting octal number into its binary equivalent, each octal digit
is replaced by its three-bit binary equivalent. The binary equivalents of all
independent octal digits are shown in table 1.2.
Table 1.2: Octal Digits and their binary equivalents
Octal Digit Binary equivalent
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
Example 1:
(273.52)8 = (? )2
Each octal digit is replaced by its three-bit binary equivalent.
2 7 3 . 5 2
Therefore, 010 111 011 . 101 010 (273.52)8 =
(010111011.101010)2
Example 2:
(63.25)8 = (? )2
Each octal digit is replaced by its three-bit binary equivalent.
6 3 . 2 5
Therefore, 110 011 . 010 101 (63.25)8 =
(110011.010101)2
1-22
For converting a binary number into octal number both the integer part
and the fractional part of the binary number are split into groups of three bits
starting from radix point (in binary number system it may be called as binary
point). If the outermost groups are not complete (i.e. of three bits), then
sufficient number of 0’s are added to make them complete (on left side of
leftmost group and on right side of rightmost group). Then each group is
replaced by its octal equivalent as shown in table 1.2.
Example 1:
(1010101.0101)2 = (? )8
The binary number is split into groups of three bits from binary point.
1 010 101 . 010 1
Here the first group and the
last group are incomplete. For completing them 0’s are added on left side of first
group and on right side of last group.
001 010 101 . 010 100
Then octal equivalent of each
group of bits is written.
001 010 101 . 010 100
1 2 5 . 2 4
Therefore, (1010101.0101)2 =
(125.24)8
Example 2:
(11010.01)2 = (? )8
The binary number is split into groups of three bits from binary point.
11 010 . 01
Here the first group and the last group
are incomplete. For completing them 0’s are added on left side of first group and
on right side of last group.
011 010 . 010
Then octal equivalent of each group
of bits is written.
011 010 . 010
3 2 . 2
Therefore,
(11010.01)2 = (32.2)8
1-20
Hexadecimal to Binary and Binary to Hexadecimal conversion
While converting hexadecimal number into its binary equivalent, each
hexadecimal digit is replaced by its four-bit binary equivalent. The binary
equivalents of all independent hexadecimal digits are shown in table 1.3.
Table 1.3: hexadecimal Digits and their binary equivalents

Hexadecimal Binary equivalent
Digit
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
A 1 0 1 0
B 1 0 1 1
C 1 1 0 0
D 1 1 0 1
E 1 1 1 0
F 1 1 1 1
Example 1:
(273. 𝐴2)16 = (? )2
Each hexadecimal digit is replaced by its four-bit binary equivalent.
2 7 3 . A 2
Therefore, 0010 0111 0011 . 1010 0010
(273. 𝐴2)16 =
(001001110011.1010
0010)2
Example 2:
(𝐸𝐵. 25)16 = (? )2
1-20
Each hexadecimal digit is replaced by its four-bit binary equivalent.
E B . 2 5
Therefore, 1110 1011 . 0010 0101
(𝐸𝐵. 25)16 =
(11101011.00100101)2
For converting a binary

number into hexadecimal
number both the
1-21
integer part and the fractional part of the binary number are split into groups of
four bits starting from radix point (in binary number system it may be called as
binary point). If the outermost groups are not complete (i.e. of four bits), then
sufficient number of 0’s are added to make them complete (on left side of leftmost
group and on right side of rightmost group). Then each group is replaced by its
octal equivalent as shown in table 1.3.
Example 1:
(100101101.01011)2 = (? )16
The binary number is split into groups of four bits from binary point.
1 0010 1101 . 0101 1
Here the first group and the
last group are incomplete. For completing them 0’s are added on left side of first
group and on right side of last group.
0001 0010 1101 . 0101 1000
Then hexadecimal
equivalent of each group of bits is written.
0001 0010 1101 . 0101 1000
1 2 D . 5 8
Therefore,
(100101101.01011)2 = (12𝐷. 58)16
Example 2:
(11010.01)2 = (? )16
The binary number is split into groups of four bits from binary point.
1 1010 . 01
Here the first group and the last group
are incomplete. For completing them 0’s are added on left side of first group and
on right side of last group.
0001 1010 . 0100
Then octal equivalent of each group
of bits is written.
0001 1010 . 0100
1 A . 4
Therefore, (11010.01)2 = (1𝐴. 4)16
Hexadecimal to Octal and Octal to Hexadecimal conversion

For converting hexadecimal number into its octal equivalent, two
methods exist. In the first method, the hexadecimal number is first converted
into its binary equivalent and then this binary number is converted into octal
number system. In the second method, the hexadecimal number is first
converted into its decimal equivalent and then this decimal number is converted
into octal number system. The first method is easier than the second.
Example 1:
(1𝐴. 4)16 = (? )8
The hexadecimal number is first converted into its binary equivalent.
. 4 1-22
1 A
0001 1010 . 0100
(1𝐴. 4)16 = (00011010.0100)2
Then the binary number is converted into its octal equivalent
00 011 010 . 010 0
000 011 010 . 010 000
0 3 2 . 2 0
Therefore,(1𝐴. 4)16 = (032.20)8 = (32.2)8

Example 2:
(12𝐷. 58)16 = (? )8
The hexadecimal number is first converted into its binary equivalent.
1 2 D . 5 8
0001 0010 1101 . 0101 1000
(12𝐷. 58)16 = (000100101101.01011000)2
Then the binary number is converted into its octal equivalent
000 100 101 101 . 010 110 00
000 100 101 101 . 010 110 000
0 4 5 5 . 2 6 0
Therefore, (12𝐷. 58)16 = (0455.260)8 = (455.26)8
For converting octal number into its hexadecimal equivalent, two

methods exist. In the first method, the octal number is first converted into its
binary equivalent and then this binary number is converted into hexadecimal
number system. In the second method, the octal number is first converted into
its decimal equivalent and then this decimal number is converted into
hexadecimal number system. The first method is easier than the second.
Example 1:
(56.03)8 = (? )16
The octal number is first converted into its binary equivalent.
5 6 . 0 3
101 110 . 000 011
(56.03)8 = (101110.000011)2
Then the binary number is converted into its hexadecimal equivalent

10 1110 . 0000 11
0010 1110 . 0000 1100
2 E . 0 C
Therefore,(56.03)8 = (2𝐸. 0𝐶)16

Example 2:
(237.41)8 = (? )16
The octal number is first converted into its binary equivalent.
1-23
2 3 7 . 4 1
010 011 111 . 100 001
(237.41)8 = (010011111.100001)2
Then the binary number is converted into its hexadecimal equivalent
0 1001 1111 . 1000 01
0000 1001 1111 . 1000 0100
0 9 F . 8 4
Therefore,(237.41)8 = (09𝐹. 84)16 = (9𝐹. 84)16
Number Representation in Binary

Positive and negative decimal numbers can be represented in binary by
using one of the formats discussed below. Generally, while using these
representations, number of bits used for representing the number
should be multiple of 8.
Sign-Bit Magnitude Representation

In this representation, MSB (Most Significant Bit) is used for
representing sign. ‘0’ is used for representing positive sign whereas ‘1’ is used for
representing negative sign. Remaining bits are used for representing magnitude
of the number.
In eight-bit representation, MSB is used as sign bit and remaining seven
bits are used for representing magnitude.
Example 1:
(−53)10 = (10110101)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Example 2:
(+53)10 = (00110101)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Example 3:
(+33)10 = (00010001)𝑠𝑖𝑔𝑛−𝑏𝑖𝑡𝑚𝑎𝑔𝑛𝑖𝑡𝑢𝑑𝑒
Using sign-bit magnitude binary representation, when eight bits are

used; numbers in the range –127 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using sign-bit
magnitude format are −(2𝑛−1 − 1) to +(2𝑛−1 − 1).
This is the simplest method of representing signed numbers.
One’s (1’s) Complement Representation

In this representation, positive decimal numbers are represented same as
that of sign-bit magnitude method. But negative numbers are represented in a
different way.
For representing negative numbers, following steps are performed.
1. Represent the number with positive sign.
2. Find its 1’s complement. (By replacing each ‘0’ with ‘1’ and vice a
versa. i.e. by inverting all the bits we get 1’s complement).
Output of step 2 is 1’s complement representation of the negative number.
Example 1:
(+53)10 = (00110101)1′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
1-24
Example 2:
(+33)10 = (00010001)1′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 3:
(−53)10 = (? )1′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
In step 1, +53 is represented as,

(+53)10 = (00110101)
Then, its 1’s complement is found as
00110101
11001010
Therefore,
(−53)10 = (11001010)1′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 4:

(+33)10 = (00010001)
Then, its 1’s complement is found as
00010001
11101110
Therefore,
(−33)10 = (11101110)1′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Using 1’s complement binary representation, when eight bits are used;
numbers in the range –127 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using 1’s
complement representation are −(2𝑛−1 − 1) to +(2𝑛−1 − 1).
Two’s (2’s) Complement Representation

In this representation, a positive number is represented same as that of
sign-bit magnitude method. A negative number is represented by computing 2’s
complement of binary equivalent of its magnitude. (2’s complement of a binary
number is computed by adding 1 in its 1’s complement).
For representing negative numbers, following steps are performed.
1. Represent the number with positive sign.
2. Find its 2’s complement. (By adding 1 in its 1’s complement).
Output of step 2 is 2’s complement representation of the negative number.
Example 1:
(+53)10 = (00110101)2′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 2:
(+33)10 = (00010001)2′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 3:

(+53)10 = (00110101)
1-25
Then, for finding its 2’s complement, first its 1’s complement is found as
00110101
11001010
Then by adding 1 in the result we get 2’s complement as,
11001010
+ 1
--------------------
11001011
Therefore,
(−53)10 = (11001011)2′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Example 4:

(+33)10 = (00010001)
Then, for finding its 2’s complement, first its 1’s complement is found as
00010001
11101110
11101110
+ 1
--------------------
11101111
Therefore,
(−33)10 = (11101111)2′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
Using 2’s complement binary representation, when eight bits are used;
numbers in the range –128 to +127 can be represented. In an n-bit
representation, range of numbers those can be represented using 1’s
complement representation are −(2𝑛−1) to +(2𝑛−1 − 1).
This is the most popular method of representing signed numbers. It is
become popular due to two reasons.
1. It is easy to generate 2’s complement of a binary number.
2. Arithmetic operations in 2’s complement method are easy.
Beyond Curriculum Point 1: Floating point numbers

Generally, floating point numbers are expressed in the following form.
𝑁 = 𝑚 × 𝑏𝑒
Here m is called significand or mantissa, e is called exponent and b is
base. Some examples are shown below.
0.000005312 = 5.312 × 10−6
531200 = 5.312 × 10+5
𝐵2𝐵. 2𝐶 = 𝐵. 2𝐵2𝐶 × 16+2
0.0031𝐹 = 3.1𝐹 × 16−3
1-26
11001.0110 = 0.110010110 × 2+5 = 0.110010110𝑒 + 0101
0.000110110 = 0.110110 × 2−3 = 0.110110𝑒 − 0011
The most commonly used format for representing floating point numbers
is IEEE-754 standard. This standard defines two basic formats as single
precision and double precision.
In single precision format, 8 bits are used for representing exponent and
24 bits are used for representing. Within 8 bits of exponent one bit is used for
representing sign of exponent and remaining 7 bits are used for representing
magnitude of exponent. So value of exponent can range from –127 to +127. (from
2−127to 2+127. i.e. from 10−38to 10+38). From 24 bits reserved for mantissa, one
bit is used as sign bit and remaining 23 bits are used for representing
magnitude of mantissa.
In double precision format, 11 bits are used for representing exponent and
53 bits are used for representing. Within 11 bits of exponent one bit is used for
representing sign of exponent and remaining 10 bits are used for representing
magnitude of exponent. So value of exponent can range from –1024 to +1024.
(from 2−1024to 2+1024. i.e. from 10−308to 10+308). From 53 bits reserved for
mantissa, one bit is used as sign bit and remaining 52 bits are used for
representing magnitude of mantissa.
Binary Arithmetic
Up to this point, we have studied various methods of data representation.
Now, it is important to study data manipulation. We can perform two types of
operations on binary data – arithmetic operations and logic operations.
Arithmetic operations include addition, subtraction, multiplication and division.
These operations are discussed here. Various logic operation like AND, OR,
NOT are discussed in chapter 2.
Binary Addition
Basic rules for performing binary addition are given below in table 1.4.
Table 1.4: Rules for binary addition
A B A+B
0 0 0
0 1 1
1 0 1
1 1 0 with carry 1
Some examples of performing binary addition are given below.
1-27
Example 1:
(1001110)2 + (11110)2 = (? )2
1 0 0 1 1 1 0
+ 1 1 1 1 0
C 1 1 1 1
1 1 0 1 1 0 0
(1001110)2 + (11110)2 = (1101100)2

Example 2:
(11000111)2 + (11110000)2 = (? )2
1 1 0 0 0 1 1 1
+ 1 1 1 1 0 0 0 0
C 1 1
1 1 0 1 1 0 1 1 1
(11000111)2 + (11110000)2 = (110110111)2
Binary Subtraction
Basic rules for performing binary subtraction are given below in table 1.5.
Table 1.5: Rules for binary subtraction
A B A–B
0 0 0
0 1 1 with borrow 1
1 0 1
1 1 0
Some examples of performing binary subtraction are given below.
Example 1:
(1001110)2 − (11110)2 = (? )2
1 0 0 1 1 1 0
– 1 1 1 1 0
B 1 1
0 1 1 1 1 0 0
(1001110)2 + (11110)2 = (111100)2
Example 2:
(11110000)2 − (11000111)2 = (? )2
1 1 1 1 0 0 0 0
– 1 1 0 0 0 1 1 1
B 1 1 1 1
0 0 1 0 1 0 0 1
(11110000)2 − (11000111)2 = (101001)2
1-28
Binary Multiplication
Basic rules for performing binary multiplication are given in table 1.6.
Table 1.6: Rules for binary multiplication
A B AXB
0 0 0
0 1 0
1 0 0
1 1 1
Some examples of performing binary multiplication are given below.
Example 1:
(1001110)2 × (110)2 = (? )2
1 0 0 1 1 1 0
X 1 1 0
0 0 0 0 0 0 0
+ 1 0 0 1 1 1 0 X
+ 1 0 0 1 1 1 0 X X
1 1 1
1 1 1 0 1 0 1 0 0
(1001110)2 × (110)2 = (111010100)2

Example 2:
(11110000)2 × (1010)2 = (? )2
1 1 1 1 0 0 0 0
X 1 0 1 0
0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 X
0 0 0 0 0 0 0 0 X X
1 1 1 1 0 0 0 0 X X X
1 1 1 1
1 0 0 1 0 1 1 0 0 0 0 0
(11110000)2 − (1010)2 = (100101100000)2
1-29
Binary Division
Binary division is performed similar to decimal division. Some examples
of performing binary division are given below.
Example 1:
(11110000)2 ÷ (1010)2 = (? )2
Q 0 0 0 1 1 0 0 0
1 0 1 0 1 1 1 1 0 0 0 0
- 1 0 1 0
0 1 0 1 0
- 1 0 1 0
R 0 0 0 0 0 0 0
(11110000)2 − (1010)2 = (11000)2
1-30
Example 2
(1001111)2 ÷ (110)2 = (? )2
Q 0 0 0 1 1 0 1
1 1 0 1 0 0 1 1 1 1
- 1 1 0
1 1
0 0 1 1 1
- 1 1 0
0 0 1 1 1
- 1 1 0
R 0 0 1
(1001111)2 ÷ (110)2 = (1101)2𝑤𝑖𝑡ℎ𝑟𝑒𝑚𝑎𝑖𝑛𝑑𝑒𝑟(001)2
One’s complement Arithmetic

Arithmetic operations discussed in 1.3.7 deals with unsigned binary
numbers only. For signed numbers, the arithmetic operations depend on the
way how they are represented. When signed numbers are represented using
one’s complement representation, we have to perform addition or subtraction by
using the steps discussed below.
As these rules deal with signed numbers, we can represent any
subtraction operation in terms of addition as shown in following examples.
𝐴 − 𝐵 = 𝐴 + (−𝐵)
−𝐴 − 𝐵 = (−𝐴) + (−𝐵)
−𝐴 − (−𝐵) = (−𝐴) + 𝐵
Following are the steps for performing 1’s complement addition
(subtraction also – First subtraction should be represented as addition).
1. Represent both the numbers using 1’s complement representation.
2. Perform simple binary addition.
3. If carry is generated out of MSBs, add it to LSB of the result.
4. If MSB is 0, result is positive. Find equivalent of result.
5. If MSB is 1, result is negative. Find 1’s complement of result and then its
equivalent.
1-31
Some examples are shown below.
Example 1:
(83)10 + (39)10 = (? )10
Step 1: 1’s complement representation of numbers
(83)10 = 01010011
(39)10 = 00100111
Step 2: Simple Binary addition

0 1 0 1 0 0 1 1
+ 0 0 1 0 0 1 1 1
1 1 1
0 1 1 1 1 0 1 0
Step 4: As MSB is 0, result is positive and it is,
01111010 = (122)10
∴ (83)10 + (39)10 = (122)10
Example 2:
(−83)10 + (39)10 = (? )10
(−83)10 =?
(83)10 = 01010011
01010011
10101100
(−83)10 = 10101100
(39)10 = 00100111
1 0 1 0 1 1 0 0
+ 0 0 1 0 0 1 1 1
1 1 1
1 1 0 1 0 0 1 1
Step 5: As MSB is 1, result is negative,
11010011
00101100
∴ 𝑅𝑒𝑠𝑢𝑙𝑡𝑖𝑠(−44)10
∴ (−83)10 + (39)10 = (−44)10
Example 3:
(83)10 − (39)10 = (? )10
1-32
The above subtraction can be represented in terms of addition as,
(83)10 + (−39)10 = (? )10
(83)10 = 01010011
(−39)10 =?
(39)10 = 00100111
00100111
11011000
(−39)10 = 11011000
0 1 0 1 0 0 1 1
+ 1 1 0 1 1 0 0 0
1 1 1
1 0 0 1 0 1 0 1 1
Step 3: Carry generated out of MSB is added to LSB of result.
0 0 1 0 1 0 1 1
+ 1
1 1
0 0 1 0 1 1 0 0
00101100 = (+44)10
∴ (83)10 − (39)10 = (+44)10
1-33
Two’s complement Arithmetic
Arithmetic operations discussed in 1.3.7 deals with unsigned binary
numbers only. For signed numbers, the arithmetic operations depend on the
way how they are represented. When signed numbers are represented using
two’s complement representation, we have to perform addition or subtraction by
using the steps discussed below.
As these rules deal with signed numbers, we can represent any
subtraction operation in terms of addition as shown in following examples.
𝐴 − 𝐵 = 𝐴 + (−𝐵)
−𝐴 − 𝐵 = (−𝐴) + (−𝐵)
−𝐴 − (−𝐵) = (−𝐴) + 𝐵
Following are the steps for performing 2’s complement addition
(subtraction also – First subtraction should be represented as addition).
1. Represent both the numbers using 2’s complement representation.
3. If any carry is generated out of MSBs, ignore it.
4. If MSB is 0, result is positive. Find equivalent of result.
5. If MSB is 1, result is negative. Find 2’s complement of result and then its
equivalent.

Example 1:
(83)10 + (39)10 = (? )10
(83)10 = 01010011
(39)10 = 00100111
0 1 0 1 0 0 1 1
+ 0 0 1 0 0 1 1 1
1 1 1
0 1 1 1 1 0 1 0
01111010 = (122)10
∴ (83)10 + (39)10 = (122)10
1-34
Example 3:
(83)10 − (39)10 = (? )10
Above subtraction can be represented in terms of addition as,
(83)10 + (−39)10 = (? )10
(83)10 = 01010011
(−39)10 =?
(39)10 = 00100111
00100111
11011000
11011000
+ 1
--------------------
11011001
(−39)10 = 11011001
0 1 0 1 0 0 1 1
+ 1 1 0 1 1 0 0 1
1 1 1 1 1
1 0 0 1 0 1 1 0 0
Step 3: Carry generated out of MSB is ignored.
00101100 = (+44)10
∴ (83)10 − (39)10 = (+44)10
1-35
Binary Coded Decimal (BCD) Code
Each decimal digit is represented by a four-bit code. The BCD codes of all
the decimal digits 0 through 9 are shown below.
Table 1.7: BCD Codes
Decimal Digit BCD Code
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
Some examples of BCD code representation are shown below. Also their
binary equivalents are shown.
Example Decimal Number BCD Code Binary equivalent
1 14 00010100 1110
2 83 10000011 01010011
3 122 000100100010 01111010
4 39 00111001 00100111
5 293.52 001010010011.01010010 100100101.10000101
6 13.25 00010011.00100101 1101.01
From above examples, it can be easily observed that more number of bits
is required for representing a number using BCD code as compared to simple
binary equivalent. This is disadvantage of BCD code. BCD arithmetic is also
somewhat critical. But even then, BCD code is convenient and useful code for
input and output operations.
Decimal to BCD conversion and BCD to Decimal conversion are very easy
as only the table 1.7 is used for doing the conversion.
BCD is also known as 8-4-2-1 code as the bits in the code have weights as
8, 4, 2 and 1.
Beyond Curriculum Point 2: Additional BCD Codes

The basic BCD code is 8421 BCD code. There are some more
weighted BCD codes as 4221 BCD code and 5421 BCD code.
Obviously, 4, 2, 2, 1 in 4221 BCD code and 5, 4, 2, 1 in 5421 BCD code
are weights of respective bits. Table
1.8 shows how decimal digits from 0 through 9 are represented using these BCD
codes.
1-36
Table 1.8: Other BCD Codes
Decimal Digit 4221 BCD 5421 BCD
Code Code
0 0 0 0 0 0 0 0 0
1 0 0 0 1 0 0 0 1
2 0 0 1 0 0 0 1 0
3 0 0 1 1 0 0 1 1
4 1 0 0 0 0 1 0 0
5 0 1 1 1 1 0 0 0
6 1 1 0 0 1 0 0 1
7 1 1 0 1 1 0 1 0
8 1 1 1 0 1 0 1 1
9 1 1 1 1 1 1 0 0
Point 3: Excess–3 Code

Excess-3 code is one more important BCD code. It is very much useful in
performing BCD arithmetic. Table 1.9 shows how decimal digits from 0 through
9 are represented using Excess–3 codes.
Table 1.8: Excess–3 Code
Decimal Digit Excess-3 Code
0 0 0 1 1
1 0 1 0 0
2 0 1 0 1
3 0 1 1 0
4 0 1 1 1
5 1 0 0 0
6 1 0 0 1
7 1 0 1 0
8 1 0 1 1
9 1 1 0 0
BCD Arithmetic
Method of performing BCD arithmetic is different from binary arithmetic.
There are different rules for doing so.
BCD Addition
There are various methods for performing BCD addition. One of them is
discussed below.
Rules for performing BCD addition are,
1. Represent both the decimal numbers in their BCD codes.
3. If any digit (4 bits) in the result contains invalid BCD code or a carry
is generated out of a digit (4 bits), add 0110 to each such digit (4 bits).
1-37
Example 1:
(83)10 + (39)10 = (? )10
Step 1: BCD code representation of numbers
(83)10 = 10000011
(39)10 = 00111001
1 0 0 0 0 0 1 1
+ 0 0 1 1 1 0 0 1
1 1
1 0 1 1 1 1 0 0
Step 3: As both digits of result contain invalid BCD codes,
1 0 1 1 1 1 0 0
+ 0 1 1 0 0 1 1 0
1 1 1 1 1 1
1 0 0 1 0 0 0 1 0
(000100100010)𝐵𝐶𝐷 = (122)10
∴ (83)10 + (39)10 = (122)10
Example 2:
(29)10 + (58)10 = (? )10
1-38
(29)10 = 00101001
(58)10 = 01011000
0 0 1 0 1 0 0 1
+ 0 1 0 1 1 0 0 0
1 1 1 1
1 0 0 0 0 0 0 1
Step 3: As carry is generated from least significant digit to next
digit 0110 is added to lest significant digit,
1 0 0 0 0 0 0 1
+ 0 1 1 0
1 0 0 0 0 1 1 1
(10000111)𝐵𝐶𝐷 = (87)10
∴ (29)10 + (58)10 = (87)10
Example 3:
(637)10 + (463)10 = (? )10
(637)10 = 011000110111
(463)10 = 010001100011
0 1 1 0 0 0 1 1 0 1 1 1
+ 0 1 0 0 0 1 1 0 0 0 1 1
1 1 1 1 1 1
1 0 1 0 1 0 0 1 1 0 1 0
Step 3: As least significant digit and most significant digit are
invalid, 0110 is added to both these digits.
1 0 1 0 1 0 0 1 1 0 1 0
+ 0 1 1 0 0 1 1 0
1 1 1 1 1 1 1
1 0 0 0 0 1 0 1 0 0 0 0 0
As result contains invalid digit, 0110 is added to that digit.
1 0 0 0 0 1 0 1 0 0 0 0 0
+ 0 1 1 0
1 1 1
1 0 0 0 1 0 0 0 0 0 0 0 0
1-39
Example 4: (0001000100000000)𝐵𝐶𝐷 = (1100)10
∴ (637)10 + (463)10 = (1100)10
1001 + 1101 =?
Step 1: The above numbers are represented in binary
representation. First number is binary equivalent of (9)10 and second number
is binary equivalent of (13)10. BCD code representation of these numbers is,
(9)10 = 1001
(13)10 = 00010011
1 0 0 1
+ 0 0 0 1 0 0 1 1
1 1
0 0 0 1 1 1 0 0
Step 3: As least significant digit is invalid, 0110 is added to that
digit.
0 0 0 1 1 1 0 0
+ 0 1 1 0
1 1 1
0 0 1 0 0 0 1 0
(00100010)𝐵𝐶𝐷 = (22)10
∴ (1001)2 + (1101)2 = (22)10 = (10110)2
BCD Subtraction
There are various methods for performing BCD subtraction. One of
them is discussed below.
Rules for performing BCD subtraction are (By considering subtraction
as A – B ),
1. Represent A in BCD code.
2. Represent 9’s complement of B in BCD code.
3. Perform BCD addition.
4. If carry is generated out of MSB, result is positive. To get correct
result, carry is added to result.
5. If carry is not generated, result is negative and it is in 9’s
complement form.
Some examples are shown

below. Example 1:
(45)10 − (27)10 = (? )10
Step 1: BCD code representation of A
(45)10 = 01000101
Step 2: 9’s complement of B is,
(27)10 = (72)9′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
1-40
BCD code is
72 = 01110010
Step 3: BCD addition
0 1 0 0 0 1 0 1
+ 0 1 1 1 0 0 1 0
1 0 1 1 0 1 1 1
As most significant digit of result contain invalid BCD code,
1 0 1 1 0 1 1 1
+ 0 1 1 0
1 1
1 0 0 0 1 0 1 1 1
Step 4: As carry is generated out of MSB, it is added to
result. (Result is positive)
0 0 0 1 0 1 1 1
+ 1
1 1 1
0 0 0 1 1 0 0 0
(00011000)𝐵𝐶𝐷 = (+18)10
Example 2: ∴ (45)10 − (27)10 = (+18)10
(45)10 − (83)10 = (? )10

Step 1: BCD code representation of A
(45)10 = 01000101
Step 2: 9’s complement of B is,
(83)10 = (16)9′𝑠𝑐𝑜𝑚𝑝𝑙𝑒𝑚𝑒𝑛𝑡
BCD code is
16 = 00010110
Step 3: BCD addition
0 1 0 0 0 1 0 1
+ 0 0 0 1 0 1 1 0
1
0 1 0 1 1 0 1 1
As least significant digit of result contain invalid BCD code,
0 1 0 1 1 0 1 1
+ 0 1 1 0
1 1 1 1
0 1 1 0 0 0 0 1
Step 5: As carry is not generated out of MSB, result is negative
and it is in 9’s complement form
(01100001)𝐵𝐶𝐷 = (61)10
1-2
But as result is in 9’s complement form, true result is
∴ (45)10 − (83)10 = (−38)10
1-3
Chapter 2
Logic GATEs AND LOGIC FAMILIES
10 Hours
12 Marks
Logic Gates
Logic gates are electronic circuits. For implementing various logic

expressions (a.k.a. Boolean expressions), logic gates can be used. The logic gate
is the most basic building block of combinational logic. Logic gate performs a
logical operation on one or more logical inputs and produce a single logical
output. Before studying logic gates one should know the things discussed here.
Truth table for a logic system lists all possible combinations of input
variables and corresponding output generated by the logic system. Output of a
logic system can be found from the logic expression (i.e. Boolean expression) of
that logic system.
When the number of input binary variables is only one, then there are
only two possible inputs, i.e. ‘0’ and ‘1’. If the number of inputs is two, there can
be four possible input combinations, i.e. 00, 01, 10 and 11. Similarly, for three
input binary variables, the number of possible input combinations becomes
eight, i.e. 000, 001, 010, 011, 100, 101, 110 and 111.
In general, if a logic circuit has n binary inputs, its truth table will have
2 possible input combinations (i.e. truth table contains 2n rows).
n
Figure 2.1 shows a sample 2–input logic system and table 2.2 shows a
sample truth table for a 2–input logic system.
A Logic
System Y
B
Figure 2.1: A sample 2–input logic system
Table 2.1: A sample Truth Table

Input Output
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
1-4
Basic Gates
Logic gate is the most basic building block of any digital system (even for
computers). Each basic logic gate is a piece of hardware or an electronic circuit
that can be used to implement some basic logic expression. For implementing
various laws of Boolean algebra, basic gates can be used. Basic gates perform
basic logical operations on the logical inputs.
There are three basic logic gates, namely the OR gate, the AND gate and
the NOT gate.
OR gate
The OR gate performs logical OR operation on two or more inputs
(generally referred as logic variables). The OR gate has two or more inputs and
a single output. Output of an OR gate is LOW if all the inputs are LOW. In all
other cases, output of OR gate is HIGH.
The OR operation on two independent logical variables A and B can be
represented by following logic expression (sometimes also called logical
equation).
𝑌 =𝐴+𝐵
It is read as Y is equal to A OR B. The logic expression shown above is
logic expression for 2–input OR gate. Logical symbol for 2 – input OR gate is
A
Y=A+B
B
Figure 2.2: Logical symbol for 2 – input OR gate

Truth table for 2 – input OR gate is shown in table 2.2.
Table 2.2: Truth table for 2 – input OR gate
i/p o/p
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Figure 2.3: IC pin configuration for IC 7432

1-5
The TTL IC used for 2 – input OR gate is 7432. It is a quad 2 – input OR
gate. i.e. There are four 2 – input OR gates in the IC. Pin configuration of IC
7432 is shown in figure 2.3.
The logic expression or logical equation for 3 – input OR gate is shown

below.
𝑌 =𝐴+𝐵+𝐶
Logical symbol for 3 – input OR gate is shown in figure 2.4.
A
B Y=A+B+C
C
Figure 2.4: Logical symbol for 3 – input OR gate

Truth table for 3 – input OR gate is shown in table 2.3.
Table 2.3: Truth table for 3 – input OR gate
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
The TTL IC used for 3 – input OR gate is 744075. It is a triple 3 – input
OR gate. i.e. There are three 3 – input OR gates in the IC.
AND gate
The AND gate performs logical AND operation on two or more inputs
(generally referred as logic variables). The AND gate has two or more inputs
and a single output. Output of an AND gate is HIGH if all the inputs are HIGH.
In all other cases, output of AND gate is LOW.
The AND operation on two independent logical variables A and B can be
equation).
𝑌 = 𝐴. 𝐵
It is read as Y is equal to A AND B. The logic expression shown above is
logic expression for 2–input AND gate. Logical symbol for 2 – input AND gate is
1-6
A
Y=A.B
B
Figure 2.5: Logical symbol for 2 – input AND gate

Truth table for 2 – input AND gate is shown in table 2.4.
Table 2.4: Truth table for 2 – input AND gate
i/p o/p
A B Y
0 0 0
0 1 0
1 0 0
1 1 1
The TTL IC used for 2 – input AND gate is 7408. It is a quad 2 – input
AND gate. i.e. There are four 2 – input AND gates in the IC. Pin configuration of
IC 7408 is shown in figure 2.6.
Figure 2.6: IC pin configuration for 7408
The logic expression or logical equation for 3 – input AND gate is shown
below.
𝑌 = 𝐴. 𝐵. 𝐶
Logical symbol for 3 – input AND gate is shown in figure 2.7.
A
B Y=A.B.C
C
Figure 2.7: Logical symbol for 3 – input AND gate

Truth table for 3 – input AND gate is shown in table 2.5.
1-7
Table 2.5: Truth table for 3 – input AND gate
i/p o/p
A B C Y
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
The TTL IC used for 3 – input AND gate is 7411. It is a triple 3 – input
AND gate. i.e. There are three 3 – input AND gates in the IC.
NOT gate
The NOT gate performs logical NOT (i.e. negation) operation on an input
(generally referred as logic variable). The NOT gate has a single input and a
single output. Output of an AND gate is complement of its input. If input is
LOW, output is HIGH and if input is HIGH, output is LOW.
The NOT operation on a logical variable X can be represented by
following logic expression (sometimes also called logical equation).
𝑌 = 𝑋̅
or
𝑌 = 𝑋̅′
It is read as Y is equal to NOT X. Logical symbol for NOT gate is shown in
figure 2.8.
X 𝑌 = 𝑋̅
Figure 2.8: Logical symbol for NOT gate

Truth table for NOT gate is shown in table 2.6.
Table 2.6: Truth table NOT gate
i/p o/p
X Y
0 1
1 0
The TTL IC used for NOT gate is 7404. It is a hex inverter. i.e. There
are six NOT gates in the IC. Pin configuration of IC 7404 is shown in figure 2.9.
1-8
Figure 2.9: IC pin configuration of 7404
Universal Gates
In addition to basic gates, other logic gates like NAND and NOR gates are
also used in designing digital circuits. The NAND gate and NOR gate are called
universal gates because using any one type of those gates any logic expression
can be realized. Implementation of any logic expression is economical if it is
done using any one type of universal gates (as compared to implementation
using basic gates). The basic reason behind this is the easier fabrication of these
gates.
NAND gate
NAND stands for NOT AND. The name suggests that it is a combination
of AND gate followed by a NOT gate as shown in figure 2.10.
A
Y
B
Figure 2.10: NAND gate as a combination of AND and NOT gates

The NAND gate has two or more inputs and a single output. Output of an
NAND gate is LOW if all the inputs are HIGH. In all other cases, output of
NAND gate is HIGH.
The NAND operation on two independent logical variables A and B can be
equation).
𝑌 = 𝐴. 𝐵
The logic expression shown above is logic expression for 2–input NAND
gate. Logical symbol for 2 – input NAND gate is shown in figure 2.11.
A
𝑌=𝐴
.𝐵
B
Figure 2.11: Logical symbol for 2 – input NAND gate

1-9
Truth table for 2 – input NAND gate is shown in table 2.7. It can be
obtained by negating the output of AND gate.
Table 2.7: Truth table for 2 – input NAND gate
i/p o/p
A B Y
0 0 1
0 1 1
1 0 1
1 1 0
The TTL IC used for 2 – input NAND gate is 7400. It is a quad 2 – input
NAND gate. i.e. There are four 2 – input NAND gates in the IC. Pin
configuration of IC 7400 is shown in figure 2.12.
Figure 2.12: IC pin configuration of 7400

The logic expression or logical equation for 3 – input NAND gate is shown
below.
𝑌 = ̅̅̅̅̅̅̅̅
𝐴. 𝐵 . 𝐶
Logical symbol for 3 – input NAND gate is shown in figure 2.13.
A
B 𝑌= ̅̅̅̅̅̅̅̅
𝐴. 𝐵 . 𝐶
C
Figure 2.13: Logical symbol for 3 – input NAND gate

Table 2.8: Truth table for 3 – input NAND gate
i/p o/p
A B C Y
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
1-10
Truth table for 3 – input NAND gate is shown in table 2.8. The TTL IC
used for 3 – input NAND gate is 7410. It is a triple 3 – input NAND gate. i.e.
There are three 3 – input NAND gates in the IC.
NOR gate
NOR stands for NOT OR. The name suggests that it is a combination of
OR gate followed by a NOT gate as shown in figure 2.14.
A
Y
B
Figure 2.14: NOR gate as a combination of OR and NOT gates

The NOR gate has two or more inputs and a single output. Output of an
NOR gate is HIGH if all the inputs are LOW. In all other cases, output of NOR
gate is LOW.
The NOR operation on two independent logical variables A and B can be
equation).
𝑌 = 𝐴 +𝐵
The logic expression shown above is logic expression for 2–input NOR
gate. Logical symbol for 2 – input NOR gate is shown in figure 2.15.
A
𝑌 = 𝐴 +𝐵
B
Figure 2.15: Logical symbol for 2 – input NOR gate

Truth table for 2 – input NOR gate is shown in table 2.9. It can be
obtained by negating the output of OR gate.
Table 2.9: Truth table for 2 – input NOR gate
i/p o/p
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
The TTL IC used for 2 – input NOR gate is 7402. It is a quad 2 – input NOR
gate. i.e. There are four 2 – input NOR gates in the IC. Pin configuration for IC
7402 is shown in figure 2.16.
1-11
The logic expression or logical equation for 3 – input NOR gate is shown
below.
𝑌 = (𝐴+𝐵+
𝐶)
Logical symbol for 3 – input NOR gate is shown in figure 2.17.
A
B 𝑌 = (𝐴+𝐵+
𝐶)
C
Figure 2.17: Logical symbol for 3 – input NOR gate

Truth table for 3 – input NOR gate is shown in table 2.10.
Table 2.10: Truth table for 3 – input NOR gate
i/p o/p
A B C Y
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
The TTL IC used for 3 – input NOR gate is 7427. It is a triple 3 – input
NOR gate. i.e. There are three 3 – input NOR gates in the IC.
Derived Gates
The gates those are derived from basic gates are called as derived gates.
Sometimes NAND gate and NOR gate are also referred as derived gates (as they
are derived from basic gates). Two more derived gates are Ex-OR gate and Ex-
NOR gate.
Ex-OR gate (XOR gate)

The Ex-OR stands for Exclusive OR. It is used for performing OR
operation exclusively. Ex-OR gate has two inputs and a single output. (We may
design multiple input Ex-OR gates. But they are not readily available). Output
1-12
of Ex-OR gate is HIGH if odd number of inputs is HIGH. If even number of
inputs is HIGH, output is LOW.
The logic expression (sometimes also called logical equation) of 2 – input
Ex-OR gate is shown below.
𝑌 = 𝐴 ⊕ 𝐵 = 𝐴𝐵 + 𝐴𝐵
It is read as Y is equal to A Ex-OR B. Logical symbol for 2 – input Ex-OR
gate is shown in figure 2.18.
A
𝑌 =𝐴⊕𝐵
B
Figure 2.18: Logical symbol for 2 – input Ex-OR gate

Table 2.11: Truth table for 2 – input Ex-OR gate
i/p o/p
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
Truth table for 2 – input Ex-OR gate is shown in table 2.11. The TTL IC
used for 2 – input Ex-OR gate is 7486. It is a quad 2 – input XOR gate. i.e. There
are four 2 – input XOR gates in the IC. Pin configuration for IC 7486 is shown in
figure 2.19.
We may design multiple-input Ex-OR gates. In multiple input Ex-OR

gates output is HIGH if odd number of inputs have HIGH value. In all other
cases, output is LOW.
Ex-NOR gate
The Ex-NOR stands for Exclusive NOR. It means NOT of Ex-OR. Ex-
NOR gate has two inputs and a single output. (We may design multiple input
Ex-NOR gates. But they are not readily available). Output of Ex-NOR gate is
HIGH if even number of inputs is HIGH. If odd number of inputs is LOW,
output is LOW.
The logic expression (sometimes also called logical equation) of 2 – input
Ex-NOR gate is shown below.
1-13
̅̅̅̅̅̅̅̅
𝑌 =𝐴 ⊕ 𝐵 = 𝐴𝐵 + ̅̅̅̅
𝐴𝐵
It is read as Y is equal to A Ex-NOR B. Logical symbol for 2 – input Ex-
NOR gate is shown in figure 2.20.
A
𝑌 = ̅̅̅̅̅̅̅̅̅̅
𝐴 ⊕ 𝐵
B
Figure 2.20: Logical symbol for 2 – input Ex-NOR gate

Truth table for 2 – input Ex-NOR gate is shown in table 2.12.
Table 2.12: Truth table for 2 – input Ex-NOR gate
i/p o/p
A B Y
0 0 1
0 1 0
1 0 0
1 1 1
The TTL IC used for 2 – input Ex-NOR gate is 747266. It is a quad 2 –
input XNOR gate. i.e. There are four 2 – input XNOR gates in the IC. Pin
configuration for IC 747266 is shown in figure 2.21.
Deriving gates from universal gates

The NAND gate and NOR gate are called universal gates because using
any one type of those gates any logic expression can be realized. We can also
derive all the gates using any one type of universal gates.
Deriving NOT gate
A 𝑌 =𝐴
Figure 2.22: NOT gate using NAND gate
1-14
A 𝑌 =𝐴
Figure 2.23: NOT gate using NOR gate
Deriving AND gate
A
𝑌 = 𝐴. 𝐵
B
Figure 2.24: AND gate using NAND gates only
𝑌 = 𝐴. 𝐵
Figure 2.25: AND gate using NOR gates only

Deriving OR gate
𝑌=𝐴+𝐵
Figure 2.26: OR gate using NAND gates only
1-15
A
𝑌=𝐴+𝐵
B
Figure 2.27: OR gate using NOR gates only
Deriving NOR gate using NAND gates
𝑌 =(̅𝐴+ ̅ ̅
̅ 𝐵 )
Figure 2.28: NOR gate using NAND gates only
Deriving NAND gate using NOR gates
𝑌 = ̅(̅𝐴.̅ ̅𝐵)̅
Figure 2.29: NAND gate using NOR gates only
Construction of logic circuits using universal gates

Using any one type of universal gates any logic expression can be
realized.
Example 1: Construct a logic circuit using NAND gates only for following
expression
𝑋̅ = 𝐴. (𝐵 + 𝐶)
1-16
A
𝑋̅ = 𝐴. (𝐵 + 𝐶)
Example 2: Construct a logic circuit using NOR gates only for following
expression
𝑋̅ = 𝐴. (𝐵 + 𝐶)
𝑋̅ = 𝐴. (𝐵 + 𝐶)
Figure 2.27: OR gate using NOR gates only
Questions:
1. Draw symbol, logical equation and truth table of 3 i/p AND gate and 3
i/p OR gate. [4M]
2. Draw pin configuration of TTL ICs used for AND gate and NAND gate.
[4M]
1-17
3. Draw logical symbol, truth table and logical expression of EX-OR gate.
[2M]
4. Draw symbol and truth table for EX-NOR gate. [2M]
5. Draw logical symbol, truth table and logical expression for NAND and
NOR gate. [4M]
6. Draw logical symbol, expression, truth table and IC pin configuration for 2
input NOR gate. [4M]
7. Draw the pin configuration with the internal schematic of IC 7400. [2M]
8. Draw symbol, logical equation, truth table and TTL IC used for 2 i/p EX-
OR and NOR gate. [4M]
9. Draw logic symbol and truth table of NOR gate. [2M]
10. Draw AND gate using NAND gates only and NOR gates only. [2M]
11. Implement AND, OR, NOT and NOR gate using NAND gates only. [4M]
12. Draw logical symbol, truth table and logical expression of NAND gate and
AND gate. [4M]
13. What is universal gate? Construct a logic circuit using NAND gates only
for following expression. [4M]
𝑋̅ = 𝐴 ∙ (𝐵 + 𝐶)
14. What are universal gates? Draw logical circuits of basic gates using
universal gates. [4M]
15. Define universal gate and design basic gates using NAND as universal
gate. [4M]
16. What is universal gate? Construct any two basic gates using NOR gate.
[4M]
17. Implement OR and AND gates by using NAND gates only. [4M]
Boolean laws
Boolean algebra is mathematics of logic. It is one of the most basic tool for
simplifying Boolean laws. Logic variables are denoted by capital letters (e.g. A,
B, C, …). If value of 𝐴 = 0, then 𝐴 = 1 and if value of 𝐴 = 1, then 𝐴 = 0. Two
Boolean expressions are said to be equal if and only if the truth tables of them
are identical.
Fundamental laws of Boolean algebra are shown below.

𝐴+0=𝐴 𝐴. 0 = 0
𝐴+1=1 𝐴. 1 = 𝐴
𝐴+𝐴=𝐴 𝐴. 𝐴 = 𝐴
𝐴+𝐴=1 𝐴. 𝐴 = 0
𝐴=𝐴
Commutative laws are shown below.

𝐴+𝐵=𝐵+𝐴
𝐴. 𝐵 = 𝐵. 𝐴
Associative laws are shown below.

(𝐴 + 𝐵) + 𝐶 = 𝐴 + (𝐵 + 𝐶)
1-18
(𝐴. 𝐵). 𝐶 = 𝐴. (𝐵. 𝐶)
Distributive laws are shown below.

𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Some more important laws are shown below.

𝐴. 𝐵 + 𝐴. 𝐵 = 𝐴
(𝐴 + 𝐵). (𝐴 + 𝐵) = 𝐴
(𝐴 + 𝐵). 𝐵 = 𝐴. 𝐵
𝐴. 𝐵 + 𝐵 = 𝐴 + 𝐵
𝐴 + 𝐴. 𝐵 = 𝐴
𝐴. (𝐴 + 𝐵) = 𝐴
De-Morgan’s theorems are shown below.
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 … . . 𝑁= 𝐴 + ̅ ̅
𝐵+𝐶+⋯ 𝑁
𝐴 + 𝐵 + 𝐶 … . . +𝑁= 𝐴 . 𝐵̅ . 𝐶 … … 𝑁
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅
De-Morgan’s first theorem states that complement of product of

variables is equal to the sum of complements of the variables.
De-Morgan’s second theorem states that complement of sum of
variables is equal to the product of complements of the variables.
Duality property states that all Boolean expressions remain valid when
following steps are performed.
Step 1: Interchange OR operator (+) and AND operator (.)
Step 2: Replace all 1’s by 0’s and all 0’s by 1’s.
e.g. As 𝐴 + 0 = 𝐴, its dual is 𝐴. 1 = 𝐴
As (𝐴 + 𝐵 ). 𝐵 = 𝐴. 𝐵, its dual is 𝐴. 𝐵 + 𝐵 = 𝐴 + 𝐵
As ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 … . . 𝑁= 𝐴 + ̅ ̅,
𝐵+𝐶+⋯ 𝑁 its dual is
𝐴 + 𝐵 + 𝐶 … . . +𝑁= 𝐴
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅ .𝐵
̅ .𝐶̅……𝑁 ̅
Proofs of Boolean laws

Any Boolean law or theorem or expression can be proved in two ways
- Using truth table
- Matching L.H.S. with R.H.S. by simplification
Proofs of Boolean laws using truth table

When proof is done with the help of truth tables, by comparing L.H.S. and
R.H.S. in the truth table, law/ theorem/ expression can be proven.
1-19
Example 1:
Prove that 𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
Proof:
1 2 3 4 5 6 7 8
A B C (B+C) A.(B+C) A.B A.C A.B+A.C
0 0 0 0 0 0 0 0
0 0 1 1 0 0 0 0
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 1 0 1 1
1 1 0 1 1 1 0 1
1 1 1 1 1 1 1 1
By comparing column number 5 and column number 8, it is proven that

𝐴. (𝐵 + 𝐶) = 𝐴. 𝐵 + 𝐴. 𝐶
Example 2:
Prove that 𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Proof:
1 2 3 4 5 6 7 8
A B C B.C A+B.C A+B A+C (A+B).(A+C)
0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0
0 1 0 0 0 1 0 0
0 1 1 1 1 1 1 1
1 0 0 0 1 1 1 1
1 0 1 0 1 1 1 1
1 1 0 0 1 1 1 1
1 1 1 1 1 1 1 1

𝐴 + 𝐵. 𝐶 = (𝐴 + 𝐵). (𝐴 + 𝐶)
Example 3:
Prove De-Morgan’s first theorem.
De-Morgan’s first theorem states that complement of product of
variables is equal to the sum of complements of the variables.
i.e. ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴. 𝐵. 𝐶 … . . 𝑁= 𝐴 + ̅
𝐵+𝐶+⋯ 𝑁 ̅
as, Proof:
Let’s try to prove the De-Morgan’s first theorem for three variables
𝐴. 𝐵.𝐶 = 𝐴 + 𝐵 + 𝐶
1-20
1 2 3 4 5 6 7 8 9
𝐴 𝐵 𝐶 𝐴. 𝐵. 𝐶 𝐴. 𝐵.𝐶 𝐴 𝐵 𝐶 𝐴 + 𝐵+ 𝐶
0 0 0 0 1 1 1 1 1
0 0 1 0 1 1 1 0 1
0 1 0 0 1 1 0 1 1
0 1 1 0 1 1 0 0 1
1 0 0 0 1 0 1 1 1
1 0 1 0 1 0 1 0 1
1 1 0 0 1 0 0 1 1
1 1 1 1 0 0 0 0 0

𝐴̅.̅ ̅𝐵.̅ ̅𝐶̅ = 𝐴̅ + 𝐵̅ + 𝐶̅
Questions:
1. State De-Morgan’s theorem. [2M]
2. State and prove De Morgan’s theorem. [4M]
3. State commutative law. [2M]
4. List different Boolean laws. Also write duality theorem. [4M]
5. State associative law and distributive law of Boolean algebra. [4M]
6. State any four Boolean laws. [2M]
7. State duality theorem and prove it. [4M]
Simplification of Boolean expressions using Boolean laws

When logic circuit is constructed (or realized) for a complex Boolean
expression, it may require more number of logic gates. If the complex Boolean
expression is simplified and then realized (or constructed), less number of logic
gates are used. This is why there is need of simplification of Boolean
expressions.
Boolean expressions may be simplified using one of the following methods
- Using Boolean laws
- Karnaugh map method
- Quine-McCluskey method
Here discussion is done on how the Boolean expressions are simplified

using Boolean laws. The discussion about Karnaugh map (K-map) method is
done in chapter 3 and Quine-McCluskey method is out of the scope of
curriculum of this subject.
1-21
Example 3:
Simplify 𝑌 = (𝐴 + 𝐵)(𝐴 + 𝐵)(𝐴 + 𝐵)
Y = (𝐴 + 𝐵) (𝐴 + 𝐵 ) (𝐴+ 𝐵)
= (𝐴. 𝐴 + 𝐴. 𝐵+ 𝐵. 𝐴 + 𝐵. 𝐵 )(𝐴 + 𝐵) By using distributive law
= (𝐴 + 𝐴. 𝐵 + 𝐵. 𝐴 + 0)(𝐴 + 𝐵) 𝐴. 𝐴 = 𝐴 and 𝐵. 𝐵 = 0
= (𝐴 + 𝐴. 𝐵 + 𝐵. 𝐴)(𝐴 + 𝐵) 𝐴+0= 𝐴
= (𝐴 + 𝐴. (𝐵+ 𝐵))(𝐴 + 𝐵) By taking A common
= (𝐴 + 𝐴. 0)(𝐴 + 𝐵) 𝐵 + 𝐵= 0
= (𝐴 + 0)(𝐴 + 𝐵) 𝐴. 0 = 0
= 𝐴. (𝐴 + 𝐵) 𝐴+0= 𝐴
= 𝐴. 𝐴 + 𝐴. 𝐵 By using distributive law
= 0 + 𝐴. 𝐵 𝐴. 𝐴 = 0
= 𝐴. 𝐵 𝐴+0= 𝐴
Therefore, 𝑌 = 𝐴. 𝐵
Construction of logic circuits
As already discussed previously, any Boolean expression can be realized

(or constructed or implemented or drawn) using logic gates. Before realizing a
Boolean expression, it should be simplified so that requirement of number of
gates may be reduced. Simplification of given Boolean expression can be
minimized (or simplified) using various methods. Here the simplification is done
using basic Boolean laws.
Example 1:
Draw logical circuit for following Boolean expression using basic gates
𝑌 = 𝐴𝐵 + 𝐵𝐶
The expression given above is already in reduced (or simplified or

minimized) form. So, further simplification is not possible.
Logical Circuit:
𝐴 𝐴 𝐵 𝐶
𝑌 = 𝐴𝐵 + 𝐵𝐶
1-22
Therefore, 𝑌 = 𝐴. 𝐵
Logic gate diagram:
𝐵 𝐵 𝐴
𝑌 = 𝐴. 𝐵
Questions:
1. Prove that 𝑌 𝑍 + 𝑊 𝑋̅ 𝑍 + 𝑊𝑋̅𝑌 𝑍 + 𝑊𝑌𝑍 = 𝑍 [4M]
2. Prove [4M]
a. 𝐴 + 𝐴𝐵 + 𝐴𝐵= 𝐴 + 𝐵
b. 𝐴𝐵 + 𝐴𝐵 + 𝐴𝐵= 𝐴 + 𝐵
3. Reduce the following expression and implement using logic gates. [4M]
𝑌 = 𝐴𝐵 + 𝐴𝐵𝐶 + 𝐴𝐵(𝐸 + 𝐹)
4. Simplify the following Boolean expressions using Boolean laws. [4M]
a. 𝑌 = 𝐴(𝐴 + 𝐶)(𝐴𝐵 + 𝐶)
b. 𝑌 = 𝐵𝐶 𝐷+ 𝐴𝐵𝐷 + 𝐴𝐵𝐷 + 𝐵𝐶𝐷+ 𝐵𝐶𝐷 + 𝐴𝐵 𝐶 𝐷 + 𝐴𝐵 𝐶 𝐷
5. Simplify following expression and draw logic gate diagram. [4M]
̅̅̅̅ + ̅̅̅̅̅̅̅̅̅
𝑌 = (𝐴𝐵 𝐴 + 𝐵 )𝐴.𝐵̅
1-23
Chapter 3
CombiNATIOnAL Logic Circuits
16 Hours
18 Marks
Standard representation for logical functions
Boolean expressions / logic expressions / logical functions are expressed in

terms of logical variables. Logical variables can have value either ‘0’ or ‘1’. The
logical functions can be represented in one of the following forms.
- Sum of Products form (SOP form)
- Product of Sums form (POS form)
Sum of Products (SOP) form

In this form, Boolean expression is defined by sum of product terms.
Various AND terms are ORed together. Each AND term may be a single
variable or a product of multiple variables (each variable may be either in
complemented or un-complemented form).
Example 1:
𝑌 = 𝐴𝐶 + 𝐴𝐵𝐶 + 𝐵
Here, Y is represented in SOP form with three terms. First AND term
contains two variables, second contains three variables and third contains a
single variable.
Example 2:
We can obtain sum of products expression from a truth table by
considering the input combinations those produce logic ‘1’ output as shown
below.
Table 3.1: Example Truth table
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
First logic ‘1’ output in the truth table is for A=0, B=0 and C=1. This is
possible when 𝐴, 𝐵and C are ANDed. So, first term is 𝐴. 𝐵. 𝐶 and other terms can
be obtained similarly to get the expression for the truth table 3.1 in sum of
products form as,
3-2
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
As this expression is a function of three variables, it can be expressed as
𝑓(𝐴, 𝐵, 𝐶). It cans also be represented as 𝑌(𝐴, 𝐵, 𝐶).
𝑌 = 𝑓(𝐴, 𝐵, 𝐶) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
Both the examples shown above are in sum of products form. But in first
example, even though the expression is function of three variables, first term is
containing only two variables whereas third term is containing only one
variable.
𝑌 = 𝐴. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐵
We may write each such incomplete term of the above expression in
expanded form as,
𝐴. 𝐶 = 𝐴. 𝐶. (𝐵 + 𝐵) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
𝐵 = 𝐵. (𝐴 + 𝐴) = 𝐴. 𝐵 + 𝐴. 𝐵 = 𝐴. 𝐵. (𝐶 + 𝐶) + 𝐴. 𝐵. (𝐶 + 𝐶)
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
Therefore, the expanded sum of product expression can be written as,
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
Expanded form of Boolean expression in which each term contains all the
Boolean variables in it is called as canonical form. It is also called as
standard sum of products form.
Example 1:
Convert following Boolean expression into standard SOP form.
𝐴𝐶 + 𝐵𝐷
The above expression is a function of four variables A, B, C and D.
As each term is not containing all the variables, it is not standard SOP. The
terms can be expanded to make it standard SOP as,
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴. 𝐶̅ + 𝐵. 𝐷
= 𝐴. (𝐵 + 𝐵̅ ). 𝐶̅ + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅ + 𝐴. 𝐵̅. 𝐶̅ + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅. (𝐷 + 𝐷̅ ) + 𝐴. 𝐵̅. 𝐶̅. (𝐷 + 𝐷̅ ) + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅ . 𝐶̅. 𝐷̅ + 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅ . 𝐶̅. 𝐷̅ + (𝐴 + 𝐴̅). 𝐵. 𝐷
= 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅ . 𝐶̅. 𝐷̅ + 𝐴. 𝐵. 𝐷 + 𝐴. 𝐵. 𝐷̅
= 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅ . 𝐶̅. 𝐷̅ + 𝐴. 𝐵. (𝐶 + 𝐶̅). 𝐷 + 𝐴. 𝐵. (𝐶 + 𝐶̅). 𝐷̅
= 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅. 𝐶̅. 𝐷̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷̅ +
𝐴. 𝐵. 𝐶̅. 𝐷̅
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅. 𝐶̅. 𝐷̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷̅
3-3
Example 2:
Standardize following Boolean expression.
𝑌 = 𝐴𝐶 + 𝐵̅𝐶
The above expression is a function of three variables A, B and C. As
each term is not containing all the variables, it is not standard SOP. The terms
can be expanded to make it standard SOP as,
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐶 + 𝐵̅. 𝐶
= 𝐴. (𝐵 + 𝐵̅ ). 𝐶 + 𝐵̅. 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐵̅. 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + (𝐴 + 𝐴̅). 𝐵̅. 𝐶
= 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵̅. 𝐶 + 𝐴. 𝐵̅ . 𝐶 + 𝐴̅. 𝐵̅. 𝐶
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
Single term in standard sum of products is called as minterm. Each

expression can be represented using minterms. Some examples are shown
below.
Example 1:
𝑌 = 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
As the above expression in standard sum of products, all terms in it are
minterms. They are,
𝐴. 𝐵. 𝐶 𝐴. 𝐵. 𝐶 𝐴. 𝐵. 𝐶
m7 m m
5
111 101 011
3
𝐴. 𝐵. 𝐶 𝐴. 𝐵. 𝐶
m6 m2
110 010
Therefore the expression can be represented as,
𝑌(𝐴, 𝐵, 𝐶) = ∑ 𝑚(2,3,5,6,7)
Example 2:
𝑌 = 𝐴. 𝐵. 𝐶̅. 𝐷 + 𝐴. 𝐵. 𝐶̅. 𝐷̅ + 𝐴. 𝐵̅. 𝐶̅. 𝐷 + 𝐴. 𝐵̅. 𝐶̅. 𝐷̅ + 𝐴. 𝐵. 𝐶. 𝐷 + 𝐴. 𝐵. 𝐶. 𝐷̅
As the above expression in standard sum of products, all terms in it are
minterms. They are,
𝐴. 𝐵. 𝐶 . 𝐷 𝐴. 𝐵. 𝐶̅. 𝐷̅ 𝐴. 𝐵̅. 𝐶̅. 𝐷
m13 m m
12
1101 1100 1001
9
𝐴. 𝐵̅. 𝐶̅. 𝐷̅
𝐴. 𝐵. 𝐶. 𝐷 𝐴. 𝐵. 𝐶. 𝐷
1 0 0 0 m8 m15 m14
1111 1110
3-4
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(8,9,12,13,14,15)
Product of Sums (POS) form

In this form, Boolean expression is defined by product of sum terms.
Various OR terms are ANDed together. Each OR term may be a single variable
or a sum of multiple variables (each variable may be either in complemented or
un-complemented form).
Example 1:
𝑌 = (𝐴 + 𝐶). (𝐵+ 𝐶). 𝐴
Here, Y is represented in POS form with three terms. First OR term
contains two variables, second contains two variables and third contains a single
variable.
Example 2:
We can obtain product of sums expression from a truth table by
considering the input combinations those produce logic ‘0’ output as shown
below.
Table 3.2: Example Truth table
i/p o/p
A B C Y
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 0
First logic ‘0’ output in the truth table is for A=0, B=0 and C=0. This is
possible when 𝐴, 𝐵 and C are ORed. So, first term is (𝐴 + 𝐵 + 𝐶) and other terms
can be obtained similarly to get the expression for the truth table 3.2 in product
of sums form as,
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
As this expression is a function of three variables, it can be expressed as
𝑓(𝐴, 𝐵, 𝐶). It cans also be represented as 𝑌(𝐴, 𝐵, 𝐶).
𝑌 = 𝑓(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
Both the examples shown above are in product of sums form. But in first
example, even though the expression is function of three variables, first term is
containing only two variables, second term is also containing only two variables
and third term is containing only one variable.
3-5
𝑌 = (𝐴 + 𝐶). (𝐵+ 𝐶). 𝐴
We may write each such incomplete term of the above expression in
expanded form as,
(𝐴 + 𝐶) = (𝐴 + 𝐵. 𝐵̅ + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵̅ + 𝐶) (𝐵̅ + 𝐶) = (𝐴. 𝐴̅ + 𝐵̅ + 𝐶)
= (𝐴 + 𝐵̅ + 𝐶). (𝐴̅ + 𝐵̅ + 𝐶)𝐴
= (𝐴 + 𝐵. 𝐵̅) = (𝐴 + 𝐵). (𝐴 + 𝐵̅)
= (𝐴 + 𝐵 + 𝐶. 𝐶̅). (𝐴 + 𝐵̅ + 𝐶. 𝐶̅)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶̅). (𝐴 + 𝐵̅ + 𝐶). (𝐴 + 𝐵̅ + 𝐶̅)
Therefore, the expanded sum of product expression can be written as,
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴
+ 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
Expanded form of Boolean expression in which each term contains all the
Boolean variables in it is called as canonical form. It is also called as
standard product of sums form.
Example 1:
Convert following Boolean expression into standard POS form.
(𝐴 + 𝐶). (𝐵 + 𝐷)
The above expression is a function of four variables A, B, C and D.
As each term is not containing all the variables, it is not standard POS. The
terms can be expanded to make it standard POS as,
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐶). (𝐵 + 𝐷)
= (𝐴 + 𝐵. 𝐵 + 𝐶). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶 + 𝐷. 𝐷). (𝐴 + 𝐵+ 𝐶 + 𝐷. 𝐷). (𝐵 + 𝐷)
= (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵+ 𝐶 + 𝐷). (𝐴 + 𝐵+ 𝐶
+ 𝐷). (𝐵 + 𝐷)
+ 𝐷). (𝐴. 𝐴 + 𝐵 + 𝐷)
+ 𝐷). (𝐴 + 𝐵 + 𝐷). (𝐴 + 𝐵 + 𝐷)
+ 𝐷). (𝐴 + 𝐵 + 𝐶. 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶. 𝐶 + 𝐷)
+ 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶
+ 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷)
As, 𝐴. 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷) . (𝐴 + 𝐵+ 𝐶 + 𝐷). (𝐴 + 𝐵+ 𝐶
+ 𝐷) . (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷)
Example 2:
Standardize following Boolean expression.
𝑌 = (𝐴 + 𝐵)(𝐴 + 𝐶)
The above expression is a function of three variables A, B and C. As
each term is not containing all the variables, it is not standard POS. The terms
3-6
can be expanded to make it standard POS as,
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵). (𝐴 + 𝐶)
= (𝐴 + 𝐵 + 𝐶. 𝐶). (𝐴 + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵. 𝐵 + 𝐶)
= (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
As, 𝐴 + 𝐴 = 𝐴
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
Single term in standard product of sumss is called as maxterm. Each

expression can be represented using maxterms. Some examples are shown
below.
Example 1:
𝑌 = (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶). (𝐴 + 𝐵 + 𝐶)
As the above expression in standard product of sums form, all terms in it
are maxterms. They are,
𝐴+𝐵+𝐶 𝐴 + 𝐵+ 𝐶 𝐴+𝐵+𝐶
M4 M0 M
0 0 0 0 1 0 2 1 0 0
𝐴+𝐵+𝐶 𝐴+𝐵+𝐶
M1 M5
0 0 1 1 0 1
𝑌(𝐴, 𝐵, 𝐶) = ∏ 𝑀(0,1,2,4,5)
Example 2:
𝑌 = (𝐴 + 𝐵 + 𝐶 + 𝐷). (𝐴 + 𝐵 + 𝐶 + 𝐷
). (𝐴 + 𝐵+ 𝐶 + 𝐷)
As the above expression in standard product of sums form, all terms in it
are maxterms. They are,
𝐴+𝐵+𝐶 +𝐷 𝐴+𝐵+𝐶 +𝐷 𝐴 + 𝐵+ 𝐶 + 𝐷
M2 M M6
0 0 1 0 0 0 1 1 3 0 1 1 0
6
𝑌(𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀(2,3,6)
Karnaugh Map
In the last chapter, we have simplified Boolean expression using Boolean

laws. That was algebraic simplification method. In that method, it is hard to
guess whether the simplified expression is in its simplest form or not (i.e.
whether simplification is to be continued or not).This drawback has been
overcome in Karnaugh map simplification.
3-7
Karnaugh map (also called K-map) is graphical representation of a logic
system. It can be drawn from minterm or maxterm Boolean expressions.
Number of cells in a K-map depends on number of variables in the Boolean
expression. Karnaugh map of a Boolean expression with n variables contain 2 n
cells (squares). Each cell in the K-map corresponds with one input combination.
Each row and each column of K-map is assigned by 0s and 1s.
A two-variable K-map can be drawn with various possibilities. Two
possibilities are shown in figure 3.1. In these notes we will use pattern shown in
figure 3.1a.
B A
0 1 0 1
A 0 0 1 B 0 0 2
1 2 3 1 1 3
a. b.
Figure 3.1: Two ways of representing a 2-variable K-map
As discussed previously, each square (or cell) in K-map corresponds to one
input combination. In figure 3.1a, cell 0 corresponds to input combination ‘00’
(i.e. 𝐴. 𝐵), cell 1 corresponds to input combination ‘01’ (i.e. 𝐴. 𝐵), cell 2
corresponds to input combination ‘10’ (i.e. 𝐴. 𝐵) and cell 3 corresponds to input
combination ‘11’ (i.e. 𝐴. 𝐵).
A three-variable K-map can be drawn with various possibilities. Four
figure 3.2a.
BC AB
00 01 11 10 00 01 11 10
A 0 0 1 3 2 C 0 0 2 6 4
1 4 5 7 6 1 1 3 7 5
a. b.
C A
0 1 0 1
AB 00 0 1 BC 00 0 4
01 2 3 01 1 5
11 6 7 11 3 7
10 4 5 10 2 6
c. d.
Figure 3.2: Four ways of representing a 3-variable K-map
3-8
A four-variable K-map can be drawn with various possibilities. Two
figure 3.3a.
3-9
CD AB
00 01 11 10 00 01 11 10
AB 00 0 1 3 2 CD 00 0 4 12 8
01 4 5 7 6 01 1 5 13 9
11 12 13 15 14 11 3 7 15 11
10 8 9 11 10 10 2 6 14 10
a. b.
Figure 3.3: Two ways of representing a 4-variable K-map
We can represent any expression which is in standard SOP (minterms)

form or standard POS (maxterms) form in a K-map.
Representation SOP on K-map

If the given Boolean expression is not in standard SOP form, it should be
first converted to standard SOP form. Then its minterms are written. For each
minterm in the expression, ‘1’ is written in the corresponding cell in the K-map
and the remaining cells are marked as ‘0’.
Example 1:
Represent following Boolean expression by K-map.
𝑌 = 𝐵𝐶 + 𝐴̅𝐵̅𝐶̅ + 𝐴𝐵𝐶̅
The above expression is in SOP form. It is a function of three
variables A, B and C. As each term is not containing all the variables, it is not in
standard SOP form. So, converting it into standard SOP form,
𝑌(𝐴, 𝐵, 𝐶) = 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶 + 𝐴. 𝐵. 𝐶
= (𝐴 + 𝐴̅). 𝐵. 𝐶 + 𝐴̅. 𝐵̅. 𝐶̅ + 𝐴. 𝐵. 𝐶̅
𝑌(𝐴, 𝐵, 𝐶) = 𝐴. 𝐵. 𝐶 + 𝐴̅. 𝐵. 𝐶 + 𝐴̅. 𝐵̅. 𝐶̅ + 𝐴. 𝐵. 𝐶̅
111 011 000 110
m7 m3 m0 m6
𝑌(𝐴, 𝐵, 𝐶) = ∑ 𝑚(0,3,6,7)
The above minterms can be represented in K-map. All the present terms
are marked as ‘1’ and remaining cells are marked as ‘0’. As the function is of
three variables, a three-variable K-map is used for representation.
BC
00 01 11 10
A 0 0 1 1 0 3 1 2 0
1 4 0 5 0 7 1 6 1
Example 2:
Represent following expression using K-map.
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∑ 𝑚(0,1,2,5,13,15)
The above minterms can be represented in K-map. All the present
terms are marked as ‘1’ and remaining cells are marked as ‘0’. As the function is
of four-variables, a four-variable K-map is used for representation.
3-10
CD
00 01 11 10
AB 00 01 11 30 21
01 40 51 70 60
11 12 0 13 1 15 1 14 0
10 80 90 11 0 10 0
Example 3:
𝑌 = ∑ 𝑚(0,1,3)
The above minterms can be represented in K-map. All the present
terms are marked as ‘1’ and remaining cells are marked as ‘0’. As the function is
of two-variables, a two-variable K-map is used for representation.
B
0 1
A0 01 11
1 20 31
Representation POS on K-map

If the given Boolean expression is not in standard POS form, it should be
first converted to standard POS form. Then its maxterms are written. For each
maxterm in the expression, ‘0’ is written in the corresponding cell in the K-map
and the remaining cells are marked as ‘1’.
Example 1:
Represent following Boolean expression by K-map.
𝑌 = (𝐴 + 𝐵) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶)
The above expression is in POS form. It is a function of three
variables A, B and C. As each term is not containing all the variables, it is not in
standard POS form. So, converting it into standard POS form,
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶)
= (𝐴 + 𝐵 + 𝐶. 𝐶) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶)
= (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶)
𝑌(𝐴, 𝐵, 𝐶) = (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶) + (𝐴 + 𝐵 + 𝐶)
0 0 0 0 0 1 1 1 1
M0 M1 M7
𝑌(𝐴, 𝐵, 𝐶) = ∏ 𝑀(0,1,7)
The above maxterms can be represented in K-map. All the present terms
are marked as ‘0’ and remaining cells are marked as ‘1’. As the function is of
three variables, a three-variable K-map is used for representation.
BC
00 01 11 10
A 0 0 0 1 0 3 1 2 1
1 4 1 5 1 7 0 6 1
3-11
Example 2:
𝑓(𝐴, 𝐵, 𝐶, 𝐷) = ∏ 𝑀(1,3,5,7,9,11,13,15)
are marked as ‘0’ and remaining cells are marked as ‘1’. As the function is of four-
variables, a four-variable K-map is used for representation.
CD
00 01 11 10
AB 00 01 10 30 21
01 41 50 70 61
11 12 1 13 0 15 0 14 1
10 81 90 11 0 10 1
Example 3:
𝑌 = ∏ 𝑀(0,2)
are marked as ‘0’ and remaining cells are marked as ‘1’. As the function is of two-
variables, a two-variable K-map is used for representation.
B
0 1
A 0 00 11
1 20 31
Grouping of adjacent cells

K-maps are used for simplification Of Boolean expressions.
The simplification is based on grouping of the terms in adjacent cells. Important aspects
of grouping are discussed below.
- Number of cells in a group must always be a power of 2. (i.e. 1, 2, 4, 8, 16 etc.)
- Two cells are said to be adjacent if they differ in only one variable. Four cells
are said to be adjacent if they differ in two variables. Eight cells are said to be
adjacent if they differ in three variables and so on.
- If K-map is represented for a SOP, grouping is done for adjacent 1’s and if K-
map is represented for a POS, grouping is done for adjacent 0’s.
- While grouping, each cell containing ‘1’ in case of SOP (‘0’ in case of POS)
must be considered at least once.
- We should try to make minimum number of groups (i.e. each group of
maximum possible size).
- ‘Don’t care entries’ may be considered in any group.
Page No:
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DESIGN OF ADDER AND SUBTRACTOR
To design and construct half adder, full adder, half subtractor and full
subtractor circuits and verify the truth table using logic gates.
THEORY:
HALF ADDER:
A half adder has two inputs for the two bits to be added and two outputs one
from the sum ‘ S’ and other from the carry ‘ c’ into the higher adder position. Above
circuit is called as a carry signal from the addition of the less significant bits sum from
the X-OR Gate the carry out from the AND gate.
FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of input; it
consists of three inputs and two outputs. A full adder is useful to add three bits at a
time but a half adder cannot do so. In full adder sum output will be taken from X-OR
Gate, carry output will be taken from OR Gate.
HALF SUBTRACTOR:
The half subtractor is constructed using X-OR and AND Gate. The half
subtractor has two input and two outputs. The outputs are difference and borrow. The
difference can be applied using X-OR Gate, borrow output can be implemented using
an AND Gate and an inverter.
Page No:
18
FULL SUBTRACTOR:
The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full
subtractor the logic circuit should have three inputs and two outputs. The two half
subtractor put together gives a full subtractor .The first half subtractor will be C and
A B. The output will be difference output of full subtractor. The expression AB
assembles the borrow output of the half subtractor and the second term is the inverted
difference output of first X-OR.
LOGIC DIAGRAM:
HALF ADDER
TRUTH TABLE:
A B CARRY SUM
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Page No:
19
K-Map for SUM: K-Map for CARRY:
SUM = A’B + AB’ CARRY = AB
LOGIC DIAGRAM:
FULL ADDER USING TWO HALF ADDER
TRUTH TABLE:
A B C CARRY SUM
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
Page No:
20
1 1 1 1 1
K-Map for SUM: K-Map for CARRY:
SUM = A’B’C + A’BC’ + ABC’ + ABC CARRY = AB + BC + AC
LOGIC DIAGRAM:
HALF
SUBTRACTOR
TRUTH TABLE:
A B BORRO DIFFERENC
W E
0 0 0 0
0 1 1 1
1 0 0 1
1 1 0 0
Page No:
21
K-Map for DIFFERENCE: K-Map for BORROW:
DIFFERENCE = A’B + AB’ BORROW = A’B
FULL SUBTRACTOR
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
Page No:
22
TRUTH TABLE:
A B C BORRO DIFFEREN
W CE
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 1 0
1 0 0 0 1
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-Map for Difference: K-Map for Borrow:
Difference = A’B’C + A’BC’ + AB’C’ + ABC Borrow = A’B + BC + A’C
Page No:
23
DESIGN AND IMPLEMENTATION OF CODE
CONVERTOR
To design and implement 4-bit

(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter
THEORY:
The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion
circuit must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible
even though each uses different binary code.
A code converter is a circuit that makes the two systems compatible even
though each uses a different binary code. To convert from binary code to Excess-3
code, the input lines must supply the bit combination of elements as specified by code
and the output lines generate the corresponding bit combination of code. Each one of
the four maps represents one of the four outputs of the circuit as a function of the four
input variables.
Page No:
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A two-level logic diagram may be obtained directly from the Boolean
expressions derived by the maps. These are various other possibilities for a logic
diagram that implements this circuit.
LOGIC DIAGRAM:
BINARY TO GRAY CODE CONVERTOR
K-Map for G3: K-Map for G2:
G3 = B3
K-Map for G1: K-Map for G0:
TRUTH TABLE:
| Binary input | Gray code output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0
LOGIC DIAGRAM:
GRAY CODE TO BINARY CONVERTOR
TRUTH TABLE:
| Gray Code | Binary Code |
G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1
K-Map for B3: K-Map for B2:
B3 = G3
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K-Map for B1: K-Map for B0:
LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR
K-Map for E3: K-Map for E2:
E3 = B3 + B2 (B0 + B1)
Page No:
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K-Map for E1: K-Map for E0:
TRUTH TABLE:
| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1
1 0 0 1 1 1 0 0
1 0 1 0 x x x X
1 0 1 1 x x x X
1 1 0 0 x x x X
1 1 0 1 x x x X
1 1 1 0 x x x X
1 1 1 1 x x x X
Page No:
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DIGITAL ELECTRONICS LAB
EXCESS-3 TO BCD CONVERTOR:
K-Map for A: K-Map for B:
A = X1 X2 + X3 X4 X1
K-Map for C: K-Map for D:
Page No:
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DIGITAL ELECTRONICS
LAB
TRUTH TABLE:
| Excess – 3 Input | BCD Output |
B3 B2 B1 B0 G3 G2 G1 G0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
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DIGITAL ELECTRONICS
LAB
DESIGN OF 4-BIT ADDER AND

SUBTRACTOR
AIM:
To design and implement 4-bit adder and subtractor using IC 7483.
THEORY:
4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two
binary numbers. It can be constructed with full adders connected in cascade, with the
output carry from each full adder connected to the input carry of next full adder in
chain. The augends bits of ‘A’ and the addend bits of ‘B’ are designated by subscript
numbers from right to left, with subscript 0 denoting the least significant bits. The
carries are connected in chain through the full adder. The input carry to the adder is
C0 and it ripples through the full adder to the output carry C4.
4 BIT BINARY SUBTRACTOR:
The circuit for subtracting A-B consists of an adder with inverters, placed
between each data input ‘B’ and the corresponding input of full adder. The input carry
C0 must be equal to 1 when performing subtraction.
Page No:
25
DIGITAL ELECTRONICS
LAB
4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with
one common binary adder. The mode input M controls the operation. When M=0, the
circuit is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER:
Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output
sum cannot be greater than 19, the 1 in the sum being an input carry. The output of
two decimal digits must be represented in BCD and should appear in the form listed
in the columns.
ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.
PIN DIAGRAM FOR IC 7483:
Page No:
26
DIGITAL ELECTRONICS
LAB
LOGIC DIAGRAM:
2-BIT BINARY ADDER
LOGIC DIAGRAM:
4-BIT BINARY SUBTRACTOR
Page No:
27
DIGITAL ELECTRONICS
LAB
LOGIC DIAGRAM:
4- BIT BINARY ADDER/SUBTRACTOR
Page No:
28
DIGITAL ELECTRONICS
LAB
TRUTH TABLE:
LOGIC DIAGRAM:
BCD ADDER
Input Data A Input Data B Addition Subtraction
A4 A3 A2 A1 B4 B B B C S S3 S2 S1 B D4 D3 D2 D1
3 2 1 4
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1
K MAP
Page No:
29
Y = S4 (S3 + S2)
TRUTH TABLE:
BCD CARR
SUM Y
S S3 S2 S1 C
4
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 0
1 0 0 0 0
1 0 0 1 0
1 0 1 0 1
1 0 1 1 1
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
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42
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND
DEMULTIPLEXER
AIM:
To design and implement multiplexer and demultiplexer using logic gates and
study of IC 74150 and IC 74154.
THEORY:
MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a
smaller number of channels or lines. A digital multiplexer is a combinational circuit
that selects binary information from one of many input lines and directs it to a single
output line. The selection of a particular input line is controlled by a set of selection
lines. Normally there are 2n input line and n selection lines whose bit combination
determine which input is selected.
DEMULTIPLEXER:
The function of Demultiplexer is in contrast to multiplexer function. It takes
information from one line and distributes it to a given number of output lines. For this
reason, the demultiplexer is also known as a data distributor. Decoder can also be
used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all
of the AND gates. The data select lines enable only one gate at a time and the data on
the data input line will pass through the selected gate to the associated data output
line.
Page No:
43
BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S S INPUTS Y
1 0
0 0 D0 → D0 S1’
S0’
0 1 D1 → D1 S1’
S0
1 0 D2 → D2 S1
S0’
1 1 D3 → D3 S1
S0
Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1 S0
CIRCUIT DIAGRAM FOR MULTIPLEXER:
Page No:
44
TRUTH TABLE:
S1 S0 Y =
OUTPUT
0 0 D0
0 1 D1
1 0 D2
1 1 D3
BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
FUNCTION TABLE:
S1 S0 INPU
T
0 0 X → D0 = X S1’
S0’
0 1 X → D1 = X S1’ S0
1 0 X → D2 = X S1 S0’
1 1 X → D3 = X S1 S0
Y = X S1’ S0’ + X S1’ S0 + X S1 S0’ + X S1
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45
S0 TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D D1 D2 D3
0
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
LOGIC DIAGRAM FOR DEMULTIPLEXER:
Page No:
46
TRUTH TABLE:
INPUT OUTPUT
S1 S0 I/P D0 D1 D2 D3
0 0 0 0 0 0 0
0 0 1 1 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 1 0
1 1 0 0 0 0 0
1 1 1 0 0 0 1
Page No:
47
DESIGN AND IMPLEMENTATION OF ENCODER
AND DECODER
AIM:
To design and implement encoder and decoder using logic gates and study of
IC 7445 and IC 74147.
THEORY:
ENCODER:
An encoder is a digital circuit that perform inverse operation of a decoder. An
encoder has 2n input lines and n output lines. In encoder the output lines generates
the binary code corresponding to the input value. In octal to binary encoder it has
eight inputs, one for each octal digit and three output that generate the corresponding
binary code. In encoder it is assumed that only one input has a value of one at any
given time otherwise the circuit is meaningless. It has an ambiguila that when
all inputs are zero the outputs are zero. The zero outputs can also be generated when
D0 = 1.
DECODER:
A decoder is a multiple input multiple output logic circuit which converts coded
input into coded output where input and output codes are different. The input code
generally has fewer bits than the output code. Each input code word produces a
different output code word i.e there is one to one mapping can be expressed in truth
table. In the block diagram of decoder circuit the encoded information is present as n
input producing 2n possible outputs. 2n output values are from 0 through out 2n – 1.
Page No:
48
PIN DIAGRAM FOR IC
7445: BCD TO DECIMAL
DECODER:
Page No:
49
LOGIC DIAGRAM FOR ENCODER:
Page No:
50
TRUTH TABLE:
INPUT OUTPUT
Y1 Y2 Y3 Y4 Y5 Y6 Y7 A B C
1 0 0 0 0 0 0 0 0 1
0 1 0 0 0 0 0 0 1 0
0 0 1 0 0 0 0 0 1 1
0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 1 1 1 1
LOGIC DIAGRAM FOR DECODER:
4-
51
TRUTH TABLE:
INPU OUTPU
T T
E A B D0 D1 D2 D3
1 0 0 1 1 1 1
0 0 0 0 1 1 1
0 0 1 1 0 1 1
0 1 0 1 1 0 1
0 1 1 1 1 1 0
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52
Chapter 4. SequentiAl Logic Circuits
4.1 Introduction to Sequential Logic circuit

16 Hours 18 Marks
Logic circuits discussed previously were combinational circuits. In those

circuits output depends only on the current input combination. But in sequential
logic circuits, output of circuit depends on current input as well as past
input or past output. For achieving this, sequential logic circuits contain
memory element for storing past input or past output.
Questions:
1. Give any four differences between combinational (or combinatorial) and
sequential logic circuit. [4M]
2. Differentiate between combinational logic and sequential logic system.
[4M]
One-bit memory cell

Memory element just discussed above, stores data (generally one
bit data is stored per element). Snapshot of a memory is called a state.
One-bit memory cell is bi-stable. It means, it has two stable internal
states. Flip-flop is common implementation of bi-stable. Therefore flip
flop is also referred as basic memory cell.
One bit memory cell stores one bit data as 0 or 1. It can be
implemented using transistors, NAND gates or NOR gates.
R Q
S Q̄
Figure 4.1: One-bit memory cell using NAND gates
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53
Table 4.1: Truth Table for One-bit memory cell (NAND
implementation)
Input Output
S R Q Q̄
0 0 Race
(both 1)
0 1 0 1
1 0 1 0
1 1 Q Q̄
R Q
S Q̄
Figure 4.2: One-bit memory cell using NOR gates
Table 4.2: Truth Table for One-bit memory cell (NOR

implementation)
Input Output
S R Q Q̄
0 0 Q Q̄
0 1 0 1
1 0 1 0
1 1 Race (both 0)
The above one-bit memory cell is also referred as SR flip flop or RS

flip flop. S input (Set) is used for setting the flip flop (i.e. to get output as
1). R input (Reset) is used for resetting the flip flop (i.e. to get output as
0).
Questions:
3. Draw 1-bit memory cell using NAND gate. [2M]
4. Draw 1-bit memory cell using NOR gate. [2M]
5. Why a flip-flop is called a basic memory cell? [2M]
Clock signal and Triggering Methods

Clock signal is a digital signal. Which is generally fed to every
sequential circuit. A sample clock signal is drawn below.
4-
54
Level 1 (HIGH)
Positiv Negative
e Edge
Edge
Level 0 (LOW)
Figure 4.3: Clock signal

Clock signal is a digital signal which has only two levels as level 0 and
level 1. Level 0 is also referred as LOW, FALSE, negative or OFFlevel. Level
1 is also referred as HIGH, TRUE, positive or ONlevel. The edge which
changes the level from level 0 to level 1 is referred as positive edge,rising
edge, leading edge or LOW-to-HIGH edge. The edge which changes the level
from level 1 to level 0 is referred as negative edge,falling edge, trailing edge
orHIGH-to-LOW edge.
Triggering is the process of activating the circuit for generating
the output. Triggering can be broadly classified in two categories as,
- Level triggering
- Edge triggering
In level triggering, the circuit is triggered at a level. There are two

types of level triggering. If circuit gets triggered at level 1 (i.e. Circuit generates
output at level 1 of clock signal), it is called level 1 triggering,HIGH level
triggering or positive level triggering. If circuit gets triggered at level 0 (i.e.
Circuit generates output at level 0 of clock signal), it is called level 0
triggering,LOW level triggering or negative level triggering.
In edge triggering, the circuit is triggered on an edge. There are two
types of edge triggering. If circuit gets triggered on positive edge (i.e. Circuit
generates output on rising edging of clock signal), it is called positive edge
triggering or rising edge triggering. If circuit gets triggered on negative
edge (i.e. Circuit generates output on falling edge of clock signal), it is called
negative edge triggering or falling edge triggering.
Questions:
1. Draw clock signal. Explain various triggering methods. [4M]
2. Name the types of triggering that can be used for clocking a flip flop. [2M]
3. Explain positive edge triggering and negative edge triggering. [4M]
4. Enlist triggering methods and explain one of them. [4M]
5. Describe different types of triggering methods for a flip-flop. [4M]
6. Explain the types of triggering methods. [4M]
Flip flops
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55
Logic gate was the most basic building block of a combinational
circuit. In sequential circuit, flip-flop is the most basic building block.Flip
flop is a bi-stable circuit. It means, it has two stable internal states. Both
the output states Q and Q̄ are stable. Circuit remains in a particular
output state indefinitely until something is done to change it.
Various types of flip-flops are
- SR Flip flop
- JK Flip flop
- T Flip flop
- D Flip flop
SR Flip Flop or RS Flip Flop

Implementation of a SR flip flop using NAND gates is shown in
figure 4.4.
Symbol of SR flip flop is shown in figure 4.5.
S Q
Q¯
R
Figure 4.4: Implementation of SR Flip Flop using NAND

gates
S
Q
SR
Flip
R Q
Figure 4.5: Symbol of SR Flip Flop
When S=0 and R=0

As S is 0 and R is 0, after inversion one input of both NAND gates
is 1. So outputs of these NAND gates are inversion of other inputs. So
output of upper NAND gate remains Q (as inversion of Q̄) and output
of lower NAND gate remains Q̄ (as inversion of Q). So output remains
unchanged.
4-
56
When S=0 and R=1
As R is 1, after inversion one input of lower NAND gate is 0 which
results in generating output 1 for the lower NAND gate. i.e. Q̄
becomes 1. As S is 0,
after inversion one input of upper NAND gate is 1. Other input of this
NAND gate is also 1 (as Q̄ is 1). So the output of upper NAND gate i.e. Q
becomes 0. Both the outputs remain stable as 0 and 1.i.e. flip flop is
reset.
When S=1 and R=0

As S is 1,after inversion one input of upper NAND gate is 0 which
results in generating output 1 for the upper NAND gate. i.e.Q becomes 1.
As R is 0, after inversion one input of lower NAND gate is 1. Other input
of this NAND gate is
also 1 (as Qis 1). So the output of lower NAND gate i.e. Q̄ becomes 0.
Both the
outputs remain stable as 1 and 0.i.e. flip flop is set.
When S=1 and R=1

As S is 1 R is 1, after inversion one input of both NAND gates is 0.
So both the NAND gates try to generate output as 1, which is race
between Q and Q̄. This is forbidden state.
Truth table of SR flip flop is shown below.

Input Output
S R Qn+1
0 0 Qn
0 1 0
1 0 1
1 1 Forbidden
Clocked SR Flip Flop

As discussed in 4.2.2, clock is fed to every sequential circuit. So, a
clocked SR flip flop can be implemented using NAND gates as shown below.
S
1
3 Q
Clock
4 Q̄
2
R
Figure 4.6: Implementation of clocked SR Flip Flop

4-
57
Symbol of clocked SR flip flop is shown below. It is positive
triggered SR flip flop.
S
SR Q
Cl k
Flip Flop
Q̄
R
Figure 4.7: Symbol of clocked SR Flip Flop
When Clk=0, S=X and R= X

Output of NAND gates 1 and 2 are always 1 regardless of value of
S and
R. As one input of NAND gates 3 and 4 are always 1, outputs of these
NAND gates are inversion of other inputs. So output of NAND gate 3
remains Q (as inversion of Q̄) and output of NAND gate 4 remains Q̄
(as inversion of Q). So output remains unchanged regardless of values
of S and R. i.e. Flip flop is not
triggered.
When Clk=1
As one input of NAND gates 1 and 2 are always 1, outputs of these
NAND gates are inversion of other inputs. i.e. Circuit responds to
values of S and R. Here NAND gates 1 and 2 work as NOT gates.
When Clk=1, S=0 and R=0

As both S and R are 0, output of NAND gates 1 and2becomes 1.
So, one input of NAND gates 3 and 4 are always 1, outputs of these
NAND gates are inversion of other inputs. So output of NAND gate 3
remains Q (as inversion of Q̄) and output of NAND gate 4 remains Q̄ (as
inversion of Q). So output remains
unchanged.

As R is 1, output of NAND gate 2 is0. As one input of NAND gate 4
is 0, its output is 1. Therefore Q̄ becomes 1. As S is 0, output of NAND gate
1 becomes
1. So both the inputs of NAND gate 3 are 1, resulting in output as 0.
Therefore Q
becomes 0. Both the outputs remain stable as 0 and 1. i.e. flip flop is
reset.

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58
As S is 1, output of NAND gate 1 is 0. As one input of NAND gate
3 is 0, its output is 1. Therefore Q becomes 1. As R is 0, output of NAND
gate 2 becomes 1. So both the inputs of NAND gate 4 are 1, resulting
in output as 0.
Therefore Q̄ becomes 0. Both the outputs remain stable as 1 and 0. i.e. flip
flop is
set.

As S is 1, output of NAND gate 1 is 0. As one input of NAND gate
3 is 0, its output is 1. Therefore Q becomes 1. As R is 1, output of NAND
gate 2 is 0. As one input of NAND gate 4 is 0, its output is 1. Therefore Q̄
becomes 1. Here both Q and Q̄ tries to become 1. That there is a
race between Qand Q̄. This is forbidden state.
Truth table of clocked (positive level triggered) SR flip flop is shown

Table
4.3: Truth Table for clocked SR Flip Flop

Input Output
Clk S R Qn+1
0 X X No change
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Forbidden
Clocked SR Flip Flop with Preset and Clear inputs

Flip flops generally have two additional inputs as Preset and
Clear. Preset input is used to preset the flip flop to 1. i.e. Q to 1.Whereas
clear input is used to clear the flip flop to 0. i.e. Q to 0. Both the Preset
and Clear inputs are active low (i.e. active when low). Aclocked SR
flip flop with preset and clear inputs can be implemented using
NAND gates as shown below.
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59
Preset
S
1 3 Q
Clock
2 4 Q̄
R
Clear
Figure 4.8: Implementation of clocked SR Flip Flop with Preset &
Clear
Symbol of clocked SR flip flop with Preset and Clear inputs is

. shown below
Pr
4-
60
S
SR Q
Clk
Flip Flop
Q̄
R
Cr
Figure 4.9: Symbol of clocked SR Flip Flop with Preset &
Clear
When Pr=0, Cr=0, Clk=X, S=X and R= X

As Pr is 0, one of the input of NAND gate 3 becomes 0. So output
of NAND gate 3 becomes 1. i.e. Q becomes 1 regardless of all other
inputs. As Cr is 0, one of the input of NAND gate 4 becomes 0. So
output of NAND gate 4
becomes 1. i.e. Q̄becomes 1 regardless of all other inputs. This should
never
happen. So this input combination is not allowed.
As Pr is 0, one of the input of NAND gate 3 becomes 0. So
output of NAND gate 3 becomes 1. i.e. Q becomes 1 regardless of all
other inputs. So flip flop is preset. Here Q̄ becomes 0.

As Cr is 0, one of the input of NAND gate 4 becomes 0. So output
of NAND gate 4 becomes 1. i.e. Q̄becomes 1 regardless of all other
inputs. Here Q becomes 0. So flip flop is clear.
When Pr=1, Cr=1
For the values of Pr and Cr as 1, flip flop works same as normal
clocked SR flip flop which is already discussed in 4.3.1.1.
Truth table of clocked (positive level triggered) SR flip flop with Preset and Clear
inputs is shown below.
Table 4.4: Truth Table for clocked SR Flip Flop with Pr&
Cr
Input Output
Pr Cr Clk S R Qn+1
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61
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0 Qn
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 Forbidden
SR Flip Flop with different triggering

methods
For flip flop to be triggered it should be clocked. Various types of
SR flip flops on the basis of triggering methods are
- Positive level triggered SR flip flop
- Negative level triggered SR flip flop
- Positive edge triggered SR flip flop
- Negative edge triggered SR flip flop
Symbols and truth tables of these flip flops are given below.
Pr
S
SR Q
Flip Flop
Clk
Q̄
R
Cr
Figure 4.10: Symbol of Positive level triggered SR Flip
Flop Table 4.5: Truth Table for Positive level triggered SR
Flip Flop
Input Output
Clk S R Qn+1
0 X X No change
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Forbidden
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62
Figure 4.11: Symbol of Negative level triggered SR Flip
Flop Table 4.6: Truth Table for Negative level triggered SR

Input Output
Flip Flop Qn+1
Clk S R
1 X X No change
0 0 0 Qn
0 0 1 0
0 1 0 1
0 1 1 Forbidden
Figure 4.12: Symbol of Positive edge triggered SR Flip
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63
Flop Table 4.7: Truth Table for Positive edge
triggered SR Flip Flop
Input Output
Clk S R Qn+1
Other X X No change
 0 0 Qn
 0 1 0
 1 0 1
 1 1 Forbidden
Figure 4.13: Symbol of Negative edge triggered SR Flip
Flop Table 4.8: Truth Table for Negative edge triggered SR

Input Output
Flip Flop Qn+1
Clk S R
Other X X No change
 0 0 Qn
 0 1 0
 1 0 1
 1 1 Forbidden
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64
JK Flip Flop
As seen in above discussion, in all versions of SR flip flops there is
one forbidden input combination. This is the main drawback of SR flip
flop. This limitation of SR flip flop is overcome in JK flip flop.
Implementation of JK flip flop is shown below. This implementation is
of positive level triggered JK flip flop with preset and clear inputs.
Preset
J 1 3 Q
Clock
K 2 4 Q̄
Clear
Figure 4.14: Implementation of clocked JK Flip Flop with Preset &
Clear Symbol of JK flip flop is shown below.

PRESET
J
JK Q
Cl k
Flip Flop
Q̄
K
Cr
Figure 4.15: Symbol of clocked JK Flip Flop with Preset &
Clear
Preset input, Clear input and Clock input work same as that of SR
flip flop. So they are not discussed here.
When J=0 and K=0

As J and K are 0, one input of NAND gates 1 and 2 are 0. So
outputs of these NAND gates is 1. S is 0 and R is 0, after inversion
one input of both NAND gates is 1. As preset and clear are also 1, two
inputs of NAND gates 3 and 4 are 1. So outputs of these NAND gates
are inversion of remaining input. So output of NAND gate 3 remains Q
(as inversion of Q̄) and output of NAND gate 4 remains Q̄(as inversion
4-
65
ofQ). So output remains unchanged.
When J=0 and K=1

As K is 1, two inputs (i.e. K and Clk) of NAND gate 2 are 1. So
output of this gate will be inversion of its third input which is Q. Now Q
may be either 0 or 1.
If Q is 0, output of NAND gate 2 will be1. For NAND gate 4 inputs
will be 1 (as output of NAND gate 2), 1 (Cr) and 0 (Q). So output of NAND
gate 4 will be
1. i.e. Q̄ will be 1.
If Q is 1, output of NAND gate 2 will be 0. For NAND gate 4 inputs
will be 0 (as output of NAND gate 2), 1 (Cr) and 1 (Q). So output of NAND
gate 4 will be
1. i.e. Q̄ will be 1.
So, regardless of value of Q the output of NAND gate 4 i.e. Q̄ will
be 1. As J is 0, one input of NAND gates 1 is 0. So output of NAND
gate 1 is 1.
For NAND gate 3 inputs will be 1 (as output of NAND gate 1), 1 (Pr) and 1
(Q̄).
So output of NAND gate 3 will be 0. i.e. Q will be 0.
Thus, Q remains 0 and Q̄ remains 1. Both the outputs remain stable
as 0 and 1. i.e. flip flop is reset.
When J=1 and K=0

As J is 1, two inputs (i.e. J and Clk) of NAND gate 1 are 1. So
output of this gate will be inversion of its third input which is Q̄. Now Q̄
may be either 0 or 1.
If Q̄ is 0, output of NAND gate 1 will be 1. For NAND gate 3 inputs
will be 1 (as output of NAND gate 1), 1 (Pr) and 0 (Q̄). So output of NAND
gate 3 will be
1. i.e. Q will be 1.
If Q̄ is 1, output of NAND gate 1 will be 0. For NAND gate 3 inputs
will be 0 (as output of NAND gate 1), 1 (Pr) and 1 (Q̄). So output of NAND
gate 3 will be
1. i.e. Q will be 1.
So, regardless of value of Q̄ the output of NAND gate 3 i.e. Q will be
1.
As K is 0, one input of NAND gates 2 is 0. So output of NAND gate
2 is 1. For NAND gate 4 inputs will be 1 (as output of NAND gate 1), 1
(Cr) and 1 (Q). So output of NAND gate 4 will be 0. i.e. Q̄ will be 0.
Thus, Q remains 1 and Q̄ remains 0. Both the outputs remain stable
as 1 and 0. i.e. flip flop is set.
When J=1 and K=1

As J is 1 and K is 1, the output of JK flip flop toggles between Qand
Q̄.
Truth table of JK flip flop with Preset and Clear inputs is shown
4-
66
below.
Table 4.9: Truth Table for clocked JK Flip Flop with Pr&
Cr
Input Output
Pr Cr Clk J K Qn+1
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0 Qn
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 Q̄¯n¯ (Toggle)
Race around condition in JK flip flop

JK flip flop overcomes the limitation of SR flip flop (which was
not handling the combination of S=1 and R=1). In JK flip flop, when
J=1 and K=1, the output of JK flip flop toggles between Qand Q̄. But in
case of a level
triggered JK flip flop like one seen above, it creates a problem.
Let us assume a positive level triggered JK flip flop. This flip
flop get triggered on the positive level. If J=1 and K=1, Qn+1 = Q̄n . This
output is toggled whenever clock is at HIGH level (i.e. 1). But if width of
a clock pulse is greater than propagation delay (discussed in 1.2.1.1) of
the circuit, output state at the end of HIGH level is not reliable as
illustrated in the figures4.16 and 4.17 below.
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Cloc
k
Signa
l
Output State Here, at the end of

Q when J = 1 positive level of
and K = 1 clock pulse, Q = 1
Figure 4.16: Sample (Sample 1) output pulse when J=K=1
Cloc
k
Signa
l
Output State Here, at the end of

Q when J = 1 positive level of
and K = 1 clock pulse, Q = 0
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Figure 4.17: Sample (Sample 2) output pulse when J=K=1
This uncertainty in the output state when J=K=1 is called as

race- around condition of JK flip flop. It can be avoided by
various ways as
1) Keeping the width of clock pulse smaller than propagation delay of the
circuit (difficult solution).
2) Using edge-triggered JK flip flop instead of level triggered JK flip flop.
3) Using Master-Slave JK flip flop (Discussed in 4.3.2.2).
Master Slave JK Flip Flop

For avoiding race around condition in JK flip flop, Master Slave
JK flip flop is used. The implementation of Master Slave JK flip flop
using two SR flip flops is shown in following figure.
Pr Pr
SN Sc
J
QN Qc Q
Clock
Clk Clk
Q̄¯¯N¯ Q̄¯¯c Q̄
K
RN Rc
Cr Cr
Slave SR
Master SR
Flip Flop
Flip Flop
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Figure 4.18: Master Slave JK Flip Flop using two SR Flip
Flops
Here two SR flip flops are used. First SR flip flop works as master
and second SR flip flop works as slave. Master SR flip flop controls the
operation of slave SR flip flop. A clock is provided to master flip flop and
the same clock is provided to slave flip flop but through a NOT gate.
Therefore, when master flip flop is enabled, slave flip flop is disables
and vice-a-versa. So output is not propagated immediately. Rather it is
propagated at the end of a complete clock pulse. This results in
avoidance of race around condition.
Symbol of MS JK flip flop is shown below.

Pr
J
MS JK Q
Clk
Flip Flop
Q̄
K
Cr
Figure 4.19: Symbol of MS JK Flip
Flop Truth table of MS JK flip flop is shown below.
Table 4.10: Truth Table for MS JK Flip Flop with Pr& Cr

Input Output
Pr Cr Clk J K Qn+1
0 0 Not used
0 1 X X X 1
1 0 X X X 0
1 1 0 X X No change
1 1 1 0 0 Qn
1 1 1 0 1 0
1 1 1 1 0 1
1 1 1 1 1 Q̄¯n¯ (Toggle)
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JK Flip Flop with different triggering methods
Various types of JK flip flops on the basis of triggering methods are
- Positive level triggered JK flip flop
- Negative level triggered JK flip flop
- Positive edge triggered JK flip flop
- Negative edge triggered JK flip flop
Pr
J
Q
JK
Clk F Fliplop
Q̄
K
Cr
Figure 4.20: Symbol of Positive level triggered JK Flip
Flop Table 4.11: Truth Table for Positive level triggered
JK Flip Flop
Input Output
Clk J K Qn+1
0 X X No change
1 0 0 Qn
1 0 1 0
1 1 0 1
1 1 1 Q̄¯n¯
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Pr
J
JK Q
Clk
Flip Flop
Q̄
K
Cr
Figure 4.21: Symbol of Negative level triggered JK Flip
Flop Table 4.12: Truth Table for Negative level triggered
JK Flip Flop
Input Output
Clk J K Qn+1
1 X X No change
0 0 0 Qn
0 0 1 0
0 1 0 1
0 1 1 Q̄¯n¯
Pr
J
JK Q
Clk
Flip Flop
Q̄
K
Cr
Figure 4.22: Symbol of Positive edge triggered JK Flip
Flop
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Table 4.13: Truth Table for Positive edge triggered
JK Flip Flop
Input Output
Clk J K Qn+1
Other X X No change
 0 0 Qn
 0 1 0
 1 0 1
 1 1 Q̄¯n¯
Table 4.14: Truth Table for Negative edge triggered JK Flip Flop
Input Output
Clk J K Qn+1
Other X X No change
 0 0 Qn
 0 1 0
 1 0 1
 1 1 Q̄¯n¯
T Flip Flop
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It is also called as Toggle flip flop. Its output changes its state each
time when it is triggered and T input is 1. We can implement T flip flop
using JK flip flop as shown below.
Pr
T J
Q
Clk JK
Flip Flop
Q̄
K
Cr
Figure 4.24: Implementation of T Flip Flop using JK
Flip Flop Symbol of T flip flop is shown below
Pr
T
T Q
k Flip Flop
Cl
Q̄
Cr
Figure 4.25: Symbol of T Flip
Flop Truth table of T flip flop is given below.
Table 4.15: Truth Table for T Flip Flop

Input Output
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T Qn+1
0 Qn (No change)
1 Q̄¯¯n¯ (Toggle)
D Flip Flop or Delay Flip Flop

It is also called as Delay flip flop. Its output generates the output
state same as its D input each time when it is triggered. i.e. It delays
the provided input. It is used as a memory latch for storing a bit in it.
We can implement D flip flop using SR flip flop as shown below.
Pr
D S
Q
SR
Clk
Flip Flop
Q̄
R
Cr
Figure 4.30: Implementation of D Flip Flop using SR Flip Flop
D flip can also be implemented using JK flip flop. This
implementation is shown below.
Pr
D J
Q
JK
Clk
Flip Flop
Q̄
K
Cr
Figure 4.31: Implementation of D Flip Flop using JK Flip Flop
Symbol of D flip flop is shown below
Pr
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D
D Q
Flip Flop
Clk
Q̄
Cr
Figure 4.32: Symbol of D Flip Flop
Truth table of D flip flop is given below.
Table 4.20: Truth Table for D Flip Flop

Input Output
D Qn+1
0 0
1 1
D Flip Flop with different triggering methods

Various types of D flip flops on the basis of triggering methods are
- Positive level triggered D flip flop
- Negative level triggered D flip flop
- Positive edge triggered D flip flop
- Negative edge triggered D flip flop
Pr
D
D Q
Flip Flop
Clk
Q̄
Cr
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Questions:
1. State different applications of flip-flops. [4M]
2. Explain clocked SR flip flop using NAND gate. [4M]
3. Draw clocked SR flip flop. [2M]
4. Draw logic circuit diagram of clocked RS flip flop using NAND gates and
draw the truth table. [4M]
5. Explain function of ‘preset’ and ‘clear’ inputs in Flip-flops. [4M]
6. Draw symbol and truth table of JK flip flop. [2M]
7. Draw logic diagram of JK flip flop and write its truth table. [4M]
8. State function of “Preset” and “Clear” terminals in a JK flip flop. [4M]
9. Give significance of “Preset” and “Clear” terminals in a JK flip flop. [4M]
10. Show logic circuit of JK Flip flop using NAND gates only. Explain its
working with truth table. [4M]
11. Draw neat circuit diagram of clocked JK Flip-flop using NAND gates.
Give its truth table explain race-around condition. [4M]
12. Explain race around condition with respect to JK flip flop. [4M]
13. What is race around condition? How to eliminate it? [4M]
14. What is race around condition? How can it be avoided? [4M]
15. Draw and explain master slave flip flop. [4M]
16. Draw and explain MS-JK flip flop. [4M]
17. List different types of flip flops. Draw diagram of master slave JK flip flop.
18. Convert SR flip flop into D flip flop and explain. [4M]
19. Draw symbol and truth table of negative edge triggered T flip flop and
positive edge triggered D flip flop. [2M]
20. With the help of suitable diagram explain how do you convert JK flip flop
into T flip flop and D flip flop. [4M]
21. Draw symbol and truth table of T and D flip flop. [4M]
22. Draw logic diagram of D flip flop and write its truth table. [4M]
23. Draw symbol and truth table for following flip-flops.
a. Clocked SR flip flop.
b. JK flip flop.
c. D filp flop.
d. T flip flop.
24. Draw symbol and truth table of T flip flop for negative edge triggered.
[4M]
25. Draw and explain D flip flop using SR flip flop. Also draw truth table.
[4M]
Applications of Flip flops
Flip flops have large set of applications as they are the basic
building blocks in all the sequential circuits. Major applications of Flip
flops are
- Memories (data storage)
- Counters
o Synchronous Counters
o Asynchronous Counters
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o Up Counters
o Down Counters
o Mod-N Counters
- Shift Registers
o Serial In Serial Out Shift Registers
o Serial In Parallel Out Shift Registers
o Parallel In Parallel Out Shift Registers
o Parallel In Serial Out Shift Registers
o Ring Counters
o Johnson Counters
- Delay Elements
- Frequency Division
- Data Transfer
Counters
Counter is a sequential logic circuit. It is cascaded arrangement
of more than one flip flop with or without some combinational logic
devices. It is basically used for counting applications like.
- Counting objects on conveyors.
- Counting incoming and outgoing vehicles.
- Counting numbers of papers in printing.
- Filling fixed number of tablets in a bottle.
For designing counters either JK flip flops or T flip flops are used.
While using JK flip flops, J and K inputs are to be shortened (i.e. JK
flip flop is to be used as T flip flop).
Counters can be broadly classified in two categories as
- Asynchronous Counters
- Synchronous Counters
These types are discussed later on.
Modulus of a counter
Modulus of a counter is number of different states it goes through
before coming back to initial state. i.e. number of states that a counter
counts is called as modulus of counter.
Example 1:
If a counter counts from 0 to 7 (as 0, 1, 2, 3, 4, 5, 6, 7),
then this counter has modulus 8 and it is said to be a mod-8
counter.
Example 2:
If a counter counts from 0 to 5 (as 0, 1, 2, 3, 4, 5), then this
counter has modulus 6 and it is said to be a mod-6 counter.
Asynchronous counter
Asynchronous counter is also called as ripple counter or serial
counter.In this type of counter, clock pulse is applied to only first flip
flop. Output of first flip flop drives clock input of second flip flop and so
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on. The counter is called asynchronous as the clock pulses of all the flip
flops are not same. Due to this all the flip flops do not change their
states at the same time. Second flip flop can change the state only after
change in the state of first flip flop. So these counters have high
propagation delay. Hence the operational frequency is low. Advantage
of this type of counter is that it is easy to design.
Steps for designing asynchronous counter or ripple counter

Fordesigning a n-bit asynchronous counter or ripple counter,
following steps are undertaken.
i. It requires n number of flip flops. The flip flops used may be either
JK flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops
are connected to logic 1 (or VCC) so that all the flip flops work
properly.
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or V CC). When T flip
flops are used, T inputs of all the n flip flops are connected to logic
1 (or VCC). Due to this, all the n flip flops always toggle their output
state at each trigger (i.e. output state of each flip flop gives the
negation of previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. QO) is connected to clock input of
flip flop number 1 (i.e. second flip flop). Output of second flip flop
(i.e. Q1) is connected to clock input of flip flop number 2 (i.e. third
flip flop) and so on.
v. Output of the counter is observed at QO (LSB), Q1, …, Qn–1(MSB)
which are output states of flip flops 0, 1, …, n-1 respectively.
Two bit asynchronous counter or 2-bit ripple counter

For designing 2-bit asynchronous counter (or 2-bit ripple counter
or 2-bit serial counter) 2 JK flip flops or 2 T flip flops are used.Preset
and Clear inputs (i.e. Pr and Cr inputs) of both flip flops are connected
to logic 1 (or VCC) so that both flip flops work properly. Following two
figures show design of 2-bit asynchronous counter using JK flip flop and
using T flip flop respectively. While implementing this counter using JK
flip flop, J and K inputs of both flip flops are connected to each other and
then to logic 1 (or VCC).While implementing this counter using T flip flop,
T input of both flip flops is connected to logic 1 (or VCC). So, flip flops work
in toggle mode. External clock pulse is connected to flip flop number 0 (i.e.
first flip flop). Output of first flip flop (i.e. QO) is connected to clock input of
flip flop number 1 (i.e. second flip flop).
Output of this counter is observed at QO (LSB) and Q1 (MSB) which
are output states of flip flop 0 and flip flop 1respectively.
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Following timing diagram illustrates how the flip flops in the
above designs change their state along with the external clock pulse
applied to flip flop
0. As the flip flops used are negative edge triggered, output changes on
negative edge of clock pulse.
Timing diagram
Following truth table shows the state transitions in the counter. It

shows how the counter counts from 0 (00) to 3 (11). After state 3 (11),
counter again
switches to 0 (00). i.e. it repeatedly counts as 0, 1, 2, 3, 0, 1, and so on.
Truth Table
Three bit asynchronous counter or 3-bit ripple counter

For designing 3-bit asynchronous counter (or 3-bit ripple counter or
3-bit serial counter) 3 JK flip flops or 3 T flip flops are used. Preset and
Clear inputs (i.e. Pr and Cr inputs) of all the three flip flops are connected
to logic 1 (or VCC) so that these flip flops work properly. Following two
figures show design of 3-bit asynchronous counter using JK flip flop and
using T flip flop respectively. While implementing this counter using JK
flip flop, J and K inputs of all the three flip flops are connected to each
other and then to logic 1 (or VCC). While implementing this counter using
T flip flop, T input of all the three flip flops is connected to logic 1 (or VCC).
So, flip flops work in toggle mode. External clock pulse is connected to flip
flop number 0 (i.e. first flip flop). Output of first flip flop (i.e. QO) is
connected to clock input of flip flop number 1 (i.e. second flip flop). Output
of second flip flop (i.e. Q1) is connected to clock input of flip flop number 2
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(i.e. third flip flop).
Output of this counter is observed at QO (LSB),Q1 and Q2 (MSB) which
are output states of flip flop 0, flip flop 1 and flip flop 2 respectively.
Design using JK flip flop

Design using T flip flop

Timing diagram

counter again
switches to 0 (000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7, 0, 1, and so
on.
Truth Table
Four bit asynchronous counter or 4-bit ripple counter

For designing 4-bit asynchronous counter (or 4-bit ripple counter or
4-bit serial counter) 4 JK flip flops or 4 T flip flops are used. Preset and
Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops are connected to
logic 1 (or VCC) so that these flip flops work properly. Following two figures
show design of 4-bit asynchronous counter using JK flip flop and using T
flip flop respectively. While implementing this counter using JK flip flop, J
and K inputs of all the four flip flops are connected to each other and then
to logic 1 (or VCC). While implementing this counter using T flip flop, T
input of all the four flip flops is connected to logic 1 (or VCC). So, flip flops
work in toggle mode. External clock pulse is connected to flip flop number 0
(i.e. first flip flop). Output of first flip flop (i.e. QO) is connected to clock
input of flip flop number 1 (i.e. second flip flop). Output of second flip flop
(i.e. Q1) is connected to clock input of flip flop number 2 (i.e. third flip
flop). Output of third flip flop (i.e. Q2) is connected to clock input of flip flop
number 3 (i.e. fourth flip flop).
Output of this counter is observed at QO (LSB), Q1, Q2 and Q3 (MSB)
which are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3
respectively.
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Design using JK flip flop Design using T flip flop

Timing diagram

shows how the counter counts from 0 (0000) to 15 (1111). After state 15
(1111), counter
again switches to 0 (0000). i.e. it repeatedly counts as 0, 1, 2, 3, 4, 5, 6, 7,
8, 9,
10, 11, 12, 13, 14, 15, 0, 1, and so on.
Truth Table
Steps for designing mod-N counter

Mod-N counter can also be called as mod-N asynchronous counter
or mod- N ripple counter or mod-N serial counter. For designing a mod-
N counter, following steps are undertaken.
i. Number of flip flops (i.e. n) required for designing
mod-N counter can be selected as follows. Number of
flip flops (i.e. n) should be the smallest number, for
which N ≤ 2n.
Example 1: For mod-5
counter N=5
If n=1, 2n is 2. Here, N is not less than or equal to
2n. If n=2, 2n is 4. Here, N is not less than or
equal to 2n. If n=3, 2n is 8. Here, N is less than 2n.
 3 flip flops are required for designing mod-5 counter.

counter N=10
equal to 2n. If n=3, 2n is 8. Here, N is not less
than or equal to 2n. If n=4, 2n is 16. Here, N is
less than 2n.
 4 flip flops are required for designing mod-10
counter.
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counter N=8
equal to 2n. If n=3, 2n is 8. Here, N is equal to 2n.
3 flip flops are required for designing mod-8 counter.
ii. Preset inputs (i.e. Pr input) of all the n flip flops are connected to
logic 1 (or VCC).
iii. When JK flip flops are used, J and K input of all the n flip flops are
connected to each other and then to logic 1 (or VCC). When T flip flops
are used, T inputs of all the n flip flops are connected to logic 1 (or
VCC). Due to this, all the n flip flops always toggle their output state at
each trigger (i.e. output state of each flip flop gives the negation of
previous state on trigger).
iv. External clock pulse is connected to flip flop number 0 (i.e. first flip
flop). Output of first flip flop (i.e. QO) is connected to clock input of flip
flop number 1 (i.e. second flip flop). Output of second flip flop (i.e. Q1)
is connected to clock input of flip flop number 2 (i.e. third flip flop) and
so on.
v. Calculate binary equivalent of N. Respective output
states for which the bits in the binary equivalent are 1,
are connected to inputs of NAND gate. Output of this
NAND gate is connected to Clear inputs (Cr inputs) of
all the flip flops. But if N = 2n, no need of NAND gate as
the counter is in its full form.
Example 1: For mod-6 counter
N = 6 = 110
1 1 0
Bit # 2 1 0
So outputs Q1 andQ2 are connected to inputs of NAND
gate and output of NAND gate is connected to Clear inputs
(Cr inputs) of all the 3 flip flops.

counter N = 11 = 1011
1 0 1 1
Bit # 3 2 1 0
So outputs QO,Q1 andQ3 are connected to inputs of
NAND gate and output of NAND gate is connected to Clear
inputs (Cr inputs) of all the 4 flip flops.
Example 3: For mod-4 counter

AsN = 2n, no need of NAND gate as the counter is in its
full
form.
vi. Output of the counter is observed at QO (LSB), Q1, …, Qn–1(MSB) which are
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output states of flip flops 0, 1, …, n-1 respectively.
Some examples are discussed below. But scope of the topic is not
limited to only these counters. We should be able to design any mod-N
counter by using above steps.
Mod-3 counter
It is also called mod-3 ripple counter, or mod-3 asynchronous
counter or mod 3 serial counter.
Here, N=3
If n=1, 2n is 2. Here, N is not less than or equal
to 2n. If n=2, 2n is 4. Here, N is less than 2n.
 2 flip flops are required for designing mod-3 counter.
So, 2 JK flip flops or 2 T flip flops are used. Preset input (i.e.
Prinput) of both the flip flops are connected to logic 1 (or V CC).
Following two figures show design of 2-bit asynchronous counter using
JK flip flop and using T flip flop respectively. While implementing this
counter using JK flip flop, J and K inputs of both the flip flops are
connected to each other and then to logic 1 (or VCC).
While implementing this counter using T flip flop, T input of both the flip
flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
External clock pulse is connected to flip flop number 0 (i.e. first flip flop).
Output of first flip flop (i.e. QO) is connected to clock input of flip flop
number 1 (i.e. second flip flop).
Binary equivalent of N = 3 is 11. So outputs QO andQ1 are connected
to inputs of NAND gate and output of NAND gate is connected to Clear
inputs (Cr inputs) of both flip flops. Due to this modification, 2-bit
asynchronous counter is converted into mod-3 counter.
Output of this counter is observed at QO (LSB) and Q1 (MSB) which
are output states of flip flop 0 and flip flop 1 respectively.

Timing diagram

counter is in state 3 (i.e. 11). But as QO and Q1 are 1, output of NAND
gate is 0 which immediately clears both flip flops. So instead of state 3
(i.e. 11), we get state 0 (i.e. 00). So, counter repeatedly counts as 0, 1, 2,
0, 1, 2, 0and so on.
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Truth Table
Mod-5 counter
counter or mod-5 serial counter.
Here, N=5
to 2n. If n=2, 2n is 4. Here, is not less than or
equal to 2n.
If n=3, 2n is 8. Here, N is less than 2n.
So, 3 JK flip flops or 3 T flip flops are used. Preset input (i.e. Pr
input) of all the three flip flops are connected to logic 1 (or VCC).
counter using JK flip flop, J and K inputs of all the three flip flops are
connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of all the three flip
flops is connected to logic 1 (or VCC). So, flip flops work in toggle mode.
number 1 (i.e. second flip flop) and output of second flip flop (i.e. Q1) is
connected to clock input of flip flop number 2 (i.e. third flip flop).
Binary equivalent of N = 5 is 101. So outputs QO andQ2 are connected
to inputs of NAND gate and output of NAND gate is connected to Clear
inputs (Cr inputs) of all the three flip flops. Due to this modification, 3-bit
asynchronous counter is converted into mod-5 counter.
Output of this counter is observed at QO (LSB), Q1 and Q2 (MSB)
which are output states of flip flop 0, flip flop 1 and flip flop 2
respectively.

applied to flip flop. As the flip flops used are negative edge triggered,
output changes on negative edge of clock pulse.
Timing diagram

counter is in state 5 (i.e. 101). But as QO and Q2 are 1, output of NAND gate
is 0 which immediately clears all the flip flops. So instead of state 5 (i.e.
101), we get 0 (i.e. 000). So, counter repeatedly counts as 0, 1, 2, 3, 4, 0,
1and so on.
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Truth Table
Mod-10 counter
counter or mod-10 serial counter.
Here, N=10
to 2n. If n=2, 2n is 4. Here, is not less than or
equal to 2n.
If n=3, 2n is 8. Here, is not less than or equal to
2n. If n=4, 2n is 16. Here, N is less than 2n.
So, 4 JK flip flops or 4 T flip flops are used. Preset input (i.e. Pr
input) of all the four flip flops are connected to logic 1 (or VCC).
counter using JK flip flop, J and K inputs of all the four flip flops are
connected to each other and then to logic 1 (or VCC). While implementing
this counter using T flip flop, T input of all the four flip flops is
connected to logic 1 (or VCC). So, flip flops work in toggle mode.
number 1 (i.e. second flip flop). Output of second flip flop (i.e. Q1) is
connected to clock input of flip flop number 2 (i.e. third flip flop)
andoutput of third flip flop (i.e. Q2) is connected to clock input of flip flop
number 3 (i.e. fourth flip flop).
Binary equivalent of N = 10 is 1010. So outputs Q1 andQ3 are
connected to inputs of NAND gate and output of NAND gate is connected
to Clear inputs (Cr inputs) of all the four flip flops. Due to this
modification, 4-bit asynchronous counter is converted into mod-10 counter.
Output of this counter is observed at QO (LSB), Q1,Q2and Q3(MSB)
which are output states of flip flop 0, flip flop 1, flip flop 2 and flip flop 3
respectively.

Timing diagram

shows how the counter counts from 0 (0000) to 9 (1001). After state 9
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(1001), counter is in state 10 (i.e. 1010). But as Q1 and Q3 are 1, output of
NAND gate is 0 which immediately clears all the flip flops. So instead of
state 10 (i.e. 1010), we get 0 (i.e. 0000). So, counter repeatedly counts as
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 0, 1, 2 and so on.
Synchronous counter
Synchronous counter is also called as parallel counter. In this
type of counter, same clock pulse is applied all the flip flops. The counter
is called synchronous as the clock pulses of all the flip flops are same. i.e.
all the flip flops are synchronized. Due to this, all the flip flops change
their states at the same time in synchronization with the clock pulse. So
these counters have low propagation delay. Hence the operational
frequency is high. Only drawback of this type of counter is that it is
difficult to design. Extra circuitry is required for designing these counters.
Steps for designing synchronous counter

For designing a n-bit asynchronous counter, following
steps are undertaken.
i. It requires n number of flip flops. The flip flops used may be either JK
flip flop or T flip flop.
ii. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the n flip flops are
connected to logic 1 (or VCC) so that all the flip flops work properly.
iii. External clock pulse is connected commonly to all the n flip flops.
iv. When JK flip flops are used, J and K input of first flip flop (flip flop 0)
is connected to logic 1 (or VCC). When T flip flops are used, T input
offirst flip flop (flip flop 0) is connected to logic 1 (or VCC).
v. In case of UP counter, output of flip flop 0 (i.e. QO) is connected to J
and K input of flip flop 1. Output of flip flop 1 (i.e. Q1) is connected to J
and K input of flip flop 2 and so on.
In case of DOWN counter, negated output of flip flop 0 (i.e. Q̄¯O¯) is
connected to J and K input of flip flop 1. Negated output of flip
flop 1 (i.e. Q̄¯1¯) is connected to J and K input of flip flop 2 and so
on.
vi. Output of the counter is observed at QO (LSB), Q1, …, Qn–1(MSB) which
are output states of flip flops 0, 1, …, n-1 respectively.
Two bit synchronous counter

For designing 2-bit synchronous counter 2 JK flip flops or 2 T flip
flops are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of both
flip flops are connected to logic 1 (or VCC) so thatboth the flip flops work
properly.External clock pulse is connected commonly to both the flip
flops. Following two figures show design of 2-bit synchronous counter
using JK flip flop and using T flip flop respectively. While implementing
this counter using JK flip flop, J and K inputof first flip flop is
connected to each other and then to logic 1 (or VCC).
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While implementing this counter using T flip flop, T input of first flip flops
is connected to logic 1 (or VCC).In case of UP counter, output of flip flop 0
(i.e. QO) is connected to J and K input of flip flop 1 (in case of T flip flop
implementation, QO is connected to T input of flip flop 1). Output of the
counter is observed at QO (LSB) andQ1 (MSB) which are output states of
flip flops 0 and 1respectively.

applied to them. As the flip flops used are negative edge triggered,
Timing diagram

shows how the counter counts from 0 (00) to 3 (11). So, counter
repeatedly counts as 0,
1, 2, 3, 0, 1, 2 and so on.
Truth Table
Two bit DOWN counter

It is a 2-bit synchronous DOWN counter. For designing 2-bit
synchronous DOWN counter 2 JK flip flops or 2 T flip flops are used.
Preset and Clear inputs (i.e. Pr and Cr inputs) of both flip flops are
connected to logic 1 (or VCC) so that both the flip flops work
flops. Following two figures show design of 2-bit synchronous DOWN
counter using JK flip flop and using T flip flop respectively. While
implementing this counter using JK flip flop, J and K input of first flip
flop is connected to each other and then to logic 1 (or VCC). While
implementing this
counter using T flip flop, T input of first flip flop is connected to logic 1
(or VCC). As it is DOWN counter, negated output of flip flop 0 (i.e. Q̄¯O¯) is
connected to J and K input of flip flop 1 (in case of T flip flop
implementation, Q̄¯O¯ is connected to T input of flip flop 1). Output of the
counter is observed at QO (LSB) andQ1
(MSB) which are output states of flip flops 0 and 1respectively.
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Timing diagram
Following truth table shows the state transitions in the counter. It shows
how the counter counts from 3 (11) to 0 (00). So, counter repeatedly counts
as 3,
2, 1, 0, 3, 2 and so on.
Truth Table
Three bit synchronous counter

flops are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the
three flip flops are connected to logic 1 (or VCC) so that all the flip flops
work properly.External clock pulse is connected commonly to all the flip
this counter using JK flip flop, J and K input of first flip flop is
this counter using T flip flop, T input of first flip flops is connected to
logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. QO) is
implementation, QO is connected to T input of flip flop 1). Output of flip
flop 0 (i.e. QO) and output of flip flop 1 (i.e. Q1) are connected to AND gate
whose output is connected to J and K input of flip flop 2 (in case of T flip
flop implementation, output of flip flop 0 (i.e. QO) and output of flip flop 1
(i.e. Q1) are connected to AND gate whose output is connected to T input
of flip flop 2).Output of the counter is observed at QO (LSB), Q1
andQ2(MSB) which are output states of flip flops 0, 1 and2respectively.

Timing diagram

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repeatedly counts as 7, 6, 5, 4, 3, 2, 1, 0, 7, 6, 5, 4and so on.
Truth Table
Three bit DOWN counter

Preset and Clear inputs (i.e. Pr and Cr inputs) of all the three flip flops
are connected to logic 1 (or VCC) so that all the flip flops work
flop is connected to each other and then to logic 1 (or V CC). While
implementing this counter using T flip flop, T input of first flip flop is
connected to logic 1 (or VCC). As it is DOWN counter, negated output of
flip flop 0 (i.e. Q̄¯O¯) is connected to
J and K input of flip flop 1 (in case of T flip flop implementation, Q̄¯O¯ is
connected
to T input of flip flop 1). Negated output of flip flop 0 (i.e. Q̄¯O¯) and negated
output of flip flop 1 (i.e. Q̄¯1¯) are connected to AND gate whose output is
implementation, negated output of flip flop 0 (i.e. Q̄¯O¯) and negated output
of flip flop 1 (i.e. Q̄¯1¯) are connected to AND gate whose output is
connected to T input of flip flop 2).Output of the counter is
observed at QO (LSB), Q1 andQ2(MSB) which are output states of flip flops
0, 1 and2 respectively.

Timing diagram

repeatedly counts as 7, 6, 5, 4, 3, 2, 1, 0, 7, 6 and so on.
Truth Table
Four bit synchronous counter

flops are used. Preset and Clear inputs (i.e. Pr and Cr inputs) of all the
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four flip flops are connected to logic 1 (or VCC) so that all the flip flops
work properly.External clock pulse is connected commonly to all the flip
this counter using JK flip flop, J and K input of first flip flop is
this counter using T flip flop, T input of first flip flops is connected to
logic 1 (or VCC). In case of UP counter, output of flip flop 0 (i.e. QO) is
implementation, QO is connected to T input of flip flop 1). Output of flip
flop 0 (i.e. QO) and output of flip flop 1 (i.e. Q1) are connected to AND gate
flop implementation, output of flip flop 0 (i.e. QO) and output of flip flop 1
(i.e. Q1) are connected to AND gate whose output is connected to T input
of flip flop 2).Output of flip flop 0 (i.e. QO), output of flip flop 1 (i.e. Q1) and
output of flip flop 2 (i.e. Q2) are connected to AND gate whose output is
implementation, output of flip flop 0 (i.e. QO), output of flip flop 1 (i.e. Q1)
and output of flip flop 2 (i.e. Q2) are connected to AND gate whose output
is connected to T input of flip flop 3).Output of the counter is observed at
QO(LSB), Q1,Q2 andQ3(MSB) which are output states of flip flops 0, 1, 2
and3respectively.

Timing diagram

repeatedly counts as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15,
14and so on.
Truth Table
Four bit DOWN counter

Preset and Clear inputs (i.e. Pr and Cr inputs) of all the four flip flops are
connected to logic 1 (or VCC) so that all the flip flops work
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flop is connected to each other and then to logic 1 (or VCC). While
implementing this counter using T flip flop, T input of first flip flopis
connected to logic 1 (or VCC). As it is DOWN counter, negated output of
flip flop 0 (i.e. Q̄¯O¯) is connected to J and K input of flip flop 1 (in case of T
flip flop implementation, Q̄¯O¯ is connected to T input of flip flop 1).
Negated output of flip flop 0 (i.e. Q̄¯O¯) and negated output of flip flop 1 (i.e.
Q̄¯1¯) are connected to AND gate whose output is connected to J and K
input of flip flop 2 (in case of T flip flop implementation, negated output
of flip flop 0 (i.e. Q̄¯O¯) and negated output of flip flop 1 (i.e. Q̄¯1¯) are
connected to AND gate whose output is connected to T input of flip flop
2). Negated output of flip flop 0 (i.e. Q̄¯O¯), negated output of flip flop 1 (i.e.
Q̄¯1¯) and negated output of flip flop 2 (i.e. Q̄¯2¯) are connected to AND gate
flop implementation, negated output of flip flop 0 (i.e. Q̄¯O¯), negated
output of flip flop 1 (i.e. Q̄¯1¯) and negated output of flip flop 2 (i.e. Q̄¯2¯) are
connected to AND gate whose output is connected to T input of flip flop
3).Output of the counter is observed at QO (LSB), Q1,Q2andQ3(MSB)
which are output states of flip flops 0, 1, 2 and3respectively.
Following timing diagram illustrates how the flip flops in the above
designs change their state along with the external clock pulse applied
to them. As the flip flops used are negative edge triggered, output
changes on negative edge of clock pulse.
Timing diagram

repeatedly counts as 15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0, 15, 14
and so on.
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Questions:
1. State two applications of counters. [2M]
2. List any four applications of counters. [2M]
3. Define counter and modulus of counter. [2M]
4. Explain ‘modulus of a counter’ with example. [2M]
5. What is modulus of a counter? [2M]
6. Draw logical circuit diagram of a 3 bit asynchronous counter and explain.
[4M]
7. Explain 4-bit asynchronous counter with circuit diagram and timing
diagram. [4M]
8. Design a 3-bit asynchronous counter. Draw its truth table. [4M]
9. How many flip flops are required to construct the following modulus
counter? Why? [4M]
i) -5 ii) 83 iii) 99 iv) 10
Tip: As counter is used for counting and counting is not done in
negative numbers, counter cannot count up to -5. So instead of -5
consider 5.
10. What is modulus of counter? Design a mod-3 ripple counter using a 2-bit
ripple counter. [4M]
Tip; For mod-3 ripple counter, N=3.  n=2. i.e. 2 flip flops are
used. So, it will be similar to 2-bit asynchronous counter with
little modifications (NAND gate, Clear inputs etc.)
11. Design mod-5 asynchronous counter. [4M]
12. Design a mod-5 ripple counter. [4M]
13. Design mod-6 asynchronous counter. [4M]
14. Design asynchronous mod-6 counter with its truth table. [4M]
15. Design mod-10 asynchronous counter with suitable flip-flop. [4M]
16. Design a mod-11 asynchronous counter giving the steps of design. [4M]
17. Draw mod-11 asynchronous counter using T flip flop. [4M]
18. List steps to design a ‘n’ bit synchronous up counter. [4M]
19. Explain 3-bit synchronous counter. [4M]
20. Explain 3-bit synchronous counter with logical circuit diagram and timing
diagram. [4M]
21. Explain working of 3-bit synchronous counter with circuit diagram. [4M]
22. Explain 3-bit synchronous counter with truth table and timing diagram.
[4M]
23. Design 3-bit synchronous up counter. [4M ]
24. raw mod 8 synchronous counter with timing diagram of truth table. [4M]
25. Compare between synchronous and asynchronous counter (4 points). [4M]
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Registers
Register is a sequential logic circuit. It is also cascaded
arrangement of more than one flip flop with or without some
combinational logic devices. It is also called as Shift Register. As seen
before, a single flip flop is 1-bit memory cell. So, a single flip flop is also
called as 1-bit register.It is basically used for storing and/or
transferring digital information. Applications of registers or shift
registers are
- Delay Line.
- Serial to Parallel Converter.
- Parallel to Serial Converter.
- Ring Counter.
- Twisted Ring Counter.
- Sequence Generator.
- Sequence Detector.
For designing counters either JK flip flops or D flip flops are used.
While using JK flip flops, J input is connected to K input through a NOT
gate. (i.e. JK flip flop is to be used as D flip flop).
Data can be entered or retrieved in serial or in parallel to or from
a shift register. Depending on the way how data is entered and
retrieved, shift registers can be classified as
- Serial In Serial Out (SISO) Shift Register
- Serial In Parallel Out (SIPO) Shift Register
- Parallel in Parallel Out (PIPO) Shift Register
- Parallel in Serial Out (PISO) Shift Register
.
Important design/ implementation issues for registers
While designing or implementing registers or shift registers,
following issues are important.
1. Number of flip flops used
For n-bit register or n-bit shift register, n flip flops are used.
If N is to be stored in a register (or shift register), then n flip flops

are required. Here value of n is selected in such a way that n should be
the smallest number, for which N ≤ 2n.
Example 1: For storing 35
N=35
equal to 2n. If n=3, 2n is 8. Here, N is not less
than or equal to 2n. If n=4, 2n is 16. Here, N is not
less than or equal to 2n. If n=5, 2n is 32. Here, N is
not less than or equal to 2n. If n=6, 2n is 64. Here,
N is less than 2n.
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6 flip flops are required for designing a register which can store 35.
Example 2: For storing decimal 24 N=24

If n=1, 2n is 2. Here, N is not less than or equal to 2n. If n=2, 2n is 4.
Here, N is not less than or equal to 2n. If n=3, 2n
is 8. Here, N is not less than or equal to 2n. If
n=4, 2n is 16. Here, N is not less than or equal to
5 flip flops are required for designing a register which can store decimal
24.
Example 3: For storing hexadecimal C

N=(C)16=(12)10=12
n=4, 2n is 16. Here, N is less than 2n.
4 flip flops are required for designing a register which can store
hexadecimal C.
Example 4: For storing octal 37

N=(37)8=(31)10=31
If n=1, 2 is 2. Here, N is not less than or equal to 2n. If n=2, 2n is 4.
n

5 flip flops are required for designing a register which can store octal 37.
Example 5: For storing 32 N=32

2n. If n=5, 2n is 32. Here, N is equal to 2n.
5 flip flops are required for designing a register which can store 32.
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2. Sequencing of flip flops
In the cascaded arrangement of flip flops, the flip flops are
numbered as A, B, C and so on. i.e. first flip is numbered as A,
second flip flop is numbered as B and so on. Serial input is
provided at input of flip flop A. In the truth table the columns of
output are numbered as QÆ, QB, QC and so on. Here QÆ is
considered as MSB and the last output state is considered as LSB.
(This is a major difference from counter implementation)
3. Types of flip flops used

Either JK flip flops or D flip flops are used for implementing
registers or shift registers. In both the implementations, Preset
and Clear inputs (i.e. Pr and Cr inputs) of all the flip flops are
connected to logic 1 (i.e. VCC) so that all the flip flops will work
normally.
4. JK flip flop implementation

When JK flip flops are used for implementation, serial input is
provided at J input of flip flop A(i.e. JÆ). J input of flip flop A is
connected to K input of flip flop A (i.e. KÆ) through a NOT gate. (i.e.
JK flip flop is to be used as D flip flop). Then output of flip flop A
(i.e. QÆ) is connected to J
input of flip flop B (i.e. JB ) and negated output of flip flop A (i.e. Q̄Æ ) is
connected to K input of flip flop B (i.e. KB). This is equivalent to
connecting J to K through a NOT gate. Similar connections are
made for further flip flops.
5. D flip flop implementation

When D flip flops are used for implementation, serial input is
provided at D input of flip flop A (i.e. DÆ). Then output of flip flop A
(i.e. QÆ) is connected to D input of flip flop B (i.e. DB). Similar
connections are made for further flip flops.
Four bit Serial In Serial Out (SISO) Shift Register

For designing or implementing 4-bit SISO shift register, either 4
JK flip flops or 4 D flip flops are used. Both these implementations are
shown below. The flip flops are numbered as A, B, C and D. In both
the implementations, Preset and Clear inputs (i.e. Pr and Cr inputs)
of all the four flip flops are connected to logic 1 (i.e. VCC) so that all the
flip flops will work normally. A common clock pulse is applied to all
the flip flops.
In implementation using JK flip flop, Serial Input(Xi) is provided
at J input of flip flop A (i.e. JÆ). J input of flip flop A is connected to K
input of flip flop A (i.e. KÆ) through a NOT gate. (i.e. JK flip flop is to be
used as D flip flop). Then output of flip flop A (i.e. QÆ) is connected to J
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input of flip flop B (i.e. JB)
and negated output of flip flop A (i.e. Q̄Æ ) is connected to K input of flip flop
B
(i.e. KB).Output of flip flop B (i.e. QB) is connected to J input of flip flop C
(i.e. JC) and negated output of flip flop B (i.e. Q̄B ) is connected to K input of
flip flop C (i.e. KC). Output of flip flop C (i.e. QC) is connected to J input of
flip flop D (i.e. JD) and negated output of flip flop C (i.e. Q̄C ) is connected to
K input of flip flop D (i.e. KD).
In implementation using D flip flop, Serial Input(Xi) is provided at
D input of flip flop A (i.e. DÆ). Then output of flip flop A (i.e. QÆ) is
connected to D input of flip flop B (i.e. DB). Output of flip flop B (i.e. QB) is
connected to D input of flip flop C (i.e. DC). Output of flip flop C (i.e. QC) is
connected to D input of flip flop D (i.e. DD).
Serial Output(Y) is observed at QD.
Design using D flip flop
Following truth table shows the state transitions in the register

for sample input sequence 10110. It shows how the flip flops change
their states on each clock pulse.
Truth Table

applied to them for the above sample input sequence.
Timing diagram
Four bit Serial In Parallel Out (SIPO) Shift Register

For designing or implementing 4-bit SIPO shift register, either 4
the flip flops.
In implementation using JK flip flop, Serial Input (Xi) is provided
at J input of flip flop A (i.e. JÆ). J input of flip flop A is connected to K
input of flip flop A (i.e. KÆ) through a NOT gate. (i.e. JK flip flop is to be
used as D flip flop). Then output of flip flop A (i.e. QÆ) is connected to J
input of flip flop B (i.e. JB)
and negated output of flip flop A (i.e. Q̄Æ ) is connected to K input of flip flop
B
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(i.e. KB). Output of flip flop B (i.e. QB) is connected to J input of flip flop C
(i.e. JC) and negated output of flip flop B (i.e. Q̄B ) is connected to K input of
flip flop C (i.e. KC). Output of flip flop C (i.e. QC) is connected to J input of
flip flop D (i.e. JD) and negated output of flip flop C (i.e. Q̄C ) is connected to
K input of flip flop D (i.e. KD).
In implementation using D flip flop, Serial Input (Xi) is provided
at D input of flip flop A (i.e. DÆ). Then output of flip flop A (i.e. QÆ) is
connected to D input of flip flop B (i.e. DB). Output of flip flop B (i.e. QB) is
connected to D input of flip flop C (i.e. DC). Output of flip flop C (i.e. QC) is
connected to D input of flip flop D (i.e. DD).
Parallel Output is observed at output states of all the four flip flops i.e.
QÆ, QB, QC and QD.
Following truth table shows the state transitions in the register for sample
input sequence 11001. It shows how the flip flops change their states on each
clock pulse.
Truth Table
Following timing diagram illustrates how the flip flops in the above
designs change their state along with the external clock pulse applied
to them for the above sample input sequence.
Timing diagram
Four bit Parallel In Parallel Out (PIPO) Shift Register

For designing or implementing 4-bit PIPO shift register, either 4
the flip flops.
In implementation using JK flip flop, J input of flip flop A is
connected to K input of flip flop A (i.e. KÆ) through a NOT gate. (i.e. JK
flip flop is to be used as D flip flop). Then output of flip flop A (i.e. QÆ) is
connected to J input of flip flop B (i.e. JB ) and negated output of flip flop A
(i.e. Q̄Æ ) is connected to K input of flip flop B (i.e. KB). Output of flip flop B
(i.e. QB) is connected to J input of flip flop C (i.e. JC ) and negated output of
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flip flop B (i.e. Q̄B ) is connected to K input of flip flop C (i.e. KC). Output of
flip flop C (i.e. QC) is connected to J input of flip flop D (i.e. JD ) and
negated output of flip flop C (i.e. Q̄C ) is connected to K input of flip flop D
(i.e. KD).
In implementation using D flip flop, output of flip flop A (i.e.
QÆ) is connected to D input of flip flop B (i.e. DB). Output of flip flop B
(i.e. QB) is connected to D input of flip flop C (i.e. DC). Output of flip
flop C (i.e. QC) is connected to D input of flip flop D (i.e. DD).
Parallel Input is provided at all the J inputs (or D inputs) of all
the four flip flops i.e. JÆ, JB, JC and JD (or DÆ, DB, DC and DD).
Parallel Output is observed at output states of all the four flip flops i.e.
QÆ, QB, QC and QD.
Following truth table shows the state transitions in the register

for sample input sequence 10110. It shows how the flip flops change
their states on each clock pulse.
Truth Table

applied to them for the above sample input sequence.
Timing diagram
Four bit Parallel In Serial Out (PISO) Shift Register

For designing or implementing 4-bit PISO shift register, either 4
the flip flops.
There is no separate design for Parallel in Serial Out (PISO) shift
register. Rather, this operation can be utilized from the design of
universal shift register. Universal Shift Register is a shift register that
can operate in any of the four typeswhich are SISO, SIPO, PIPO and
PISO.
Here, inputs to the flip flops are provided differently. An extra
input SHIFT/L̄¯Ō¯Ā¯D̄¯ is used. When this input is 1, SHIFT operations
takes place. i.e. Input is given serially. When this input is 0, LOAD
operation takes place. i.e.
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Input is given in parallel.
In implementation using JK flip flop, J inputs of all the flip
flopsare connected to K inputs of the same flip flops through a NOT
gates. (i.e. JK flip flops are to be used as D flip flops).
J inputs (or D inputs) are driven by output of OR gates. These OR
gates are driven by outputs of two AND gates. For each first AND gate,
one input is taken from SHIFT/L̄¯Ō¯Ā¯D̄¯input and the other input is taken
from output of
previous flip flop. In case of first flip flop this other input is taken from
Serial Input. For each second AND gate, one input is taken from
SHIFT/L̄¯Ō¯Ā¯D̄¯ input through NOT gate and the other input is taken
fromParallel InputsJÆ, JB, JC and JD (or DÆ, DB, DC and DD).
Serial Output may be observed at output of flip flop D. Parallel
Output may be observed at output of flip flops A,B, C and D (i.e.).
Then output of flip flop A (i.e. QÆ) is connected to J input of flip flop
B (i.e. JB ) and negated output of flip flop A (i.e. Q̄Æ ) is connected to K input
of flip flop B (i.e. KB). Output of flip flop B (i.e. QB) is connected to J input
of flip flop C (i.e. JC) and negated output of flip flop B (i.e. Q̄B ) is connected
to K input of flip flop C (i.e. KC). Output of flip flop C (i.e. QC) is connected
to J input of flip flop D (i.e. JD) and negated output of flip flop C (i.e. Q̄C ) is
connected to K input of flip flop D (i.e. KD).
In implementation using D flip flop, output of flip flop A (i.e.
QÆ) is connected to D input of flip flop B (i.e. DB). Output of flip flop B
(i.e. QB) is connected to D input of flip flop C (i.e. DC). Output of flip
flop C (i.e. QC) is connected to D input of flip flop D (i.e. DD).
Parallel Input is provided at all the J inputs (or D inputs) of all
the four flip flops i.e. JÆ, JB, JC and JD (or DÆ, DB, DC and DD).
Parallel Output is observed at output states of all the four flip
flops i.e.QÆ, QB, QC and QD.
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Universal Shift Register
As already discussed in 4.4.2.5, Universal Shift Register is a shift
register that can operate universally. It can take serial as well as parallel
input. Alos it can generate serial as well as parallel output. So, it can
operate in any of the four types which are Serial In Serial Out, Serial In
Parallel Out, Parallel In Parallel Out and Parallel In Serial Out.
Design or implementation of universal shift register using JK flip
flop as well as D flip flop is already shown in 4.4.2.5.
IC 7495 can be used as universal shift register.Pin diagram of this 14-
pin IC is shown in following figure. Pin 1 is used for serial input and pin
numbers 2, 3, 4 and 5 are used for parallel input. Parallel output can be
taken from pin numbers 13, 12, 11 and 10. Pin 10 (as it is output of last flip
flop. i.e. QD) is used for serial output. Pin 6 is used for selecting Mode of
operation of the IC. Pin number 9 (CLK1) is used for providing clock for
normal right shift operation and pin 8 (CLK1) is used for left-shift (or LOAD
operation. i.e. parallel input). Pin number 7 and 14 are used for providing
ground and VCC respectively.
Ring Counter
It is also called as Circulating Register. It is one of the application
of shift register. It shifts a bit within the flip flops continuously.A ring
counter is obtained from a shift register by directly feeding back the output
of the last flip- flop to the J input (or D input) of the first flip-flop.
Ring counter can be implemented using JK flip flops as well as D
flip flops. These implementations are shown in following
figuresrespectively.In J-K flip-flop implementation, outputs of the last flip-
flop (i.e. QD and Q̄D ) are respectively fed back to the J and Kinputs of the
first flip-flop (i.e. JÆ and KÆ).In D flip-flop implementation, output of the
last flip-flop (i.e. QD) is fed back to the
D input of the first flip-flop (i.e. DÆ).
Assuming that flip flop A is initially set to 1 and remaining flip flops
are set to 0, initial output of the ring counter will be 1000.With the first
clock pulse, this ‘1’ gets shifted to the second flip-flop output and the counter
output becomes 0100. Similarly, with the second and thirdclock pulses, the
counter output will become 0010 and 0001. With the fourth clock pulse, the
counteroutput will again become 1000. The count cycle repeats in the
subsequent clock pulses.
Truth table for this sample is shown below.
4-
102
Truth table
Timing diagram for the same sample is shown below.
Timing Diagram
Twisted Ring Counter

It is also called as Johnson Counter. It is one of the application of shift
register. A twisted ring counter is obtained from a shift register by directly
feeding back the negated output of the last flip-flop to the J input (or D input)
of the first flip-flop and output of the last flip flop to K input of the first flip
flop.
Twisted ring counter can be implemented using JK flip flops
as well as D flip flops. These implementations are shown in
following figures respectively. In J-K flip-flop implementation,
outputs of the last flip-flop (i.e. QDand Q̄ D ) are respectively fed back
to the K and Jinputs of the first flip-flop (i.e. JÆ and KÆ).(i.e. Q̄ D is
fed back to JÆ and QD is fed back to KÆ .In D flip-flop implementation,
negated output of the last flip-flop (i.e. Q̄ D ) is fed back to the D
input of the first flip-flop (i.e. DÆ).
Assuming that all the flip flopsare initially reset to 0, initial output of
the ring counter will be 0000. With the first clock pulse, output becomes
1000.
Similarly, with the second, thirdand fourth clock pulses, the counter output
will become 1100, 1110 and 1111. With the fifth clock pulse, the
counteroutput will again become 0111. Then on consecutive clock pulses
output will be 0011, 0001, 0000, 1000 and so on.
Truth table for this sample is shown
below. Truth table
Timing diagram for the same sample is shown
below. Timing Diagram
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103
Questions:
1. Compare counters and shift registers. [4M]
2. Give applications of shift register. [4M]
3. List different types of shift registers. [2M]
4. List different types of shift registers and draw 4-bit SISO shift register.
[4M]
5. Draw logical circuit diagram of 4-bit serial in serial out shift register.
Explain with truth table. [4M]
6. Draw and explain SISO with truth table and timing diagram. [4M][
7. Draw block diagram of SISO (Right shift mode) shift register with its
truth table and logic diagram. [4M]
8. Explain the function of 3-bit SISO with waveforms and block diagram.
[4M]
9. Draw and explain working of 4-bit SIPO shift register with truth table.
[4M]
10. Draw diagram of Serial In Parallel Out (SIPO) shift register. Also draw
timing diagram. [4M]
11. Explain 4-bit SIPO shift register with the help of block diagram, truth
table and timing diagrams. [4M]
12. Draw and describe universal shift register. [4M]
13. Draw pin diagram of universal shift register IC 7495. [2M]
14. Draw pin diagram of universal shift register IC 7495. List any two
applications of shift register. [4M]
15. Study given figure. Initial output condition is QA QB Qc = 010. Write
truth table of output QA QB Qc for 4 clock pulses. [4M]
P P P
D QÆ D QÆ D QÆ
Clk Clk Clk

Q̄¯Æ¯ Q̄¯Æ¯ Q̄¯Æ¯
C C C
Cloc
16. With the help of block diagram explain working of ring counter. [4M]
17. How many flip flops are required to build a shift register to store following
number. [4M]
i) Decimal 28 ii) Binary 6 bits iii) Octal 17 iv) Hexadecimal A
4-
104
Memories
Semiconductor memories can be classified on the basis of

various factors
- Based on principle of operation
- Based on accessing method
- Based on fabrication technology
Classification based on principle of operation

On the basis of principle of operation, semiconductor memories
can be classified as
- Read Only Memory (ROM)
- Random Access Memory (RAM)
Read Only Memory (ROM)

In this type of semiconductor memory, data can be only read from
the memory. So, data is written in ROM at the time of manufacturing
only. But, data can be read any number of times from ROM. ROM is non-
volatile memory.
i.e. Contents of ROM don’t get vanished even after power given to the
computer is switched off.
Major use of ROM is to store BIOS information and bootstrap
program.
ROM can be further classified as

- Programmable Read Only Memory (PROM)
In this type of ROM, data can be written in the memory only
once after manufacturing it. For this PROM Programmer is
required.
- Erasable Programmable Read Only Memory (EPROM)
In this type of ROM, data written in it can be erased with the
help
of ultra-violet (UV) rays. As data can be erased at any number of
times, this type of ROM can be programmed (data can be written)
at multiple times.
- Electrically Erasable Programmable Read Only Memory (EEPROM)
As erasing data from EPROM requires UV rays, it becomes
cumbersome task. So, in this type of ROM, data can be erased
electrically. It is also called as E2PROM.
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105
Random Access Memory (RAM)
In this type of semiconductor memory, data can be read from the
memory as well as written into the memory. As data can be read or written
randomly, it is called as Random Access Memory. RAM is volatile memory.
i.e. Contents of RAM get vanished when power given to the computer is
switched off.
RAM is used as main memory of computer system. It is generally used
for storing data, program instructions and intermediate data during
execution of program. Data can be read or written any number of times.
Depending on type of memory cell used, RAM can be further classified

as
- Static Random Access Memory (Static RAM)
- Dynamic Random Access Memory (Dynamic RAM)
Static RAM
Basic element used in static RAM (also referred as SRAM) is a
latch memory cell. Latch memory cell holds its contents as long as power
is provided to it. So, contents of SRAM don’t get lost until power given to
the computer is not switched off.
Speed of operation of SRAM is more as compared to dynamic RAM.
But Memory capacity of SRAM is less as compared to dynamic RAM.
Dynamic RAM
Basic element used in dynamic RAM (also referred as DRAM) is a
capacitor and MOSFET. Capacitor stores the contents as charge. But as
capacitor may get discharged contents of DRAM may get lost even if
power given to the computer is not switched off. So, refreshing of memory
is required at regular intervals (after every 5-10 ms) even if power is
connected to the computer. For this, additional refreshing circuit is
required which is major disadvantage of DRAM.
Most important advantage of this memory is its high density. i.e.
More number of bits. So, cost per bit is less. So, memory capacity of DRAM is
more as compared to SRAM whereas cost is less for DRAM as compared to
SRAM.
Speed of operation of DRAM is less as compared to SRAM.
Classification based on accessing method

On the basis of accessing method, semiconductor memories can
be classified as
- Sequential Access Memory
In this type of memory, memory is accessed (read/written)
sequentially. e.g. Fifth byte cannot be accessed directly. For
accessing fifth byte one has to go sequentially as 1st, 2nd, 3rd, 4th and
then only 5th byte can be accessed.
4-
106
So, in general speed of operation is very less.
- Random Access Memory
In this type of memory, memory can be accessed
(read/written) randomly. i.e. Any byte can be accessed at any
time regardless of its position.
So, in general speed of operation is high.
Classification based on fabrication technology

On the basis of fabrication technology, semiconductor memories
can be classified as
- Bipolar Memory
In this type of memory, memory is fabricated using
bipolar components like transistors.
- Unipolar Memory
In this type of memory, memory is fabricated using
unipolar components like MOSFETs.
Questions:
1. Give classification of different types of semiconductor memories. [2M]
2. Classify memories. Give function of each type. [4M]
3. Describe how memories can be classified. [4M]
4. State how memories can be classified on the basis of principle of operation.
[4M]
5. Give classification of different types of ROM memory. [4M]
6. Give classification of different types of semiconductor memories based on
fabrication technology. [2M]
7. Classify memories and explain ROM. [4M]
8. Compare ROM and RAM (4 points). [2M], [4M]
9. Differentiate between ROM and RAM. [4M]
10. Compare static RAM and dynamic RAM. [4M]
11. Differentiate between static and dynamic RAM. (any four points) [4M]
12. Write advantages and disadvantages of dynamic RAM. [4M]
13. State advantages and disadvantages of static RAM. [4M]
14. Give four features of dynamic RAM. [4M]
15. Explain EPROM. [4M]
16. State advantages and disadvantages of EPROM. [4M]
Distinguish between ROM, PROM, EPROM and EEPR
4-
107
SHIFT REGISTERS
4-
108
4-
109
4-
110
4-
111
Chapter 5
DATA Converters AND PLDS
16 Hours
14 Marks
When digital devices are to be interfaced with analog

devices (or vice a versa), Digital to Analog converter and
Analog to Digital converter play important role.
Give necessity of data converter. [2M]
Digital to Analog Converters (D-A Converter/ DAC)
A digital to analog converter (DAC) takes digital data as its

input and converts it into analog voltage or current that is
proportional to the weighted sum of digital inputs. Input to
a DAC is N-bit binary signal in parallel form. The analog
output voltage V0 of an N-bit DAC is generally calculated
as,
VO = K (2N–1bN–1 + 2N–2bN–2 + ⋯ + 22b2 + 2b1 + bO)
Where, K is a proportionality factor and bn is nth bit of

digital input (whose value can be either 0 or 1).
4-
112
D to A Converter Specifications
Major performance specifications of digital to analog
converters are specified below.
- Resolution
- Accuracy
- Conversion speed or Setting (or settling) time
- Dynamic range
- Linearity
- Nonlinearity and Differential nonlinearity
- Monotonocity
- Temperature Sensitivity
Resolution
Resolution of a digital to analog converter is
number of states (2n) into which the full scale range is
divided or resolved. Here ‘n’ is number of bits in the
input digital word. Higher the number of bits, better the
resolution.
8-bit DAC has 255 (i.e. 2n – 1) resolvable levels. It has
8-bit resolution.
Accuracy
Accuracy of a digital to analog converter is the
difference between actual analog output and expected
ideal output when a digital input is given.
Various sources of errors that may affect accuracy
are gain errors, offset errors and nonlinearity errors.
Conversion speed or Setting (or settling) time
Conversion speed of a digital to analog converter is
expressed in terms of its setting time. Setting time is
the time period that has elapsed for analog output to
reach its final value after change in digital input has
occurred.
General purpose digital to analog converters have
setting time in the range of microseconds whereas some4-
high-speed DACs have setting time in the range of113
nanoseconds.
Dynamic range
Dynamic range of a digital to analog converter is
ratio of the largest output to the smallest output
(excluding zero). It is expressed in dB.
Linearity
In DAC, equal increment in digital input should
result in equal increment in the analog output voltage.
Linearity of DAC is a measure of the precision with
which linear input output relationship is satisfied.
Nonlinearity and Differential nonlinearity

Nonlinearity of a digital to analog converter is
maximum deviation of analog output voltage from a
straight line drawn between end-points in terms of
LSBs.
Differential nonlinearity is the worst-case deviation
of any adjacent analog outputs from the ideal one-LSB
step size.
Monotonocity
In ideal digital to analog converter, analog output
should increase by identical step size for every one LSB
increase in digital input. In such case DAC is said to be
having perfect monotonocity.
Temperature Sensitivity
Analog output voltage for any fixed digital input
varies with temperature. This is called as temperature
sensitivity. This is due to temperature sensitivity of
voltage source, resistors, OP-AMPs and other
components.
4-
114
Questions:
1. State DAC specifications (any four). [4M]
2. State 2 specifications of DAC. [2M]
3. Define specifications of DAC (Any 4). [4M]
4. Define resolution and accuracy with respect to D-A converter.
[4M]
5. What are important specifications of DAC (Write any 4). [4M]
6. Define following with respect to DAC. [2M]
i) Resolution ii) Setting time
Types of Digital to Analog Converters (DAC)

There are various types of digital to analog
converts. Two of them are discussed below. They are,
- Weighted resistor DAC
- R-2R ladder DAC
Binary Weighted Resistor D/A Converter
The binary weighted resistor DAC uses an op-amp to sum n binary
weighted currents derived from a reference voltage VR via current
scaling resistors 2R, 4R, 8R ….. 2nR. This circuit arrangement is
shown in the figure.
4-
115
Switch positions are controlled by the digital inputs. When digital input
is logic 1, it connects the corresponding resistance to the reference
voltage V R; otherwise, it leaves resistor open. Hence,
Here, operational amplifier is used as a summing amplifier. Due to high

input impedance of op- amp, summing current will flow through Rf.
Hence the total current through R f can be given be
4-
116
R-2R Ladder D/A Converter
R/2R ladder D/A converter uses only two resistor values.

This avoids resistance spread drawback of binary
weighted D/A converter. Fig.4.13 shows R/2R ladder
DAC. Like binary weighted resistor DAC, it also uses
4-
117
shunt resistors to generate n binary weighted currents;
however it uses voltage scaling and identical resistors
instead of resistor scaling and common voltage reference
used in binary weighted resistor DAC. Voltage scaling
requires an additional set of voltage dropping series
resistances between adjacent nodes, as shown in the
figure.
Here, each bit of the binary word connects the

corresponding switch either to ground or to the inverting
input terminal of the op-amp which is at the virtual
ground. Since both the positions of switches are at
ground potential, the current flowing through resistances
is constant and it is independent of switch position.
These currents can be given as
4-
118
4-
119
The inverting R/2R ladder DAC works on the principle of summing
currents and it is also said to operate in the current mode. An important advantage
of the current mode is that all ladder node voltages remain constant with
changing input codes, thus avoiding any shutdown effects by stray capacitances.
Problem: Suggest the values of resistors and reference voltage if resolution

required is 0.5 V for 4 bit R/2R ladder type DAC.
4-
120
Advantages of R-2R ladder DACs:
1. Easier to build accurately as only two precision metal film resistors are
required.
2. Number of bits can be expanded by adding more sections of same
R/2R values.
3. In inverted R/2R ladder DAC, node voltages remain constant with
changing input binary words. This avoids any slowdown effects by
stray capacitances.
Analog to digital converter (ADC)
DEFINITION :
 An electronic integrated circuit which transforms a signal from
analog(continues) to digital(discrete) form.
 Analog signals are directly measurable quantities.

Digital signals only have two states for digital computer we
refer to binary states, 0 and 1.
Types of analog to digital converter –
There are many different types of analog to digital converters:

a. Counter type or Digital-Ramp or Dual slope
b. Successive approximation
c. Flash type ( Parallel converters )
a. Counter type

One of the simplest types of analog to digital converter is counter type
ADC.
Also known as Counter-Ramp or Digital Ramp ADC.
121
The Dual Slope ADC functions in this manner:
When an analog value is applied the capacitor begins to charge in a
linear manner and the oscillator passes to the counter.
The counter continues to count until it reaches a predetermined
value. Once this value is reached the count stops and the counter is
reset.
The control logic switches the input to the first comparator to a
reference voltage, providing a discharge path for the capacitor.
As the capacitor discharges the counter counts.
When the capacitor voltage reaches the reference voltage the
count stops and the value is stored in the register.
Examples of A/D Applications
• Microphones - take your voice varying pressure waves in the air

and convert them into varying electrical signals
• Strain Gages - determines the amount of strain (change in

dimensions) when a stress is applied
• Thermocouple – temperature measuring device converts thermal

energy to electric energy
• Voltmeters
• Digital Multimeters
122
123
b. Successive Approximation ADC


The successive-approximation converter shown in Figure operates by
approximating the analogue input signal with a binary code.
This binary code is successively revising by changing each bit in the code
until the best approximation is achieved.
At each step in the approximation, the present estimate of the binary value
corresponding to the analogue input signal is saved in the successive
approximation register.
The contents of this register are converted to an analogue signal by a DAC so
that a single comparator can determine whether the approximation is larger or
smaller than the input signal.
As shown in Figure the first approximation sets the most significant bit, the
MSB, of the successive approximation register and resets all the other bits (i.e.
makes them zero).
If the DAC output (which is therefore equal, at this point, to half full-scale) is
smaller than the analogue input, the MSB is left on; if the DAC output is too
large, then the MSB is turned off.
In the next clock cycle, the next most significant bit is set (i.e. at the DAC
output is now equal to either 3/4 or 1/4 of full-scale, depending on whether the
most significant bit was left on or not) and this new approximation is compared
with the analogue input.
124
Each successive bit is similarly tested.
After the least significant bit has been tested, the conversion is complete and
the output register contains the binary code.
Programmable Logic Devices (PLAS)

Definitions
PLDS are also known as “Field Programmable Logic Device (FPLD)”
An integrated circuit chip that can be configured by the user to
implement different digital hardware.
Purpose of PLDs --
Permits elaborate digital logic designs to be implemented by the user on
a single device.
Is capable of being erased and reprogrammed with a new design.
Advantages of PLDs
Cost effective in lower volumes
Short design time
Programmability
Re-programmability
PLDs can be reprogrammed without being removed from the circuit board.
Low cost of design
Immediate hardware implementation
PLDs are often used for address decoding, where they have several
clear advantages over the 7400-series TTL parts that they replaced: One
chip requires less board area, power, and wiring than several do. The
design inside the chip is flexible, so a change in the logic does not
require any rewiring of the board. Rather, simply replacing one PLD with
another part that has been programmed with the new design can alter the decoding
logic.
Types of PLDs
SPLDs (Simple Programmable Logic Devices)
– ROM (Read-Only Memory)

– PLA (Programmable Logic Array)
125
– PAL (Programmable Array Logic)
– GAL (Generic Array Logic)
Simple Programmable Logic

Devices (SPLDs)
Simple programmable logic devices (SPLD) are the simplest, smallest
and least-expensive forms of programmable logic devices. SPLDs can be
used in boards to replace 7400-series TTL components (AND, OR, and
NOT gates).
Most SPLDs use either fuses or non-volatile memory cells (EPROM,
EEPROM, FLASH, and others) to define the functionality.
Programmable Logic Arrays (PLAS)

A programmable logic array (PLA) is a kind of programmable
logic device used to implement combinational logic circuits.
The PLA has a set of programmable AND gate planes, which link to a
set of programmable OR gate planes, which can then be conditionally
complemented to produce an output.
Programmable Logic Array or PLA is used to implement logic functions
in digital circuits. The structure has programmable AND- matrix,
programmable OR-matrix, input and output buffers. Block diagram of a
PLA device is as shown below;
126
PLD Configuration
Combination of a logic device and memory
Memory stores the pattern the PLD was
programmed with
– EPROM
• Non-volatile and reprogrammable
– EEPROM
• Non-volatile and reprogrammable
– Static RAM (SRAM)

• Volatile memory
– Flash memory
• Non-volatile memory
Complex Programmable Logic Device (CPLD)
Introduction:
 A CPLD (complex programmable logic device) chip includes
several circuit blocks on a single chip with inside wiring resources
to attach the circuit blocks. Each circuit block is comparable to a
PLA or a PAL. These chips are inadequate to fairly modest sizes,
normally supporting a mutual number of inputs and outputs of not
more than 32. For designing of these circuits that need more
inputs and outputs, either numerous PLAs/ PALs can be employed
or else a more classy type of chip can be used called a CPLD.
What is a Complex Programmable Logic Device?

 The acronym of the CPLD is “Complex programmable logic
devices.
127
 it is a one kind of integrated circuit that application designers
design to implement digital hardware like mobile phones.
 These can handle knowingly higher designs than SPLDs (simple
programmable logic devices).
 But It offer less logic than FPGAs (field programmable gate
arrays).
 CPLDs include numerous logic blocks.
 Each of the blocks includes 8-16 macrocells.
 Every logic block executes a specific function.
 All of the macrocells in a logic block are fully connected.
 Depending upon the use, these blocks may or may not be
connected to one another.
 Most CPLDs have macrocells with a sum of logic function and an
elective flip-flop.
 Depending on the chip, the combinatorial logic function supports
from 4 to 16 product terms
 CPLDs also differ in terms of shift registers and logic gates.
 Due to this reason, CPLDs with a huge number of logic gates may
be used instead of FPGAs.
 Another CPLD specification signifies the number of product terms
that a macrocell can accomplish.
 Product terms are the product of digital signals that execute a
specific logic function.
 CPLDs are available in several IC package forms and logic
families.
128
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PRAVIN PATIL COLLEGE OF DIPLOMA

ENGINEERING AND TECHNOLOGY

SUBJECT – DIGITAL TECHNIQUES

CLASS – CO3IA/B/ EJ3I

MRS. PRACHI KALPANDE

Basics of Digital Techniques

Modern digital computers, mobile communication systems, Internet etc.

Digital Signal and Digital Systems

Figure 1.1: Sample analog signal

Figure 1.2: Sample digital signal

Advantages of Digital Systems

Disadvantages of Digital Systems

Applications of Digital Systems

For producing different types of digital integrated circuits (ICs) different

There is variety of logic families. Selection of a logic

Figure 1.5: Computation of tpLH and tpHL

Current and Voltage Parameters

Fan–in is the number of inputs to a gate. For a two-input gate,

Power Supply Requirements

Classification of Logic Families

Figure 1.7: Classification of Logic Families

Transistor–Transistor Logic (TTL) Family

Emitter–Coupled Logic (ECL) Family

Complementary Metal Oxide Semiconductor (CMOS) Family

In a number system there is an ordered set of symbols (digits) with rules

Integer part Radix Point Fractional part

Decimal Number System

Binary Number System

Table 1.1: Units in Binary number system

Advantages of Binary Number System

Octal Number System

Hexadecimal Number System

Advantages of Hexadecimal Number System

Conversion of Number Systems

Binary to Decimal conversion

Octal to Decimal conversion

Hexadecimal to Decimal conversion

Decimal to Binary conversion

Decimal to Octal conversion

Decimal to Hexadecimal conversion

Converting the integer part (293)10:

Octal to Binary and Binary to Octal conversion

Table 1.3: hexadecimal Digits and their binary equivalents

For converting a binary

Hexadecimal to Octal and Octal to Hexadecimal conversion

Therefore,(1𝐴. 4)16 = (032.20)8 = (32.2)8

Therefore, (12𝐷. 58)16 = (0455.260)8 = (455.26)8

For converting octal number into its hexadecimal equivalent, two

Then the binary number is converted into its hexadecimal equivalent

Therefore,(56.03)8 = (2𝐸. 0𝐶)16

Therefore,(237.41)8 = (09𝐹. 84)16 = (9𝐹. 84)16

Number Representation in Binary

Sign-Bit Magnitude Representation

Using sign-bit magnitude binary representation, when eight bits are

One’s (1’s) Complement Representation

In step 1, +53 is represented as,

In step 1, +33 is represented as,

Two’s (2’s) Complement Representation