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1.1 INTRODUCTION:
Electronic systems usually deal with information. Representation of information is called a signal.
Signal in electronics is generally in form of voltage or current. Value of a signal is proportional to
some physical quantity and it gives information about it. For example, temperature represented in
terms of voltage signal.
There are two types of signals which are different in terms of their characteristics with respect to
time and value.
1. Analog Signals
2. Digital Signals
A signal whose value is defined at all instances of time is called continuous time signal. On the other
hand signal whose values are defined only at discrete instances of time is called discrete time signal.
Most of the signals that occur in nature are analog in form. A discrete time signal can be obtained
from continuous time signal by process called sampling. This has been illustrated in Fig. 1.1.
Fig. 1.1: (a) Continuous time signal x(t) sampled at every T interval, (b) Resulting discrete time signal x(n)
Similarly if a signal can take any value in a given range between some minimum and maximum value
then the signal is called continuous value signal. On the other hand if a signal takes only certain fixed
values in a given range then it is called discrete value signal. The process of converting a continuous
value signal to a discrete value signal is called quantization. This is illustrated in Fig. 1.2.
Fig. 1.2: Continuous value signal (solid line) and discrete value signal (dotted line)
Analog signal: Signals that are continuous in time and continuous in value are called analog signal.
Digital signal: Signals that are discrete in time and discrete in values are called digital signals. Digital
signals are generally processed by digital systems like computers and hence their values are represented
in terms of binary as shown in Fig. 1.2.
Analog signal being continuous in time will have infinite values in any given period of time. Practically
a digital system like computer cannot handle infinite values due to limited physical resources and
processing power. This is the reason why a continuous time signal has to be sampled and converted
to discrete time signal.
Again analog signals are continuous in value and hence can take any value in a given range. Now
ideally number of values in any given range will be infinite which cannot be represented by finite
number of bits on a computer. For example, as shown in Fig. 1.2, with three bits used for representing
values only eight different values can be represented. Thus a continuous value signal has to be
quantized and converted to discrete value signal.
Digital electronic circuits have become increasingly popular and successful due to integrated circuit
(IC) technology. Advancement in IC technology has made it possible to construct large number of
devices (eg. transistor, diode, resistors, capacitors, etc) on a very small chip. Classification of IC
technology based on number of components per chip is as follows.
A digital system uses a building blocks approach. Many small operational units are interconnected
to make up the overall system.
The most basic logical unit system is gate circuit. There are several different types of gates with each
perform differently from other logic gates.
Digital signal consist of only two values, ‘0’ and ‘1’. These two values have logical meaning i.e. ‘1’
represents the existence of particular condition and ‘0’ represents the absence of condition.
1. Truth Table:
Truth table plots inputs and outputs in terms of 1s and 0s.
2. Function Table:
Function table plots inputs and outputs in term of HIGH and LOW voltage levels.
The design of digital system may be roughly divided into three stages;
1. System Design:
It involves breaking the overall system into subsystem and specifying the characteristics of each
subsystem. For example, the system design of a digital computers involves specifying the number
and type of memory, ALU and i/p – o/p devices.
2. Logic Design:
It involves how to interconnect basic logic building blocks to perform specific function. For
example, to make a flip flop different logic gates are needs to be connected in specific manner.
3. Circuit Design:
It involves specifying the interconnection of specific components like resistors, transistors,
diodes, CMOS etc. to create a logic gates.
Digital system use the binary number system. Therefore, two-state devices are used to represent
the two binary digits 1s & 0s by two different voltage levels, called HIGH and LOW.
Normally, the binary 0 and 1 are represented by the logic voltage levels 0 V and +5 V.
Usually any voltage between 0 V to 0.8 V represents the logic 0 and any voltage between 2 V to 5 V
represents the logic 1. This voltage levels can be varies according to the different logical systems.
There are three types of logics available in digital systems.
1. Positive Logic
2. Negative Logic
3. Mixed Logic
1. Positive Logic:
In positive logic high voltage level is represent as logic 1 and low voltage level is represent as logic 0.
High (1)
Leading Edge Trailing Edge
Low (0)
Fig. 1.3: Illustration of positive logic
2. Negative Logic:
In positive logic high voltage level is represent as logic 0 and low voltage level is represent as logic 1.
High (0)
Low (1)
3. Mixed Logic:
This scheme uses positive logic in some portions (e.g inputs) of the system while applying negative
logic (e.g. outputs) in other portion of the system.
Suppose some function X = AB’ + A’B for this function the representation of all the logics are as
follow;
A
B’
X
A’
B
Truth table of the given function for all the logics is shown as follow;
Table 1.1: Truth table of Positive logic, Negative logic, Mixed logic for X = AB’ + A’B
Number system is the basis for counting various items. On hearing the word ‘number’, we
immediately think of the familiar decimal number system with 10 digits 0 to 9. But modern
computers communicate and operate with binary numbers which use only 2 digits 0 & 1. Also
different types of number systems like octal and hexadecimal are also used widely. Depending upon
the type of number system, we use different digits to represent various numbers.
(ii) Digit
Each symbol in the number system is called a Digit.
(iii) The largest value of a digit is always one less than the base
For ex, in decimal system, the largest digit is 9 (since base is 10)
(iv) Each digit position (i.e. place) represents a different multiple of base
This means that the numbers have positional importance. Hence the number systems are known
as Positional Weighted Number System. It means that the value attached to a symbol depends
on its location with respect to the decimal point.
For example decimal number 123.4 (base 10) can actually be represented as;
Where;
r is the base and Di is any valid digit in the number system of base r.
The digits on the left side of the decimal point form the integer part of a number and those on the
right side form the fractional part.
The left most digit in any number representation, which has the greatest positional weight out of all
the digits present in that number is called the most significant digit (MSD).
The right most digit in any number representation, which has the least positional weight out of all
the digits present in that number is called the least significant digit (LSD).
Different number systems are used in various applications. The commonly used number systems
along with their base, 1st digit, last digit and available digits are as shown below:
Sr. Number System Base First digit Last digit All digits
No
1 Binary 2 0 1 0,1
2 Octal 8 0 7 0,1,2,3,4,5,6,7
3 Decimal 10 0 9 0,1,2,3,4,5,6,7,8,9
4 Hexadecimal 16 0 F 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F
Note: In hexadecimal number system, meaning of A≈10, B≈11, C≈12, D≈13, E≈14 & F≈15.
Decimal number system is the most familiar no. system used in day-to-day life. The decimal system
consists of 10 unique symbols. Hence the base or radix is 10. It is a positional weighted system. In
this system, any number (integer, fraction or mixed) of any magnitude can be represented by the use
of these ten symbols only.
The digits on the left side of the decimal point form the integer part of a decimal number while those
on right side from the fractional part. The digits on the right of the decimal point have weights which
are negative powers of 10 and the digits to the left of the decimal point have weights which are
positive powers of 10. The sum of all the digits multiplied by their weights gives the total number
being represented.
is given by
(dn x 10n) + (dn-1 x 10n-1) + . . . + (d1 x 101) + (d0 x 100) + (d-1 x 10-1) + . . + (d-k x 10-k)
MSD .... 103 102 101 100 10-1 10-2 10-3 . . . . LSD
RADIX POINT
Fig. 1.6: Decimal position values as power of 10
The binary number system is a positional weighted system. The base or radix of this number system
is 2. Hence, it has two independent symbols. The base itself cannot be a symbol. The symbols used
are 0 & 1. A binary digit is called a bit. A binary number consists of a sequence of bits, each of which
is either a 0 or a 1. The binary point separates the integer and fraction part. The weight of each bit
position is one power of 2 greater than the weight of the position to its immediate right. The place
values left on the binary point in binary are 64, 32, 16, 8, 4, 2 and 1.
is given by
(bn x 2n) + (bn-1 x 2n-1) + . . . + (b1 x 21) + (b0 x 20) + (b-1 x 2-1) + . . + (b-k x 2-k)
RADIX POINT
Fig. 1.7: Binary position values as power of 2
Counting in Binary
Counting in binary is very similar to decimal counting. Start counting with 0, the next count is 1.
Moving ahead, we put 1 in the column to the left and continue the counting. Thus, 11 is the maximum
we can count using two bits. Similarly, we can continue counting with 5, 6, ... bits.
Applications
The binary number system is used in digital computers because the switching circuits used in these
computers use two-state devices such as transistors, diodes, etc. These devices have to exist in one
of the two possible states: ON of OFF, OPEN or CLOSED. So, these two states can be represented by
the symbols 0 and 1, respectively.
The octal number system was extensively used by early minicomputers. It is also a positional
weighted system. Its base or radix is 8. It has 8 independent symbols 0 to 7.
Since its base 8 = 23, every 3-bit group of binary can be represented by an octal digit. An octal number
is, thus 1/3 rd. the length of the corresponding binary number.
RADIX POINT
Fig. 1.8: Octal position values as power of 8
In computer work, binary numbers up to 64 bits are not uncommon. These binary numbers do not
always represent a numerical quantity; they often represent some type of code. While dealing with
large binary numbers, it is convenient and more efficient for us to write the numbers in octal rather
than binary. The ease with which conversions can be made between octal and binary makes the octal
system more attractive as a shorthand means of expressing large binary numbers.
Binary numbers are too long. These numbers are fine for machines butt are too lengthy to be handled
by human beings. So, there is a need to represent the binary numbers concisely. One number system
developed with this objective is the hexadecimal number system (or Hex). Although it is somewhat
difficult to interpret than the octal number system, it has become the most popular means of direct
data entry and retrieval in digital systems.
The hexadecimal number system is positional weighted system. The base or radix is 16 that means,
it has 16 independent symbols. The symbols used are 0 to 9 and A to F. since its base is 16 = 24, every
4 bit binary digit combination can be represented by one hexadecimal digit. So, a hexadecimal
number is ¼ th the length of the corresponding binary number.
A 4-bit group is called a nibble. Since computer words come in 8, 16, 32 bits and so on, they can be
easily represented in hexadecimal. The hexadecimal number system is particularly used for human
communications with computers. It is used in both large and small computers.
MSD .... 163 162 161 160 16-1 16-2 16-3 . . . LSD
RADIX POINT
Fig. 1.9: Hexadecimal position values as power of 16
10 A 31 1F
11 B 32 20
12 C 33 21
13 D 34 22
14 E 35 23
15 F 36 24
16 10 37 25
17 11 38 26
18 12 39 27
19 13 40 28
20 14 41 29
The human beings use decimal number system while computer uses binary number system.
Therefore, it is essential to convert decimal number into its equivalent binary while feeding number
into computer and to convert binary number into its decimal equivalent while displaying result of
operation to the human beings.
However, dealing with a large quantity of binary numbers of many bits is inconvenient for human
beings. Therefore, octal and hexadecimal numbers are used as a shorthand means of expressing large
binary numbers. Hence inter conversion among different number systems is required.
The below table shows the decimal, binary, octal and hexadecimal numbers.
9 1001 11 9
10 1010 12 A
11 1011 13 B
12 1100 14 C
13 1101 15 D
14 1110 16 E
15 1111 17 F
Binary numbers can be converted to their decimal equivalents by the positional weights method. In
this method, each binary digit of the number is multiplied by its position weight and the product
terms are added to obtain the decimal number.
Solution:
Positional weights are: 24 23 22 21 20
1 0 1 0 1 = (1 x 24) + (0 x 23) + (1 x 22) + (0 x 21) + (1 x 20)
= 16 + 0 + 4 + 0 + 1
= 21
Hence, (10101)2 = (21)10
Solution:
Positional weights are: 24 23 22 21 20 . 2-1 2-2 2-3
1 1 0 1.1 0 1 = (1 x 24) + (1 x 23) + (0 x 22) + (1 x 21) + (1 x 20) + (1 x 2-1) + (0 x 2-2) +
(1 x 2-3)
= 16 + 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125
= 27.625
Hence, (11011.101)2 = (27.625)10
To convert an octal number to a decimal number, multiply each digit in the octal number by the
weight of its position and add all the product terms.
Solution:
Positional weights are: 83 82 81 80 . 8-1 8-2
4057.068 = (4 x 83) + (0 x 82) + (5 x 81) + (7 x 80) + (0 x 8-1) + (6 x 8-2)
= 2048 + 0 + 40 + 7 + 0 + 0.0937
= 2095.0937
Hence, (4057.06)8 = (2095.0937)10
Multiply each digit in the hex number by its position weight and add all those product terms. In this
way, we get the decimal equivalent of the hexadecimal number.
Solution:
Positional weights are: 162 161 160
5C716 = (5 x 162) + (12 x 161) + (7 x 160)
= 1280 + 192 + 7
= 147910
Hence, (5C7)16 = (1479)10
Solution:
Positional weights are: 163 162 161 160.16-1 16-2 16-3
A0F9.0EB16 = (10 x 163) + (0 x 162) + (15 x 161) + (9 x 160) + (0 x 16-1) + (14 x 16-2)
+ (11 x 16-3)
= 40960 + 0 + 240 + 9 + 0 + 0.0546 + 0.0026
= 41209.057210
Hence, (A0F9.0EB)16 = (41209.0572)10
The conversion of decimal number to binary is carried out in 2 steps. In step 1, we have to convert
integer part and in step 2, we have to convert fractional part.
For integer part conversion, we use successive division-by-2 method. In this method we repeatedly
divide the integer part of the decimal number by 2 until the quotient is zero. The remainder of each
division becomes the numeral in the new radix. The remainders are taken in the reverse order to
form a new radix number. This means that the first remainder is the LSD and the last remainder is
the MSD in the new radix number. Thus the integers read from bottom to top give the equivalent
binary fraction.
Similarly, for fractional part, we use successive multiplication-by-2 method. In this method, the
number to be converted is multiplied by the radix of new number, producing a product that has an
integer part and a fractional part. The integer part (carry) of the product becomes a numeral in the
new radix number. The fractional part is again multiplied by the radix and this process is repeated
until fractional part reaches 0 or until the new radix number is carried out to significant digits. The
integer part (carry) of each product is read from top to bottom to represent the new radix number.
Here the number is integer number so we need to divide the given decimal number by 2 and read
the remainders from bottom to top to get the equivalent binary number.
2 52 Remainder
2 26 0
2 13 0
2 6 1
2 3 0
2 1 1
0 1
Solution:
Step 1: Separate the integer and fractional parts of the decimal number. Now for integer part, we carry
successive division-by-2 method as follows:
2 163 Remainder
2 81 1
2 40 1
2 20 0
2 10 0
2 5 0
2 2 1
2 1 0
0 1
Step 2: Now the fraction part is 0.87510. Carrying out successive multiplication-by-2 as follows:
0.875 x 2 = 1.75 1
0.75 x 2 = 1.5 1
0.5 x 2 = 1.0 1
Decimal to Octal conversion can be done in similar way as decimal to binary conversion. The integer
and fractional parts are to be separated and the same procedure is carried out. But the division and
multiplication are carried out by 8 as the base of octal number is 8. Following the same steps, we can
get the equivalent octal number of the given decimal number.
8 378 Remainder
8 47 2
8 5 7
0 5
0.93 x 8 = 7.44 7
0.44 x 8 = 3.52 3
0.52 x 8 = 4.16 4
0.16 x 8 = 1.28 1
So, 0.9310 = 0.73418
Decimal to hexadecimal conversion is carried out by 2 steps. In the first step, the integer part of the
decimal number is divided by 16 successively and the remainder is noted. The remainders read from
bottom to top gives the equivalent hexadecimal integer. In the second step, the successive
multiplication of fractional part by 16 is done and the integers are noted down. Reading the integers
from bottom to top gives the hexadecimal fraction.
Solution:
Step1: Conversion of integer part by successive division-by-16 method
16 3509 Remainder
16 219 5
16 13 11 = B
0 13 = D
0.75 x 16 = 12.0 12 = C
To convert a given octal number to binary, just replace each octal digit by its 3-bit binary equivalent.
Solution:
Given octal number is 3 6 7 . 5 2
Convert each octal digit to binary 011 110 111 . 101 010
To convert a given hexadecimal number to binary, just replace each hexadecimal digit by its 4-bit
binary equivalent.
Solution:
Given hexadecimal number is 4 B A C
Solution:
Given hexadecimal number is 3 A 9 . B 0 D
Convert each digit to 4-bit binary 0011 1010 1001 . 1011 0000 110
To convert a binary number to an octal number, starting from the binary point make groups of 3 bits
each, on either side of the binary point and replace each 3-bit binary group by the equivalent octal
digit.
Solution:
Group of 3 bits are 110 101 . 101 010
Solution:
Group of 3 bits are 10 101 111 001 . 011 1
To convert a binary number to an octal number, starting from the binary point make groups of 4 bits
each, on either side of the binary point and replace each 4-bit binary group by the equivalent
hexadecimal digit.
Solution:
Group of 4 bits are 10 1111 1011 . 0111 11
To convert an octal number to hexadecimal, the simplest way is to first convert the given octal
number to binary and then the binary number to hexadecimal.
Solution:
Given octal number is 1 2 4 5
Solution:
Given octal number is 7 5 6 . 6 0 3
Convert each octal digit to binary 111 101 110 . 110 000 011
To convert hexadecimal number to octal, the simplest way is to first convert the given hexadecimal
number to binary and then the binary number to octal.
Solution:
Given hex number is B 9 F . A E
Convert each hex digit to binary 1011 1001 1111 . 1010 1110
Group of 3 bits are 101 110 011 111 . 101 011 100
We can convert a given number in radix r to decimal by multiplying each digit by its positional weights
and taking sum of all the products.
Solution:
Here, the given number is in base 3. Its positional weights are: 33 32 31 30
1 2 2 1 = (1 x 33) + (2 x 32) + (2 x 31) + (1 x 30)
= 27 + 18 + 6 + 1
= 52
Hence, (1221)3 = (52)10
Solution:
Here, the given number is in base 5. Its positional weights are: 52 51 50 . 5-1 5-2
2 3 4 . 0 2 = (2 x 52) + (3 x 51) + (4 x 50) + (0 x 5-1) + (2 x 5-2)
= 50 + 15 + 4 + 0 + 0.08
= 69.08
Hence, (234.02)5 = (69.08)10
Decimal number can be converted in any radix by 2 steps. In step1, the integer part of the decimal
number is divided successively by the radix r and the remainders are noted down. Taking the
remainders from bottom to top gives the radix r equivalent of the integer part. Similarly, the
fractional part is successively multiplied by the radix r and the integer part of the result is noted
down. Noting the carry from top to bottom gives the fractional part equivalent in radix r.
Solution:
Step 1: Separate the integer and fractional parts of the decimal number. Now for integer part, we carry
successive division-by-12 method as follows:
12 1989 Remainder
12 165 9
12 13 9
12 1 1
0 1
So, (1989)10 = (1199)12
Step 2: Now the fraction part is 0.3510. Carrying out successive multiplication-by-12 as follows:
Solution:
We have, (33)10 = (201)b
33 = 2 x b2 + 0 x b1 + 1 x b0
= 2b2 + 1
2b2 = 32
b2 = 16
b = ±4
But base of any number cannot be negative. Hence value of b = 4.
Solution:
We have, (193)b = (623)8
1 x b2 + 9 x b1 + 3 x b0 = 6 x 82 + 2 x 81 + 3 x 80
b2 + 9b + 3 = 384 + 16 + 3
b2 + 9b + 3 = 403
b2 + 9b – 400 = 0
b = 16, b = -25
It is a numeric code that is used to represent decimal using binary bits i.e. 1’s and 0’s. It is different
from representation of a decimal number in binary system i.e. base 2 system.
In BCD representation each digit of a decimal number is represented by a group of four bits. These
bits are given with weights of 8-4-2-1 and hence many a times BCD code is also called 8421 code.
Code for each digit of decimal is as follows.
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Solution:
Decimal: 5 8
0101 1000
Thus (58)10 = (01011000)BCD.
It should be noted that binary representation of (58)10 will be (111010)2 which is quite different from
the BCD representation.
Solution:
BCD: 0010 0101 1001
2 5 9
(001001011001)BCD = (259)10
It can be observed that BCD codes are less efficient for representation compared to binary as it
requires more number of bits then required in binary representation. However, it is popular because
of its ease of conversion to and from decimal.
Logic gates are the fundamental building blocks of digital systems. They are the physical devices that
performs the basic Boolean operations of AND, OR and NOT.
Input and outputs of logic gates (that is basically a voltage signal) can occur only in two levels. These
two levels are termed as High and Low or True and False or ON and OFF or simply 1 and 0. In
representation of higher of the two voltage levels is symbolized as 1 and lower symbolized as 0 the
gate is said to be positive logic gate. However, if higher of the two voltage levels is symbolized as 0
and lower as 1 then it is said to be negative logic gate.
Input output behavior of a gate is generally represented using truth table. It is a table that lists output
for all possible combinations of inputs.
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 22
Unit: 1 – Binary Systems and Logic Circuits
There are total seven logic gates in which three are basic logic gates (AND, OR, NOT) and two are
universal logic gates (NAND, NOR).
1. NOT Gate:
NOT gate has one inputs and one output. The output becomes logic 1 when input is at logic 0 and
output becomes logic 0 when the input is at logic 1. Thus it inverts or complements the logic available
at input and hence called and inverter or complement. It is represented by a bar over the variable
“ ̅ ”or with a symbol “ ’ ”. Thus, for example, X = A΄ or X = A read as “X is equal to Not A or A bar
or A complement”. NOT gate and its truth table are shown in fig. 1.10.
2. AND Gate:
Operation of AND gate can be understood through the example of two switches connected in series
as shown in fig. 1.11. Here we assume switches A and B to present logic 1 when in ON condition and
logic 0 in OFF condition. Similarly, if lamp is ON we assume logic 1 and in OFF condition we assume
it as logic 0. Then it can be determined that the lamp will be ON (at logic 1) only when both the
switches A and B are ON (at logic 1).
3. OR Gate:
It also means Inequality detector because it gives output high when both inputs are different.
Exclusive OR gate give output equal to 1 when the two inputs are exclusively different. This is the
reason why it is also known as inequality gate. The schematic symbol and truth table of the gate is
shown in fig. 1.13. It is represented by a symbol . Thus, for example, X A B is read as “X is
equal to A XOR B.” The logic expression this gate in terms of AND, OR and NOT operation is
X A B AB AB .
It also means equality detector because it gives output high when both inputs are same.
Exclusive NOR gate is XOR gate followed by inverter. Thus it is complement of XOR gate. This is
the reason why it is also known as equality gate. The logic symbol, logic expression, schematic
symbol, truth table of the gate is shown in fig. 1.14.
X = AB + A’B’
6. NAND Gate:
NAND gate represents combination of AND gate followed by NOT gate. It represents complement of
AND operation. Schematic symbol of NAND gate and its truth table are shown in fig. 1.15. The logic
expression is given as X ( A B) or X = (A·B)’.
3. Implementing OR gate
The OR gate is replaced by a NAND gate with all its inputs complemented by NAND gate inverters.
7. NOR Gate:
NOR gate represents combination of OR gate followed by NOT gate. It represents complement of OR
operation. Schematic symbol of NOR gate and its truth table are shown in fig. 4.16. The logic
expression is given as X ( A B) or X = (A+B)’.
3. Implementing OR gate
The OR is replaced by a NOR gate with its output complemented by a NOR gate inverter.
Any logic gates can be designed to accept three or more input values.
As an example, three-input AND gate produces an output of 1 only if all input values are 1.
Constructing Gates
A transistor is a device that acts, depending on the voltage level of an input signal, either as a wire
that conducts electricity or as a resistor that blocks the flow of electricity
A transistor has no moving parts, yet acts like a switch.
It is made of a semiconductor material, which is neither a particularly good conductor of electricity,
such as copper, nor a particularly good insulator, such as rubber.
A transistor is shown in fig. 1.18.
Different logic families falling in the first category are called bipolar families, and these include
o Diode Logic (DL)
o Resistor Transfer Logic (RTL)
o Diode Transistor Logic (DTL)
o Transistor Transistor Logic (TTL)
o Emitter Coupled Logic (ECL)
o Integrated Injection Logic (I2L)
The logic families that use MOS devices as their basis are known as MOS families, and the prominent
members belonging to this category are
o PMOS Family (using P-channel MOSFETs)
o NMOS Family (using N-channel MOSFETs)
o CMOS Family (using both N- and P-channel devices)
o Bi-MOS Logic Family uses both Bipolar and MOS devices
Of all the logic families listed above, the first three, i.e. DL, RTL and DTL have become obsolete
Diode Logic used diode & resistors and in fact was never implemented in integrated circuits
RTL Family used resistors and bipolar transistors
DTL Family used resistors, diodes and bipolar transistors.
PMOS and I2L logic families, which were mainly intended for use in custom large-scale integrated
(LSI) circuit devices, have also become more or less obsolete.
Logic families that are still in widespread used include TTL, CMOS, ECL, NMOS and Bi-CMOS.
When this is done, an interface between the different elements may be required.
An interface consists of circuits that translate the output signals from one family to the input signals
required by the other family.
A family is said to be compatible with another family when both families can be interconnected
without requiring interface circuits.
1.5.2 Fan-Out
In a digital system, a given gate may drive the inputs to several other gates.
The no. of inputs that can be driven by the gate is referred to as fan-out of the circuit
Most of the circuits of a family will require the same input current, but a few may require more.
If so, the specs for such a circuit will indicate that the input is equivalent to some multiple of standard
loads.
For e.g., a circuit may present an equivalent input of two standard loads.
If fan-out of a gate is specified as 10, only five of these circuits could be safely driven.
Fig. 1.23 shows an AND gate loaded with 4 inputs, assuming each circuit presents one standard load
to the AND gate output.
Noise margin specifies the maximum amplitude noise pulse that will not change the state of the
driven stage.
Noise margin can be evaluated from a consideration of the voltage levels V IHmin, VILmax, VOHmin and
VOLmax.
Fig. 1.24 shows two logic circuits that are cascaded
VOHmin VIHmin
A B
Inputs Outputs
VOLmax VILmax
If VILmax = 0.8 V for circuit B, this means that the input must be less than 0.8 V to guarantee that circuit
B interprets this value as a low level
If circuit A has a value of VOLmax = 0.4 V, a noise spike of less than the difference 0.8 - 0.4 = 0.4 V
cannot lead to level misinterpretation by circuit b. The difference
VILmax – VOLmax
is called Low Level Noise Margin
Assuming that VIHmin = 2 V for circuit B and VOHmin = 2.7 V for circuit A, the high level margin is 2.7 –
2.0 = 0.7 V. The difference
VOHmin – VIHmin
is called High Level Noise Margin
Since the minimum voltage developed by circuit A at the high level is 2.7 V, while circuit B requires
only 2.0 V to interpret the signal as high level, a negative noise spike of -0.7 V or less will not result
in an error.
Both low- and high-level noise margins are demonstrated in fig. 1.25.
As more gate inputs are connected to a given output, the voltages generated at both high and low
levels are affected as a result of increased current flow. Thus, fan-out is influenced by noise margin.
Another quantity that is used to characterize switching circuits is the speed with which the device
responds to the input changes.
For switching circuits, the graph of Fig. 1.26 shows different delay times.
Different delay times are of an inverter gate.
Different definitions are as follows:
o tpHL : Difference in time between the point where ein rises to 50% of its final value and the time
when eout falls to its 50% point
o tpLH : Time difference between 50% points of the trailing edges of the input and output signals
o Propagation Delay : The average of tpHL and tpLH, or
t pHL t pLH
t pd
2
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 34
Unit: 1 – Binary Systems and Logic Circuits
o Fall Time, tf : 90% to 10% values as the output voltage swing between upper and lower voltage
level
o Rise Time, tr : 10% to 90% values as the output voltage swing between lower and upper voltage
level
In Boolean algebra there is nothing like subtracting or division, no negative or fractional numbers.
Boolean algebra represent logical operation only. Logical multiplication is same as AND operation
and logical addition is same as OR operation.
Boolean algebra has only two values 0 & 1.
In Boolean algebra;
If A = 0 then A ≠ 1. & If A = 1 then A ≠ 0.
Axioms or postulate of Boolean algebra are a set of logical expression that we accept without proof
& upon which we can build a set of useful theorems.
Axioms 1: 0 · 0 = 0
Axioms 2: 0 · 1 = 0
Axioms 3: 1 · 0 = 0
Axioms 4: 1 · 1 = 1
Axioms 5: 0 + 0 = 0
Axioms 6: 0 + 1 = 1
Axioms 7: 1 + 0 = 1
Axioms 8: 1 · 1 = 1
Axioms 9: 1’ = 0
Axioms 10: 0’ = 1
Its behavior is described by the set of output Its behavior is described by the set of next
function. state function and the set of output
function.
No feedback is available. Feedback is available.
It does not contains periodic clock signal. It contains clock signals.
Faster than sequential circuit. Slower than combinational circuit.
e.g. half adder, full adder, etc. e.g. Flip flop, counter, etc.
The term complement simply means to invert, i.e. to change 0’s to 1’s and 1’s to 0’s.
Law 1: 0’ = 1
Law 2: 1’ = 0
Law 3: If A = 0 then A’ = 1
Law 4: If A = 1 then A’ = 0
Law 5: A’’ = A
2. AND Laws:
Law 1: A · 0 = 0
Law 2: A · 1 = A
Law 3: A · A = A
Law 4: A · A’ = 0
3. OR Laws:
Law 1: A + 0 = A
Law 2: A + 1 = 1
Law 3: A + A = A
Law 4: A + A’ = 1
4. Commutative Laws:
Law 1: A + B = B + A
Proof:
Law 2: A · B = B · A
Proof:
5. Associative Laws:
Law 1: (A + B) + C = A + (B + C)
Proof:
Law 2: (A · B) · C = A · (B · C)
Proof:
6. Distributive Laws:
Law 1: A (B + C) = AB + AC
Proof:
Law 2: A + BC = (A + B) (A + C)
Proof: R.H.S. = (A + B) (A + C)
= AA + AC + BA + BC
= A + AC + BA + BC
= A + BC (B’cz 1 + C + B = 1 + B = 1)
= L.H.S.
Law 3: A + A’B = A + B
Proof: L.H.S. = A + A’B
= (A + A’) (A + B)
=A+B
= R.H.S.
7. Idempotence Laws:
Law 1: A · A = A
Proof:
Case 1: If A = 0 A · A = 0 · 0 = 0 = A
Case 2: If A = 1 A · A = 1 · 1 = 1 = A
Law 2: A + A = A
Proof:
Case 1: If A = 0 A + A = 0 + 0 = 0 = A
Case 2: If A = 1 A + A = 1 + 1 = 1 = A
Law 1: A · A’ = 0
Proof:
Case 1: If A = 0 A’ = 1 So, A · A’ = 0 · 1 = 0
Case 2: If A = 1 A’ = 0 So, A · A’ = 1 · 0 = 0
Law 2: A + A’ = 1
Proof:
Case 1: If A = 0 A’ = 1 So, A + A’ = 0 + 1 = 1
Case 2: If A = 1 A’ = 0 So, A + A’ = 1 + 0 = 1
This law states that double negation of a variables is equal to the variable itself.
Law 1: A’’ = A
Proof:
Case 1: If A = 0 A’’ = 0’’ = 1’ = A
Case 2: If A = 1 A’’ = 1’’ = 0’ = A
Law 1: A · 1 = A
Proof:
Case 1: If A= 1 A · 1 = 1 · 1 = 1 = A
Case 2: If A= 0 A · 0 = 0 · 0 = 0 = A
Law 2: A + 1 = 1
Proof:
Case 1: If A= 1 A + 1 = 1 + 1 = 1 = A
Case 2: If A= 0 A + 0 = 0 + 0 = 0 = A
Law 1: A · 0 = 0
Proof:
Case 1: If A= 1 A · 0 = 1 · 0 = 0 = 0
Case 2: If A= 0 A · 0 = 0 · 0 = 0 = 0
Law 2: A + 0 = A
Proof:
Case 1: If A= 1 A + 0 = 1 + 0 = 1 = A
Case 2: If A= 0 A + 0 = 0 + 0 = 0 = A
Law 1: A + AB = A
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 8
Unit: 2 – Boolean Algebra and Mapping Methods
Proof: L.H.S. = A + AB
= A (1 + B)
= A (1)
=A
R.H.S.
Law 2: A (A + B) = A
Proof: L.H.S. = A (A + B)
= A · A + AB
= A + AB
= A (1 + B)
= A (1)
=A
= L.H.S.
R.H.S. = (A + B) (A’ + C)
= AA’ + AC + BA’ + BC
= 0 + AC + BA’ + BC
= AC + A’B + BC …………………………(2)
Law 1: (A + B)’ = A’ · B’
Proof:
Duality theorem arises as a result of presence of two logic system i.e. positive & negative logic
system.
This theorem helps to convert from one logic system to another.
From changing one logic system to another following steps are taken:
1) 0 becomes 1, 1 becomes 0.
2) AND becomes OR, OR becomes AND.
3) ‘+’ becomes ‘·’, ‘·’ becomes ‘+’.
4) Variables are not complemented in the process.
Example 4: [P (Q + R)]’
Answer: [P (Q + R)]’
= P’ + (Q + R)’
= P’ + Q’ R’
= A [ B + C’ (AB)’ (AC’)’ ]
= A [ B + C’ (A’ + B’) (A’ + C) ]
= A [ B + (A’ C’ + B’ C’) (A’ + C) ]
= A [ B + (A’ C’A’ + B’ C’A’) (A’ C’ C + B’ C’ C) ]
= A [ B + (A’C’ + B’ C’A’) (0 + 0) ]
= A [ B + A’C’ ( 1 + B’) ]
= A [ B + A’C’]
= AB + A’AC’
= AB + 0
= AB
Example 2: A + B [ AC + (B + C’)D ]
Answer: A + B [ AC + (B + C’)D ]
= A + B [ AC + (BD + C’D) ]
= A + ABC + BBD + BC’D
= A + ABC + BD + BC’D
= A (1 + BC) + BD (1 + C’)
= A (1) + BD (1)
= A + BD
= BB + BD
= B + BD
= B (1 + D)
=B
Example 9: A’B + AB
Answer: A’B + AB
= B (A’ + A)
= B (1)
=B
Example 12: [(A + B’) (A’ + B’)] + [(A’ + B’) (A’ + B’)]
In this configuration, the terms that form the function may contain one, two, or any number of
literals.
There are two types of standard forms: (i) sum of product (SOP) (ii) product of sum (POS).
SOP is a Boolean expression containing AND terms, called product terms, of one or more literals
each. The sum denote the ORing of these terms.
An example of a function expressed in sum of product is:
F = Y’ + XY + X’YZ’
The OPS is a Boolean expression containing OR terms, called sum terms. Each terms may have any
no. of literals. The product denotes ANDing of these terms.
An example of a function expressed in product of sum is:
F = X (Y’ + Z) (X’ + Y + Z’ + W)
A Boolean expression function may be expressed in a nonstandard form. For example the function:
F = (AB + CD) (A’B’ + C’D’)
Above function is neither sum of product nor in product sums. It can be changed to a standard
form by using distributive law as below;
F = ABC’D’ + A’B’CD
Any boolean expression can be expressed in Sum of Product (SOP) form or Product of Sum (POS)
form, they are called canonical form.
A standard SOP form is one in which a no. of product terms, each one of which contains all the
variables of the function either in complemented or non-complemented form, summed together.
Each of the product term is called MINTERM.
For minterms,
Each non-complemented variable 1
Each complemented variable 0
Decimal equivalent is expressed in terms of lower case ‘m’.
For example,
1. XYZ = 111 = m7
2. A’BC = 011 = m3
3. P’Q’R’ = 000 = m0
4. T’S’ = 00 = m0
5. B’C = 01 = m1
Example 2: F2 = P’Q’ + PQ
= 00 + 11
= m0 + m3
= Σm(0,3)
A standard POS form is one in which a no. of sum terms, each one of which contains all the variables
of the function either in complemented or non-complemented form, are multiplied together.
Each of the product term is called MAXTERM.
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 17
Unit: 2 – Boolean Algebra and Mapping Methods
For maxterms,
Each non-complemented variable 0
Each complemented variable 1
Decimal equivalent is expressed in terms of upper case ‘M’.
For example,
1. X+Y+Z = 000 = M0
2. P’+Q’+R’ = 111 = M7
3. A’+B+C’+D = 1010 = M10
Example 1: F1 = (P’+Q)(P+Q’)
= (10)(01) = M2·M1
= ΠM(1,2)
Example 3: F3 = (A’+B+C)(A+B’+C)(A+B+C’)
= (100) (010) (001)
= M4 M2 M1
= ΠM(1,2,4)
The complement of a function expressed as the sum of minterms equals the sum of minterms
missing from original function
This is because the original function is expressed by those minterms that make the function equal to
1, while its complement is 1 for those minterms that the function is 0.
Example 1:
F(A,B,C)= Σ(1,4,5,6,7) F’(A,B,C) = ΠM(0,2,3)
STEP 1:
Take complement of the given function;
F’(A,B,C) = Σ(0,2,3) = (m0 + m2 + m3)’
STEP 2:
Put value of MINTERM in form of variables;
F’= (A’B’C’ + A’BC’ + A’BC)’
= (A+B+C)(A+B’+C)(A+B’+C’)
= M0·M2·M3
= ΠM(0,2,3)
In general, mj’ = Mj
Example 2:
F(A,B,C,D)= ΠM(0,3,7,10,14,15)
STEP 1:
Take complement of the given function;
F’(A,B,C,D)= ΠM(1,2,4,5,6,8,9,11,12,13) = (M1 M2 M4 M5 M6 M8 M9 M11 M12 M13)’
STEP 2:
Put value of MAXTERM in form of variables;
F’= [(A+B+C+D’)(A+B+C’+D)(A+B’+C+D)(A+B’+C+D’)(A+B’+C’+D)
(A’+B+C+D)(A’+B+C+D’)(A’+B+C’+D’)(A’+B’+C+D)(A’+B’+C+D’)]’
= (A’B’C’D) + (A’B’CD’) + (A’BC’D’) + (A’BC’D) + (A’BCD’)
(AB’C’D’) + (AB’C’D) + (AB’CD) + (ABC’D’) + (ABC’D)
= m1 + m2 + m4 + m5 + m6 + m8 + m9 + m11 + m12 + m13
= Σm(1,2,4,5,6,8,9,11,12,13)
Convert to Minterms
Example 1:
F = A + B’C
Convert to Maxterms
Example 1:
F = A (B + C’)
A = A + BB’ + CC’
= (A + B) (A +B’) + CC
= (A + B + CC’) (A + B’ + CC’)
= (A + B + C) (A + B + C’) (A + B’ + C) (A + B’ + C’)
Answer: F = XY + X’Y
= (XY + X’) (XY + Z)
= (X +X’) (Y + X’) (X + Z) (Y + Z)
= (Y + X’) (X + Z) (Y + Z)
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 20
Unit: 2 – Boolean Algebra and Mapping Methods
X’ + Y = X’ + Y + ZZ’
= (X’ + Y + Z) (X’ + Y + Z’)
= (100) (101)
X + Z = X’ + Z + YY’
= (X + Y + Z) (X + Y’ + Z)
= (000) (010)
Y + Z = Y + Z + XX’
= (X + Y + Z) (X’ + Y + Z)
= (000) (100)
So, F = XY + X’Z
= (100) (101) (000) (010)
= M4 M5 M0 M2
F = ΠM(0,2,4,5)
K-map cells are arranged such that adjacent cells correspond to truth rows that differ in only one bit
position (logical adjacency)
K-Map are often used to simplify logic problems with up to 6 variables
No. of Cells = 2n, where n is a number of variables.
The Karnaugh map is completed by entering a ‘1’ (or ‘0’) in each of the appropriate cells.
Within the map, adjacent cells containing 1's (or 0’s) are grouped together in twos, fours, or eights
and so on.
SOP Minterms A’B’ (m0, 00) ; A’B (m1, 01) ; AB’ (m2, 10) ; AB (m3, 11)
POS Maxterms A + B (M0, 00) ; A + B’ (M1, 01) ; A’ + B (M2, 10) ;
A’ + B’ (M3, 11)
B B
B’ B B’ B
A 0 1 A 0 1
A’ 0 A’B’ A’B A’ 0 m0 m1
0 1 0 1
A 1 AB’ AB m2 m3
A 1
2 3 2 3
A’ 0 1 0
0 1
A 1 1 1
2 3
F = A’B’ + AB
Example 1: F = AB
B
B’ B
A 0 1
A’ 0 0 0
0 1
A 1 0 1
2 3
B
B’ B
A 0 1
A’ 0 1 1
0 1
A 1 1 0
2 3
B
B’ B
A 0 1
A’ 0 1 0
0 1
A 1 1 0
2 3
Example 4: F = m0 + m1
B
B’ B
A 0 1
A’ 0 1 1
0 1
A 1 0 0
2 3
B B
B B’ B B’
A 0 1 A 0 1
A 0 A+B A+B’ A 0 M0 M1
0 1 0 1
A’ 1 A’+B A’+B’ M2 M3
A’ 1
2 3 2 3
B
B’ B
A 0 1
A’ 0 0 1
0 1
A 1 0 0
2 3
B
B B’
A 0 1
A 0 0 1
0 1
0 1
A’ 1
2 3
Example 2: F = M0·M1·M2
B
B B’
A 0 1
A 0 0 0
0 1
0 1
A’ 1
2 3
Example 3: F = ΠM(1,3)
B
B B’
A 0 1
A 0 1 0
0 1
1 0
A’ 1
2 3
Example 1: F = m0 + m1
B
B’ B
A 0 1
A’ 0 1 1
0 1
A 1 0 0
2 3
F = A’
Example 2: F = A’B’ + AB’
B
B’ B
A 0 1
A’ 0 1 0
0 1
A 1 1 0
2 3
F = B’
Example 3: F = Σ(1,3)
B
B’ B
A 0 1
A’ 0 0 1
0 1
A 1 0 1
2 3
F=B
Example 4: F = m2 + m3
B
B’ B
A 0 1
A’ 0 0 0
0 1
A 1 1 1
2 3
F=A
Example 5: F = ∑m(0,1,2,3)
B
B’ B
A 0 1
A’ 0 1 1
0 1
A 1 1 1
2 3
F=1
Example 1: F = Π(0,2,3)
B
B B’
A 0 1
A 0 0 1
0 1
0 0
A’ 1
2 3
F = A’B
A 0 0 0
0 1
0 1
A’ 1
2 3
F = AB
Example 3: F = M3·M1·M2
B
B B’
A 0 1
A 0 1 0
0 1
0 0
A’ 1
2 3
F = A’B’
Example 4: m2 + m3
F = m2 + m3 = Π(0,1)
B
B B’
A 0 1
A 0 0 0
0 1
1 1
A’ 1
2 3
F=A
Example 5: F = ΠM(0,1,2,3)
B
B B’
A 0 1
A 0 0 0
0 1
0 0
A’ 1
2 3
F=0
For the case of 3 variables, we form a map consisting of 23=8 cells as shown in Figure
EXAMPLE 2: F = Σ(1,6,7)
F = A’B’C’ + AB
EXAMPLE 4: F = Σm(0,1,2,4,5,6)
F = B’ + C’
EXAMPLE 5: F = m3 + m4 +m6 + m7
F = BC + AC’
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 29
Unit: 2 – Boolean Algebra and Mapping Methods
EXAMPLE 6: F = Σm(3,7,1,6,0,2,5,4)
F=1
For the case of 3 variables, we form a map consisting of 23=8 cells as shown in Figure
EXAMPLE 1: F = (A’+B’+C’)(A’+B+C’)
F = (A’ + C’)
EXAMPLE 2: F = ΠM(1,2,5)
F = (B + C’) (A + B + C)
EXAMPLE 3: F = M0·M3·M7
F = (A + B + C) (B’ + C’)
EXAMPLE 4: F = (A+B+C)(A+B’+C’)(A’+B+C)
F = (B + C) (A + B’ + C’)
EXAMPLE 5: F = ΠM(5,7,0,3,2,4,6,1)
F=0
Looping:
EXAMPLES:
EXAMPLE 1: ∑ (0,1,2,4,5,6,8,9,12,13,14)
F = C’ + A’D’ + BD’
EXAMPLE 3: ∑ (0,1,2,3,5,7,8,9,12,13)
EXAMPLE 4: ∑ (0,1,3,4,5,6,7,13,15)
EXAMPLE 5: ∑m (5,6,7,9,10,11,13,14,15)
F = BD + BC + AD + AC
EXAMPLE 1: ΠM (0,1,2,5,7,8,9,10,14,15)
EXAMPLE 1: ∑m (0,2,3,10,11,12,13,16,17,18,19,20,21,26,27)
EXAMPLE 2: ∑m (0,2,4,6,9,11,13,15,17,21,25,27,29,31)
F = BE + AD’E + A’B’E’
EXAMPLE 3: ΠM (1,4,5,6,7,8,9,14,15,22,23,24,25,28,29,30,31)
K-map is useful tool in logic function minimization if fewer than six variables are involved.
When no. of variables increases, the calculation becomes tough.
The VARIABLE-ENTERED MAP can be used to plot an n-variable problem on an n-1 variable map.
For e.g. 5 variable problem can be solved using 4 variable K-map.
Also 5 variable problem can be solved using 3 & lesser variable K-map, but the method becomes
difficult.
F = B’ + AB
ANS:
EXAMPLE 1: F = AB’CD + A’BC’D + AB’CD’ + ABC’D + A’B’C’D Consider D as MEV (Mapped Entered
Variable)
ANS:
STEP 1: A’B’C’(D) + A’BC’(D) + AB’C(D + D’) + ABC’(D)
STEP 2:
ANS:
STEP 1: A’B’C’(D) + A’BC’(D’ + D) + AB’C’(D’) + AB’C(D’ + D) + ABC(D’)
STEP 2:
ANS:
STEP 1: A’B’C’D’(E) + A’B’C’D(E) + A’BCD’(E’ + E) + AB’C’D’(E’ + E) +
AB’C’D(E’ + E) + A’BCDE’
STEP 2:
ANS:
STEP 1: A’BC’D’(E’) + ABC’D’(E’) + A’BC’D(E’ + E) + A’BCD’(E + E’) +
A’B’CD’(E) + ABCD’(E’ + E)
STEP 2:
ANS:
F = BC’E + AD (E + E’)
F = BC’E + AD
ANS:
EXAMPLE 7: F = A’BC’ + A’BC + ABC’ + AB’C’ Consider C as MEV (Mapped Entered Variable).
ANS:
STEP 1: F = A’B(C’ + C) + AB(C’) + AB’(C’)
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 43
Unit: 2 – Boolean Algebra and Mapping Methods
STEP 2:
F = AC’ + A’B
EXAMPLE 8: Y = A’B’C’D’ + A’B’CD’ + AB’C’D’ + AB’C’D + AB’CD + AB’CD’ Consider D as MEV (Mapped
Entered Variable).
ANS:
STEP 1: F = A’B’C’(D’) + A’B’C(D’) + AB’C’(D’+D) + AB’C(D + D’)
STEP 2:
F = AB’(D’ + D) + B’D’
F = AB’ + B’D’
ANS:
STEP 1: X = A’B’(C’D’ + CD’) + AB(CD) + AB’(CD + CD’)
STEP 2:
EXAMPLE 2: X=A’B’C’D’ + A’B’C’D + A’B’CD’ + A’BCD + ABCD+ AB’CD Use C & D as MEV
ANS:
STEP 1: X = A’B’(C’D’ + C’D + CD’) + A’B(CD) + AB(CD)+ AB’(CD)
STEP 2:
3.1 MULTIPLEXER:
Multiplexer is a special type of combinational circuit.
The figure below shows the n x 1 multiplexer and its equivalent circuit representation.
There are ‘n’ data inputs, 1 output and ‘m’ select lines, i.e. 2 m=n.
A multiplexer is a digital circuit which selects one of the n data inputs and routes it to the output.
The selection of one of the n inputs is done by the select inputs
To select ‘n’ inputs, ‘m’ select lines such that 2m=n.
Depending on the digital code applied at the select inputs, one out of ‘n’ data sources is elected and
transmitted to the single output.
As shown in the figure, the multiplexer acts like a digitally controlled single pole, multiple way switch.
The output gets connected to only one of the ‘n’ data inputs at given instant of time.
It is also called DATA SELECTOR.
n
2 Data Data
Inputs Output
n
Selection Inputs
Fig. 3.1: Illustration of multiplexer
3.1.1 2 X 1 Multiplexer
It has two data inputs I0 and I1, one select input S, and one output Y.
Block Diagram
Truth Table
Table 3.1: Truth table of 2 X 1 multiplexer
Boolean Equation
Y = S’I0 + SI1
Circuit Diagram
I0
Y
I1
S
Fig. 3.3: Circuit diagram of 2 X 1 multiplexer
Working
When S=0, the upper AND gate will turn ON and lower AND gate will turn OFF, and so the input I 0
appears in the output.
When S=1, the upper AND gate will turn OFF and lower AND gate will turn ON, and so the input I 1
appears in the output.
3.1.2 4 X 1 Multiplexer
It has four data inputs I3, I2, I1 and I0, two select inputs S1 & S0, and one output Y.
Here 2n=4 inputs, i.e. n=2 select lines and m = 1 output.
Block Diagram
Truth Table
Table 3.2: Truth table of 4 X 1 multiplexer
Working
According to the truth table, when S1 S0=00, the input I0 is selected and routed to the output.
When S1 S0=01, the input I1 is selected and routed to the output.
Similarly, when S1 S0=10, then Y=I2 & when S1 S0=11, then Y=I3.
Boolean Equation
Circuit Diagram
I0
I1
Y
I2
I3
S1 S0
3.1.3 8 X 1 Multiplexer
It has 8 data inputs I7, I6, I5, I4, I3, I2, I1 and I0, three select inputs S2, S1 & S0, and one output Y.
Here 2n=8 inputs, i.e. n=3 select lines and m = 1 output.
Circuit Diagram
Truth Table
Table 3.3: Truth table of 8 X 1 multiplexer
Boolean Equation
Operation
According to the truth table, when S2S1 S0=000, the input I0 is selected and routed to the output.
When S2S1 S0=001, the input I1 is selected and routed to the output.
Similarly, for other combinations of select lines particular input is routed to the output.
Example 4: Implement the function F (A, B, C, D) = ∑ (1, 3, 4, 11, 12, 13, 14, 15) using 8 X 1 multiplexer.
3.2 DEMULTIPLEXER:
It has one input common data, ‘n’ select lines and ‘m’ output lines.
A demultiplexer performs the reverse operation of a multiplexer i.e. it receives one input and
distributes it over several outputs.
At a time only one output line is selected by the select lines and the input is transmitted to the
selected output line.
Relation between ‘n’ output lines and m select lines is as follows :
n = 2m
3.2.1 1 X 4 Demultiplexer
1 to 4 Demultiplexer has one data input F; select line inputs a,b and four outputs A, B, C & D.
The select lines control the data to be routed. It helps in selecting the output on which the data will
be routed.
Switch Representation
Truth Table
Table 3.4: Truth table of 1 X 4 demultiplexer
Select Line
Output Line
b a
0 0 A
0 1 B
1 0 C
1 1 D
Boolean Equation
A = Fb′a′; B = Fb′a;
C = Fba′; D = Fba;
Working
Circuit Diagram
3.2.2 1 X 8 Demultiplexer
1 to 8 Demultiplexer has one data input I; select line inputs are S 2, S1 & S0 and eight outputs F0, F1,
F2, F3, F4, F5, F6, F7 & F8.
The select lines control the data to be routed. It helps in selecting the output on which the data i.e.
‘I’ will be routed.
Truth Table
Table 3.5: Truth table of 1 X 8 demultiplexer
Select Line
Output Line
S2 S1 S0
0 0 0 F0
0 0 1 F1
0 1 0 F2
0 1 1 F3
1 0 0 F4
1 0 1 F5
1 1 0 F6
1 1 1 F7
Boolean Equation
F0 = IS̅̅̅2 S̅1 ̅̅̅
S0 ; F1 = IS̅̅̅2 S̅1 S0 ;
F2 = IS̅̅̅2 S1 ̅̅̅
S0 ; F3 = IS̅̅̅2 S1 S0 ;
F6 = IS2 S1 ̅̅̅
S0 ; F7 = IS2 S1 S0
Working
Circuit Diagram
3.3 ENCODER:
It is a combinational circuit.
It has ‘n’ input lines & ‘m’ output lines.
An encoder produces an ‘m’ bit binary code corresponding to the digital input number of ‘n’ bits.
Many types of Encoders – Octal to Binary (8 to 3), Decimal to BCD (10 to 4) etc.
The block diagram is as shown below,
Inputs Outputs
D3 D2 D1 D0 Y1 Y0
0 0 0 0 X X
0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1
Y1 = D 3 + D 2 Y0 = D3 + D2’ D1
Input Output
D0 D1 D2 D3 D4 D5 D6 D7 Q2 Q1 Q0
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Boolean Equation
Q0 = D1 + D3 + D5 + D7
Q1 = D2 + D3 + D6 + D7
Q2 = D4 + D5 + D6 + D7
Circuit Diagram
3.4 DECODER:
Decoder is a device which does the reverse operation of Encoder. It is a combinational circuit that
converts binary information from ‘n’ input lines to a maximum of ‘2n’ unique output lines.
Decoder is identical to a demultiplexer without any data input.
E.g.: 2 to 4 Decoder, 3 to 8 Decoder, BCD to Seven Segment Decoder.
I0 & I1 are two inputs whereas y3, y2, y1 & y0 are four outputs.
The truth table shows that each output is ‘1’ for only a specific combination of inputs.
Block Diagram
Truth Table
Table 3.8: Truth table of 2 to 4 decoder
Inputs Output
I1 I0 y0 y1 y2 y3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
Working
According to the truth table, when I1I0=00, the output Y0 is set to ‘1’, others are ‘0’
When I1I0=01, the output Y1 is set to ‘1’, others are ‘0’
Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’
Boolean Equation
y0 = I̅1 I̅0 ;
y1 = I̅1 I0 ;
y2 = I1 I̅0 ;
y3 = I1 I0
Circuit Diagram
Y3
Y2
Y1
Y0
I1
I0
3.4.2 3 to 8 Decoder
Block Diagram
Truth Table
Table 3.9: Truth table of 3 to 8 decoder
Inputs Output
I2 I1 I0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Working
According to the truth table, when I2I1I0=000, the output Y0 is set to ‘1’, others are ‘0’
When I2I1I0=001, the output Y1 is set to ‘1’, others are ‘0’
Similarly, for other input combinations, particular output is set to ‘1’ & others are ‘0’
Boolean Equation
Circuit Diagram
Y7
Y6
Y5
Y4
Y3
Y2
Y1
Y0
I2
I1
I0
Inputs Output
E I1 I0 Y0 Y1 Y2 Y3
0 X X 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
Y3
Y2
Y1
Y0
I1
I0
E
Truth Table
Table 3.11: Truth table of magnitude comparator
Inputs Outputs
A1 A0 B1 B0 G E L
0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0
1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0
Boolean Equation
For E,
For L,
For G,
Circuit Diagram
Circuit Diagram
Fig. 3.29: Circuit diagram of 8 bit magnitude comparator using 4 bit bit magnitude comparator
The parity bit can be attached to the code group either at the beginning or at the end depending on
system design.
A given system operates with either even or odd parity but not both. So, a word always contains
either an even or an odd number of 1s.
At the receiving end, if the word received has an even number of 1s in the odd parity system or an
odd number of 1s in the even parity system, it implies that an error has occurred.
In order to check or generate the proper parity bit in a given code word, the basic principle used is
“the modulo sum of an even number of 1s is always a 1”.
Therefore, in order to check for an error, all the bits in the received word are added.
If the modulo sum is a o for an odd parity system or a 1 for an even parity system, an error is detected.
To generate an even parity, the four data bits are added using three X-OR gates. The sum bit will be
the parity. Fig. (a) shows the logic diagram of an even parity generator.
To generate an odd parity bit, the four data bits are added using three X-OR gates and the sum bit is
inverter. Fig. (b) shows the logic diagram of an odd parity generator.
Fig. (c) & (d) shows an even bit parity checker and an odd parity checker respectively
Truth Table
Table 3.13: Truth table of even parity bit generator for 4 bit input
Boolean Equation
Circuit Diagram
Fig. 3.31: Circuit diagram of even parity bit generator for 4 bit input
An odd parity bit generator outputs a 1, when the number of 1s in the data bits is even, so that the
total number of 1s in the data bits and parity bit together is odd.
Since odd parity is the complement of even parity.
So, an inverter is connected at the output of an even parity generator.
The truth table, the K-map and the logic diagram for the odd parity generator are shown in figure
below.
From the K-map, it can be seen that no minimization is possible.
If the expression for the parity bit is implemented as it is, 40 gate inputs are required.
To reduce the cost, the expression may be manipulated in terms of X-OR gates and implemented.
Truth Table
Table 3.14: Truth table of odd parity bit generator for 4 bit input
Boolean Equation
Circuit Diagram
Fig. 3.32: Circuit diagram of odd parity bit generator for 4 bit input
4.1 Introduction
Combinational Circuit
A combinational circuit can be defined as a circuit whose output is dependent only on the
inputs at the same instant of time. Half Adder, Full Adder, Half Subtractor, Full Subtractor are
examples of combinational circuits.
Sequential Circuit
A sequential circuit can be defined as a circuit whose output depends not only on the present
inputs but also on the past history of inputs.
For a sequential circuit, the values of the variable are usually specified at certain discrete time
instants rather than over the whole continuous time. Flip-Flops, Registers, Counters form the
sequential circuit.
A sequential circuit consists of combinational circuit and memory elements are connected to it
to form a feedback path as shown in the block diagram below:
Synchronous Sequential Circuit: Output changes at discrete interval of time. It is a circuit based
on an equal state time or a state time defined by external means such as clock. Examples of
synchronous sequential circuit are Flip Flops, Synchronous Counter.
Prof. A. H. Pambhar, EC Department | 2131004 – Digital Electronics 1
Unit: 4 – Flip-Flops, Counters and Registers
Asynchronous Sequential Circuit: Output can be changed at any instant of time by changing the
input. It is a circuit whose state time depends solely upon the internal logic circuit delays.
Example of asynchronous sequential circuit is Asynchronous Counter.
Further differences between combinational and sequential circuits can be listed as follows:
4.2 Flip-Flops
Memory element used in clocked sequential circuit is known as Flip Flop. It is capable of storing
binary information. It is a Binary cell capable of storing one bit. A Flip Flop circuit can maintain a
Binary state until directed by an input signal to switch into other state.
It is also known as Bi-stable Multivibrator, because it has two stable states either ‘Logic 0’ or
‘Logic 1’. It can be also known as Latch.
The Flip Flop is made up of an assembly of Logic Gates. Even though, a Logic gate by itself has
no storage capability, several gates can be connected in such a way that, permit the
information to be stored.
There are various types of Flip Flops, like SR Flip Flop, D Flip Flop, JK Flip Flop, T Flip Flop etc. but
the major difference between various Flip Flops, are in the number of inputs they possess and
the manner in which the input affect the binary states at the output.
It can be constructed using NOR gate. Which is also known as ( S-R Latch) / (R-S Flip Flop) / (Set
– Clear Latch)/ (S-C Latch).
Figure 4.3 shows Basic Flip Flop circuit, upon which we can construct other type of Flip Flops.
This type of Flip Flop is called direct coupled R-S Flip Flop. Here cross coupled connection
constitutes the feedback path. This is an Asynchronous sequential circuit.
S-R Flip Flop has two inputs SET and RESET as well as two outputs Q and ´ OR Q and Q’. Both
the outputs are complement of each other. For different combination of inputs, outputs are
shown in Truth Table.
When S=1, R=0 then output is Q=1 (SET condition of Flip Flop)
When S=0, R=1 then output is Q=0 (RESET condition of Flip Flop)
When S=0, R=0 then output is Q=Q0 (Previous condition of Flip Flop)/Memory State
When S=1, R=1 then output is Q=0, and ´ =0 (Invalid condition of Flip Flop as Q and ´ are
always complement of each other)
Timing Diagram:
It can be constructed using NAND gate. Figure 4.5 shows Basic Flip Flop circuit, using NAND
Gate.
When S=1, R=0 then output is Q=0 ( SET condition of Flip Flop)
When S=0, R=1 then output is Q=1 ( RESET condition of Flip Flop)
When S=1, R=1 then output is Q=Q0 ( Previous condition of Flip Flop)/Memory State
When S=0, R=0 then output is Q=1, and ´ =1 ( Invalid condition of Flip Flop as Q and ´ are
always complement of each other)
Active low RS Flip Flop can be converted into Active High by connecting an Inverter at both
the inputs OR by applying inverted inputs.
The output of a flip flop can be changed by bringing a small change in the input signal. This
small change can be brought with the help of a clock pulse or commonly known as a trigger
pulse. It is difficult to apply all the inputs simultaneously at the input terminal of flip flop, so to
synchronize these inputs, a clock or triggering pulse is applied.
When such a trigger pulse is applied to the input, the output changes and thus the flip flop is
said to be triggered. Flip flops are applicable in designing counters or registers which stores
data in the form of multi-bit numbers. But such registers and counters need a group of flip flops
connected to each other as sequential circuits. And these sequential circuits require trigger
pulses.
If a clock pulse is given to the input of the flip flop at the same time when the output of the flip
flop is changing, it may cause instability to the circuit. The reason for this instability is the
feedback that is given from the output combinational circuit to the memory elements. This
problem can be solved to a certain level by making the flip flop more sensitive to the pulse
transition rather than the pulse duration.
There are mainly four types of pulse-triggering methods. They differ in the manner in which the
Flip- Flop responds to the pulse.
When a flip flop is required to respond at its HIGH state, a HIGH level triggering method is used.
It is mainly identified from the straight lead from the clock input. Take a look at the symbolic
representation shown below.
When a flip flop is required to respond at its LOW state, a LOW level triggering method is used..
It is mainly identified from the clock input lead along with a low state indicator bubble. Take a
look at the symbolic representation shown below.
When a flip flop is required to respond at a LOW to HIGH transition state, a POSITIVE edge
triggering method is used. It is mainly identified from the clock input lead along with a triangle.
Take a look at the symbolic representation shown below.
A Clocked RS Flip Flop requires a clocked pulse for synchronization purpose. It’s S and R input
can control the output only when ENABLE (clock) signal is high. It is also known as clocked SR
latch or Synchronous SR latch.
This type of Flip Flop responds to the changes in input only when clock is HIGH. It is also called
LEVEL TRIGGERED Flip Flop.
When S=1, R=0 then output is Q=1 which is SET condition of Flip Flop
When S=0, R=1 then output is Q=0 which is RESET condition of Flip Flop
When S=0, R=0 then output is Q=Q0 which is Previous condition of Flip Flop. It is also considered
as Memory State.
When S=1, R=1 then output is Q=0, and ´ =0 which Invalid / indeterminate condition of Flip
Flop as Q and ´ are always complement of each other
Figure 4.10 Circuit Diagram and Symbol of Clocked S-R Flip-Flop using NAND Gate
Figure 4.10 shows the circuit diagram & symbol of clocked SR Flip Flop. Truth table is derived
from the above circuit base on previous state. In truth table Q(t + 1) indicates the next state.
Transition as per Truth table occurs only when clock pulse is HIGH i.e. Clock is ENABLE. The
timing diagram of Level Triggered SR Flip Flop is shown in Figure 4.13.
.
Figure 4.11 Truth Table Of Clocked S-R Flip-Flop
K-Map derived from truth table is as follow with characteristic equation. S=1, R=1 is considered
as don’t care condition.
Timing Diagram:
SR Flip Flop can be also derived using only NOR Gate as shown in Figure 4.14.
D Flip Flop is a modification of Clocked SR Flip Flop. It is also known as gated D latch. The D Flip
Flop receives designation ‘D’ from the ability to transfer ‘Data’ into a Flip Flop.
It is basically a RS Flip Flop with an inverter at R Input. So number of input is only one in D Flip
Flop.
D flip flop is actually a slight modification of the clocked SR flip-flop. From the figure you can
see that the D input is connected to the S input and the complement of the D input is
connected to the R input. The D input is passed on to the flip flop when the value of CP is ‘1’.
When CP is HIGH, the flip flop moves to the SET state. If it is ’0′, the flip flop switches to the
CLEAR state.
Timing Diagram:
Figure 4.18 Timing Diagram for Positive Edge Triggered D Flip Flop
A JK flip-flop has two inputs similar to that of RS Flip-Flop. We can say JK flip-flop is a
refinement of RS flip-flop. JK means Jack Kilby, a Texas instrument engineer who invented IC.
The two inputs of JK Flip-flop is J (set) and K (reset). A JK flip-flop is nothing but a RS flip-flop
along with two AND gates which are augmented to it.
The flip-flop is constructed in such a way that the output Q is ANDed with K and CP. This
arrangement is made so that the flip-flop is cleared during a clock pulse only if Q was previously
1. Similarly Q’ is ANDed with J and CP, so that the flip-flop is cleared during a clock pulse only if
Q’ was previously 1.
When J=K=0
When both J and K are 0, the clock pulse has no effect on the output and the output of the flip-
flop is the same as its previous value. This is because when both the J and K are 0, the output of
their respective AND gate becomes 0.
When J=K=1
Consider the condition of CP=1 and J=K=1.
When both the inputs J and K have a HIGH state, the flip-flop switches to the complement
state. So, for a value of Q = 1, it switches to Q=0 and for a value of Q = 0, it switches to Q=1.
This will cause the output to complement again and again. This complement operation
continues until the Clock pulse goes back to 0. Since this condition is undesirable, we have to
find a way to eliminate this condition. This can be avoided by setting time duration of pulse
lesser than the propagation delay through the flip-flop. But it very difficult to generate the
pulse with duration less than propagation delay time. So the restriction on the pulse width can
be eliminated with a master-slave JK Flip Flop or Edge-triggered JK Flip Flop.
In JK Flip Flop when J=K=1 and Clock pulse is also HIGH i.e CP=1, the flip-flop switches to the
complement state. So, for a previous value of Q = 1, it switches to Q=0 and for a previous value
of Q = 0, it switches to Q=1.
This will cause the output to complement again and again. It means that output toggles
between 1 and 0 when J=K=CP=1. This complement operation continues until the Clock pulse
goes back to 0. This situation is called Race Around condition. Since this condition is
undesirable, we have to find a way to eliminate this condition.
This can be avoided by setting time duration of pulse lesser than the propagation delay through
the flip-flop. But it very difficult to generate the pulse with duration less than propagation delay
time. So the restriction on the pulse width can be eliminated with a master-slave JK Flip Flop or
Edge-triggered JK Flip Flop.
T flip-flops are similar to JK flip-flops. T flip-flops are single input version of JK flip-flops. This
modified form of JK flip-flop is obtained by connecting both inputs J and K together. This flip-
flop has only one input along with Clock pulse. These flip-flops are called T flip-flops because of
their ability to complement its state (i.e.) Toggle. So they are called as Toggle flip-flop.
Here also the restriction on the pulse width can be eliminated with a master-slave or edge-
triggered construction. Take a look at the circuit and truth table given for T Flip Flop.
Master-slave flip flop is designed using two separate flip flops. Out of these, one acts as the
Master and the other as a Slave.
In previous exercise, we discussed the JK flip-flop and its undesirable operation. When J=1 and
K=1, there is a restriction on pulse width due to toggle operation (where output complements
again and again until clock pulse goes to 0). This restriction can be overcome by using the
Master-Slave Flip-flop.
A master-slave flip-flop is normally constructed from two flip-flops, one is the Master flip-flop
and the other is the Slave. In addition to these two flip-flops, the circuit also includes an
inverter. The inverter is connected to clock pulse in such a way that the inverted CP is given to
the slave flip-flop. For example, if the CP=0 for a master flip-flop, then the output of the
inverter is 1, and this value is assigned to the slave flip-flop. In other words if CP=0 for a master
flip-flop, then CP=1 for a slave flip-flop.
A master-slave flip flop can be constructed using any type of flip-flop which forms a
combination with a clocked RS flip-flop, and with an inverter as slave circuit. Block diagram of
Master Slave Flip Flop is as shown in Figure 4.27.
Figure 4.27 Block Diagram of Master Slave using S-R Flip Flop
When CP=0
Now when CP=0, the master flip-flop is disabled. So the external inputs R and S of the master
flip-flop will not affect the circuit until CP goes to 1. The inverter output goes to 1 and it enables
the slave flip-flop. The output Q=Y and Q’=Y’.
When CP=1
When CP=1, the master flip-flop is enabled and the slave flip-flop remains isolated from the
circuit until CP goes back to 0. Now Y and Y’ depends on the external inputs R and S of the
master flip-flop.
Assume that the flip-flop is in a clear state and no clock pulse is applied to the circuit. The
external inputs given are S=1 and R=0. This input will not affect the state of the system until the
CP=1. Now the next clock pulse applied should change the state to SET state (S=1, R=0).
During the clock pulse transition from 0 to 1, the master flip-flop goes to set state and changes
the output Y to 1. However this does not affect the output of the system since the slave flip-flop
is isolated from the system (CP=0 for slave). So no change is observed at the output of the
system.
When the CP returns to 0, the master flip-flop is disabled while the slave is enabled. So the
information from the master is allowed to pass through to the slave. Since Y=1, this changes the
output Q to 1.
From this behavior of the master slave flip-flop it is quite clear that the state change in flip-
flops coincide with the negative edge transition of the pulse.
A JK master slave flip-flop can be constructed using NAND gates. It is constructed using two flip-
flops. Gate I to 4 represents master flip-flop and gate 5 to 8 represents slave flip-flop. Gate 9
represents the inverter
During the positive edge of the flip-flop, the information from external inputs J and K is passed
through to the master flip-flop. It is held there until the negative edge transition of the flip-flop
occurs. Then the information is passed to the slave, clocked RS flip-flop, and the output is
observed.
Usually the clock pulse is 0 at start, so the values of J and K will not affect the state of the
system, and the master flip-flop is isolated. But the output of gate 9 is 1, hence the slave flip-
flop provides the output Q=Y and Q’=Y’. When the clock pulse goes to 1, the slave is isolated; J
and K inputs may affect the state of the system. The slave flip-flop is isolated until the CP goes
to 0. When the CP goes back to 0, information is passed from the master flip-flop to the slave
and output is obtained.
Prof. A. H. Pambhar, EC Department | 2131004 – Digital Electronics 21
Unit: 4 – Flip-Flops, Counters and Registers
From the timing diagram of Master Slave Flip Flop it has been observed that Output Q
actually makes the transition only when trailing edge of clock pulse arrives.
In Flip Flop when power is switched ON, the state of the circuit is uncertain, it may be Q=1 or
Q=0.
In many applications it is desired to initially SET or RESET the Flip Flop i.e. initial state of the flip
flop is to be assigned. This is accomplished by direct or asynchronous inputs, referred as Preset
(PRE) and Clear (CLR) inputs. These inputs are not in synchronism with main inputs.
Figure 4.30 shows D flip-flop with Preset and Clear. If Preset and Clear is 1 then circuit operates
in accordance with the Truth table of D Flip Flop. It has no effect on the performance of Flip
Flop.
If Preset = 0 and Clear = 1 then Q =1, which SET the Flip Flop irrespective of main inputs, prior
to its working/operation, hence the name given Preset. Once initial known state is obtained,
Preset is kept now in Preset=1 condition for normal operation of Flip Flop. So Preset SET the
initial condition prior to the working of Flip Flop with PRE=0.
If Preset = 1 and Clear = 0 then Q =0, which RESET the Flip Flop irrespective of main inputs,
prior to its working/operation, hence the name given Clear. Once initial known state is
obtained, Clear is kept now in Clear=1 condition for normal operation of Flip Flop. So Clear
RESET the initial condition prior to the working of Flip Flop with CLR=0.
Once the state of the flip Flop is established asynchronously, the direct inputs Preset and Clear
must be connected to 1, before next clock or main inputs are applied. Figure 4.30 shows logic
symbol of Flip Flop with Preset and Clear. The bubble used with Preset and Clear indicates that
these are Active Low control signal i.e. its function will be performed when it is in low state 0.
Figure 4.31 Symbol of Flip Flops with Preset and Clear signal
Figure 4.32 Master Slave Flip Flops with Preset and Clear signal
The interval of time required after an input signal has been applied for the resulting output
change to occur.
Different signals take different paths through the logic gates. Four categories of propagation
delay:
c) Propagation delay measured from leading edge of preset input to low to high transition
of the output.
d) Propagation delay measured from the leading edge of the clear input to the high to low
transition of the output.
2) Set-up Time:
The minimum amount of time required for the logic levels to be maintained constantly on the
inputs (J and K, or S and R, or D) prior to the triggering edge of the clock pulse in order for the
levels to be reliably clocked into the flip-flop.
3) Hold Time:
The minimum amount of time required for the logic levels to remain on the inputs after the
triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
To convert one type of flip-flop into another type, a combinational circuit is designed such that
if the inputs of the required flip-flop (along with the outputs of the actual flip-flop if required)
are fed as inputs to the combinational circuit and the output of the combinational circuit is
connected to the inputs of the actual flip-flop, then the output of the actual flip-flop is the
output of the required flip-flop.
In other words, it means that, to convert one type of flip-flop into another type, we have to
obtain the expressions for the inputs of the existing flip-flop in terms of the inputs of the
required flip-flop and the present state variables of the existing flip-flop and implement them.
The arrangement is as shown in figure 4.36.
Here, the external inputs to the already available S-R flip-flop will be J and K. S and R are the
outputs of the combinational circuit, which are also the actual inputs to the S-R flip-flop.
We write a truth table with J, K, Qn, Qn+1, S and R, where Qn is the present state of the flip-flop
and Qn+1 is next state of the flip-flop before the application of the inputs and Qn+1 refers to the
state obtained by the flip-flop after the application of inputs.
J, K and Qn can have eight combinations. For each combination of J, K and Q n, find the
corresponding Qn+1, i.e. determine to which next state (Qn+1) the J-K flip-flop will go from the
present state Qn if the present inputs J and K are applied.
Now complete the table by writing the values of S and R required to get each Q n+1 from the
corresponding Qn, i.e. write what values of S and R are required to change the state of the flip-
flop from Qn to Qn+1.
The conversion table, the K-maps for S and R in terms of J, K and Qn and the logic diagram
showing the conversion from S-R to J-K are shown in figure 4.37.
Here, the external inputs to the already available J-K flip-flop will be S and R. J and K are the
outputs of the combinational circuit, which are also the actual inputs to the J-K flip-flop.
So, we have to get the values of J and K in terms of S, R, and Q n. thus, write a table using S, R,
Qn, Qn+1, J and K. the external inputs S and R and the present output Qn can make eight possible
combinations. For each combination find the corresponding next state Qn+1.
In the S-R flip-flop, the combination S=1 and R=1 is not permitted. So, the corresponding output
is invalid and therefore, the corresponding J and K are don’t cares. Complete the table by
writing the values of J and K required to get each Qn+1 from the corresponding Qn.
The conversion table, the K-maps for J and K in terms of S, R and Qn and the logic diagram
showing the conversion from J-K to S-R are shown in figure 4.38.
Here S-R flip-flop is available and we want the operation of D flip-flop from it. So D is the
external input and the outputs of the combinational circuit are the inputs to the available S-R
flip-flop. Express the inputs of the existing flip-flops S and R in terms of the external input D and
the present state Qn.
The conversion table, the K-maps for S and R in terms of D and Qn and the logic diagram
showing the conversion from S-R to D are shown in figure 4.39.
Here D flip-flop is available and we want the operation of S-R flip-flop from it. So S and R is the
external input and D is the actual input to the existing flip-flop. S, R and Qn make eight possible
combinations, but S=R=1 is an invalid combination. So, the corresponding entries for Qn+1 and D
are don’t cares. Express D in terms of S, R and Qn.
The conversion table, the K-maps for D in terms of S-R and Qn and the logic diagram showing
the conversion from D to S-R are shown in figure 4.40.
Here J-K flip-flop is available and we want the operation of T flip-flop from it. So T is the
external input and J and K are the actual inputs to the existing flip-flop. T and Qn make four
combinations. Express J and K in terms of T and Qn.
The conversion table, the K-maps for J and K in terms of T and Qn and the logic diagram showing
the conversion from J-K to T are shown in figure 4.41.
Here J-K flip-flop is available and we want the operation of D flip-flop from it. So D is the
external input and J and K are the actual inputs to the existing flip-flop. D and Qn make four
combinations. Express J and K in terms of D and Qn.
The conversion table, the K-maps for J and K in terms of D and Qn and the logic diagram
showing the conversion from J-J to D are shown in figure 4.42.
Here D flip-flop is available and we want the operation of J-K flip-flop from it. So J-K is the
external input, i.e. inputs to the combinational circuit and D is the actual input to the existing
flip-flop.
J, K and Qn make eight combinations. Express the input of the existing flip-flop D in terms of
external inputs J, K and present state Qn.
The conversion table, the K-maps for D in terms of J, K and Qn and the logic diagram showing
the conversion from J-J to D are shown in figure 4.43.
4.3 Register
A Register is a set of Flip Flops to store Binary information. As a Flip Flop can able to store one
bit either “0” or “1”, it can be considered as one bit Register. When more bits of data are to be
stored, numbers of Flip Flops are used. A group of Flip Flops constitutes a Register.
The storage capacity of a Register is the number of bits (data) it can retain or store. To store
bits (data) into the Register, these data is to be loaded either in serial or parallel. Loading of
Register means SETTING or RESETTING of Flip Flops of Register. Loading may be in serial or
parallel form.
In serial loading data transferred into Register one by one in serial fashion. In parallel loading
data transferred/entered into Register in parallel form i.e. all the data entered at the same
time. A Register may output the data in serial or parallel form.
Buffer Register:
Some registers do nothing than storing a binary information/data. Buffer register is a simplest
form of registers which is simply used to store binary information. Most of buffer register use
“D Flip Flop”.
Figure 4.44 shows buffer register. The binary word which is to be stored is applied to the input
terminal of D Flip Flop. On application of clock pulse all the data will be loaded into the register
and because of D Flip Flop used, output will be same as input.
Buffer register can be controlled by external combinational gates also, such that we can store
the data at a particular time and also able to clear the previous data to load new data into the
register.
Shift Register:
A register may input and output data in serial or parallel form. It can also shift the data left or
right. A number of Flip Flops connected together in such a way that data may be shifted into
and out of the register is called Shift register.
The number of individual data Flip Flop/latches required to make up a single Shift Register
device is usually determined by the number of bits to be stored. The most common being 8-
bits (one byte) wide constructed from eight individual data latches.
The Shift Register is used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format. The individual data
latches that make up a single shift register are all driven by a common clock signal making them
synchronous devices.
Shift register IC’s are generally provided with a CLEAR or RESET connection so that they can be
“SET” or “RESET” as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register.
Depending upon data entered into the register and output taken from register, there are four
basic types of shift register.
Figure 4.45 All the possible ways of input and output from shift register
The data is shifted serially “IN” and “OUT” of the register, one bit at a time in either a left or
right direction under clock control.
The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal. The logic circuit diagram in Figure 4.46 shows a generalized serial-in serial-out shift
register.
This type of Shift Register also acts as a temporary storage device or as a time delay device for
the data, with the amount of time delay being controlled by the number of stages in the
register, 4, 8, 16 etc. or by varying the application of the clock pulses. Commonly available IC’s
include the 74HC595 8-bit Serial-in to Serial-out Shift Register all with 3-state outputs.
Figure 4.47 and Figure 4.48 shows truth table and timing diagram/waveforms for Serial input
serial output shift Register, indicating how data stored and shifted within this register.
Truth Table:
For example, the data input to the register is D=1111. From the truth table it has been observed
that after 4 clock pulses are required to store complete binary word “1111” within the register.
Now if we need output serially then another 4 clock pulses are required to obtain output
serially. In total 8 clock pulses are required to obtain 4 bit data word serially, if data input is in
serial form. So speed of operation is slower in SISO shift register.
Timing Diagram/waveform:
Before application of clock signal let Q0 Q1 Q2 Q3 = 0000 and apply LSB bit of the number to
be entered to Din. So Din= D3=1. Apply the clock. On the first leading edge of clock, the FF-3 is
set, and stored word in the register is Q0 Q1 Q2 Q3 = 1000.
Apply the next bit to Din. So Din=1. As soon as the next positive edge of the clock hits, FF-2 will
set and the stored word change to Q0 Q1 Q2 Q3 = 1100.
Apply the next bit to be stored i.e. 1 to Din. Apply the clock pulse. As soon as the third positive
clock edge hits, FF-1 will be set and output will be modified to Q0 Q1 Q2 Q3 = 1110.
Similarly with Din=1 and with the fourth positive clock edge arriving, the stored word in the
register is Q0 Q1 Q2 Q3 = 1111.
In such types of operations, the data is entered serially and taken out in parallel fashion. Data is
loaded bit by bit. The outputs are disabled as long as the data is loading. As soon as the data
loading gets completed, all the flip-flops contain their required data; the outputs are enabled so
that all the loaded data is made available over all the output lines at the same time. 4 clock
cycles are required to load a four bit word serially. After loading and shifting all the data will be
available simultaneously because of parallel output.
The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format in which all the data bits
enter their inputs simultaneously, to the parallel input of the register. The data is then read out
sequentially in the normal shift-right mode from the register.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this system a clock pulse is not required to parallel load the register as it is
already present, but four clock pulses are required to unload the data.
As this type of shift register converts parallel data, into serial format, it can be used to
multiplex many different input lines into a single serial DATA stream which can be sent directly
to a computer or transmitted over a communications line. Commonly available IC’s include the
74HC166 8-bit Parallel-in/Serial-out Shift Registers.
The circuit shown below is a four bit parallel input serial output register. Output of previous Flip
Flop is connected to the input of the next one via a combinational circuit. The binary input
word D0, D1, D2, D3 is applied though the same combinational circuit.
There are two modes in which this circuit can work namely shift mode or load mode.
When the shift/load bar line is low (0), the AND gate 2, 4 and 6 become active. They will pass
D1, D2, D3 bits to the corresponding flip-flops. On the positive going edge of clock, the binary
input D0, D1, D2, D3 will get loaded into the corresponding flip-flops. Thus parallel loading
takes place.
When the shift/load bar line is high (1), the AND gate 2, 4 and 6 become inactive. Hence the
parallel loading of the data becomes impossible. But the AND gate 1, 3 and 5 become active.
Therefore the shifting of data takes place from left to right bit by bit upon application of clock
pulses. Thus the parallel in serial out operation take place.
In this mode, the 4 bit binary input D0, D1, D2, D3 is applied to the data inputs respectively of
the four D flip-flops. As soon as a Positive clock edge is applied, the input binary bits will be
loaded into the flip-flops simultaneously. The loaded bits will appear simultaneously to the
output side. Only 1 clock pulse is essential to load all the bits.
If a binary number is shifted left by one position then it is equivalent to multiplying the original
number by 2. Similarly if a binary number is shifted right by one position then it is equivalent to
dividing the original number by 2.
Hence if we want to use the shift register to multiply and divide the given binary number, then
we should be able to move the data in either left or right direction. Such a register is called as a
bi-directional register. A four bit bi-directional shift register is shown in Figure 4.53
There is one input which can load the data serially from left side or right side which is
connected to AND gate 1 and 8. One control signal RIGHT / ̅̅̅̅̅̅̅ used to operate register in
either of two modes:
Working:
If RIGHT/̅̅̅̅̅̅̅ = 1, then the AND gates 1, 3, 5 and 7 are enable whereas the remaining AND
gates 2, 4, 6 & 8 will be disabled
The data at input is shifted to right bit by bit from FF-3 to FF-0 on the application of clock
pulses. Thus with RIGHT/̅̅̅̅̅̅̅ = 1 we get the serial right shift operation
When the mode control RIGHT/̅̅̅̅̅̅̅ is connected to 0 then the AND gates 2, 4, 6 & 8 are
enabled while 1, 3, 5 & 7 are disabled.
The data at DL is shifted left bit by bit from FF-0 to FF-3 on the application of clock pulses. Thus
with RIGHT/̅̅̅̅̅̅̅= 0 we get the serial left shift operation.
A shift register which can shift the data in only one direction is called a uni-directional shift
register. A shift register which can shift the data in both directions is called a bi-directional shift
register. Applying the same logic, a shift register which can shift the data in both directions as
well as load it parallely, then it is known as a universal shift register.
1. Parallel loading
2. Left shifting
3. Right shifting
The mode control input is connected to logic 1 for parallel loading operation whereas it is
connected to 0 for serial shifting. With mode control pin connected to ground, the universal
shift register acts as a bi-directional register. For serial left operation, the input is applied to the
serial input which goes to AND gate-1 shown in figure 4.54 whereas for the shift right
operation, the serial input is applied to D input.
Today, there are many high speed bi-directional “universal” type Shift Registers available such
as the TTL 74LS194, 74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices
that can be used in either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-
to-serial, and as a parallel-to-parallel multifunction data register, hence the name “Universal”.
These universal shift registers can perform any combination of parallel and serial input to
output operations but require additional inputs to specify desired function and to pre-load and
reset the device. A commonly used universal shift register is the TTL 74LS194 as shown in figure
4.55.
Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory, delay information such as the SISO
or PIPO configuration modes or transfer data from one point to another in either a serial or
parallel format. Universal shift registers are frequently used in arithmetic operations to shift
data to the left or right for multiplication or division .
4.4 Counter:
A counter is a digital sequential logic device that will go through a certain predefined states (for
example counting up or down) based on the application of the input pulses. They are utilized in
almost all computers and digital electronics systems.
Counting is frequently required in digital computers and other digital systems to record the
number of events occurring in a specified interval of time. Normally an electronic counter is
used for counting the number of pulses coming at the input line in a specified time period. The
counter must possess memory since it has to remember its past states. As with other sequential
logic circuits counters can be synchronous or asynchronous.
If we broadly classify the counter then it can be classified as (1) Asynchronous counters and
(2) Synchronous counters
As the name suggests, it is a circuit which counts. The main purpose of the counter is to record
the number of occurrence of some input. There are many types of counter both binary and
decimal. Some of commonly used counters are for example….
JK Flip Flop and T Flip Flops are preferred for the design of various counters.
This counter counts the number of clock pulses applied to it. In this type of counter each Flip
Flop is triggered by the output of previous flip flop (except the first Flip Flop). In this type of
counter, all the Flip Flop does not change the states in exact synchronism with clock pulse.
Only first Flip Flop responds to the input clock pulse. So it is known as Asynchronous counter.
It is also known as Ripple counter because of the manner in which it operates. Because Flip
Flop-1 responds to the external input pulse, then second Flip Flop-2 has to wait for Flip Flop-1
to change states before it toggles. Flip Flop-3 has to wait for Flip Flop-2 and so on.
This counter can be designed using T Flip Flop or J-K Flip Flop easily. It can be also considered
as serial or series counter. A counter may count up or count down or count up and down
depending on the input control. So a counter may be Up counter or a Down counter.
The number of states through which counter passes before returning to the starting state is
called modules of the counter (or mod of counter). Hence modules or mod of a counter is
equal to the number of states (counts), a counter can store (including zero state). If n is
number of Flip Flops used in counter then mod of the counter equals to 2 n.
For example a: A two bit counter which requires two Flip Flop has four states 00, 01, 10 and
11. So it is called a Mod-4 counter. It divides the input clock frequency by 4. So it is also called
divide-by-4 counter.
Asynchronous counters are slower than synchronous counters because of the delay in the
transmission of the pulses from flip-flop to flip-flop.
This type of counters has JK Flop-Flops arranged in a way that the output of one flip-flop feeds
the clock of the following flip-flop as shown in the figure 4.56 with associated wave form. Flip
Flop used is negative edge triggered JK Flip Flop (T Flip Flop can be also used).
Figure 4.56 Two bit binary Ripple Up Counter with wave form & count table
Figure 4.57 Four bit binary Ripple Up Counter with wave form
Design of 2 Bit Binary Up counter using positive edge triggered JK Flip Flop:
(2 Bit Binary Ripple Up counter)/ (Mod-4 counter)/ (divide-by-4 counter)
This type of counters has JK Flop-Flops arranged in a way that the output of one flip-flop feeds
the clock of the following flip-flop as shown in the figure 4.59 with associated wave form. Flip
Flop used is positive edge triggered JK Flip Flop (T Flip Flop can be also used).
Figure 4.59 Two Bit Ripple Up Counter with wave form & count sequence
Design of 3 Bit Binary Up counter using positive edge triggered JK Flip Flop:
(3 Bit Binary Ripple Up counter)/ (Mod-8 counter)/ (divide-by-8 counter)
This type of counters has JK Flop-Flops arranged in a way that the output of one flip-flop feeds
the clock of the following flip-flop as shown in the figure 4.60 with associated wave form. Flip
Flop used is positive edge triggered JK Flip Flop (T Flip Flop can be also used).
Figure 4.61 Three Bit Ripple Up Counter with wave form & count sequence
Figure 4.62 Three Bit Ripple Down Counter with wave form
This type of counters has JK Flop-Flops arranged in a way that the output of one flip-flop feeds
the clock of the following flip-flop as shown in the figure 4.62 with associated wave form. Flip
Flop used is negative edge triggered JK Flip Flop (T Flip Flop can be also used).
In Asynchronous counter external clock is given to only first flip flop and remaining all flip flops
receives clock from output of previous flip flop. Input is JK=1 common to all Flip Flops. Output
frequency of last flip flop is 1/8 of the applied clock frequency so it is called frequency divider
counter. In the same way a four bit counter is known as divide by 16 counters. If number of
Flip-Flops are “n” the maximum counting capability is given as N = 2n – 1.
Figure 4.64 shows Up/Down Counter using negative edge triggered J-K Flip Flop. Counter can
be designed using T Flip Flop also. It is programmable counter because When Up=1 and
Down=0, it counts upward. When Up=0 and Down=1, it counts downward.
We can design the MOD 3 counter using 2 FFs as 3 is less than 4 i.e. 22 and greater than 2. We
can see directly that as we have to reset the counter only after 2 i.e. when output is 3 we reset
the counter and hence we need to reset only when we have Q0= 1 & Q1=1. Now firstly design
MOD-4 counter using 2 FFs and then take NAND of Q0 & Q1 and feed the output to CLEAR of
both FFs.
To reset the Counter, now if we draw a table to list the different input combinations to
Combinational circuit and their corresponding output as:
̅̅̅̅ ̅̅̅̅ ̅̅̅̅̅̅̅̅ (Which is NAND of Q0 and Q1) as per De-Morgan’s Theorem
We can design the MOD 6 counter using 3 FFs as 6 is less than 8 i.e. 2 3 and greater than 4. We
can see directly that as we have to reset the counter only after 5 i.e. when output is 6 (i.e.
Q2Q1Q0=110) we reset the counter and hence we need to reset only when we have Q0= 0,
Q1=1 & Q2=1. Now firstly design MOD-8 counter using 3 FFs and then take NAND of Q1 & Q2
and feed the output to CLEAR of all the FFs.
And now we draw the table to represent the desired output of the combinational circuit to
reset FFs as:
̅̅̅̅ ̅̅̅̅ ̅̅̅̅̅̅̅̅ (Which is NAND of Q2 and Q1) as per De-Morgan’s Theorem
Mod-6 counter will count up to 6 states, starting from 000 to 101. Flip Flop used here is
negative edge triggered JK Flip Flop.
We can design the MOD 10 counter using 4 FFs as 10 is less than 16 i.e. 24 and greater than 8.
We can see directly that as we have to reset the counter only after 9 i.e. when output is 10
(i.e. Q3Q2Q1Q0=1010) we reset the counter and hence we need to reset only when we have
Q0= 0, Q1=1, Q2=0 & Q3=1. Now firstly design MOD-16 counter using 4 FFs and then take
NAND of Q0, Q2 & Q3 and feed the output to CLEAR of all the FFs.
A mod-10 counter is also referred as “Decade Counter”. A decade counter is any counter that
has 10 distinct states, no matter what is the sequence. A decade counter as shown in figure
which counts sequence from 0000 (Zero) to 1001 (Decimal Nine) is also called BCD counter
because it uses only 10 BCD group codes.
It is also known as Parallel Counter because all the Flip Flop responds to the external input
pulse simultaneously in synchronism.
This counter can be designed using T Flip Flop or JK Flip Flop easily. A counter may count up or
count down or count up and down depending on the input control. So a counter may be Up
counter or a Down counter.
The number of states through which counter passes before returning to the starting state is
called modules of the counter (or mod of counter). Hence modules or mod of a counter is
equal to the number of states (counts), a counter can store (including zero state). If n is number
of Flip Flops used in counter then mod of the counter equals to 2 n.
For example a: A two bit counter which requires two Flip Flop has four states 00, 01, 10 and 11.
So it is called a Mod-4 counter. It divides the input clock frequency by 4. So it is also called
divide-by-4 counter.
Excitation Table:
Characteristic tables/Truth Table provides the next state when the inputs and the present state
are known. When designing digital circuits, using flip-flops one is usually given the present state
and the next state. So inputs are required to be derived from present state and next state. For
this reason we use excitation tables, which indicate the inputs required to change output from
one state to another. Excitation table is very useful in design of counters.
Synchronous counter, in contrast to an asynchronous counter, is one whose output bits change
state simultaneously, with no ripple. This counter can be easily designed using either J-K or T
Flip Flop. Positive edged triggered Flip Flop or Negative edge triggered Flip Flop can be used.
Two Flip Flops are required for 2 bit counter which counts the four states 00, 01, 10, 11 and
repeat the same sequence again, so it is also called Mod-4 counter. As frequency of last flip flop
is ¼ of input clock frequency, it is also called divide by 4 counter. As clock is common to all the
flip flops, it is also called parallel counter. Figure.2 show two bit synchronous up counter using
J-K Flip Flop.
Excitation Table of J-K Flip Flop:
Present Next Inputs
State State
Q Q(t+1) J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
Prof. A. H. Pambhar, EC Department | 2131004 – Digital Electronics 61
Unit: 4 – Flip-Flops, Counters and Registers
Two bit synchronous Up Counter using Positive edge triggered J-K Flip Flop:
Figure 4.71 Two bit synchronous Up Counter using Positive edge triggered J-K Flip Flop
Figure 4.72 Timing Diagram for Two bit synchronous Up Counter using Positive edge triggered J-K Flip Flop
Two bit synchronous Up Counter using Negative edge triggered J-K Flip Flop:
Figure 4.73 Two bit synchronous Up Counter using Negative edge triggered J-K Flip Flop
Figure 4.74 Timing Diagram for Two bit synchronous Up Counter using Negative edge triggered J-K Flip Flop
Two bit synchronous Up Counter using Negative edge triggered T Flip Flop (T flip is equivalent
to JK Flip flop with J and K inputs are connected to gather) :
Figure 4.75 Two bit synchronous Up Counter with Negative edge triggered Flip Flop
In Synchronous counter clock is common to all the Flip Flops. Output frequency of last flip flop
is ¼ of the applied clock frequency so it is called frequency divider counter. In the same way a
four bit counter is known as divide by 16 counters. If number of Flip Flops are n the maximum
counting capability is given as N = 2n – 1.
Figure 4.76 shows Up/Down Counter using positive edge triggered JK Flip Flop. It is
programmable counter because when control signal Up/ = 1, it work as Up Counter and
when control signal Up/ = 0, it works as Down Counter.
Three bit synchronous Up Counter using Positive edge triggered T Flip Flop (or
using J-K Flip Flop with identical J, K inputs)
Synchronous counter, in contrast to an asynchronous counter, is one whose output bits change
state simultaneously, with no ripple. This counter can be easily designed using either J-K or T
Flip Flop. Positive edged triggered Flip Flop or Negative edge triggered Flip Flop can be used.
Three Flip Flops are required for 3 bit counter which counts the eight states 000, 001, 010, 011,
100, 101, 110, 111 and repeat the same sequence again, so it is also called Mod-8 counter. As
frequency of last flip flop is 1/8 of input clock frequency, it is also called divide by 8 counter. As
clock is common to all the flip flops, it is also called parallel counter.
Figure 4.77 shows state table and K-map derived for T Flip Flops. Equations derived from K-map
are the required inputs of T Flip Flop. If JK Flip Flop is used then T Flip Flop can be derived from
JK Flip Flop by shorting both J and K inputs.
Figure 4.77 Three bit synchronous Up Counter with state stable, K-Map & design Equation
In Synchronous counter clock is common to all the Flip Flops. Output frequency of last flip flop
is 1/8 of the applied clock frequency so it is called frequency divider counter. In the same way a
four bit counter is known as divide by 16 counters. If number of Flip Flops are n the maximum
counting capability is given as N = 2n – 1. Here it counts from 000 to 111 for up counting and
111 to 000 for down counting.
Counter can be designed using T Flip Flop also. Figure 4.78 shows Up/Down Counter using
positive edge triggered T Flip Flop. It is programmable counter because when control signal
Up/ = 1, it work as Up Counter and when control signal Up/ = 0, it works as Down
Counter.
Design equations:
TQ0 = 1
TQ1 = (Q0.Up) + (Q0'.Up')
TQ2 = (Q0.Q1.Up) + (Q0'.Q1'.Up')
Four bit synchronous Up Counter using Positive edge triggered T Flip Flop (or
using J-K Flip Flop with identical J, K inputs)
Synchronous counter, in contrast to an asynchronous counter, is one whose output bits change
state simultaneously, with no ripple. This counter can be easily designed using either J-K or T
Flip Flop. Positive edged triggered Flip Flop or Negative edge triggered Flip Flop can be used.
Four Flip Flops are required for 4 bit counter which counts the eight states from 0000 to 1111
and repeat the same sequence again, so it is also called Mod-16 counter. As frequency of last
flip flop is 1/16 of input clock frequency, it is also called divide by 16 counter. As clock is
Prof. A. H. Pambhar, EC Department | 2131004 – Digital Electronics 67
Unit: 4 – Flip-Flops, Counters and Registers
Figure 4.79 shows circuit diagram and design equations derived from K-map, required at inputs
of T Flip Flop. If JK Flip Flop is used then T Flip Flop can be derived from JK Flip Flop by shorting
both J and K inputs.
Design Equations:
Synchronous counter, in contrast to an asynchronous counter, is one whose output bits change
state simultaneously, with no ripple. This counter can be easily designed using either J-K or T
Flip Flop. Positive edged triggered Flip Flop or Negative edge triggered Flip Flop can be used.
We can design the MOD 10 counter using 4 FFs as 10 is less than 16 i.e. 24 and greater than 8. A
mod-10 counter is also referred as “Decade Counter”. A decade counter is any counter that has
10 distinct states, no matter what is the sequence. A decade counter as shown in figure which
counts sequence from 0000 (Zero) to 1001 (Decimal Nine) is also called BCD counter because it
uses only 10 BCD group codes.
Figure 4.80 shows circuit diagram and design equations derived from K-map, required at inputs
of T Flip Flop. If JK Flip Flop is used then T Flip Flop can be derived from JK Flip Flop by shorting
both J and K inputs.
Clock pulse Q3 Q2 Q1 Q0
Initially 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 (recycle) 0 0 0 0
Design Equations:
T0 = 1
T1 = Q3'.Q0
T2 = Q1.Q0
T3 = Q2.Q1.Q0 + Q3.Q0
Ring Counter:
The output of the last stage is connected to the D input of the first stage.
An n-bit ring counter cycles through n states.
No decoding gates are required, as there is an output that corresponds to every state the
counter is in.
Preset Control signal of 1st Flip Flop is connected to 0 to set the Flip Flop.
Clear control signal of all the remaining Flip Flop except 1st flip flop is connected to 0 to reset
the flip flop.
Normally Preset and Clear control signals are connected to 1.
Figure 4.82 State Table & State Diagram of 6-bit Ring Counter
Johnson Counter:
The complement of the output of the last stage is connected back to the D input of the first
stage.
Also called the twisted-ring counter.
Require fewer flip-flops than ring counters but more flip-flops than binary counters.
An n-bit Johnson counter cycles through 2n states.
Require more decoding circuitry than ring counter but less than binary counters.
State: Each of the outputs of a sequential circuit is called its state. For e.g. a flip-flop have 2
states: 0 & 1.
State Table: The time sequence of inputs, outputs & the flip-flop states may be written in a
table called state table. It is also called transition table.
State diagram: The information available in a state table may be represented graphically in a
state diagram. In this diagram, a state is represented by a circle & the transition between states
is indicated by directed lines connecting the circles.
State equation: It is an algebraic expression that specifies the conditions for a flip-flop state
transition. It is also known as application equation.
The left side of the equation denotes the next state of a flip-flop & the right side, a Boolean
function that specifies the present state condition that makes the next state equal to 1. The
state equation is derived directly from a state table.
Input & output equations: The part of the circuit that generates the inputs to the flip-flops is
described algebraically by a set of Boolean functions called flip-flop input function.
The part of combinational circuit that generates external outputs is described algebraically by
the circuit output functions.
For ex: JA = BC’x + y ; KA = B + x are input functions
y = AB’x is output function
State Machine: State machine also called a sequential machine is a system that can be
described in terms of set of states that the system may enter. Once in a particular state, the
system may be capable of remaining in that state for some finite period of time even if the
system inputs change.
Prof. A. H. Pambhar, EC Department | 2131004 – Digital Electronics 1
Unit: 5 – Introduction to State Machines
As the system progresses from one state to another, the next state reached depends on the
inputs & present state. The outputs also depend on inputs & present state.
A set of n flip-flops can produce 2n possible unique output codes and thus could have 2n
possible unique states of existence. Hence n lines driven by combinational variables can also
take on 2n different unique codes, but these are not states since they cannot exist
independently of the input variable. A set of n flip-flops can exist in a particular state different
from the set of input values, and this is the requirement of state machine. They are also known
as Finite State Machines (FSM).
If a state machine changes state in response to clock & all inputs are synchronous, we will
classify that circuit as synchronous system.
If the state changes occur in response to clock but one or more inputs are not clock driven, the
machine will be called mainly synchronous system.
If the state changes are input-driven rather than clock-driven, the system is asynchronous one.
(i) The state machine design method leads to minimal design. This method results in the
minimum no. of flip-flops & it can minimize other circuitry in the system as well.
(ii) It is a well-developed, orderly procedure that anticipates & solves commonly occurring
problems like unwanted narrow pulse or glitches & occasional oscillations can be removed.
(iii) It reduces the time taken to debug the implemented hardware & can be applied to the
solution of a wide variety of practical circuit problems.
A sequential machine or a state machine must possess memory capability. Generally, clocked
flip-flops are used as storage elements. The code that defines each state then corresponds
directly to the code contained by the flip-flops.
1. Mealy machine
2. Moore machine
A Mealy machine is the one in which the output depends on the present state as well as the
inputs of the circuit. The input forming logic (IFL) and the output forming logic (OFL) are made
up of combinational logic circuits. The memory section contains the state of the system. A path
is provided from memory output to the IFL.
Both input signals and the present state signals drive the IFL to determine the next state of the
system. The outputs are determined by the present state & system inputs. The general model
of a Mealy machine is shown as below:
A Moore machine is the one in which the output depends only on the present state of the
system. The only difference between Mealy & Moore machine is that in Moore machine, the
outputs are determined only by the present state. There is no effect of input directly on the
output state. The general model of Moore machine is shown as below:
The output depends only the present state. The output depends on the present state as well
Z(t)= g {s(t)} as input. Z(t)= g{s(t),x(t)}
Input changes do not affect the output. Input changes may affect the output of the
circuit.
It requires more number of states for It requires less number of states for
implementing the same function. implementing same function.
Problems like input transients & glitches do not Problem like input transients & glitches are
affect the output. directly conveyed to the output.
The characteristic table defines the logical properties of flip-flop & completely characterizes its
operation. It defines the next state when the inputs & present states are known.
The table which gives the flip-flop input condition that will cause the required transition from
present state to next state is known as excitation table.
Excitation tables:
(i) SR flip-flop:
Qn Qn+1 S R
0 0 0 X
0 1 1 0
1 0 0 1
1 1 X 0
(ii) JK flip-flop:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
(iii) D flip-flop:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
(iv) T flip-flop:
Qn Qn+1 T
0 0 0
0 1 1
1 0 1
1 1 0
Here, X represents don’t-care condition which means the input can either be 1 or 0.
The behavior of a sequential circuit is determined from the inputs, the outputs and the states of its
flip-flops. Both the output and the next state are a function of the inputs and the present state.
The suggested analysis procedure of a sequential circuit is set out in below Figure.
We start with the logic schematic from which we can derive excitation equations for each flip-
flop input.
Then, to obtain next-state equations, we insert the excitation equations into the characteristic
equations. The output equations can be derived from the schematic, and once we have our
output and next-state equations, we can generate the next-state and output tables as well as
state diagrams.
When we reach this stage, we use either the table or the state diagram to develop a timing
diagram which can be verified through simulation.
Sequential circuits are divided into two main types: synchronous and asynchronous. Their
classification depends on the timing of their signals.
Synchronous sequential circuits change their states and output values at discrete instants of
time, which are specified by the rising and falling edge of a free-running clock signal.
The memory elements used in synchronous sequential circuits are usually flip-flops. These
circuits are binary cells capable of storing one bit of information. Synchronous sequential
circuits are also known as clocked sequential circuits.
In asynchronous sequential circuits, the transition from one state to another is initiated by the
change in the primary inputs; there is no external synchronization. The memory commonly
used in asynchronous sequential circuits is time-delayed devices, usually implemented by
feedback among logic gates.
The design of a synchronous sequential circuit starts from a set of specifications and culminates
in a logic diagram or a list of Boolean functions from which a logic diagram can be obtained. In
contrast to a combinational logic, which is fully specified by a truth table, a sequential circuit
requires a state table for its specification.
The first step in the design of sequential circuits is to obtain a state table or an equivalence
representation, such as a state diagram.
A synchronous sequential circuit is made up of flip-flops and combinational gates. The design of
the circuit consists of choosing the flip-flops and then finding the combinational structure
which, together with the flip-flops, produces a circuit that fulfills the required specifications.
The number of flip-flops is determined from the number of states needed in the circuit.
The recommended steps for the design of sequential circuits are set out below.
For example, the sequence of states desired might be 000, 011, 101, 111, 100, 000, 011 . . .
Incorrect information is set into the flip-flops if we do not observe this specification. Thus the
output of the flip-flop will be an ambiguous (not clear or decided) state. This must be avoided
to achieve reliable state machine operation.
For synchronous input signals, driven by a clock transition, the state change must take place
long enough after the clock transition to allow the flip-flop inputs to settle & the data-to-clock
setup time to be satisfied. There are 2 methods used to delay the state changes sufficiently:
In the AST scheme, the state changes are caused to occur on the alternate clock transition to
input data changes. If the data changes are driven on the positive clock transition, the state
changes must take place on the negative clock transition. Data changes on the negative clock
transition dictate positive clock transition changes.
For a 50% duty cycle clock, the AST method allows one-half of the clock period between input
change & state change. Hence in equation form,
𝑇
> 𝑡𝑐𝑑 + 𝑡𝑝𝑙𝐹𝐿 + 𝑡𝑠𝑢
2
The maximum usable clock frequency can then be found as:
1 1
𝑓= <
𝑇 2(𝑡𝑐𝑑 + 𝑡𝑝𝑙𝐹𝐿 + 𝑡𝑠𝑢 )
In the DST system, the same clock transition drives both the data changes & the state changes,
but the clock signal to the state flip-flops is delayed. The number of delaying inverters used
between the clock and the flip-flops is determined by two factors: the total clock delay tt and
the correct number of inversions.
Generally the AST method is sued for synchronous state machines. This method is more
popular in state machine design except for situations involving very critical timing problems.
The traditional method of IFL design uses gates. This method is very significant in applications
using standard IC chips. When IFL is constructed from gates, this circuitry can be minimized by
the following 2 principles:
Principle 1: States having the same next state for a given input condition should have
logically adjacent state assignments.
Principle 2: States that are next states of a single state should have logically adjacent
assignments.
The IFL of the state machine can be designed with MUXs instead of gates. The general
arrangement of the direct-addressed MUX system is as shown below. Although the IFL shown
consists of gates & MUXs, the gates often are either very simple or not required at all.
In this scheme, the outputs of the state flip-flops are connected to the select lines of all MUXs
in parallel. Each state then addresses a different set of MUX inputs. One MUX is required for
each state flip-flop and each MUX must have n select lines, where n is the number of state flip-
flops. A direct-addressed MUX design requires n - 2n : 1 MUXs to design the IFL.
Disadvantage:
A conditional output is the one which depend not only on the system state, but also requires
certain input conditions before the output is asserted.
An unconditional output is one that depends only on the state of the system. When a particular
state is entered, an AND gate or IC decoder reflects this fact by asserting an output line. It is
also known as immediate output.
In OFL design, there are 2 bases upon which state assignment may be made.
(i) For minimizing no. of gates required to implement the design, a decoder chip is used to
generate state machine outputs. Although it is often more costly, but this approach can
minimize chip count especially if several outputs are generated.
The flip-flop outputs are directly connected to the decode inputs leading to the assertion of
a particular line in each state. The decoder output lines corresponding to all states
producing the same output signal are ORed to generate the output.
Glitches or slivers are very narrow pulses, often having a width of few nanoseconds, which
occur during the switching of variables. They are also referred to as “runt” pulses.
The output forming logic is driven by the state flip-flops. Although the state-changing clock
transition is applied simultaneously to all state flip-flops, due to differences in clock-to-
output delay times, the flip-flop outputs will not change at exactly the same time. Since
these outputs drive gates or decoders, the possibility of glitches must be considered.
There are applications in which glitches can be tolerated. When an output drives a slow-
responding device, glitches may be allowable. For example, when an output is taken from a
light-emitting diode (LED), a short glitch may not affect the output of the state machine.
Here, glitch is tolerable and there is no requirement of further design to eliminate glitch.
Many digital controllers require outputs to drive digital circuits such as counters o flip-flops.
In such a case, the output must occur only at specified time. Here, glitch is not tolerated and
glitch-free design is essential to produce a reliable system in this type of application.
a) The unequal switching times of the state flip-flops that drive the OFL
b) Due to conditional outputs
The state diagram is essential in the hardware design of the system and hence after the timing
chart, the system design can proceed to the development of the state diagram. A trial-and-
error procedure is often the most efficient method to be used.
Here, X and Y are the system inputs and the clock signal is also shown. The system does not give
the output as long as X & Y are simultaneously 0. We have to develop a state diagram to
implement this timing chart with a minimum number of states and without using counters.
All state changes must take place on the positive-going transitions of the clock since the inputs
change on the negative transition.
The output assertions begin at the positive transition of the clock
In state machine design, one of the first tools used is the state diagram. Some of these
diagrams may contain extra or redundant states that could be eliminated to decrease the
design complexity. In a state machine, two major tasks are completed during each stage:
I Equivalent states: If a state machine is started from either of two states and identical output
sequences are generated from every possible set of input sequences, the two states are said to
be identical.
II Redundant states: A state that is equivalent to another state is called a redundant state.
The redundant states can be removed. Hence a reduced state diagram contains no equivalent
states. There is an orderly method available to identify and eliminate redundant states. This
method is a simplified version of a more complex method that is generally applied to
asynchronous system.
For practical synchronous systems, the following method is often sufficient to create the
reduced state diagram.
Actually, the simplified method of reducing states does not guarantee a minimal no. of states.
More complex method can be carried out by executing the following steps:
a) Reduce the state table as far as possible using the simple method.
b) Group states having equivalent outputs together.
c) Within each group, eliminate those states that are not potentially equivalent.
d) Within each group, assume the equivalence of every possible pair of states.
The general state machine architecture consists of input forming logic, memory and
output forming logic. The next state and the outputs are generated according to the
design.
The output holding register is added to latch the outputs into this register at the
midpoint of the state machine or after the state flip-flops settle. This arrangement is
used to filter out the glitches from the output decoder.
The methods of state machine design are based on the use of minimum number of state flip-
flops. If m states are required to implement a sequential controller, the no of state flip-flops
required n, is found by selecting the minimum value of n to satisfy: 2n ≥ m
This approach minimizes hardware requirements but there are certain disadvantages in certain
applications.
In sequential controllers for digital computers, there is often a need for the state machine to be
in 2 states simultaneously. Since, conventional state machines always exist in a single unique
state at any given time, only one series of operations can be controlled.
The “one-hot” state machine, which associates each state with the assertion of a specific state
flip-flop, can solve this problem. In a sequential system that progresses through a series of
unique states, only one flip-flop is asserted during each stage. However, if two states must exist
simultaneously, two flip-flops can be asserted. The output signals produced by each state flip-
flop can then be used to control two operations simultaneously.
These types of system allow the implementation of the fork and join operations in digital
controllers. The figure below shows the idea of forking and jerking in a state machine
controller.
The state machine progresses from state a to b. at this point, depending on an input, the
system creates two states, c and g, that exist during t3. Two states also exist during t4 (d and h)
and during t5 (e and i). As t6 is entered, the system returns to a single state f. during time slots t3
, t4 & t5 , two separate processes can be controlled concurrently.
Synchronous and asynchronous state machines can be design according to the application.
There are various advantages & disadvantages of both the systems.
Here, X and Y are the system inputs while Z is the system output. The signal Z is fed back to a
gate input to determine its new value.
There is always a delay from change in X or Y to change in Z. the addition of delay times of both
the inputs X and Y leads to change in Z signal. It is possible to force a change in feedback
variable Z, by changing system input.
The fundamental-mode model is used for the analysis of asynchronous digital circuits. The
model for the above circuit is as shown. Here, the gates are considered to have no delay in this
model, while the delay element has an output that follows its input after a delay of ∆t.
The variable at the input of the delay element is called the excitation variable, while the
feedback variable appears at the output of the delay element. This model produces the delay
of the feedback variable but predicts no delay between input and output. The overall behavior
of the actual circuit can be predicted rather accurately applying this particular model.
1. Hazards
A glitch is when a signal temporary takes on the wrong value. Glitches caused by structure of
circuit and propagation delays are called hazards.
a) Static Hazards
When signal is not supposed to change its value in response to a specific change in an input,
but instead momentarily does change is known as static hazard.
b) Dynamic Hazards
This is when a signal is supposed to change value, but there is a small oscillation.
A change to a primary input often has more than one path of propagation to an output.
When one path has a longer propagation delay than the others, we may find a static hazard.
This can be eliminated by examining the K-map of the output. A potential hazard exists
whenever two adjacent ones (or 0’s if we are doing a product-of-sum implementation) are
not covered by a common product term (sum term for product-of-sum).
To guarantee no static hazards, obtain a cover such that each pair of adjacent one’s (zero’s)
is covered by a common product term (sum term).
A dynamic hazard is caused by the structure of a circuit. It is caused by a circuit with more
than two levels, in which changes to an input have more than one path to propagate. A
circuit with a dynamic hazard must also contain a static hazard
2. Oscillations
A second problem that can occur in a poorly designed circuit is that of oscillation. Consider the
excitation map as shown below.
If the system is in state a, a change of input from B = 0 to B = 1 sends the system to state c.
State c is the transient state, and thus the excitation variable X changes to 1.
A short time later, x changes to 1, moving the system to state d. This state is also the
transient state changing back X to 0, followed by change in x to 0.
The system now oscillates between states c and d. this is known as oscillation and is
unacceptable in most systems. Hence, the situation depicted by states c and d of the map
must be avoided.
3. Critical races
A third problem in asynchronous design is that of critical races. This situation can occur only
when two or more feedback variables are present in the system. The below figure
demonstrates the critical race problem.
This system has two external inputs, A and B, and two excitation variables, X and Y, that are
feedback to the input of the circuit.
Due to unequal propagation delays, one of the excitation variables will reach a value of 1,
while the other has not changed from a value of 0. The final stable state reached from this
condition depends on the relative switching speeds of variables X and Y. This situation is
referred to as critical race.
In some cases, a final state is never reached. Such a situation is also called critical race.
Critical races obviously must be avoided.
Hence, in designing asynchronous circuits, hazards, oscillations and critical races must be
avoided.
For designing a system, we are given only the system behavior. There may be several different
circuits that can satisfy the specifications. We generally can define the stable states in the
system. We then must add transient or cycle states to cause the system to sequence through
the proper states without introducing any critical races.
Then, a primitive excitation table having only one stable state per row is produced. Once, the
feedback variables are assigned, the excitation variables for the stable states are also
determined. The transient states are not fixed at this point and can be selected to eliminate
races or oscillations.
Thereafter, expressions for the excitation variables are written and the circuit is implemented.
The logic families TTL, ECL, IIL, MOS & CMOS are currently in use.
The TTL & CMOS are suitable for Small Scale Integration (SSI) & Medium Scale Integration (MSI).
The MOS & CMOS are particularly suitable for Large Scale Integration (LSI).
The IIL is mainly suitable for Very Large Scale Integration (VLSI) & Ultra Large Scale Integration (ULSI).
The logic families currently used are compared as follows;
Fig. 8.1: Voltage range at input and output side of NOT gate
The high noise margin & low noise margin are as shown below:
Advantages
It is a non-saturated logic, in the sense that the transistors are not allowed to go into saturation. So,
storage time delays are eliminated and, therefore, the speed of operation is increased.
Currents are kept high, and the output impedance is so low that circuit & stray capacitances can be
quickly charged & discharged.
It has limited voltage swing between LOW & HIGH voltage levels.
Disadvantages
High Cost
Low Noise Margin
High Power Dissipation
Its negative supply voltage and logic levels are not compatible with other logic families (making it
difficult to use ECL in conjunction with TTL and MOS circuits)
Problem of cooling
Application
The circuit shown below is of inverter/buffer which used Current Mode Logic (CML).
This circuit has both an inverting output (OUT1) and a non-inverting output (OUT2).
Two transistors are connected as a differential amplifier with common emitter resistor.
There are two cases for NOT gate;
o Case – 1: When VIN is HIGH, transistor Q1 is ON, but not saturated, and transistor Q2 is OFF. This
is true because of careful choice of resistor values and voltage levels. Thus VOUT2 is pulled to 5.0
V (HIGH) through R2, and it can be shown that the voltage drop across R1 is about 0.8 V, so that
VOUT1 is about 4.2 V (LOW).
o Case – 2: When VIN is LOW, as shown in figure, transistor Q2 is ON, but not saturated, and
transistor Q1 is OFF. Thus, VOUT1 is pulled to 5.0 V through R1, and it can be shown that VOUT2
is about 4.2 V.
Fig. 8.4(a)
Fig. 8.4(b)
Advantages
Disadvantages
The operating speed of MOS is slower than TTL, so, they are hardly used in SSI and MSI applications
Because of the very high impedance present at MOSFET’s input, the MOS logic families are
susceptible to static charge damage.
Both NMOS & PMOS have greater packing density than that of CMOS, and are therefore, more
economical than CMOS.
The CMOS family has more complex architecture compared to NMOS & PMOS family.
CMOS possesses the important advantages of higher speed & much lower power dissipation
compared to NMOS & PMOS family.
CMOS family has improved noise margin compared to NMOS & PMOS family.
In the N MOS NAND gate shown, Q1 is acting as a load resistor and Q2 and Q3 as awitches controlled
by input levels A and B res[ectively.
When both A and B are 0 V, both Q2 and Q3 are OFF. So the equivalent circuit 8.6 (b) results with
Vout = + 5 V.
When both A = 0 V and B = + 5 V, both Q2 is OFF and Q3 is ON. So the equivalent circuit 8.6 (b) results
with Vout = + 5 V.
When both A = + 5 V and B = 0 V, both Q2 is ON and Q3 is OFF. So the equivalent circuit 8.6 (b) results
with Vout = + 5 V.
When both A = + 5 V and B = + 5 V, both Q2 and Q3 are ON. So the equivalent circuit 8.6 (b) results
with Vout = 0 V.
Thus the above circuit works as positive logic two inputs two input NAND gate.
When A is LOW and B is LOW, Q2 is OFF and Q3 is OFF, so the equivalent circuit (b) results with Vout
= + 5 V.
When A is LOW and B is HIGH, Q2 is OFF and Q3 is ON, so the equivalent circuit (b) results with Vout
= 0 V.
When A is LOW and B is LOW, Q2 is ON and Q3 is OFF, so the equivalent circuit (b) results with Vout
= 0 V.
When A is LOW and B is LOW, Q2 is ON and Q3 is ON, so the equivalent circuit (b) results with Vout
= 0 V.
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 8
Unit: 8 – Logic Families
The operation of any circuit depends on IC chips used & electrical connection between chips.
No access to internal interconnections of IC chips.
To design circuit, internal circuit diagram is to be specified.
Once designed, the intended function can be performed.
If the function changes, design needs to modified.
So the internal circuit diagram needs to be changed.
Such systems are called HARDWIRED SYSTEM.
2. Programmable Circuit
PLD is an IC chip that includes arrays of logic elements and allows a user to specify the
connections among many of these elements.
1. Advantages:
Chip count & physical size of a system can be minimized.
Time from conception of system to marketing of the system can be minimized.
Less chip count leads to integration of system on a single chip or small no. of chips.
Low development cost.
Less space requirement.
High reliability.
Easy circuit testing.
Easy design modification.
2. Disadvantages:
Interconnections between elements on the chip must be specified or programmed.
PLDs also have hard wired connection but they cannot function until they are programmed while
Hardwired System functions.
3. More complex
FPGA (Field Programmable Gate Arrays)
CPLD (Complex Programmable Logic Devices)
9.2.1.1 OR Array:
OR Array is as shown in below figure. In OR Array initially all the links are connected by Fusible Link.
According to the required output functions one needs to program the OR Array IC.
In OR Array all the required output functions can be taken out from the OR gates as shown in figure.
Burn the Fusible Link in each array, which connections are not required as shown in below figure.
AND Array is as shown in below figure. In AND Array initially all the links are connected by Fusible
Link.
According to the required output functions one needs to program the AND Array IC.
In AND Array all the required output functions can be taken out from the AND gates as shown in
below figure.
Burn the Fusible Link in each array, which connections are not required as shown in below figure.
ROM Consists of an array of semiconductor devices interconnected to store an array of binary data.
Can’t be changed once burned in.
Conceptually, consist of a decoder and a memory array.
Advantages:
1. Design become extremely easy.
2. It is possible to change or modify the design quickly.
3. Reduced cost.
4. Modification takes less time than SSI/MSI circuits.
Disadvantages:
1. Increase in power requirement.
2. Complete circuit is not utilizes
3. Increase in size with increase in number of input variables.
EXAMPLE 1: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four
Boolean functions:
A(X,Y,Z) = ∑m(1,3,4,6)
B(X,Y,Z) = ∑m(2,4,5,7)
C(X,Y,Z) = ∑m(0,1,5,7)
D(X,Y,Z) = ∑m(1,2,3,4)
ANS:
Here, total No. of inputs are three A,B,C
Total No. of outputs are four A,B,C,D
ROM size is = 8 X 4 So, according 2n X m Inputs = n = 3, Output = m = 4,
Size of Decoder = n X 2n = 3 X 8
INPUT OUTPUT
A B C D
X’Y’Z’(000) 0 0 1 0
X’Y’Z (001) 1 0 1 1
X’YZ’ (010) 0 1 0 1
X’YZ (011) 1 0 0 1
XY’Z’ (100) 1 1 0 1
XY’Z (101) 0 1 1 0
XYZ’ (110) 1 0 0 0
XYZ (111) 0 1 1 0
ANS:
F3 = D7 + D5 + D2 = A2A0 + A2’A1A0’
F2 = D7 + D0 = A2A1A0 + A2’A1’A0’
F1 = D4 + D1 = A2 A1’A0’ + A2’A1’A0
F0 = D7 + D5 + D1 = A2A0 + A1’A0
EXAMPLE 3: Tabulate the truth for an 8 X 4 ROM / PROM that implements the following four
Boolean functions:
A(X,Y,Z) = ∑m(3,6,7);
B(X,Y,Z) = ∑m(0,1,4,5,6)
C(X,Y,Z) = ∑m(2,3,4);
D(X,Y,Z) = ∑m(2,3,4,7)
ANS:
ROM size is = 8 X 4 So, according 2n X m Inputs = n = 3, Output = m = 4,
Size of Decoder = n X 2n = 3 X 8
Inputs are X,Y,Z
Outputs are A,B,C,D
ANS:
ROM size is = 8 X 4 So, according 2n X m Inputs = n = 3, Output = m = 4,
Size of Decoder = n X 2n = 3 X 8
Inputs are A,B,C
Outputs are F1,F2,F3,F4 Here, F4 is not given so mark all the connection for F4 with X.
INPUT OUTPUT
F1 F2 F3 F4
A’B’C’(000) 0 0 1 X
A’B’C(001) 0 1 0 X
A’BC’ (010) 0 1 0 X
A’BC (011) 1 1 0 X
AB’C’ (100) 0 0 0 X
AB’C (101) 1 0 0 X
ABC’ (110) 1 0 0 X
ABC (111) 0 0 1 X
ANS:
Here, Inputs are A,B
Outputs are F1,F2,F3
F1 = D0 + D1 + D3
F2 = D2
F3 = D1 + D2
EXAMPLE 6: Using ROM / PROM, Implement the logic design that generates gray code for given 4
bit binary input.
ANS:
Here, 4 bit gray code is to be designed for 4 bit binary input
So, Inputs are (n) A,B,C,D
Outputs are (m) W,X,Y,Z
ANS:
ROM size is = 8 X 2 So, according 2n X m Inputs = n = 3, Output = m = 2,
Size of Decoder = n X 2n = 3 X 8
Inputs are X,Y,Z
Outputs are S (SUM), C (CARRY)
So, S = ∑(1,2,4,7) = D1 + D2 + D4 + D7
C = ∑(3,5,6,7) = D3 + D5 + D6 + D7
ANS:
ROM size is = 8 X 2 So, according 2n X m Inputs = n = 3, Output = m = 2,
Size of Decoder = n X 2n = 3 X 8
Inputs are X,Y,Z
Outputs are S (SUBTRACT), B (BORROW)
So, S = ∑(1,2,4,7) = D1 + D2 + D4 + D7
C = ∑(3,5,6,7) = D1 + D2 + D3 + D7
EXAMPLE 9: Using 8 X 6 ROM / PROM implement design that generates square of the input at the
output.
ANS:
ROM size is = 8 X 6 So, according 2n X m Inputs = n = 3, Output = m = 6,
Size of Decoder = n X 2n = 3 X 8
PAL is most commonly used type of PLD. It is a programmable array of logic gates.
The array of logic gates is on single chip and it is in the AND-OR configuration.
The special feature of PLA is that a programmable AND array and fixed OR array.
Also note that in each OR gate in the OR array gets input from some of the AND gates. That means
output of all AND gates are not applied to any of the OR gates.
Basic block diagram is shown as below.
Fusible Link
Fig. 9.7: Un-programmed PAL
In Un-programmed PAL all the links are connected with Fusible Link as shown in below figure.
As per required output function one needs to burn the fusible link and this kind of PAL is known
as a programmed PAL.
Simplified representation of PAL is shown in below figure.
i. Input Buffers:
Input buffer in a PAL is used for avoiding the loading of sources connected at the inputs.
The buffer produce inverted and non-inverted versions of their corresponding inputs.
One such buffer is used for each of the input lines as shown in above figure.
iii. OR Matrix:
OR matrix is shown as above figure. In PAL fixed OR array is used so there is no need to do
programming to the OR array.
No. of OR arrays are equal to the required No. of functions at the output.
The input and output circuit of PAL are similar to those PLAs.
The No. of fusible link in PAL is equal to 2M x n. where M = No. of available inputs and n =
Corresponds to No. of product terms.
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 15
Unit: 9 – Programmable Logic Devices
Advantages:
1. For given internal complexity, a PAL can have larger N and M.
2. Some PALs have outputs that can be complemented, adding POS functions.
3. No multilevel circuit implementations in ROM (without external connections from output to
input). PAL has outputs from OR terms as internal inputs to all AND terms, making
implementation of multi-level circuits easier.
Disadvantages:
1. n x m ROM guaranteed to implement any m functions of n inputs. PAL may have too few
inputs to the OR gates.
NOTE: Out of first three steps, all three steps may not require in all examples
EXAMPLE 1: A combinational circuit is defined by given truth Table for that Implement the circuit
using PAL.
ANS:
STEP 4: List of product terms for each of the function and decide total No. of AND & OR gates
required.
W = A + BD + BC
X = BC’
Y=B+C
Z = A’B’C’D + BCD + AD’ + B’CD’
Total No. of AND gate = 16 (B’cz maximum No. of product terms are in function Z (4 product
terms) and total No. of functions are 4 so 4 X 4 = 16).
Total No. of OR gates = Total No. of required functions at the output side (W,X,Y,Z) = 4.
Prof. Bhavesh S. Bhensdadiya, EC Department | 2131004 – Digital Electronics 17
Unit: 9 – Programmable Logic Devices
STEP 5: Decide connections of AND and OR matrix & draw logic diagram.
ANS:
STEP 3: Find the Boolean expressions using K-map or reducing Boolean expression method.
This step is not required in this example.
STEP 4: List of product terms for each of the function and decide total No. of AND & OR gates
required.
Y = S1’S0’D0 + S1’S0D1 + S1S0’D2 + S1S0D3
Total No. of AND gate = 4 (B’cz No. of product terms in function Y = 4 (S 1’S0’D0, S1’S0D1, S1S0’D2,
S1S0D3).
Total No. of OR gates = Total No. of required functions at the output side (Y) = 1.
STEP 5: Decide connections of AND and OR matrix & draw logic diagram.
A PLD generally consist of programmable array of logic gates. Interconnections are made with the
array inputs.
PLA consist two levels of logic, an AND-plane and an OR-plane, where both levels are programmable.
The outputs are connected to the device pins through inverting or non-inverting buffers and flip
flops.
The basic block diagram of a PLA is shown in below figure.
Here programmable AND matrix can be used to implement the product terms in the SOP form and
the programmable OR array can be used for implementing the sum of the product terms.
Logic gates used can be two level AND-OR, NAND-NAND or NOR-NOR configuration. Sometimes
AND-OR-EXOR configuration is also used. But generally AND-OR is most preferable configuration.
Simplified representation of PLA is shown in below figure.
1. Input Buffers:
Input buffer in PLA is used for avoiding the loading of sources connected at the inputs.
Buffer of two types namely, inverted buffers and non-inverted buffers as shown in below figure.
One such buffer is used in each of the M input lines.
2. AND Matrix:
The X indicates that a connection is present. Each AND gate has 2M inputs which are shown only by
single line where, M is No. of inputs (e.g. A,B,C, etc….).
When a logic function is to be implemented, we have to program the array. In programming the
desired connections are left with the (X) marks and such mark is not used when connection is not
required.
3. OR Matrix:
Applications of PLA:
1. We can implement combinational circuit using PLA. For this only ouput buffers are used.
2. We can also implement sequential circuit using PLA. For implement this flip flops and buffers are
included in output stage.
NOTE: Out of first three steps, all three steps may not require in all examples
EXAMPLE 1: Draw combinational circuit for a PLA with three inputs, three product terms and two
outputs.
ANS:
Given No. of inputs = 3 = I0, I1, I2
No. of Outputs = 2 = No. of OR gates.
NO. of product terms = No. of AND gates.
EXAMPLE 2: calculate the Inputs, Product terms and Outputs for 16 x 48 x 8 PLA.
ANS:
According to the size of PLA = M x P x N = 16 x 48 x 8
So No. of inputs = M = 16
No. of output = N = 8
No. of product terms = P = 48
ANS:
STEP 1: Prepare the Truth Table.
This step is not required in this example.
STEP 3: Reduce the Boolean expressions using K-map or reducing Boolean expression method.
For F1:
F1 = AB’ + AC
For F2:
F2 = AC + BC
STEP 6: Decide connections of AND and OR matix & draw logic diagram.
EXAMPLE 4: A combinational circuit is defined by given truth Table for that Implement the circuit
using PLA.
ANS:
STEP 1: Prepare the Truth Table.
This step is not required in this example because it is given.
STEP 3: Find the Boolean expressions using K-map or reducing Boolean expression method.
STEP 6: Decide connections of AND and OR matix & draw logic diagram.
According to the size of PLA = M x P x N
So No. of inputs = M = 4 (A,B,C,D) = No. of input Buffers
B X X X X X
X X
C X X X X
X X
D X X X
X X
W
X X X
X
X
Y
X X
Z
X X X X
ANS:
STEP 1: Prepare the Truth Table.
This step is not required in this example.
STEP 3: Reduce the Boolean expressions using K-map or reducing Boolean expression method.
For F1:
F1 = A’B + AC’
For F2:
F2 = (AC’ + B’C)’
F2 = (AC’)’ (B’C)’
F2 = (A’ + C’’) (B’’ + C’)
F2= (A’ + C) (B + C’)
F2 = A’B + A’C’ + BC + CC’
F2 = A’B + A’C’ + BC
STEP 6: Decide connections of AND and OR matix & draw logic diagram.
EXAMPLE 6: Implement following equations using PLA with use of 4 inputs, 6 AND plane & 3 OR
plane.
X = ABC + B’D’ + AB’D + C’D’
Y = BC + D’
Z = CD + B’D’ + A’BC
ANS:
STEP 3: Reduce the Boolean expressions using K-map or reducing Boolean expression method.
STEP 6: Decide connections of AND and OR matix & draw logic diagram.
Multiple copies of CLB slices are arranged in a matrix on the surface of the chip
CLBs are connected column-wise & row-wise.
At the intersections of columns & rows are programmable switch matrices.
In this figure the output of one CLB is connected with the inputs of two other CLBs.
The signal passes through three PIs and two PSMs.
PSMs make the FPGA versatile, but they slow down the signals.
There are extra routes for e.g. reset lines or clock lines.
Input/Output Blocks are used to get the signals into the FPGA and out of the FPGA.
Fig. shows simplified IOB. Each IOB can be used as input & output depending on the state of the
Output Enable (OE).
If OE is set to one, then IOB acts as an output, otherwise as an input.
IOBs contain D Flip Flops for latching the input & output signals. The latches can be bypassed by
appropriately programmed MUXs.
EXERCISE:
EXAMPLE 1: Design a combinational logic circuit using ROM / PROM, the circuit accepts the three
bit binary number and generates its equivalent excess 3 code.
EXAMPLE 6: Design a BCD to Excess-3 code converter and implement it using PAL.
EXAMPLE 8: Implement 3-bit binary to gray code & 3-bit Gray code to binary converter using PLA.
EXAMPLE 13: Implement 3-bit Gray code to binary converter using PLA.