Integrated Circuit Fabrication Technology

• Reference

Semiconductor Devices
By Mauro Zambuto
 WAFER PREPARATION
Crystal Growing
• In the most popular crystal-growing processes the refined material is
first melted and then brought back to solid state temperatures in the
presence of a properly oriented seed crystal. During this process, the
appropriate amount of dopant is added to the high-purity
semiconductor material.
• Several techniques are in common use:
• the Czochralski technique
• the float zone process
• the Bridgman technique
 The Czochralski Technique
• Precisely measured quantities of dopant
are added to the melt to obtain an
extrinsic semiconductor of the required
resistivity.
• The computation of the quantity of
dopant for each melt is complicated by
the fact that the dopant concentration in
the solid phase equals that of the liquid
phase times an equilibrium segregation
coefficient depending on both dopant
and host materials.
 Segregation Coefficient

Following are some of the most common dopants

and their equilibrium segregation coefficients (in parentheses):

Host N-type P-type

Si P (0.35); As (0.3) B (0.8)

GaAs Se (0.1); Si (2) Zn (0.42)
• Less contaminated boules are obtained
by the float zone process, in which the
refined polycrystalline material is
originally made into a rod.
• A small region of the rod is then
melted by localized· heating through a
small RF coil, while the rod is slowly
rotated.
• Such narrow zone melting starts at the
bottom of the rod, where a seed crystal is
located to determine the crystallographic
orientation. The RF coil is then slowly
raised, so that the molten zone moves
toward the top of the rod, while the lower
layers, no longer under RF radiation.
solidify into a single crystal
 The float zone process

• There is no crucible and so no

contamination source. Good doping
uniformity is achieved.
• Very low levels of contamination can
be obtained by the float zone
process, especially by repeated
recrystallizations through several
passes, so the process is often used
for high-resistivity devices.
 Epitaxial Growth
• The wafers to be epitaxially coated,
supported by a graphite susceptor, are intro-
duced into an induction oven, where the
susceptor is heated by RF energy to a
temperature below the substrate melting
point (about 1200°C for Si).
• The oven atmosphere is a gas mixture,
pumped as a continuous flow by a system of
pipes which permit a precise control of its
composition, rate of flow, temperature, etc.
Epitaxy on Si substrates is based on the
reversible reaction

2H2 + SiCl4 4HCI + Si

 Epitaxial Growth and Etching

• The ratio y is the SiCl4 concentration

to the total molecular concentration of
the gas atmosphere (mole fraction).
• At low values of y the rate of growth is
seen to increase linearly with y; then
the plot begins to deviate from
linearity, reaching a maximum
around y = 0.11. For y > 0.28 the
rate of growth actually becomes
negative, resulting in etching instead
of epitaxial growth. This behavior is
due to the reaction
SiCl4 + Si = 2SiCl2
 Liquid Phase Epitaxy
• In this technique the material
that will form the epitaxial
layer is dissolved in a solvent.
• The temperature is then
slowly dropped until the
solution is slightly
supersaturated.
• When the substrate is put in
contact with this solution,
the material precipitates
forming the epitaxial layer.
 Molecular Beam Epitaxy
• The different constituent of
the layer to be grown
(including the impurities) are
evaporated, each in its
individual effusion oven.
• The ovens are arranged inside
a high vacuum chamber
housing the substrate on its
rotating support.
• Each oven is calibrated to obtain a
specific evaporation rate of the
component in it, yielding a gas that
leaves the effusion oven in the form of
a thermal molecular beam of the
desired properties for optimal
deposition of that constituent.
• The corresponding constituent is
deposited on the substrate.
• Down to a resolution of single-
molecule layers. This technique can be
used, for instance, to obtain extremely
accurate doping profiles.
 Oxidation
• Layers of Si02 (and some other
materials) are used as insulators,
dielectrics, protective films, and, at
several fabrication stages, as masks,
passivators, inhibitors.,
• placed in a quartz tube, which is
slowly inserted into a furnace,
heated by resistive elements to
temperatures usually between 900 and
l200°C.
 Oxidation
• A controlled flow of an oxidant
atmosphere is maintained through
the tube.
• Flow rate of the oxidant
atmosphere, time of exposure,
entry, and withdrawal rate into
and from the furnace, and gas
composition are all automatically
and carefully controlled.
 Dry Oxidation
• Dry oxidation occurs in an oxygen atmosphere according to the
reaction

• The rate of growth is slow, but the oxide layers are very uniform,
relatively free from defects, and electrically very reliable.
• The process is used for thin dielectric layers, such as required in
MOSFET fabrication and often referred to as gate oxides
 Wet Oxidation
• Wet oxidation uses a steam atmosphere.

• The reaction yields much higher rates of growth with layers well
suited for insulation, protection, and masking applications
• But not as free of microscopic faults as dry oxidation products, Such
layers are often referred to as field oxides.
 Sio2 Formation
• As the wafer surface is oxidized, the next Si molecules to react with
the oxidizing agent are those in the next deeper lattice layer of the
crystal, so the silicon interface moves deeper and deeper into the crystal.
• when a Si02 layer of thickness x is formed, the Si interface moves into the
crystal by only 0.4x, so the insulating layer grows partly into and partly
above the original Si crystal.
 Rate of Growth
• The molecules of the oxidizing agent, in order to react with more Si,
must first reach the Si interface, crossing the already generated Si02
layer. This penetration occurs by solid state diffusion, so the rate at
which new Si02 is produced
• (the rate of growth) is influenced both by the diffusion rate (the time
required to diffuse through the oxide, depending on the diffusion
coefficient D) and by the speed at which the atoms react (the reaction
rate coefficient r).
 Oxide Thickness
• The thickness of the oxide layer after oxidation of duration t is expressed
by

• where A, B, and t are constants related to the characteristics of the

oxidation process
Linear rate constant vs Temperature
Parabolic rate constant vs Temperature
 Reaction controlled Oxidation
• A simple mathematical analysis shows that, in the reaction
controlled domain, growth is essentially linear in time
• For reaction controlled oxidation (thin oxide layers: x<< A/2, short
duration oxidation), 4B(t + t )/A2 << 1 and the last main equation can
be approximated by

• showing that growth is linear with linear rate constant B/A.

 Diffusion controlled Oxidation
• In the diffusion controlled domain, growth follows a parabolic time
variation.
• For diffusion controlled oxidation (thick oxide layers: x>> A/2, long
duration of oxidation), 4B(t + t ) >> 1 and last main equation becomes

• showing that growth is parabolic with parabolic rate constant B.

 Rate Constants Computer Calculations
For computer calculations, the rate constants can be obtained
analytically
Rate Constant = R∞ e-Ea/ kT

• in which Ea (known as the activation energy) is indicated for

each case in the previous Figure, k = 8.625 x10 e-5 eV/K is
Boltzmann's constant.
 R∞ Values

• For process design, the following values of R∞ yield satisfactory

results:
• Linear rate:
• R∞ depends on type of process and on the crystal's surface
orientation and has the following values in micrometers per hour:

• Parabolic rate:
• Dry oxidation: R∞= 810 µm2/h
• Wet oxidation: R∞= 243 µm2/h
 Calculation of t
• Process design also requires computation of the constant t

• where A and B can be computed from the linear and parabolic rate constants
and xo is the oxide thickness at the beginning of the process, so that the
equation implies that an oxide layer of thickness xo is already present on the
substrate before the oxidation process begins
• In conclusion, for the purposes of practical computations, for dry oxidation, xo
can be assumed to be 200 A°. For wet oxidation instead, xo (and so t) can be
assumed to be 0.
 Oxidation of a Non Uniform Surface
• It is evident that prolonged oxidation will soon result in a coating of
essentially uniform thickness over the whole face of the specimen,
practically eliminating the initial oxide step at the surface.
• Several fabrication sequences take advantage of this phenomenon to
produce essentially uniform oxide coatings without having to strip
previous coatings from the specimen's surface.
 Chemical Vapor Deposition (CVD)

• CVD ovens are similar to oxidation furnaces and so are the physical
processing steps. Chemically, however, oven atmospheres are
different and the insulating layer is deposited from the vapor phase
above the surface of the substrate.
 CVD Different Processes
• Energy-enhanced CVD, in which deposition occurs in the presence of an
electric field or other source of energy (such as ultraviolet radiation, electron
beam, etc.
• Si02 layers can also be obtained by CVD processes. These oxides are usually
inferior to those obtained by oxidation. In Si-based devices they are used for special
purposes, for instance when low-temperature processing is mandated.

• Silicon nitride, deposited by CVD, is often used for its high dielectric constant and its
chemical and physicochemical properties.

• Strongly doped polysilicon layers are often obtained by CVD. They are used as
electrodes, because of their superior resistance to high temperatures and because of
other favorable properties
 THE PHOTOLITHOGRAPHIC STEP
• Often, certain fabrication processes must be limited to well-defined
regions of the device. Then these regions must be precisely delimited and
the rest of the device must be protected, so as not to be affected by
the action of the fabrication process.
• This is most often done by a photolithographic step, which creates a
protective mask capable of selectively inhibiting the specific process in
certain regions while leaving other parts of the device open to its action.
• In practice, to achieve this end, a whole sequence of masks is usually
created. In a typical sequence, a photomask is used to create a
photoresist mask, which is in turn used to produce a Si02 mask.
 The Photomask

• Once the designer has determined which regions of the device must be
exposed to a subsequent process (such as etching) and which parts must
be protected from it,
• An appropriate photomask is made. This is a pattern in which the regions
to be exposed are opaque and the ones to be protected are transparent
(or vice versa, depending on the subsequent processing). A typical
photomask is shown in the following Figure.
• A whole variety of photomask production techniques are used.
Transistor Fabrication
 PhotoMask Fabrication
• The pattern features may be appropriately programmed on a computer,
which produces the mask by driving a scribing beam of electrons to
expose the photographic plate directly.
• In all cases, the final product is a plate, similar to a photographic transpar-
ency. The minimum detail size to be reproduced determines the required
resolution.
• Many technological problems are connected with the need for cleanliness
and registration in the preparation and use of these photomasks
 The Photoresist Mask
• The pattern is transferred from the optical mask to a photoresist coating on
the wafer surface by optical printing.
• A typical photoresist film consists of an organic material soluble in some
solvent. If a region of this film is exposed to light (usually ultraviolet) .
When developed, i.e. treated with the solvent, the unexposed regions of
the film are washed away in the bath, but the exposed ones remain,
forming an image.
• The portions of the wafer under the exposed regions are covered by a
polymerized film; the rest of the wafer surface is left unprotected.
 The Photoresist Mask
• The photoresist just described is of the negative type (regions exposed to
light become insoluble). A positive photoresist is originally exposed to
light become insoluble.
• The photoresist is originally in the liquid state. It is spread over the
surface to be processed by the spinner and dries to a thin film adhering
to the SiO2.
• Exposure of the photoresist is a photographic printing process. The light
used is commonly ultraviolet.
• After exposure the photoresist mask is developed by the removal of
the soluble portion by washing with a solvent
Photolithography
 Silicon Dioxide and Other Insulator Masks
• Once the photoresist mask is in place, the next localized fabrication
process can be performed. This is very often the etching of an insulating
layer to produce an insulator mask (most often consisting of SiO2).
• Where the SiO2 layer comes in contact with the solution it is etched away,
leaving the underlying semiconductor surface exposed, but where the
Si02 is protected by the photoresist mask, it remains intact.
• The photoresist is then stripped away by oxidizing or dissolving it, leaving
only the Si02 mask.
• The final result is therefore a SiO2 mask, exactly reproducing the pattern
of the photoresist mask.
In practice, the wet etching action does not occur only in the direction
perpendicular to the SiO2 surface.
Some etching spreads parallel to this surface under the photoresist, eating away
some SiO2 near the edges of the photoresist mask, as shown in Figure. This limits the
resolution of SiO2 masks produced by the wet etching technique.
 Importance of Photolithography
• Economically, the already mentioned problem of registration of the
relative positioning of subsequent masks is critically important.
• The final cost of fabrication and the percentage yield of acceptable
devices are strongly influenced by the number of photolithographic steps
required during the complete fabrication cycle, so that the minimization
of such steps is one important criterion in device fabrication design
 Localized Doping
• Accurately controlled concentrations of impurities can be obtained during
wafer preparation by appropriately doping the melt. By such methods,
however, it is extremely difficult to produce precisely localized varia-
tions in doping, such as those required in PN junctions.
• This is generally achieved by introducing the impurity atoms into the
semiconductor crystal in the solid state, i.e. operating at temperatures
below the melting point.
• The process is localized by means of suitable protective masks. The
two main methods used are:
• Solid state diffusion (a high-temperature process)
• Ion implantation (a low-temperature process)
 Diffusion
• Selected regions of the semiconductor
crystal surface are exposed to high
concentrations of dopant atoms under
conditions assuring reasonably high
diffusivity (e.g., high temperature).
• The impurity atoms then enter into
solid solution at the crystal surface and
from there diffuse into the body of the
crystal.
Diffusion ovens are similar to oxidation furnaces, but the gas atmosphere consists
of an appropriate chemical compound of the desired impurity. The dopant source
can be a solid, liquid, or gas.
 Diffusion Process
• The source is exposed to the flow of an inert
gas, which flushes away with it the high
concentrated amount of the source's
molecules.
• The Figure is an example of a liquid source
diffusion apparatus.
• The resulting dopant-enriched gas, mixed, if
necessary, with other active and/or inert
gases, is pumped into the oven containing
the wafers.
• At the oven temperature, the gases in the
mixture react with each other and with the
wafer material, wherever this is left exposed
by the SiO2 mask.
 Solid Solubility
• The surface concentration of the
dopant after dissolution depends on the
dopant and semiconductor species
(e.g., B and Si), on the oven
temperature and on the partial
pressure of the doping gas. If the latter
is high enough, the dopant
concentration equals the solid solubility
No. Solid solubility curves are shown in
Figure for several dopants in Si.
 Concentration Distribution
• The high concentration of dopant
atoms in the solid solution at the
surface now creates a concentration
gradient, which in turn results in
diffusion of the dopant molecules
into the body of the semiconductor
• As time elapses, the dopant
molecules penetrate deeper and
deeper into the semiconductor and
the extrinsic layer generated
becomes thicker
 Doping Profile
• Notice that the surface concentration
remains constant because the atoms
migrating by diffusion are replaced as new
atoms enter the surface solution from the
external dopant atmosphere.
• The impurity concentration N(x) decreases
from the surface into the crystal body to
maintain diffusion and so a doping profile is
created, as shown in Figure.
• Notice that, may be the substrate is
already extrinsic, with a uniform dopant
background concentration NBG. Where N(x)
= NBG and so the semiconductor changes
type, is the junction depth xd.
 Predeposition
• Diffusion occurring under the condition
described above is known as
predeposition. For given conditions the
doping profile (and with it the junction
depth) extends deeper into the crystal
the longer the duration of the diffusion
process, but the surface doping No is
independent of this duration.
 Drive-In Diffusion
• It is often desirable to alter the doping profile, making it smoother; then a
second diffusion process is applied: drive-in diffusion
• Technologically this process is identical to predeposition, except that the
gas atmosphere in the oven now consists of inert gases exclusively and
does not contain any dopant.
• As surface dopant molecules migrate by diffusion, they are no longer
replaced from the outside. Therefore, as the process progresses, the
surface impurity concentration decreases, the doped layer is driven
deeper into the crystal and so, in most cases, is the junction depth.
 Concentration as a function of Depth
• In the continuity equation solution of this differential equation yields the
concentration N of impurity atoms at any depth x duration t. The doping profile so
obtained depends on the diffusivity D and on the boundary conditions.

• Where

• where Ea is the activation energy in electron volts and k = 8.625 x 10-5 eV/K is
Boltzmann's constant
 Predeposition
• The boundary conditions are N(0) = No ; N(∞) = 0, where No can
usually be assumed to equal the solid state solubility. The solution of
the partial differential equation becomes

• An important characteristic of the predeposition process is the

impurity dose:
 Predeposition with Back Ground Doping
• The impurity dose represents the total number of impurity atoms that
have been injected into the crystal per unit exposed surface area over a
predeposition duration t. This quantity is important in computing drive in
diffusion profiles.
• Notice that, for predeposition into an extrinsic semiconductor with a back
ground density NBG of a dopant of type opposite to that of the diffusing
impurity, a PN junction is formed with net impurity concentration
distribution (doping profile):
 The Junction Depth
• The junction depth xd , as computed by setting N = 0 is
 DRIVE-IN DIFFUSION
• In this case what remains constant is not the impurity concentration at
the surface but the total number of impurity molecules injected in the
semiconductor), therefore

• which constitutes a boundary condition for the solution of the differential

equation for drive-in diffusion. The other boundary condition is N(∞,t) = 0.
The solution is a gaussian profile:
• In integrated circuits, resistors are often fabricated as thin sheets of
extrinsic semiconductor material of appropriate thickness and shape.
• These are usually thin diffused layers, so that the dopant concentration
is not uniform but varies with depth.
• The computation of the sheet resistance can be done using the average
conductivity:
 Ion Implantation
• Considerably improved accuracy in
controlling the doping profiles, lateral diffu-
sion, etc., can be achieved by aiming a
beam of high-velocity impurity ions at the
target window to be doped.
• A typical ion implantation system is shown.
Mass separation is obtained by an
analyzer magnet focusing only desired
ions into the beam, thereby limiting possible
unwanted impurities.
• The desired beam energy is controlled by
the voltage applied to the ion acceleration
tube and the beam is aimed by the
vertical and horizontal scanner electrodes.
Beam energies commonly vary between tens
and hundreds of kiloelectronvolts
 Ion Implantation Process
• The ions penetrate the surface (i.e., are
implanted in the crystal) because of their
high initial energy and come to rest only
when this energy has been dissipated by
collisions with the crystal elements.
• By controlling the ion beam energy, the
depth of penetration can be controlled.
Because of the randomness of the
collisions with crystal atoms the
implanted ion population is not all
concentrated at the projected range,
but is distributed in a gaussian manner
around it over a range of depths.
• Ion implantation can afford doping control
orders of magnitude more accurate than
thermal diffusion
Advantages and Disadvantages of Ion Implantation
• A major advantage of ion implantation is the fact that it is a low
temperature process, so that it can be introduced in the fabrication
sequence at moments in which the high temperature involved in diffusion
would damage already fabricated structures.
• One important drawback of ion implantation is crystal lattice damage. The
energetic ions, colliding with crystal atoms, may displace some of them
from their lattice positions, adversely affecting important material
characteristics (lifetime, mobility, etc.).
• To help restore desired crystal properties, annealing processes are used,
generally under special precautions to minimize doping profile degradation
by diffusion.
 Electrode Material
• For use in circuits, electrical access to the devices requires appropriate
electrodes, which must make low-resistance, ohmic contact with the
various portions of the device.
• Several types of metals are used, the most common being AI and the
silicides.
• An important role in electrode production is being played by heavily
doped polysilicon films, especially in MOSFET technologies.
 Electrode Deposition
• Metal electrodes are most often deposited on the semiconductor
surface from the vapor phase, in a process called metallization. This is
usually obtained by either physical or chemical means.
• Chemical vapor deposition (CVD) technologies for metal deposition are
quite similar to those used for dielectric deposition, except, of course, for
the materials used and the chemical reactions involved.
• In physical vapor deposition (PVD) the wafers are placed in a
vacuum chamber(Evaporator), often under low pressures of inert gases.
Here they are exposed to the metal vapors produced by heating solid
metal sources
 Electrode Realization
• The whole surface of the wafers may be coated and the metal film dry
etched in a photolithographic step to obtain the desired electrode
configuration.
• Conversely, the photoresist pattern may be created on the substrate
before the metal deposition, so that both the exposed regions and the
photoresist mask are coated with the metallic film. Then the photoresist
mask is dissolved by a suitable solvent. When this happens, the portions
of the metallic film formed on the photoresist are lifted away, while the
portions adhering to the substrate remain in place, again yielding the
desired electrode configuration. This second method, is known as the
liftoff technique.
 Integrated Circuit Fabrication
• One important characteristic of the technologies described so far is that
they make it easy to fabricate a large number of identical devices on one
wafer. Indeed, each component of the device structure can be fabricated
simultaneously on any number of devices on the same wafer by one and
the same operation, so that many devices are produced "in parallel" as it
were.
• The economic advantages of this mode of operation are evident:
many devices can be produced for essentially the price of one. However,
another technical advantage can also be derived: all devices fabricated
simultaneously enjoy the best probability of being well matched
 Two Identical Diodes Fabrication
• The next step in this line of reasoning is
quite natural. Is it possible to produce
simultaneously on the same wafer not only
identical devices but also a variety of
different circuit components? If so, then a
single chip can contain not just a circuit
component, but the entire circuit,
automatically assembled with the
attendant advantages on production
time and cost, size, and uniformity of
product.
• The figure shows the fabrication of two
identical diodes.
 Devices Isolation
• One way of obtaining device isolation is
shown in Figure. Remember that, when
the junctions were first formed, the
support used consisted of an N-type layer
(such as might have been epitaxially
grown} over a p + wafer.
• The Figure indicates that, using the
SiO2 mask, a deep p+ layer is now
diffused between the two devices. This
layer reaches all the way through the N-
type semiconductor to the underlying p+
substrate (reach-through diffusion).
Fabrication Examples
 PN Diode Fabrication Steps
• 1. An N-type semiconductor layer is
epitaxially grown on a p+ substrate.
• 2. A thick masking oxide layer is grown on
the whole face of the wafer, usually by the
wet process.
• 3. Using a mask ( # 1) and a photostep, a
well is etched in the thick oxide to expose
the surface of the underlying N-type
semiconductor, where the P-type anode
region will be fabricated.
• 4. By a diffusion process, using the thick
oxide as a mask, a P-type layer is
diffused into the anode region. This forms
the junction.
 PN Diode Fabrication Steps (continued)
• 5. The thick oxide is now etched off and
the surface of the wafer is again oxidized
• 6. Using a mask ( # 2) and a photo step,
two wells are etched in the oxide, to
expose a region of the P-type and a region
of the N-type semiconductor.
• 7. By a metallization process, a metal layer
is deposited on the whole wafer face.
• 8. Using a mask ( # 3) and a photo step,
the metal is etched to isolate the two
electrodes from each other and give them
the desired shape
MOSFET Fabrication
 P-MOSFET Fabrication Steps
• 1. The surface of an N-type wafer (the substrate) is
oxidized, usually by the wet process. This oxide layer
will be used not only during fabrication, as a mask for
diffusion processes (masking oxide), but will also
remain, as field oxide, in the finished product. It must
therefore be thick enough to act as an efficient
diffusion mask.
• 2. By a photostep, using mask # 1 and subsequent
etching, two windows are opened in the oxide layer,
exposing two areas of the underlying semiconductor
surface. Then, through the windows, a p + layer is
diffused into each of these areas of the substrate.
These p + regions will later become the source and
drain of the MOSFET.
 P-MOSFET Fabrication Steps (Continued)
• 3. The device is now submitted to a second
oxidation process resulting in an oxide layer
that covers the entire surface. Although this
oxidation is performed without stripping off the
existing mask oxide, the thickness of the
resulting field oxide is essentially uniform,
because of the faster oxidation rate in the
regions where the substrate is exposed.
• 4. By a photostep, using mask # 2, a well is
etched in the oxide between the source and
drain regions. It is of fundamental importance
for the future operation of the device that this
well should expose not only all of the length L of
the substrate between the source and drain but
also some portion of these two regions.
 P-MOSFET Fabrication Steps (Continued)
• 5 Next, a thin film of high-quality oxide of
accurately controlled thickness (the gate oxide) is
grown over the semiconductor surfaces exposed
by this well. Because of the strict quality and
dimensional requirements, the dry process is
almost universally used in this step. This process
also negligibly increases the thickness of the field
oxide.
• 6. Using mask # 3 and a photo step, two windows
are etched in the field oxide to expose the two p +
regions (the source and the drain), so that ohmic
contacts with these semiconductors can be
fabricated.
 P-MOSFET Fabrication Steps(Continued)
• 7. To obtain these contacts, the whole
wafer surface is covered with a metallic
layer by a metallization process step.
• 8. Using mask #4 and a final photo
step, the metal layer is etched to form
the source, drain, and gate electrodes.
Notice that, at this time, the substrate
is often electrically connected to the
source terminal.
 P-MOSFET Fabrication Steps(Continued)

It should be mentioned here that a technological

breakthrough of particular importance in MOSFET fabrication
was achieved with the introduction of the polysilicon gate
technology, in which layers of doped, conductive poly
crystalline silicon (polysilicon) are used for the gate electrode
instead of metal.
 Measurement and Test Techniques
• The characteristics of the materials and structures fabricated by the
above described technology must, of course, be measured and verified.
• Following is an introductory description of some of the measurements and
tests most frequently used to characterize materials and devices.
 Four Probe Method
• The doping of extrinsic
semiconductor materials is
characterized in terms of their
Resistivity
• Measurements of resistivity of
homogeneous materials are
usually performed by the four-contact
probe method.
The four contacts in the probe are
located along a straight line at a
constant distance s between any two
adjacent contacts and the probe is
touched to the sample. A constant
current generator injects a current I into
the external contacts AA and a voltmeter
V measures the difference of potential
between the internal contacts BB
 Effect of Sample Dimensions
• Notice that this configuration is
influenced by the finite dimensions of
the sample. For thin resistive layers
(w<< s), it is easily shown that

• where KF is a shape coefficient plotted

vs. d/s as shown in the Figure. and
tends to 4.532 for d>>s.
 Effect of Sample Dimensions

• The condition that the sample must

be thinner than the interelectrode dis-
tance (w<< s) is usually amply met by
both wafers and diffused resistors. For
the latter, however, the condition d>>s
is often not valid and the correction
coefficient must be determined
 Doping Profile Measurements
Doping profiles can be evaluated by reverse-biased capacitance
measurements.
 Junction Depth

• This parameter can be measured

by optical inspection. A wedge-
shaped cross section of the
junction is obtained by lapping
the sample at a small angle Ѳ from
the surface, as shown in Fig.
 Junction Depth

• The exposed section of the

junction is then treated with a
chemical which stains the P-type
semiconductor darker than the
N-type. Observation under a
microscope permits measurement
of the length I of the section of the
top region. The junction depth is
then
xd = l sin q
 Hall Effect
• Consider the specimen in the
Figure. It is subjected to a
magnetic field B (in the -z
direction in the figure) while a
current density J is made to flow
through it in a direction
perpendicular to the magnetic
field (in the y direction in the
figure) , a voltage V is
generated across the specimen.
 Hall Effect

• If B, J, and I are known,

measurement of the transverse
Hall effect voltage V permits the
computation of qN in magnitude
and sign, showing that Hall
effect measurements permit
determination of the net
concentration of dopant
impurities in semiconductor
specimen and also detect the
type of the majority carriers
(electrons or holes).
 Carrier Lifetime
• The action of an external source of energy
on an extrinsic semiconductor may raise the
carrier generation rate above the thermal
value, finally increasing the minority carrier
concentration at steady state.
• If the external source is abruptly removed,
recombination becomes prevalent and the
minority carrier concentration relaxes
exponentially to the thermal equilibrium
value, with a time constant t defined as the
carrier lifetime.
 Lifetime Measurements

• A current is made to flow, If the sample

is flooded with light, then, after steady
state is reached, the current is constant
and proportional to the carrier
concentrations.
• If the light source is suddenly
extinguished, the scope displays a time-
varying current. The minority carrier
lifetime can then be measured as the
time constant of the displayed decay.
 The Haynes-Shockley Experiment

• This technique can be used to

measure several important
parameters, such as mobility.
• At time t = 0, the pulse generator
produced a positive pulse of voltage
v(t), which injects into the
semiconductor a pulse of minority
carriers at the position xo of the
point contact.
 The Haynes-Shockley Experiment

• Two cases will be considered:

• 1. If switch S is open, then there is no
significant electric field in the semiconductor,
e = 0, there is no drift current, and the cloud
of injected holes shown at position xo
moves exclusively by diffusion. It can
therefore be expected that the localized
high concentration of holes will spread
along the length of the semiconductor,
recombining as it goes; as times goes by it
will ”flatten out" and disperse.
 The Haynes-Shockley Experiment
• 2. If switch S is closed, then a uniform
field e in the u" direction is present in
the semiconductor, resulting in a small
current proportional to the carrier
concentration, flowing through the
specimen into resistor R. We can
expect this field to add a drift
component to the motion of the cloud
of injected holes, so that, while
spreading by diffusion, as in case (l),
the cloud also moves to the right at a
constant drift speed
 The Haynes-Shockley Experiment

• Notice that in this drift

motion, the cloud will
eventually reach the contact
B, where its localized higher
carrier concentration will
generate an increment in the
drift current normally flowing
through R and produce a peak
of voltage at the oscilloscope
input.
 The Haynes-Shockley Experiment
• The scope display will then look as
in Fig.. If the distance between A
and B is d, then, the delay with
which the peak of the cloud reaches
B and is detected by the scope

• As both e and d are known and ∆t

can be measured from the
oscilloscope trace, µh can easily be
computed.
END