Lec1 Single Stage Amp
Lec1 Single Stage Amp
Lec1 Single Stage Amp
Lecture Notes
Discrete Single Stage
Transistor Amplifier
Fall 2022
Single Stage Transistor Amplifier
Emitter is grounded
Input is between Base and Ground
Output is between Collector and Ground
Collector is grounded
Input is between Base and Ground
Output is between Emitter and Ground
Common Base (CB)
Base is grounded
Input is between Emitter and Grounded
Output is between Collector and Ground
The diagrams we saw in the previous page are called “Conceptual
Circuit diagram of 3 Amplifies configurations.”
Why conceptual?
Ans: The diagrams give us the basic idea of how input and output would be
connected in these configurations. This is not the complete amplifier
circuit because “Biasing” is missing here. Without biasing a transistor
amplifier will not work. We need to apply DC biasing. In the conceptual
diagram we are only showing AC input signal and AC output signal.
VB = VBE + IERE
2) VBE is fixed.
3) We can control IE by RE.
We know,
IC = 𝐼𝐸 In most cases,
= 𝛽 𝐼𝐵 𝛽>>1 ∴ 1
IE = IC + IB
= ( 1 + 𝛽) IB
So, we can say IC IE
For accurate result we can take ∝ 0.99 and then calculate IC. It will be
±1% more/less and for most practical system this much error is
acceptable.
VC = VCC - ICRC
Here, 1) VCC is fixed (Supply voltage)
2) RC is fixed
3) IC we can adjust by IE , which can be adjusted by RE.
Thus VC can be varied by varying IC and for RB condition, we must
keep VC > VB .
In that case, we control IC accordingly to fulfil the condition.
Or we can control RC if for IC we have to ensure a fixed value.
Then, we can increase/decrease RC to decrease/increase VC .
IC > iLmax
When we connect load to the circuit, part of IC will flow through that load.
If IC is smaller than iLmax, then all of IC will go to the load and transistor
will go into “Cut off” mode.
VC > vomax + VB and IC RC > vomax
For faithful reproduction of the output signal. Otherwise, the output voltage signal
will be distorted.
*** First we will see the load requirements
CE with DC Biasing:
What happens when input signal and the load at the output are
connected directly to the amplifier?
changes
Unnecessary IDC will flow in the source which may be damaging for the
source.
Detailed circuit
diagram of
Common Emitter
Amplifier
We made the Base grounded through CC1 . For AC signal capacitor acts
are short circuit, so there will be no voltage drop. There is only DC
voltage (VB). The capacitor is open circuit for DC.
We need RC here because without voltage drop across it, we will not get voltage
at the output (vo).
*The circuits we saw until now (with all the resistors, capacitors,
signals together) are called Discrete Amplifier Circuits.
CE Amplifier:
Parameters we are interested in:
1) Voltage gain, AV
2) Current gain, Ai
3) Input resistance (Ri) is seen by the signal source.
4) Output resistance (Ro) is seen by the load.
vo AC output voltage
VCC DC supply voltage
𝑟𝜋 = (𝛽 + 1)𝑟e
re Resistance Reflection Rule
We see that,
Ri = 𝑟 , Ro = 𝑟 Av = =
Here, Ri and Ro are part of the Amplifier; whereas, RS comes with the source and RL is from Load. They are
external part. Due to Emitter being grounded, Ro becomes same as ro .
Io = - gmvbe usually,
ro >> RL because ro is in 100
- gmvbe kΩ RL is in 2kΩ
𝑟𝑜
∴ 1
𝑟𝑜 𝑅𝐿
A small amount of current will be going through ro, so most of the current from
“gmvbe” source will go through RL. Thus, we say io = -gmvbe .
ii = ib
Ai = =- = - gmrπ
=- .
=- = -β
Now, we will see the range of values these parameters can have.
We got, Ri = rπ =
Ro = ro =
gm = = = = 40 mA/V
. .
∴ Ai = -β -100 (High)
For CE Amplifier both the voltage gain and current gain is high.
Power gain, AP = = = AvAi = very high
Ri is the resistance we look from the Base side, but we do not have any resistance
there. We have re and RL at the Emitter side. So, they will be reflected to the Base.
∴ Ri β+ re + RL) by Resistance Reflection Rule
or we can do Ri = = = β+ re+RL)
Ri (β+1) ( re + RL )
(β+1)re + (β+1)RL
= rπ + (β+1)RL >> rπ (High)
Among the three amplifier configurations, CC Amplifier has the highest input
resistance.
R’o = re + Rs is reflected to the Emitter side
Ro = re + (Low)
vb = ie (re + RL)
vo = ioRL = ieRL
𝑣𝑜 𝑖𝑒 𝑅𝐿
∴ =
𝑣𝑏 𝑖𝑒 𝑟𝑒 𝑅𝐿
𝑅𝐿
= <1
𝑟𝑒 𝑅𝐿
At input side we see
∴ = <1
∴Av = = <1
Ai = = β+1 (High)
∴ Av =
ie
Ri (β+1)(re + RE)
(β+1) re + (β+1) RE Adding RE has increased
the value of Ri
= rπ + (β+1) RE > Ri | CE
(High)
− ;
CE -gmRL ; as ro>>RL
= - RL ;
<
CE with RE CE
∴ The higher RE 1) Higher Ri
2) Higher Ro
3) Lower
= <1
Ai = = =- = -β