Module 2

Digital Design and Computer Organization BCS302
Module- 2
COMBINATIONAL CIRCUITS
INTRODUCTION:
The digital system consists of two types of circuits, namely
(i) Combinational circuits
(ii) Sequential circuits
Combinational circuit consists of logic gates whose output at any time is

determined from the present combination of inputs. The logic gate is the most basic
building block of combinational logic. The logical function performed by a
combinational circuit is fully defined by a set of Boolean expressions.
Sequential logic circuit comprises both logic gates and the state of storage
elements such as flip-flops. As a consequence, the output of a sequential circuit depends
not only on present value of inputs but also on the past state of inputs.
In the previous chapter, we have discussed binary numbers, codes, Boolean
algebra and simplification of Boolean function and logic gates. In this chapter,
formulation and analysis of various systematic designs of combinational circuits will be
discussed.
A combinational circuit consists of input variables, logic gates, and output

variables. The logic gates accept signals from inputs and output signals are generated
according to the logic circuits employed in it. Binary information from the given data
transforms to desired output data in this process. Both input and output are obviously the
binary signals, i.e., both the input and output signals are of two possible states, logic 1
and logic 0.
Block diagram of a combinational logic circuit
For n number of input variables to a combinational circuit, 2n possible

combinations of binary input states are possible. For each possible combination, there is
one and only one possible output combination. A combinational logic circuit can be
described by m Boolean functions and each output can be expressed in terms of n input
variables.
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DESIGN PROCEDURE:
Any combinational circuit can be designed by the following steps of design procedure.
1. The problem is stated.
2. Identify the input and output variables.
3. The input and output variables are assigned letter symbols.
4. Construction of a truth table to meet input -output requirements.
5. Writing Boolean expressions for various output variables in terms of input
variables.
6. The simplified Boolean expression is obtained by any method of minimization—
algebraic method, Karnaugh map method, or tabulation method.
7. A logic diagram is realized from the simplified boolean expression using logic
gates.
The following guidelines should be followed while choosing the preferred form for
hardware implementation:
1. The implementation should have the minimum number of gates, with the gates
used having the minimum number of inputs.
2. There should be a minimum number of interconnections.
3. Limitation on the driving capability of the gates should not be ignored.
ARITHMETIC CIRCUITS – BASIC BUILDING BLOCKS:
In this section, we will discuss those combinational logic building blocks that can
be used to perform addition and subtraction operations on binary numbers. Addition and
subtraction are the two most commonly used arithmetic operations, as the other two,
namely multiplication and division, are respectively the processes of repeated addition
and repeated subtraction.
The basic building blocks that form the basis of all hardware used to perform the
arithmetic operations on binary numbers are half-adder, full adder, half-subtractor, full-
subtractor.
Half-Adder:
A half-adder is a combinational circuit that can be used to add two binary bits. It
has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY.
Block schematic of half-adde

The truth table of a half-adder, showing all possible input combinations and
the corresponding outputs are shown below.
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Inputs Outputs
A B Carry (C) Sum (S)
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Truth table of half-adder
K-map simplification for carry and sum:
The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S= A’B+ AB’= A ⊕ B
Carry C= A . B
The first one representing the SUM output is that of an EX-OR gate, the second one
representing the CARRY output is that of an AND gate.
The logic diagram of the half adder is,
Logic Implementation of Half-adder

Full-Adder:
A full adder is a combinational circuit that forms the arithmetic sum of three input
bits. It consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added. The third
input represents the carry from previous lower significant position. The block diagram of
full adder is given by,
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Block schematic of full-adder

The full adder circuit overcomes the limitation of the half-adder, which can be
used to add two bits only. As there are three input variables, eight different input
combinations are possible. The truth table is shown below,
Truth Table:
Inputs Outputs
A B Cin Sum (S) Carry
(Cout)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
To derive the simplified Boolean expression from the truth table, the Karnaugh map method
is adopted as,
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The Boolean expressions for the SUM and CARRY outputs are given by the
equations,
Sum, S = A’B’Cin+ A’BC’in + AB’C’in + ABCin
Carry, Cout = AB+ ACin + BCin .
The logic diagram for the above functions is shown as,
Implementation of full-adder in Sum of Products

The logic diagram of the full adder can also be implemented with two half- adders
and one OR gate. The S output from the second half adder is the exclusive-OR of Cin and
the output of the first half-adder, giving
Sum = Cin ⊕ (A ⊕ B) [x⊕y = x‘y+ xy‘]

= Cin ⊕(A‘B+AB‘)
= C‘in (A‘B+AB‘) + Cin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= C‘in (A‘B+AB‘) + Cin (AB+A‘B‘)
= A‘BC‘in + AB‘C‘in + ABCin + A‘B‘Cin .
and the carry output is,
Carry, Cout = AB+ Cin (A’B+AB’)
= AB+ A‘BCin+ AB‘Cin
= AB (Cin+1) + A‘BCin+ AB‘Cin [Cin+1= 1]
= ABCin+ AB+ A‘BCin+ AB‘Cin
= AB+ ACin (B+B‘) + A‘BCin
= AB+ ACin+ A‘BCin
= AB (Cin+1) + ACin+ A‘BCin [Cin+1=
1]
= ABCin+ AB+ ACin+ A‘BCin
= AB+ ACin+ BCin (A +A‘)
= AB+ ACin+ Bcin.
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Implementation of full adder with two half-adders and an OR gate
Half -Subtractor:
A half-subtractor is a combinational circuit that can be used to subtract one binary
digit from another to produce a DIFFERENCE output and a BORROW output. The
BORROW output here specifies whether a ‗1‘ has been borrowed to perform the subtraction.
Block schematic of half-subtractor
The truth table of half-subtractor, showing all possible input combinations and the
corresponding outputs are shown below.
Input Output
A B Difference (D) Borrow (Bout)
0 0 0 0
0 1 1 1
1 0 1 0
1 1 0 0
K-map simplification for half subtractor:
The Boolean expressions for the DIFFERENCE and BORROW outputs are given
by the equations,
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Difference, D = A’B+ AB’= A ⊕B

Borrow, Bout= A’ . B
The first one representing the DIFFERENCE (D)output is that of an exclusive-OR

gate, the expression for the BORROW output (Bout) is that of an AND gate with input A
complemented before it is fed to the gate.
The logic diagram of the half adder is,
Logic Implementation of Half-Subtractor
Comparing a half-subtractor with a half-adder, we find that the expressions for the
SUM and DIFFERENCE outputs are just the same. The expression for BORROW in the
case of the half-subtractor is also similar to what we have for CARRY in the case of the
half-adder. If the input A, ie., the minuend is complemented, an AND gate can be used to
implement the BORROW output.
Full Subtractor:
A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and
also takes into consideration whether a ‗1‘ has already been borrowed by the previous
adjacent lower minuend bit or not.
As a result, there are three bits to be handled at the input of a full subtractor,
namely the two bits to be subtracted and a borrow bit designated as Bin. There are two
outputs, namely the DIFFERENCE output D and the BORROW output Bo. The
BORROW output bit tells whether the minuend bit needs to borrow a ‗1‘ from the next
possible higher minuend bit.
Block schematic of full-adder
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The truth table for full-subtractor is,

Inputs Outputs
A B Bi Difference(D) Borrow(Bout)
n
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
K-map simplification for full-subtractor:
The Boolean expressions for the DIFFERENCE and BORROW outputs are
given by the equations,
Difference, D= A’B’Bin+ A’BB’in + AB’B’in + ABBin
Borrow, Bout= A’B+ A’Cin + BBin .
The logic diagram for the above functions is shown as,
Implementation of full-adder in Sum of Products
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The logic diagram of the full-subtractor can also be implemented with two half-
subtractors and one OR gate. The difference,D output from the second half subtractor is
the exclusive-OR of Bin and the output of the first half-subtractor, giving
Difference,D= Bin⊕(A ⊕ B) [x ⊕ y = x‘y+ xy‘]
= Bin ⊕ (A‘B+AB‘)
= B‘in (A‘B+AB‘) + Bin (A‘B+AB‘)‘ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= B‘in (A‘B+AB‘) + Bin (AB+A‘B‘)
= A‘BB‘in + AB‘B‘in + ABBin + A‘B‘Bin .
and the borrow output is,
Borrow, Bout = A’B + Bin (A’B+AB’)’ [(x‘y+xy‘)‘= (xy+x‘y‘)]
= A‘B+ Bin (AB+A‘B‘)
= A‘B+ ABBin+ A‘B‘Bin
= A‘B (Bin+1) + ABBin+ A‘B‘Bin [Cin+1= 1]
= A‘BBin+ A‘B+ ABBin+ A‘B‘Bin
= A‘B+ BBin (A+A‘) + A‘B‘Bin [A+A‘= 1]
= A‘B+ BBin+ A‘B‘Bin
= A‘B (Bin+1) + BBin+ A‘B‘Bin [Cin+1= 1]
= A‘BBin+ A‘B+ BBin+ A‘B‘Bin
= A‘B+ BBin+ A‘Bin (B +B‘)
= A‘B+ BBin+ A‘Bin.
Therefore,
we can implement full-subtractor using two half-subtractors and OR gate as,
Implementation of full-subtractor with two half-subtractors and an OR gate
Binary Adder (Parallel Adder):
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The 4-bit binary adder using full adder circuits is capable of adding two 4-bit
numbers resulting in a 4-bit sum and a carry output as shown in figure below.
4-bit binary parallel Adder
Since all the bits of augend and addend are fed into the adder circuits
simultaneously and the additions in each position are taking place at the same time, this
circuit is known as parallel adder.
Let the 4-bit words to be added be represented by, A3A2A1A0=

1111 and B3B2B1B0= 0011.
The bits are added with full adders, starting from the least significant position, to
form the sum it and carry bit. The input carry C0 in the least significant position must be
0. The carry output of the lower order stage is connected to the carry input of the next higher
order stage. Hence this type of adder is called ripple-carry adder.
In the least significant stage, A0, B0 and C0 (which is 0) are added resulting
in sum S0 and carry C1. This carry C1 becomes the carry input to the second stage.
Similarly in the second stage, A1, B1 and C1 are added resulting in sum S1 and carry
C2, in the third stage, A2, B2 and C2 are added resulting in sum S2 and carry C3, in the
third stage, A3, B3 and C3 are added resulting in sum S3 and C4, which is the
output carry. Thus the circuit results in a sum (S3S2S1S0) and a carry output (Cout).
Though the parallel binary adder is said to generate its output immediately after
the inputs are applied, its speed of operation is limited by the carry propagation delay
through all stages. However, there are several methods to reduce this delay.
One of the methods of speeding up this process is look-ahead carry addition which
eliminates the ripple-carry delay.
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Carry Propagation–Look-Ahead Carry Generator:

In Parallel adder, all the bits of the augend and the addend are available for
computation at the same time. The carry output of each full-adder stage is connected to
the carry input of the next high-order stage. Since each bit of the sum output depends on
the value of the input carry, time delay occurs in the addition process. This time delay is
called as carry propagation delay.
For example, addition of two numbers (0011+ 0101) gives the result as 1000.
Addition of the LSB position produces a carry into the second position. This carry when
added to the bits of the second position, produces a carry into the third position. This
carry when added to bits of the third position, produces a carry into the last
position. The sum bit generated in the last position (MSB) depends on the carry that
was generated by the addition in the previous position. i.e., the adder will not produce
correct result until LSB carry has propagated through the intermediate full-adders. This
represents a time delay that depends on the propagation delay produced in an each full-
adder. For example, if each full adder is considered to have a propagation delay of
30nsec, then S3 will not react its correct value until 90 nsec after LSB is generated.
Therefore total time required to perform addition is 90+ 30 = 120nsec.
4-bit Parallel Adder
The method of speeding up this process by eliminating inter stage carry delay is
called look ahead-carry addition. This method utilizes logic gates to look at the lower
order bits of the augend and addend to see if a higher-order carry is to be generated. It
uses two functions: carry generate and carry propagate.
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Full-Adder circuit
Consider the circuit of the full-adder shown above. Here we define two
functions: carry generate (Gi) and carry propagate (Pi) as,
Carry generate, Gi = Ai ⊕ Bi
Carry propagate, Pi = Ai ⊕Bi
the output sum and carry can be expressed as,
Si= Pi ⊕Ci
Ci+1=Gi⊕PiCi
Gi (carry generate), it produces a carry 1 when both Ai and Bi are 1, regardless of the input
carry Ci.
Pi (carry propagate) because it is the term associated with the propagation of the carry
from Ci to Ci+1.
The Boolean functions for the carry outputs of each stage and substitute for each Ci
its value from the previous equation:
C0= input carry
C1= G0 + P0C0
C2= G1 + P1C1 = G1 + P1 (G0 + P0C0)
= G1 + P1G0 + P1P0C0
C3= G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0)
= G2 + P2G1 + P2P1G0 + P2P1P0C0
Since the Boolean function for each output carry is expressed in sum of products,
each function can be implemented with one level of AND gates followed by an OR gate.
The three Boolean functions for C1, C2 and C3 are implemented in the carry look-ahead
generator as shown below. Note that C3 does not have to wait for C2 and C1 to
propagate; in fact C3 is propagated at the same time as C1 and C2.
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Logic diagram of Carry Look-ahead Generator

Using a Look-ahead Generator we can easily construct a 4-bit parallel adder with
a Look-ahead carry scheme. Each sum output requires two exclusive-OR gates. The
output of the first exclusive-OR gate generates the Pi variable, and the AND gate
generates the Gi variable. The carries are propagated through the carry look-ahead
generator and applied as inputs to the second exclusive-OR gate. All output carries are
generated after a delay through two levels of gates. Thus, outputs S1 through S3 have
equal propagation delay times.
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4-Bit Adder with Carry Look-ahead
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Binary Subtractor (Parallel Subtractor):

The subtraction of unsigned binary numbers can be done most conveniently by
means of complements. The subtraction A-B can be done by taking the 2‘s complement of B
and adding it to A. The 2‘s complement can be obtained by taking the 1‘s complement and
adding 1 to the least significant pair of bits. The 1‘s complement can be implemented
with inverters and a 1 can be added to the sum through the input carry.The circuit for
subtracting A-B consists of an adder with inverters placed between each data input B and
the corresponding input of the full adder. The input carry C0 must be equal to 1 when
performing subtraction. The operation thus performed becomes A, plus the 1‘s complement
of B, plus1. This is equal to A plus the 2‘s complement of B.
4-bit Parallel Subtractor
Parallel Adder/ Subtractor:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. This is done by including an exclusive-OR gate with each full
adder. A 4-bit adder Subtractor circuit is shown below.
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4-Bit Adder Subtractor

The mode input M controls the operation. When M= 0, the circuit is an adder and when
M=1, the circuit becomes a Subtractor. Each exclusive-OR gate receives input M and one of
the inputs of B. When M=0, we have B 0= B. The full adders receive the value of B, the
input carry is 0, and the circuit performs A plus B. When M=1, we have B 1= B‘ and C0=1.
The B inputs are all complemented and a 1 is added through the input carry. The circuit
performs the operation A plus the 2‘s complement of B. The exclusive-OR with output V is
for detecting an overflow.
Decimal Adder (BCD Adder):
The digital system handles the decimal number in the form of binary coded decimal
numbers (BCD). A BCD adder is a circuit that adds two BCD bits and produces a sum digit
also in BCD.
Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 9+ 9+1 = 19; the 1 is the sum being an input carry. The adder will
form the sum in binary and produce a result that ranges from 0 through 19.
These binary numbers are labeled by symbols K, Z 8, Z4, Z2, Z1, K is the carry. The
columns under the binary sum list the binary values that appear in the outputs of the 4-
bit binary adder. The output sum of the two decimal digits must be represented in BCD.
Binary Sum BCD Sum

Decimal
K Z Z Z Z1 C S8 S S2 S1
8 4 2 4
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 1 0 0 0 0 1 1
0 0 0 1 0 0 0 0 1 0 2
0 0 0 1 1 0 0 0 1 1 3
0 0 1 0 0 0 0 1 0 0 4
0 0 1 0 1 0 0 1 0 1 5
0 0 1 1 0 0 0 1 1 0 6
0 0 1 1 1 0 0 1 1 1 7
0 1 0 0 0 0 1 0 0 0 8
0 1 0 0 1 0 1 0 0 1 9
0 1 0 1 0 1 0 0 0 0 10
0 1 0 1 1 1 0 0 0 1 11
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0 1 1 0 0 1 0 0 1 0 12
0 1 1 0 1 1 0 0 1 1 13
0 1 1 1 0 1 0 1 0 0 14
0 1 1 1 1 1 0 1 0 1 15
1 0 0 0 0 1 0 1 1 0 16
1 0 0 0 1 1 0 1 1 1 17
1 0 0 1 0 1 1 0 0 0 18
1 0 0 1 1 1 1 0 0 1 19
In examining the contents of the table, it is apparent that when the binary sum is equal to
or less than 1001, the corresponding BCD number is identical, and therefore no conversion is
needed. When the binary sum is greater than 9 (1001), we obtain a non- valid BCD
representation. The addition of binary 6 (0110) to the binary sum converts it to the correct
BCD representation and also produces an output carry as required.
The logic circuit to detect sum greater than 9 can be determined by simplifying the
boolean expression of the given truth table.
To implement BCD adder we require:

 4-bit binary adder for initial addition
 Logic circuit to detect sum greater than 9 and
 One more 4-bit adder to add 01102 in the sum if the sum is greater than 9 or carry is 1.
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The two decimal digits, together with the input carry, are first added in the top4-
bit binary adder to provide the binary sum. When the output carry is equal to zero,
nothing is added to the binary sum. When it is equal to one, binary 0110 is added to the
binary sum through the bottom 4-bit adder. The output carry generated from the bottom
adder can be ignored, since it supplies information already available at the output carry
terminal. The output carry from one stage must be connected to the input carry of the
next higher-order stage.
Block diagram of BCD adder
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DECODERS:
A decoder is a combinational circuit that converts binary information from ‗n‘ input lines
to a maximum of ‗2n‘ unique output lines. The general structure of decoder circuit is –
General structure of decoder
The encoded information is presented as ‗n‘ inputs producing ‗2n‘ possible outputs. The
2n output values are from 0 through 2n-1. A decoder is provided with enable inputs to
activate decoded output based on data inputs. When any one enable input is unasserted, all
outputs of decoder are disabled.
Binary Decoder (2 to 4 decoder):

A binary decoder has ‗n‘ bit binary input and a one activated output out of 2 n outputs. A
binary decoder is used when it is necessary to activate exactly one of 2n outputs based on an
n-bit input value.
2-to-4 Line decoder
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Here the 2 inputs are decoded into 4 outputs, each output representing one of the
minterms of the two input variables.
Inputs Outputs
Enable A B Y3 Y2 Y1 Y0
0 x x 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
As shown in the truth table, if enable input is 1 (EN= 1) only one of the outputs (Y0 –
Y3), is active for a given input.
The output Y0 is active, ie.,
Y0= 1 when inputs A= B= 0,
Y1 is active when inputs, A= 0 and B= 1,
Y2 is active, when input A= 1 and B= 0,
Y3 is active, when inputs A= B= 1.
3-to-8 Line Decoder:

A 3-to-8 line decoder has three inputs (A, B, C) and eight outputs (Y0- Y7). Based
on the 3 inputs one of the eight outputs is selected.
The three inputs are decoded into eight outputs, each output representing one of the
minterms of the 3-input variables. This decoder is used for binary-to-octal conversion.
The input variables may represent a binary number and the outputs will represent the eight
digits in the octal number system. The output variables are mutually exclusive because only
one output can be equal to 1 at any one time. The output line whose value is equal to 1
represents the minterm equivalent of the binary number presently available in the input
lines.
Inputs Outputs
A B C Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
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3-to-8 line decoder

Applications of decoders:
1. Decoders are used in counter system.
2. They are used in analog to digital converter.
3. Decoder outputs can be used to drive a display system.
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ENCODERS:
An encoder is a digital circuit that performs the inverse operation of a decoder. Hence, the
opposite of the decoding process is called encoding. An encoder is a combinational circuit that
converts binary information from 2n input lines to a maximum of ‗n‘ unique output lines.
The general structure of encoder circuit is –
General structure of Encoder
It has 2n input lines, only one which 1 is active at any time and n‘ output
lines. It encodes one of the active inputs to a coded binary output with n‘ bits. In an
encoder, the number of outputs is less than the number of inputs.
Octal-to-Binary Encoder:
It has eight inputs (one for each of the octal digits) and the three outputs that generate
the corresponding binary number. It is assumed that only one input has a value of 1 at any
given time.
Inputs Outputs
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
The encoder can be implemented with OR gates whose inputs are determined directly
from the truth table. Output z is equal to 1, when the input octal digit is 1 or 3 or 5 or 7.
Output y is 1 for octal digits 2, 3, 6, or 7 and the output is 1 for digits 4, 5, 6 or
7. These conditions can be expressed by the following output Boolean functions:
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z= D1+ D3+ D5+ D7

y= D2+ D3+ D6+ D7
x= D4+ D5+ D6+ D7
The encoder can be implemented with three OR gates. The encoder defined in the
below table, has the limitation that only one input can be active at any given time. If two
inputs are active simultaneously, the output produces an undefined combination.
For eg., if D3 and D6 are 1 simultaneously, the output of the encoder may be 111.
This does not represent either D6 or D3. To resolve this problem, encoder circuits must
establish an input priority to ensure that only one input is encoded. If we establish a higher
priority for inputs with higher subscript numbers and if D 3 and D6 are 1 at the same time,
the output will be 110 because D6 has higher priority than D3.
Octal-to-Binary Encoder
Another problem in the octal-to-binary encoder is that an output with all 0‘s is generated
when all the inputs are 0; this output is same as when D 0 is equal to 1. The discrepancy can be
resolved by providing one more output to indicate that atleast one input is equal to 1.
Priority Encoder:
A priority encoder is an encoder circuit that includes the priority function. In priority
encoder, if two or more inputs are equal to 1 at the same time, the input having the highest
priority will take precedence.
In addition to the two outputs x and y, the circuit has a third output, V (valid bit
indicator). It is set to 1 when one or more inputs are equal to 1. If all inputs are 0, there
is no valid input and V is equal to 0.
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The higher the subscript number, higher the priority of the input. Input D3, has the
highest priority. So, regardless of the values of the other inputs, when D3 is 1, the output for xy
is 11.
D2 has the next priority level. The output is 10, if D2= 1 provided D3= 0. The output
for D1 is generated only if higher priority inputs are 0, and so on down the priority levels.
Truth table:
Inputs Outputs
D0 D1 D2 D3 x y V
0 0 0 0 x x 0
1 0 0 0 0 0 1
x 1 0 0 0 1 1
x x 1 0 1 0 1
x x x 1 1 1 1
Although the above table has only five rows, when each don‘t care condition is
replaced first by 0 and then by 1, we obtain all 16 possible input combinations. For example,
the third row in the table with X100 represents minterms 0100 and 1100. The don‘t care
condition is replaced by 0 and 1 as shown in the table below.
K-map Simplification:
VVIET 24
The priority encoder is implemented according to the above Boolean functions.
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MULTIPLEXER: (Data Selector)

A multiplexer or MUX, is a combinational circuit with more than one input line, one
output line and more than one selection line. A multiplexer selects binary information
present from one of many input lines, depending upon the logic status of the selection
inputs, and routes it to the output line. Normally, there are 2 n input lines and n selection
lines whose bit combinations determine which input is selected. The multiplexer is often
labeled as MUX in block diagrams.
A multiplexer is also called a data selector, since it selects one of many inputs and
steers the binary information to the output line.
Block diagram of Multiplexer
2-to-1- line Multiplexer:

has 21 inputs, 1 select line and one output
Circuit diagram
Truth table:
A Y
0 I0
1 I1
The circuit has two data input lines, one output line and one selection line, A .
When A= 0, the upper AND gate is enabled and I0 has a path to the output.
When A=1, the lower AND gate is enabled and I1 has a path to the output.
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Logic diagram
The multiplexer acts like an electronic switch that selects one of the two sources.
4-to-1-line Multiplexer:
4 to 1 MUX has 22 = 4 inputs, 2 select line and one output
A 4-to-1-line multiplexer has four (2n) input lines, two (n) select lines and one output
line. It is the multiplexer consisting of four input channels and information of one of the
channels can be selected and transmitted to an output line according to the select inputs
combinations. Selection of one of the four input channel is possible by two selection inputs.
Each of the four inputs I0 through I3, is applied to one input of AND gate. Selection
lines S1 and S0 are decoded to select a particular AND gate. The outputs of the AND gate
are applied to a single OR gate that provides the 1-line output.
VVIET 27
Truth table:
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
To demonstrate the circuit operation, consider the case when S1S0= 10. The AND gate
associated with input I2 has two of its inputs equal to 1 and the third input connected to I2.
The other three AND gates have atleast one input equal to 0, which makes their outputs equal
to 0. The OR output is now equal to the value of I2, providing a path from the selected input
to the output.
The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘.

The data output is equal to I1 only if S1= 0 and S0= 1; Y= I1S1‘S0.
The data output is equal to I2 only if S1= 1 and S0= 0; Y= I2S1S0‘.
The data output is equal to I3 only if S1= 1 and S0= 1; Y= I3S1S0.
When these terms are ORed, the total expression for the data output is,
Y= I0S1’S0’+ I1S1’S0 +I2S1S0’+ I3S1S0.
As in decoder, multiplexers may have an enable input to control the operation of the unit.
When the enable input is in the inactive state, the outputs are disabled, and when it is in the
active state, the circuit functions as a normal multiplexer.
4-to-1-Line Multiplexer
8 to1 Line Multiplexer:
8 to1 MUX has 23 = 8 inputs, 3 select line and one output
VVIET 28
Z=A’B’C’I0+A’B’CI1+A’BC’I2+A’BCI3+AB’C’I4+AB’CI5+ABC’I6+ABCI7
De-multiplexer
A De-multiplexer is a combinational circuit that has only 1 input line and 2 N output lines. Simply, the
multiplexer is a single-input and multi-output combinational circuit. The information is received from
the single input lines and directed to the output line. On the basis of the values of the selection lines,
the input will be connected to one of these outputs. De-multiplexer is opposite to the multiplexer.
Unlike encoder and decoder, there are n selection lines and 2n outputs. So, there is a total of 2n
possible combinations of inputs. De-multiplexer is also treated as De-mux.
There are various types of De-multiplexer which are as follows:
VVIET 29
1×2 De-multiplexer:
In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y 0, and Y1, 1 selection lines, i.e., S0, and
single input, i.e., A. On the basis of the selection value, the input will be connected to one of the
outputs. The block diagram and the truth table of the 1×2 multiplexer are given below.
Block Diagram:
Truth Table:
The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:
VVIET 30
1×4 De-multiplexer:
In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y 0, Y1, Y2, and Y3, 2 selection lines, i.e.,
S0 and S1 and single input, i.e., A. On the basis of the combination of inputs which are present at the
selection lines S0 and S1, the input be connected to one of the outputs. The block diagram and the truth
table of the 1×4 multiplexer are given below.
Block Diagram:
VVIET 31
Truth Table:

Y0=S1'S0'A
y1=S1'S0A
y2=S1S0'A
y3=S1S0A
VVIET 32
1×8 De-multiplexer
In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y 0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7, 3
selection lines, i.e., S0, S1and S2 and single input, i.e., A. On the basis of the combination of inputs
which are present at the selection lines S 0, S1 and S2, the input will be connected to one of these
outputs. The block diagram and the truth table of the 1×8 de-multiplexer are given below.
Block Diagram:
Truth Table:
VVIET 33
Y0=S0'.S1'.S2'.A
Y1=S0.S1'.S2'.A
Y2=S0'.S1.S2'.A
Y3=S0.S1.S2'.A
Y4=S0'.S1'.S2A
Y5=S0.S1'.S2A
Y6=S0'.S1.S2A
Y7=S0.S1.S3.A
VVIET 34
Sequential Circuits:
The sequential circuit is a special type of circuit that has a series of inputs and outputs. The outputs
of the sequential circuits depend on both the combination of present inputs and previous outputs.
The previous output is treated as the present state. So, the sequential circuit contains the
combinational circuit and its memory storage elements. A sequential circuit doesn't need to always
contain a combinational circuit. So, the sequential circuit can contain only the memory element.
Block Diagram of Sequntial Circuit
Difference between the combinational circuits and sequential circuits are given below:
Combinational Circuits Sequential Circuits

The outputs of the sequential circuits
The outputs of the combinational circuit depend only
depend on both present inputs and
on the present inputs.
present state(previous output).
The feedback path is not present in the combinational The feedback path is present in the
circuit. sequential circuits.
In combinational circuits, memory elements are not In the sequential circuit, memory
required. elements play an important role and
VVIET 35
require.
The clock signal is not required for combinational The clock signal is required for
circuits. sequential circuits.
It is not simple to design a sequential

The combinational circuit is simple to design.
circuit.
Types of Sequential Circuits

Asynchronous sequential circuits
The clock signals are not used by the Asynchronous sequential circuits. The asynchronous circuit
is operated through the pulses. So, the changes in the input can change the state of the circuit. The
asynchronous circuits do not use clock pulses. The internal state is changed when the input variable
is changed. The un-clocked flip-flops or time-delayed are the memory elements of asynchronous
sequential circuits. The asynchronous sequential circuit is similar to the combinational circuits with
feedback.
Synchronous sequential circuits
In synchronous sequential circuits, synchronization of the memory element's state is done by the
clock signal. The output is stored in either flip-flops or latches(memory devices). The
synchronization of the outputs is done with either only negative edges of the clock signal or only
positive edges.
There are two types of Memory Elements
(iii) Latches
(iv) Flip Flop
VVIET 36
What Is a Latch?
A latch is an electronic device that changes its output immediately on the basis of the applied input.
One can use it to store either 0 or 1 at a specified time. A latch contains two inputs- SET and RESET,
and it also has two outputs. They complement each other. One can use a latch for storing one bit of
data. It is a memory device- just like the flip-flop. But it is not synchronous, and it does not work on
the edges of the clock like the flip-flop.
Difference between Flip-flop and Latch :

Flip-flop Latch
Flip-flop is a bistable device i.e., it has two stable Latch is also a bistable device whose states
states that are represented as 0 and 1. are also represented as 0 and 1.
It checks the inputs but changes the output only at It checks the inputs continuously and
times defined by the clock signal or any other responds to the changes in inputs
control signal. immediately.
It is a edge triggered device. It is a level triggered device.
Gates like NOR, NOT, AND, NAND are building

blocks of flip flops. These are also made up of gates.
They are classified into asynchronous or

synchronous flipflops. There is no such classification in latches.
These can be used for the designing of

It forms the building blocks of many sequential sequential circuits but are not generally
circuits like counters. preferred.
a, Flip-flop always have a clock signal Latches doesn’t have a clock signal
Flip-flop can be build from Latches Latches can be build from gates
ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch
VVIET 37
What is a Flip-Flop?
A flip-flop is a digital memory circuit that stores one bit of data. They are the primary blocks of the
most sequential circuits. It is also called one-bit memory, binary, or a bistable multivibrator. Flip-flops
act as memory elements in a sequential circuit. You can obtain the output in the sequential circuits
using a flip-flop, a combinational circuit, or both.
A flip-flop state repeatedly changes at an active state of the clock pulses. They remain unaffected even
when the clock pulse does not stay active. The clocked flip-flops particularly act as the memory
elements of the synchronous sequential circuit- while the un-clocked ones (latches) function as the
memory elements of asynchronous sequential circuits.
A circuit that has two stable states is treated as a flip flop. These stable states are used to store binary
data that can be changed by applying varying inputs. The flip flops are the fundamental building
blocks of the digital system. Flip flops and latches are examples of data storage elements. In the
sequential logical circuit, the flip flop is the basic storage element. The latches and flip flops are the
basic storage elements but different in working.
There are the following types of flip flops:
• SR Flip Flop
• J K Flip Flop
• D Flip Flop
• T Flip Flop
Logic diagrams and truth tables of the different types of flip-flops are as follows:
SR Flip Flop
Block Diagram:
The S-R Flip Flop is the most common flip flop used in the digital system. In SR flip flop, when the
set input "S" is true, the output Y will be high, and Y' will be low. It is required that the wiring of the
circuit is maintained when the outputs are established. We maintain the wiring until set or reset input
goes high, or power is shutdown.
VVIET 38
The S-R flip flop is the simplest and easiest circuit to understand.
The SR flip flop has two inputs SET ‘S’ and RESET ‘R’. As the name suggests, when S = 1, output Q
becomes 1, and when R = 1, output Q becomes 0. The output Q’ is the complement of Q.
Truth Table
S R Q Q’ Comments
0 0 Q Q’ No change
0 1 0 1 Reset
1 0 1 0 Set
1 1 x x Invalid
For S = 1 and R = 1, output Q = x i.e. 1 or 0. Hence, S=1 and R=1 input combination
is invalid and must be avoided in the SR flip flop.
J-K Flip-flop
Block Diagram:
VVIET 39
The JK Flip Flop is used to remove the drawback of the S-R flip flop, i.e., undefined states. The JK
flip flop is formed by doing modification in the SR flip flop. The S-R flip flop is improved in order to
construct the J-K flip flop. When S and R input is set to true, the SR flip flop gives an inaccurate
result. But in the case of JK flip flop, it gives the correct output.
In J-K flip flop, if both of its inputs are different, the value of J at the next clock edge is taken by the
output Y. If both of its input is low, then no change occurs, and if high at the clock edge, then from one
state to the other, the output will be toggled. The JK Flip Flop is a Set or Reset Flip flop in the digital
system.
Truth Table:
VVIET 40
D Flip Flop
D flip flop is a widely used flip flop in digital systems. The D flip flop is mostly used in shift-registers,
counters, and input synchronization.
Truth Table:
VVIET 41
T Flip Flop
Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input", and CLK defines the
clock signal input.
Just like JK flip-flop, T flip flop is used. Unlike JK flip flop, in T flip flop, there is only single input
with the clock input. The T flip flop is constructed by connecting both of the inputs of JK flip flop
together as a single input.
The T flip flop is also known as Toggle flip-flop. These T flip-flops are able to find the complement of
its state.
Truth Table:
VVIET 42

Module 2

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Module 2

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Digital Design and Computer Organization BCS302

Combinational circuit consists of logic gates whose output at any time is

A combinational circuit consists of input variables, logic gates, and output

Block diagram of a combinational logic circuit

For n number of input variables to a combinational circuit, 2n possible

ARITHMETIC CIRCUITS – BASIC BUILDING BLOCKS:

Block schematic of half-adde

K-map simplification for carry and sum:

Logic Implementation of Half-adder

Block schematic of full-adder

The logic diagram for the above functions is shown as,

Implementation of full-adder in Sum of Products

Sum = Cin ⊕ (A ⊕ B) [x⊕y = x‘y+ xy‘]

Implementation of full adder with two half-adders and an OR gate

K-map simplification for half subtractor:

Difference, D = A’B+ AB’= A ⊕B

The first one representing the DIFFERENCE (D)output is that of an exclusive-OR

Logic Implementation of Half-Subtractor

Block schematic of full-adder

The truth table for full-subtractor is,

K-map simplification for full-subtractor:

The logic diagram for the above functions is shown as,

Implementation of full-adder in Sum of Products

Implementation of full-subtractor with two half-subtractors and an OR gate

Binary Adder (Parallel Adder):

4-bit binary parallel Adder

Let the 4-bit words to be added be represented by, A3A2A1A0=

Carry Propagation–Look-Ahead Carry Generator:

4-bit Parallel Adder

Logic diagram of Carry Look-ahead Generator

4-Bit Adder with Carry Look-ahead

Binary Subtractor (Parallel Subtractor):

4-bit Parallel Subtractor

Parallel Adder/ Subtractor:

4-Bit Adder Subtractor

Decimal Adder (BCD Adder):

Binary Sum BCD Sum

To implement BCD adder we require:

Block diagram of BCD adder

General structure of decoder

Binary Decoder (2 to 4 decoder):

3-to-8 Line Decoder:

3-to-8 line decoder

General structure of Encoder

z= D1+ D3+ D5+ D7

The priority encoder is implemented according to the above Boolean functions.

MULTIPLEXER: (Data Selector)

Block diagram of Multiplexer

2-to-1- line Multiplexer:

The data output is equal to I0 only if S1= 0 and S0= 0; Y= I0S1‘S0‘.

The logical expression of the term Y is as follows:

Logical circuit of the above expressions is given below:

The logical expression of the term Y is as follows:

Logical circuit of the above expressions is given below:

The logical expression of the term Y is as follows:

Logical circuit of the above expressions is given below:

Block Diagram of Sequntial Circuit

Combinational Circuits Sequential Circuits

It is not simple to design a sequential

Types of Sequential Circuits

Difference between Flip-flop and Latch :

It is a edge triggered device. It is a level triggered device.

Gates like NOR, NOT, AND, NAND are building

They are classified into asynchronous or

These can be used for the designing of

ex:D Flip-flop, JK Flip-flop ex:SR Latch, D Latch

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