COMBINATIONAL CIRCUITS

A combinational circuit is one where the output at any time depends only on the present
combination of inputs at that point of time with total disregard to the past state of the inputs. The
logic gate is the most basic building block of combinational logic. The logical function performed
by a combinational circuit is fully defined by a set of Boolean expressions. Some of the
characteristics of combinational circuits are as follows:
 The output of combinational circuit at any instant of time, depends only on the levels
present at input terminals.
 The combinational circuits do not use any memory. The previous state of input does not
have any effect on the present state of the circuit.
 A combinational circuit can have an n number of inputs and m number of outputs.
The Figure shows the block schematic representation of a generalized combinational circuit having
n input variables and m output variables or simply outputs. Since the number of input variables is
n, there are 2n possible combinations of bits at the input. Each output can be expressed in terms of
input variables by a Boolean expression, with the result that the generalized system can be
expressed by m Boolean expressions as shown.

Generalized Combinational circuit.

Implementing Combinational Logic

The different steps involved in the design of a combinational logic circuit are as follows:
1.Statement of the problem.
2. Identification of input and output variables.
3. Expressing the relationship between the input and output variables.
4. Construction of a truth table to meet input–output requirements.
5. Writing Boolean expressions for various output variables in terms of input variables.
6. Minimization of Boolean expressions.
7. Implementation of minimized Boolean expressions.

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Some of the combinational logic circuits in computer hardware to be covered are:
 Half Adder
 Full Adder
 Subtractors
 Comparators
 Multiplexers
 Demultiplexers
 Encoders
 Decoders

1.0 HALF ADDER

An adder is a digital circuit that performs addition of numbers. A half adder is an arithmetic circuit
block that can be used to add two bits. The two binary digits are known as augend and addend.Such
a circuit thus has two inputs that represent the two bits to be added and two outputs, with one
producing the SUM output and the other producing the CARRY. Figure 1.0 shows the truth table
of a half adder, showing all possible input combinations and the corresponding outputs.

Figure 1.0 Half Adder truth table

The Boolean expressions for the SUM and CARRY outputs are given by the equations
SUM (S) = 𝐴. 𝐵 + 𝐴. 𝐵 [=A (X-OR) B]
CARRY (C) = A.B
An examination of the two expressions tells that there is no scope for further simplification. While
the first one representing the SUM output is that of an X-OR gate, the second one representing the
CARRY output is that of an AND gate.

Therefore, the simplest way to hardware-implement a half–adder would be to use a two-input X-

OR gate for the SUM output and a two-input AND gate for the CARRY output, as shown in Figure
1.1.

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 Figure 1.1 Half Adder logic circuit.

The half-adder can also be represented in block diagram form as shown in figure 2(c).

Figure 1.2 Block diagram of Half Adder

2.0 FULL ADDER

A full adder circuit is an arithmetic circuit that can be used to add three bits to produce SUM and
CARRY outputs. The two binary inputs (A and B) could be referred to as operands, while the third
one can be referred to as CARRY IN (Cin). Such a building block becomes a necessity when it
comes to adding binary numbers with a large number of bits. The full adder circuit overcomes the
limitation of the half-adder, which can be used to add two bits only. A full adder is therefore
essential for the hardware implementation of an adder circuit capable of adding larger binary
numbers. A half-adder can be used for addition of LSBs only.

Figure 2.0 shows the truth table of a full adder circuit showing all possible input combinations and
corresponding outputs. In order to arrive at the logic circuit for hardware implementation of a full
adder, we will firstly write the Boolean expressions for the two output variables, that is, the SUM
and CARRY outputs, in terms of input variables.

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 Figure 2.0 Full Adder truth table.

The Boolean expressions for the two outputs are given by:

SUM (S) = A. B.Cin + A.B.Cin + A.B. Cin + A. B.Cin and

CARRYOUT (Cout) = A. B.Cin + A. B.Cin + A.B. Cin + A.B.Cin

A full adder can also be seen to comprise two half-adders and an OR gate. The expressions for
SUM and CARRY outputs can be rewritten as follows:

S = A. B.Cin + A.B.Cin + A.B. Cin + A.B.Cin

= A.B.Cin + A.B. Cin + A. B.Cin + A.B.Cin
= Cin(A. B + A. B)+ Cin(A. B + A.B)
= Cin(A⊕B) + Cin(A ⊕ B)

Let X be A⊕B
Thus, S = Cin.X + Cin.X
= Cin ⊕ X
⸫ S = A ⊕ B ⊕ Cin

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Similarly, the expression for CARRY output can be rewritten as follows:
Cout = A. B.Cin + A.B.Cin + A.B.Cin + A.B.Cin
= Cin(A. B + A. B) + A.B(Cin + Cin)
= Cin(A ⊕ B) + A.B
= A.B + Cin(A ⊕ B)

Figure 2.1 shows the circuit symbol and logic circuit of a full adder using two half adders and an
OR gate.

i) Full Adder symbol.

ii) Full Adder block diagram using two Half Adders.

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 iii) Full Adder logic circuit using two Half Adders.

Figure 2.1 Full Adder symbol and logic circuit.

2.2 PARALLEL ADDER

The full adder of the type described above forms the basic building block of binary adders.
However, a single full adder circuit can be used to add two one-bit binary numbers only. A cascade
arrangement of these adders can be used to construct adders capable of adding binary numbers
with a larger number of bits. For example, a four-bit binary adder would require four full adders
of the type shown in Figure 2.2 to be connected in cascade. The Figure shows such an arrangement.
(A3A2A1A0) and (B3B2B1B0) are the two binary numbers to be added, with A0 and B0 representing
LSBs and A3 and B3 representing MSBs of the two numbers.

Figure 2.2 Four bit binary adder

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For example, given that A=A3A2 A1A0 = 1101 and B=B3B2B1B0 = 1011, the two numbers could be
added as:

The addition process starts by adding the Least Significant Bits (LSBs) of the augend and added.

If 5 bit numbers were to be added, the circuit is implemented by adding one more full adder to the
left.

8.4 HALF SUBTRACTOR

A half-subtractor is a combinational circuit that can be used to subtract one binary digit from
another to produce a DIFFERENCE output and a BORROW output. The BORROW output here
specifies whether a ‘1’ has been borrowed to perform the subtraction. The truth table of a half-
subtractor, as shown in figure 8.4 explains this further. The Boolean expressions for the two
outputs are given by the equations
D = 𝐴 . 𝐵 + 𝐴. 𝐵
BO = 𝐴 . 𝐵
While the expression for the DIFFERENCE (D) output is that of an XOR gate, the expression for
the BORROW output (Bo) is that of an AND gate with input A complemented before it is fed to
the gate. Figure 8.4 shows the logic implementation of a half-subtractor.

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 a) Truth table and block diagram

b) Logic circuit

Figure 8.4 Half Subtractor

8.5 FULL SUBTRACTOR

A full subtractor performs subtraction operation on two bits, a minuend and a subtrahend, and also
takes into consideration whether a ‘1’ has already been borrowed by the previous adjacent lower
minuend bit or not. As a result, there are three bits to be handled at the input of a full subtractor,
namely the two bits to be subtracted and a borrow bit designated as Bin. There are two outputs,
namely the DIFFERENCE output (D) and the BORROW output (Bo). The BORROW output bit
tells whether the minuend bit needs to borrow a ‘1’ from the next possible higher minuend bit.
Table 8.5 shows the truth table of a full subtractor.

A B Bin D Bout
0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1

Table 8.5 Full subtractor truth table

In the least significant place of the subtraction a difference can only be obtained by borrowing a 1
from the next most significant state. The difference is now a 1 and this is entered in the least

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significant place of the difference. However, the borrow has to be replaced and this process is
illustrated in the Bout.

The Boolean expressions for the Difference is given by the equation:

𝐷 = 𝐴. 𝐵.Bin + 𝐴. 𝐵. 𝐵in + A.𝐵. 𝐵in + A.B.Bin
= A.B.𝐵in + A.B. Bin + A. B.Bin + A.B.Bin
= Bin(A. B + A. B)+ Bin(A. B + A.B)
= Bin(A⊕B) + Bin(A ⊕ B)

Now, let X be A⊕B

Thus, D = Bin.X + Bin.X
= Bin ⊕ X
⸫ D = A ⊕ B ⊕ Bin

The Boolean expressions for the Borrow out is given by the equation:

BO = 𝐴. 𝐵.Bin + 𝐴. 𝐵. 𝐵in + 𝐴. 𝐵. 𝐵in + A.B.Bin

= 𝐴. 𝐵.Bin + A.B.Bin + 𝐴. 𝐵. 𝐵in + 𝐴. 𝐵. 𝐵in
= Bin(A. B + A. B.) + A.B(Bin + Bin)
= Bin(𝐀 ⊕ 𝐁) + 𝐀.B

If we compare these expressions with those derived earlier in the case of a full adder, we find that
the expression for DIFFERENCE output (D) is the same as that for the SUM output. Also, the
expression for BORROW output Bo is similar to the expression for CARRY-OUT (Cout). In the
case of a half-subtractor, the A input is complemented. By a similar analysis it can be shown that
a full subtractor can be implemented with half-subtractors in the same way as a full adder was
constructed using half-adders. Relevant diagrams are shown in figures 10. Again, more than one
full subtractor can be connected in cascade to perform subtraction on two larger binary numbers.
As an illustration, Fig. 8.5 shows a four-bit subtractor.

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 a) Block diagram

b) Full Subtractor using Half Subtractors

Figure 8.5 Full Subtractor

Again, more than one full subtractor can be connected in cascade to perform subtraction on two
larger binary numbers. As an illustration, Figure 8.5.1 shows a four-bit subtractor.

Figure 8.5.1 Four bit Subtractor

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8.6 COMPARATORS
Comparators are combinational logic circuits used to compare two binary numbers. They are used
for testing whether the value represented by one binary word is greater than, less than, or equal to
the value represented by another binary word. Two basic types of comparator can be used.
 Equality comparators.
 Magnitude comparators.

8.6.1 Equality Comparators

Equality comparators compares whether two binary numbers are equal.

i) 1 bit equality comparator

A one bit comparator of figure 8.6.1(a) is the simplest to implement as it is based on the Exclusive-
NOR (XNOR) gate.

Figure 8.6.1(a) 1 bit comparator

ii) 4-bit equality comparator

The circuit of the 4-bit equality comparator shown in figure 8.6.1(b) consists of an exclusive NOR
gate (XNOR) per pair of input bits. If the two inputs are identical, an output of logic 1 is obtained.
The outputs of the XNOR gates are then combined in an AND gate, the output of which will be 1,
only when all the XNOR gates indicate matched inputs. A logic1 will be present at the output if
the two input words match, otherwise the output remains at 0. If the two numbers, are four-bit
binary numbers and are designated as (A3 A2 A1 A0) and (B3 B2 B1 B0), the two numbers will be
equal if all pairs of significant digits are equal, that is, A3 =B3, A2 =B2 A1 =B1 and A0 =B0.

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 Figure 8.6.1(b) Four Bit Equality Comparator
An equality comparator is the simplest multi-bit logic comparator, and can be used for such circuits
as electronic locks and security devices where a binary password consisting of multiple bits is
input to the comparator to be compared with another preset word.

8.6.2 Magnitude Comparators

A magnitude comparator is a combinational circuit that compares two given numbers and
determines whether one is equal to, less than or greater than the other. The output is in the form of
three binary variables representing the conditions A=B, A>B and A<B, if A and B are the two
numbers being compared. Figure 8.6.2(a) shows the logic circuit of a 1 bit magnitude comparator.

Figure 8.6.2(a) One Bit Magnitude Comparator

This basic circuit for a magnitude comparator may be extended for any number of bits but the more
bits the circuit has to compare, the more complex the circuit becomes. Figure 8.6.2(b) shows the
logic circuit of a four bit magnitude comparator.

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 Figure 8.6.2(b) Four bit magnitude comparator

8.7 Multiplexers
These are also called data selectors. A digital multiplexer (MUX) is a logic circuit that accepts
several digital data inputs and selects one of them at any given time to pass on to the output. The
routing of the desired data input to the output is controlled by SELECT inputs. If there are n
selection lines, then the number of maximum possible input lines is 2 n and the multiplexer is
referred to as a 2n-to-1 multiplexer or 2n×1 multiplexer. Figure 8.7 shows the functional diagram
of a general multiplexer.

Figure 8.7 MUX functional diagram

The multiplexer acts like a digitally controlled multi-position switch where a digital code applied
to SELECT inputs controls which data inputs will be switched to the output. For example, output

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Y will equal data input I0 for some particular SELECT input code, Y will equal data input I1 for
another particular SELECT input code and so on. Therefore, a multiplexer selects 1 out of N input
data sources and transmits the selected data to a single output channel. This is called multiplexing.

8.7.1 2-to-1 Multiplexer

Figure 8.7.1 shows the logic circuit for a two input multiplexer with data inputs I0 and I1
and SELECT input S. The logic level applied to the S input determines which AND gate is
enabled so that its data input passes through the OR gate to output Y. Therefore, the Boolean
expressions for the out is
Y = I0.𝑺 + I1.S
With S=0, the expression becomes
Y = I0.1 + I1.0
= I0
which indicates that Y will be identical to input signal I 0.

With S=1, the expression becomes

Y = I0.0 + I1.1
= I1
showing that the output Y will be identical to input signal I1.

I0 2:1
Data inputs MUX Output (Y)
I1

SELECT (S)

a) 2:1 MUX block symbol

Select input (S) Output (Y)

0 I0
1 I1

b) 2:1 MUX truth table

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 c) 2:1 MUX logic circuit

Figure 8.7.1 2:1 MUX symbol, truth table and logic circuit

Example
The timing diagram shown below is applied to a two-input multiplexer shown in Fig. 8.7.1
(a). Sketch the output waveform Y.

Solution
 If the SELECT line input, S = 0, the output, Y = I0, and if S = 1, Y = I1. These
conditions are applied to sketch the output waveform for the two-input multiplexer
with the given set of waveforms.
 Within the time period between t0 - t1, S = 0, therefore Y = I0.
 Within the time period between t1 - t2, S = 1, therefore, Y = I1.

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 Notice that within the time period, t0 - t1, the Y waveform is the same as I0 waveform.
Similarly, within the time period t1 - t2, the Y waveform is the same as I1.

8.7.2 4-to -1 Multiplexer

A 4: 1 MUX has 4 input bits, designated as I0, I1, I2 and I3 with one output Y. Two SELECT
bits S0 and S1 are used to decide which input bit should have to be selected and passed
through to the output. Each data input is gated with different combinations of select input
levels.
 I0 is gated with 𝑆0. 𝑆1 so that I0 will pass through its AND gate to output Y only
when S1 = 0 and S0 = 0.
 I1 is gated with S0. 𝑆1 so that I1 will pass through its AND gate to output Y only
when S1 = 0 and S0 = 1.
 I2 is gated with 𝑆0.S1 so that I2 will pass through its AND gate to output Y only when
S1 = 1 and S0 = 0.
 I3 is gated with S1.S0 so that I3 will pass through its AND gate
to output Y only when S1 = 1 and S0 = 1.

From the truth table, the Boolean expression for the output can be represented as shown
below.

Y = 𝑆0. 𝑆1.I0 + S0. 𝑆1.I1 + 𝑆0.S1.I2 + S0.S1.I3

Figure 8.7.2 shows the logic symbol, truth table and logic circuit implementation.

a) Symbol

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 b) Truth table

c) Logic circuit
Figure 8.7.2 4:1 MUX (a) Symbol (b) Truth table (c) Logic circuit

8.7.3 Multiplexer with Enable input

Multiplexers usually have an ENABLE input that can be used to control the multiplexing
function. When this input is enabled, that is, when it is in logic ‘1’ or logic ‘0’ state,
depending upon whether the ENABLE input is active HIGH or active LOW respectively,
the output is enabled, and the multiplexer functions normally. When the ENABLE input is
inactive, the output is disabled and permanently goes to either logic ‘0’ or logic ‘1’ state,
depending upon whether the output is uncomplemented or complemented. Figure 8.7.3(i)
shows how the 2-to-1 multiplexer can be modified to include an ENABLE input. The
ENABLE input here is active when HIGH.

a) 2:1 MUX symbol with ENABLE input

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 b) Truth table for 2:1 MUX with ENABLE input

c) 2:1 MUX Logic circuit with ENABLE input

Figure 8.7.3 (i) 2:1 MUX with ENABLE input

Figure 8.7.3(ii) shows a 4-to-1 multiplexer with an active LOW ENABLE input. When the
input to the ENABLE line is 0, the four AND gates are enabled. When ENABLE is 1, the
operation of the MUX is inhibited.

a) 4:1 MUX symbol with ENABLE input

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b) 4:1 MUX with ENABLE truth table

c) 4:1 MUX logic circuit with ENABLE

Figure 8.7.3(ii) 4:1 MUX with ENABLE input

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8.8 DEMULTIPLEXERS
These are also called data distributors. A demultiplexer (DEMUX) performs the reverse operation
of a multiplexer. That is, it takes a single input and distributes it over several outputs. It has an
input line, 2n output lines and n SELECT lines. It routes the information present on the input line
to any of the output lines. The output line that gets the information present on the input line is
decided by the bit status of the selection lines. Figure 8.7.4 illustrates the basic idea of a DEMUX.

Figure 8.8 Functional diagram of a DEMUX.

8.8.1 1 to 2 Demultiplexer
A 1-to-2 demultiplexer consists of one input line, two output lines and one SELECT line.
Since there are only two possible ways to connect the input to output lines, only one
SELECT signal is needed to do the demultiplexing operation.

The truth table of a 1-to-2 demultiplexer shows that the input routed to Y0 and Y1 depends
on the value of SELECT input S. Output Y1 is active when the combination of SELECT line
and input line are high. Therefore, the output Y1 = S.D and similarly the output Y0 is equal
to 𝑆.D. Figure 8.8.1 show the 1: 2 demultiplexer symbol, truth table and logic circuit.

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 a) Symbol

b) Truth table

c) Logic circuit

Figure 8.8.1 1:2 Demultiplexer

8.8.2 1:4 Demultiplexer

A 1-to-4 demux has a single input (I), two selection lines (S1 and S0) and four outputs (Y0
to Y3). The input data goes to any one of the four outputs at a given time for a particular

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combination of SELECT lines. The block diagram, truth table and logic circuit of a 1: 4
demultiplexer are shown in figure 8.8.2. From the table, the output logic can be expressed
as minterms and are given as follows:
Y0 = 𝑆0. 𝑆1.I
Y1 = S0. 𝑆1.I
Y2 = 𝑆0.S1.I
Y3 = S0.S1.I

a) Block symbol

b) Truth table

c) Logic circuit

Figure 8.8.2 1:4 Demultiplexer

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8.8.3 1-to-8 Demultiplexer
Figure 8.8.3(a) shows the block diagram of a 1-to-8 demultiplexer that consists of a single
input I, three SELECT inputs S2, S1 and S0 and eight outputs from Y0 to Y7. From the truth
table, the Boolean expressions for all the outputs can be written as follows:

From the obtained output expressions, the logic diagram of this demultiplexer can be
implemented by using eight AND gates and three NOT gates as shown in (c).

a) Block symbol

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 b) Truth table

Data Select Outputs

Input Inputs
D S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
D 0 0 0 0 0 0 0 0 0 0 D
D 0 0 1 0 0 0 0 0 0 D 0
D 0 1 0 0 0 0 0 0 D 0 0
D 0 1 1 0 0 0 0 D 0 0 0
D 1 0 0 0 0 0 D 0 0 0 0
D 1 0 1 0 0 D 0 0 0 0 0
D 1 1 0 0 D 0 0 0 0 0 0
D 1 1 1 D 0 0 0 0 0 0 0

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 c) Logic circuit

Figure 8.8.3 1:8 Demultiplexer

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8.9 ENCODERS
An encoder is used to generate a coded output (such as binary or BCD) from the active input line.
It has a number of input lines, only one of which is activated at a given time and produces an N-
bit output code, depending on which input is activated. Encoder takes ALL its data inputs one at a
time and then converts them into a single encoded output. Therefore, a binary encoder is a multi-
input combinational logic circuit that converts the logic level “1” data at its inputs into an
equivalent binary code at its output. Generally, digital encoders produce outputs of 2-bit, 3-bit or
4-bit codes depending upon the number of data input lines. An n - bit binary encoder has 2n input
lines and n- bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line
configurations

Figure 8.9 shows a general diagram for an encoder with M inputs and N outputs.

Figure 8.9 General encoder diagram

8.9.1 4 to 2 Encoder
A four bit Encoder allows only four inputs such as I0, I1, I2 and I3, and generates two outputs
such as A0 and A1. The assumption is that there are only four types of input signals: 0001,
0010, 0100 and 1000. Figure 8.9.1 shows the circuit symbol, truth table and logic circuit.

One of the main disadvantages of standard digital encoders is that they can generate the
wrong output code when there is more than one input present at logic level 1. For example,
if inputs I1 and I2 are made HIGH (logic 1) at the same time, the resulting output is neither
at 01 nor at 10 but will be at 11 which is an output binary number that is different to the
actual input present. In addition, an output code of all logic 0s can be generated when all
of its inputs are at 0 or when input I0 is equal to one.

a) Symbol

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 b) Truth table

c) Logic circuit

Figure 8.9.1 4:2 Encoder

8.9.2 Octal – to – Binary Encoder

An Octal-to-Binary Encoder has eight input lines, each representing an octal digit, and
three output lines for producing three bit binary output code corresponding to the activated
input line. D0 to D7 represent octal digits 0 to 7, while A, B and C represent the binary
digits. Figure 8.9.2 shows the circuit symbol, truth table and logic circuit.

From this table it may be noted that binary output A gives the logic 1 if any of the input
digits D4 or D5 or D6 or D7 is at logic 1. Therefore the Boolean expression for A is given
by:
A = D4 + D5 + D6 + D7
Similarly, the expressions for B and C may be given as:

B = D2 + D3 + D6 + D7
C = D1 + D3 + D5 + D7

Output A is the Most Significant Bit (MSB), while C in the Least Significant Bit (LSB).

The logic circuit for the octal – to – binary encoder with active high inputs is as shown in
figure 8.9.2

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 a) Block symbol

b) Truth table

c) Logic circuit

Figure 8.9.2 Octal-to-Binary Encoder

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8.9.3 Decimal – to – BCD Encoder
A decimal encoder is also known as a 10 line to 4 line encoder. It accepts 10 inputs and
produces a 4 - bit output corresponding to the activated decimal input. For example, when
line 2 is set to 1 and all other inputs to 0, the output will be 0010. This shows that the output
gives count of the input which is selected. Similarly, if input 5 is set to 1 and others to 0
then its BCD output will be 0101. Figure 8.9.3 shows the circuit symbol, truth table and
logic circuit.

From the truth table, the output expressions could be written as:
A = D1 + D3 + D5 + D7 + D9
B = D2 + D3 + D6 + D7
C = D4 + D5 + D6 + D7
D = D8 + D9

a) Block symbol

b) Truth table

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 c) Logic circuit

Figure 8.9.3 Decimal – to – BCD Encoder

Note
The encoder designs described have the following drawbacks:
 At any given time, only one input must be active (HIGH).
 If the number of active inputs is greater than one, then the output is incorrect.
 When no inputs are active, then all outputs are low which is also similar to the
output generated by active input D0.
A priority encoder is used to overcome the short comings of standard encoders.

8.9.4 Priority Encoder

A priority encoder is a practical form of an encoder. The encoders available in IC form are
all priority encoders. In this type of encoder, a priority is assigned to each input so that,
when more than one input is simultaneously active, the input with the highest priority is
encoded. The Most Significant Bit (MSB) has the highest priority and the Lowest
Significant Bit (LSB) has the lowest priority. As an illustration, let us assume that the octal-
to-binary encoder described in the previous section has an input priority for higher-order
digits. Let us also assume that input lines D2, D4 and D7 are all simultaneously in logic ‘1’
state. In that case, only D7 will be encoded and the output will be 111. The truth table of
such a priority encoder will then be modified to what is shown in table 8.9.4. Looking at

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 the last row of the table, it implies that, if D7 = 1, then, irrespective of the logic status of
other inputs, the output is 111 as D7 will only be encoded.

Figure 8.9.4 Priority encoder

8.10 DECODERS
A decoder is a combinational circuit that decodes the information on n input lines to a maximum
of 2n unique output lines. In general, if n and m are respectively the numbers of input and output
lines, then m≤ 2n. It accepts a set of inputs which represents a binary number and activates only
the output that corresponds to the input number. A decoder is thus a special case of a demultiplexer
without the
input line.

Figure 8.10 General decoder diagram

8.10.1 2 to 4 Decoder
A 2 to 4 decoder has two inputs and four outputs. It uses all AND gates and so the outputs are
active-HIGH. It may be noted that for a given input code, the only output that is active is the one
corresponding to the decimal equivalent of the binary input code. The output Y0 goes high only
when BA=002=010. Similarly, Y1 goes HIGH only when BA=012=110. The operation of the decoder
is given in the truth table. From the truth table, the expressions for the outputs are:

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 Y0 = 𝐴 𝐵
Y1 = A𝐵
Y2 = 𝐴 𝐵
Y3 = AB

a) Block symbol

b) Truth table

c) Logic circuit

Figure 8.10.1 2:4 decoder

8.10.2 3 to 8 Decoder
This decoder has three inputs designated as A, B and C and eight outputs designated as D0,
D1, D2, D3, D4, D5, D6 and D7. From the truth table, it is clear that, for any given input
combination, only one of the eight outputs is in logic ‘1’ state. Thus, each output produces
a certain minterm that corresponds to the binary number currently present at the input.

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From the truth table D0, D1, D2, D3, D4, D5, D6 and D7 respectively represent the following
minterms:

D0 = 𝐴 . 𝐵.𝐶
D1 = 𝐴 . 𝐵. 𝐶
D2 = 𝐴 . 𝐵. 𝐶
D3 = 𝐴 . 𝐵. 𝐶
D4 = 𝐴. 𝐵.𝐶
D5 = 𝐴. 𝐵.c
D6 = A.B. 𝐶
D7 = A.B.C

The operation of the circuit is shown in Fig. 8.10.2.

a) Block symbol

b) Truth table

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 c) Truth table

Figure 8.10.2 3:8 decoder

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